80 lines
3.0 KiB
C
80 lines
3.0 KiB
C
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/*
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* adc.c
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*
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* Created on: 2025<EFBFBD><EFBFBD>2<EFBFBD><EFBFBD>25<EFBFBD><EFBFBD>
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* Author: Cerlink
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*/
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#include "../../init/inc/adc.h"
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static void adc_Init(void)
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{
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ADC_InitTypeDef ADC_InitStructure = {0};
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GPIO_InitTypeDef GPIO_InitStructure = {0};
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RCC_PB2PeriphClockCmd(RCC_PB2Periph_GPIOA, ENABLE);
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RCC_PB2PeriphClockCmd(RCC_PB2Periph_ADC1, ENABLE);
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RCC_ADCCLKConfig(RCC_PCLK2_Div8); //8M/8
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GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_1|GPIO_Pin_2|GPIO_Pin_6|GPIO_Pin_7;
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GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AIN;
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GPIO_Init(GPIOA, &GPIO_InitStructure);
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ADC_DeInit(ADC1);
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ADC_InitStructure.ADC_Mode = ADC_Mode_Independent;
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ADC_InitStructure.ADC_ScanConvMode = ENABLE;
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ADC_InitStructure.ADC_ContinuousConvMode = ENABLE;
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ADC_InitStructure.ADC_ExternalTrigConv = ADC_ExternalTrigConv_None;
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ADC_InitStructure.ADC_DataAlign = ADC_DataAlign_Right;
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ADC_InitStructure.ADC_NbrOfChannel = 5;
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ADC_Init(ADC1, &ADC_InitStructure);
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ADC_DMACmd(ADC1, ENABLE);
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ADC_Cmd(ADC1, ENABLE);
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ADC_FIFO_Cmd(ADC1, ENABLE);
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ADC_BufferCmd(ADC1, DISABLE); //disable buffer
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ADC_ResetCalibration(ADC1);
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while(ADC_GetResetCalibrationStatus(ADC1));
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ADC_StartCalibration(ADC1);
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while(ADC_GetCalibrationStatus(ADC1));
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}
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static void adc_dma_Tx_Init(DMA_Channel_TypeDef *DMA_CHx, u32 ppadr, u32 memadr, u16 bufsize)
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{
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DMA_InitTypeDef DMA_InitStructure = {0};
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RCC_HBPeriphClockCmd(RCC_HBPeriph_DMA1, ENABLE);
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DMA_DeInit(DMA_CHx);
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DMA_InitStructure.DMA_PeripheralBaseAddr = ppadr;
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DMA_InitStructure.DMA_MemoryBaseAddr = memadr;
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DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralSRC;
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DMA_InitStructure.DMA_BufferSize = bufsize;
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DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable;
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DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable;
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DMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_HalfWord;
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DMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_HalfWord;
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DMA_InitStructure.DMA_Mode = DMA_Mode_Circular;
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DMA_InitStructure.DMA_Priority = DMA_Priority_VeryHigh;
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DMA_InitStructure.DMA_M2M = DMA_M2M_Disable;
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DMA_Init(DMA_CHx, &DMA_InitStructure);
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}
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uint16_t gADCBuf[5];
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void all_adc_init(void)
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{
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adc_Init();
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adc_dma_Tx_Init(DMA1_Channel1, (u32)&ADC1->RDATAR, (u32)gADCBuf, 5);
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DMA_Cmd(DMA1_Channel1, ENABLE);
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ADC_RegularChannelConfig(ADC1, ADC_Channel_0, 1, ADC_SampleTime_CyclesMode7);//(239.5+1.5)*1/1M = 0.000241s = 241 us
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ADC_RegularChannelConfig(ADC1, ADC_Channel_1, 2, ADC_SampleTime_CyclesMode7);//(239.5+1.5)*1/1M = 0.000241s = 241 us
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ADC_RegularChannelConfig(ADC1, ADC_Channel_2, 3, ADC_SampleTime_CyclesMode7);//(239.5+1.5)*1/1M = 0.000241s = 241 us
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ADC_RegularChannelConfig(ADC1, ADC_Channel_6, 4, ADC_SampleTime_CyclesMode7);//(239.5+1.5)*1/1M = 0.000241s = 241 us
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ADC_RegularChannelConfig(ADC1, ADC_Channel_7, 5, ADC_SampleTime_CyclesMode7);//(239.5+1.5)*1/1M = 0.000241s = 241 us<75><73>241*5 = 1205 us
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ADC_SoftwareStartConvCmd(ADC1, ENABLE);
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}
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