From 973b2a01510010917692fc64b340980dbdee014c Mon Sep 17 00:00:00 2001 From: 95384 <664090429@qq.com> Date: Wed, 19 Feb 2025 14:18:30 +0800 Subject: [PATCH] First commit --- ZDBMS/BMS_CC/.cproject | 144 + ZDBMS/BMS_CC/.project | 34 + ZDBMS/BMS_CC/.settings/language.settings.xml | 14 + ZDBMS/BMS_CC/.template | 17 + ZDBMS/BMS_CC/BMS_CC.launch | 61 + ZDBMS/BMS_CC/BMS_CC.wvproj | 1 + ZDBMS/BMS_CC/Core/core_riscv.c | 306 ++ ZDBMS/BMS_CC/Core/core_riscv.h | 585 ++ ZDBMS/BMS_CC/Debug/debug.c | 192 + ZDBMS/BMS_CC/Debug/debug.h | 54 + ZDBMS/BMS_CC/Ld/Link.ld | 1 + ZDBMS/BMS_CC/Peripheral/inc/ch32l103.h | 4759 +++++++++++++++++ ZDBMS/BMS_CC/Peripheral/inc/ch32l103_adc.h | 211 + ZDBMS/BMS_CC/Peripheral/inc/ch32l103_bkp.h | 65 + ZDBMS/BMS_CC/Peripheral/inc/ch32l103_can.h | 630 +++ ZDBMS/BMS_CC/Peripheral/inc/ch32l103_crc.h | 33 + ZDBMS/BMS_CC/Peripheral/inc/ch32l103_dbgmcu.h | 46 + ZDBMS/BMS_CC/Peripheral/inc/ch32l103_dma.h | 184 + ZDBMS/BMS_CC/Peripheral/inc/ch32l103_exti.h | 90 + ZDBMS/BMS_CC/Peripheral/inc/ch32l103_flash.h | 142 + ZDBMS/BMS_CC/Peripheral/inc/ch32l103_gpio.h | 178 + ZDBMS/BMS_CC/Peripheral/inc/ch32l103_i2c.h | 424 ++ ZDBMS/BMS_CC/Peripheral/inc/ch32l103_iwdg.h | 50 + ZDBMS/BMS_CC/Peripheral/inc/ch32l103_lptim.h | 200 + ZDBMS/BMS_CC/Peripheral/inc/ch32l103_misc.h | 72 + ZDBMS/BMS_CC/Peripheral/inc/ch32l103_opa.h | 243 + ZDBMS/BMS_CC/Peripheral/inc/ch32l103_pwr.h | 68 + ZDBMS/BMS_CC/Peripheral/inc/ch32l103_rcc.h | 220 + ZDBMS/BMS_CC/Peripheral/inc/ch32l103_rtc.h | 55 + ZDBMS/BMS_CC/Peripheral/inc/ch32l103_spi.h | 158 + ZDBMS/BMS_CC/Peripheral/inc/ch32l103_tim.h | 517 ++ ZDBMS/BMS_CC/Peripheral/inc/ch32l103_usart.h | 188 + ZDBMS/BMS_CC/Peripheral/inc/ch32l103_usb.h | 513 ++ ZDBMS/BMS_CC/Peripheral/inc/ch32l103_usbpd.h | 408 ++ ZDBMS/BMS_CC/Peripheral/inc/ch32l103_wwdg.h | 41 + ZDBMS/BMS_CC/Peripheral/src/ch32l103_adc.c | 1344 +++++ ZDBMS/BMS_CC/Peripheral/src/ch32l103_bkp.c | 244 + ZDBMS/BMS_CC/Peripheral/src/ch32l103_can.c | 1697 ++++++ ZDBMS/BMS_CC/Peripheral/src/ch32l103_crc.c | 99 + ZDBMS/BMS_CC/Peripheral/src/ch32l103_dbgmcu.c | 126 + ZDBMS/BMS_CC/Peripheral/src/ch32l103_dma.c | 432 ++ ZDBMS/BMS_CC/Peripheral/src/ch32l103_exti.c | 182 + ZDBMS/BMS_CC/Peripheral/src/ch32l103_flash.c | 1009 ++++ ZDBMS/BMS_CC/Peripheral/src/ch32l103_gpio.c | 696 +++ ZDBMS/BMS_CC/Peripheral/src/ch32l103_i2c.c | 1013 ++++ ZDBMS/BMS_CC/Peripheral/src/ch32l103_iwdg.c | 123 + ZDBMS/BMS_CC/Peripheral/src/ch32l103_lptim.c | 363 ++ ZDBMS/BMS_CC/Peripheral/src/ch32l103_misc.c | 81 + ZDBMS/BMS_CC/Peripheral/src/ch32l103_opa.c | 343 ++ ZDBMS/BMS_CC/Peripheral/src/ch32l103_pwr.c | 466 ++ ZDBMS/BMS_CC/Peripheral/src/ch32l103_rcc.c | 1045 ++++ ZDBMS/BMS_CC/Peripheral/src/ch32l103_rtc.c | 281 + ZDBMS/BMS_CC/Peripheral/src/ch32l103_spi.c | 536 ++ ZDBMS/BMS_CC/Peripheral/src/ch32l103_tim.c | 2412 +++++++++ ZDBMS/BMS_CC/Peripheral/src/ch32l103_usart.c | 816 +++ ZDBMS/BMS_CC/Peripheral/src/ch32l103_wwdg.c | 142 + ZDBMS/BMS_CC/Startup/startup_ch32l103.S | 269 + ZDBMS/BMS_CC/User/ch32l103_conf.h | 38 + ZDBMS/BMS_CC/User/ch32l103_it.c | 47 + ZDBMS/BMS_CC/User/ch32l103_it.h | 17 + ZDBMS/BMS_CC/User/main.c | 50 + ZDBMS/BMS_CC/User/system_ch32l103.c | 754 +++ ZDBMS/BMS_CC/User/system_ch32l103.h | 29 + ZDBMS/BMS_CC/obj/BMS_CC.elf | Bin 0 -> 101624 bytes ZDBMS/BMS_CC/obj/BMS_CC.hex | 488 ++ ZDBMS/BMS_CC/obj/BMS_CC.lst | 3311 ++++++++++++ ZDBMS/BMS_CC/obj/BMS_CC.map | 2101 ++++++++ ZDBMS/BMS_CC/obj/Core/core_riscv.d | 1 + ZDBMS/BMS_CC/obj/Core/core_riscv.o | Bin 0 -> 16496 bytes ZDBMS/BMS_CC/obj/Core/subdir.mk | 21 + ZDBMS/BMS_CC/obj/Debug/debug.d | 87 + ZDBMS/BMS_CC/obj/Debug/debug.o | Bin 0 -> 29656 bytes ZDBMS/BMS_CC/obj/Debug/subdir.mk | 21 + .../BMS_CC/obj/Peripheral/src/ch32l103_adc.d | 85 + .../BMS_CC/obj/Peripheral/src/ch32l103_adc.o | Bin 0 -> 98632 bytes .../BMS_CC/obj/Peripheral/src/ch32l103_bkp.d | 85 + .../BMS_CC/obj/Peripheral/src/ch32l103_bkp.o | Bin 0 -> 27512 bytes .../BMS_CC/obj/Peripheral/src/ch32l103_can.d | 85 + .../BMS_CC/obj/Peripheral/src/ch32l103_can.o | Bin 0 -> 119588 bytes .../BMS_CC/obj/Peripheral/src/ch32l103_crc.d | 85 + .../BMS_CC/obj/Peripheral/src/ch32l103_crc.o | Bin 0 -> 17776 bytes .../obj/Peripheral/src/ch32l103_dbgmcu.d | 85 + .../obj/Peripheral/src/ch32l103_dbgmcu.o | Bin 0 -> 18100 bytes .../BMS_CC/obj/Peripheral/src/ch32l103_dma.d | 85 + .../BMS_CC/obj/Peripheral/src/ch32l103_dma.o | Bin 0 -> 28892 bytes .../BMS_CC/obj/Peripheral/src/ch32l103_exti.d | 85 + .../BMS_CC/obj/Peripheral/src/ch32l103_exti.o | Bin 0 -> 23708 bytes .../obj/Peripheral/src/ch32l103_flash.d | 85 + .../obj/Peripheral/src/ch32l103_flash.o | Bin 0 -> 86436 bytes .../BMS_CC/obj/Peripheral/src/ch32l103_gpio.d | 85 + .../BMS_CC/obj/Peripheral/src/ch32l103_gpio.o | Bin 0 -> 64856 bytes .../BMS_CC/obj/Peripheral/src/ch32l103_i2c.d | 85 + .../BMS_CC/obj/Peripheral/src/ch32l103_i2c.o | Bin 0 -> 65536 bytes .../BMS_CC/obj/Peripheral/src/ch32l103_iwdg.d | 85 + .../BMS_CC/obj/Peripheral/src/ch32l103_iwdg.o | Bin 0 -> 18324 bytes .../obj/Peripheral/src/ch32l103_lptim.d | 85 + .../obj/Peripheral/src/ch32l103_lptim.o | Bin 0 -> 32232 bytes .../BMS_CC/obj/Peripheral/src/ch32l103_misc.d | 85 + .../BMS_CC/obj/Peripheral/src/ch32l103_misc.o | Bin 0 -> 22064 bytes .../BMS_CC/obj/Peripheral/src/ch32l103_opa.d | 85 + .../BMS_CC/obj/Peripheral/src/ch32l103_opa.o | Bin 0 -> 41552 bytes .../BMS_CC/obj/Peripheral/src/ch32l103_pwr.d | 85 + .../BMS_CC/obj/Peripheral/src/ch32l103_pwr.o | Bin 0 -> 45916 bytes .../BMS_CC/obj/Peripheral/src/ch32l103_rcc.d | 85 + .../BMS_CC/obj/Peripheral/src/ch32l103_rcc.o | Bin 0 -> 66596 bytes .../BMS_CC/obj/Peripheral/src/ch32l103_rtc.d | 85 + .../BMS_CC/obj/Peripheral/src/ch32l103_rtc.o | Bin 0 -> 32496 bytes .../BMS_CC/obj/Peripheral/src/ch32l103_spi.d | 85 + .../BMS_CC/obj/Peripheral/src/ch32l103_spi.o | Bin 0 -> 43060 bytes .../BMS_CC/obj/Peripheral/src/ch32l103_tim.d | 85 + .../BMS_CC/obj/Peripheral/src/ch32l103_tim.o | Bin 0 -> 179704 bytes .../obj/Peripheral/src/ch32l103_usart.d | 85 + .../obj/Peripheral/src/ch32l103_usart.o | Bin 0 -> 61312 bytes .../BMS_CC/obj/Peripheral/src/ch32l103_wwdg.d | 85 + .../BMS_CC/obj/Peripheral/src/ch32l103_wwdg.o | Bin 0 -> 20532 bytes ZDBMS/BMS_CC/obj/Peripheral/src/subdir.mk | 81 + ZDBMS/BMS_CC/obj/Startup/startup_ch32l103.d | 1 + ZDBMS/BMS_CC/obj/Startup/startup_ch32l103.o | Bin 0 -> 8160 bytes ZDBMS/BMS_CC/obj/Startup/subdir.mk | 21 + ZDBMS/BMS_CC/obj/User/ch32l103_it.d | 87 + ZDBMS/BMS_CC/obj/User/ch32l103_it.o | Bin 0 -> 14868 bytes ZDBMS/BMS_CC/obj/User/main.d | 84 + ZDBMS/BMS_CC/obj/User/main.o | Bin 0 -> 14912 bytes ZDBMS/BMS_CC/obj/User/subdir.mk | 27 + ZDBMS/BMS_CC/obj/User/system_ch32l103.d | 85 + ZDBMS/BMS_CC/obj/User/system_ch32l103.o | Bin 0 -> 22400 bytes ZDBMS/BMS_CC/obj/makefile | 75 + ZDBMS/BMS_CC/obj/objects.mk | 9 + ZDBMS/BMS_CC/obj/sources.mk | 31 + ZDBMS/BMS_MC/.cproject | 144 + ZDBMS/BMS_MC/.project | 34 + ZDBMS/BMS_MC/.settings/language.settings.xml | 14 + ZDBMS/BMS_MC/.template | 17 + ZDBMS/BMS_MC/BMS_MC.launch | 61 + ZDBMS/BMS_MC/BMS_MC.wvproj | 1 + ZDBMS/BMS_MC/Core/core_riscv.c | 306 ++ ZDBMS/BMS_MC/Core/core_riscv.h | 585 ++ ZDBMS/BMS_MC/Debug/debug.c | 192 + ZDBMS/BMS_MC/Debug/debug.h | 54 + ZDBMS/BMS_MC/Ld/Link.ld | 1 + ZDBMS/BMS_MC/Peripheral/inc/ch32l103.h | 4759 +++++++++++++++++ ZDBMS/BMS_MC/Peripheral/inc/ch32l103_adc.h | 211 + ZDBMS/BMS_MC/Peripheral/inc/ch32l103_bkp.h | 65 + ZDBMS/BMS_MC/Peripheral/inc/ch32l103_can.h | 630 +++ ZDBMS/BMS_MC/Peripheral/inc/ch32l103_crc.h | 33 + ZDBMS/BMS_MC/Peripheral/inc/ch32l103_dbgmcu.h | 46 + ZDBMS/BMS_MC/Peripheral/inc/ch32l103_dma.h | 184 + ZDBMS/BMS_MC/Peripheral/inc/ch32l103_exti.h | 90 + ZDBMS/BMS_MC/Peripheral/inc/ch32l103_flash.h | 142 + ZDBMS/BMS_MC/Peripheral/inc/ch32l103_gpio.h | 178 + ZDBMS/BMS_MC/Peripheral/inc/ch32l103_i2c.h | 424 ++ ZDBMS/BMS_MC/Peripheral/inc/ch32l103_iwdg.h | 50 + ZDBMS/BMS_MC/Peripheral/inc/ch32l103_lptim.h | 200 + ZDBMS/BMS_MC/Peripheral/inc/ch32l103_misc.h | 72 + ZDBMS/BMS_MC/Peripheral/inc/ch32l103_opa.h | 243 + ZDBMS/BMS_MC/Peripheral/inc/ch32l103_pwr.h | 68 + ZDBMS/BMS_MC/Peripheral/inc/ch32l103_rcc.h | 220 + ZDBMS/BMS_MC/Peripheral/inc/ch32l103_rtc.h | 55 + ZDBMS/BMS_MC/Peripheral/inc/ch32l103_spi.h | 158 + ZDBMS/BMS_MC/Peripheral/inc/ch32l103_tim.h | 517 ++ ZDBMS/BMS_MC/Peripheral/inc/ch32l103_usart.h | 188 + ZDBMS/BMS_MC/Peripheral/inc/ch32l103_usb.h | 513 ++ ZDBMS/BMS_MC/Peripheral/inc/ch32l103_usbpd.h | 408 ++ ZDBMS/BMS_MC/Peripheral/inc/ch32l103_wwdg.h | 41 + ZDBMS/BMS_MC/Peripheral/src/ch32l103_adc.c | 1344 +++++ ZDBMS/BMS_MC/Peripheral/src/ch32l103_bkp.c | 244 + ZDBMS/BMS_MC/Peripheral/src/ch32l103_can.c | 1697 ++++++ ZDBMS/BMS_MC/Peripheral/src/ch32l103_crc.c | 99 + ZDBMS/BMS_MC/Peripheral/src/ch32l103_dbgmcu.c | 126 + ZDBMS/BMS_MC/Peripheral/src/ch32l103_dma.c | 432 ++ ZDBMS/BMS_MC/Peripheral/src/ch32l103_exti.c | 182 + ZDBMS/BMS_MC/Peripheral/src/ch32l103_flash.c | 1009 ++++ ZDBMS/BMS_MC/Peripheral/src/ch32l103_gpio.c | 696 +++ ZDBMS/BMS_MC/Peripheral/src/ch32l103_i2c.c | 1013 ++++ ZDBMS/BMS_MC/Peripheral/src/ch32l103_iwdg.c | 123 + ZDBMS/BMS_MC/Peripheral/src/ch32l103_lptim.c | 363 ++ ZDBMS/BMS_MC/Peripheral/src/ch32l103_misc.c | 81 + ZDBMS/BMS_MC/Peripheral/src/ch32l103_opa.c | 343 ++ ZDBMS/BMS_MC/Peripheral/src/ch32l103_pwr.c | 466 ++ ZDBMS/BMS_MC/Peripheral/src/ch32l103_rcc.c | 1045 ++++ ZDBMS/BMS_MC/Peripheral/src/ch32l103_rtc.c | 281 + ZDBMS/BMS_MC/Peripheral/src/ch32l103_spi.c | 536 ++ ZDBMS/BMS_MC/Peripheral/src/ch32l103_tim.c | 2412 +++++++++ ZDBMS/BMS_MC/Peripheral/src/ch32l103_usart.c | 816 +++ ZDBMS/BMS_MC/Peripheral/src/ch32l103_wwdg.c | 142 + ZDBMS/BMS_MC/Startup/startup_ch32l103.S | 269 + ZDBMS/BMS_MC/User/ch32l103_conf.h | 38 + ZDBMS/BMS_MC/User/ch32l103_it.c | 47 + ZDBMS/BMS_MC/User/ch32l103_it.h | 17 + ZDBMS/BMS_MC/User/main.c | 50 + ZDBMS/BMS_MC/User/system_ch32l103.c | 754 +++ ZDBMS/BMS_MC/User/system_ch32l103.h | 29 + ZDBMS/BMS_MC/obj/BMS_MC.elf | Bin 0 -> 101624 bytes ZDBMS/BMS_MC/obj/BMS_MC.hex | 488 ++ ZDBMS/BMS_MC/obj/BMS_MC.lst | 3310 ++++++++++++ ZDBMS/BMS_MC/obj/BMS_MC.map | 2100 ++++++++ ZDBMS/BMS_MC/obj/Core/core_riscv.d | 1 + ZDBMS/BMS_MC/obj/Core/core_riscv.o | Bin 0 -> 16496 bytes ZDBMS/BMS_MC/obj/Core/subdir.mk | 21 + ZDBMS/BMS_MC/obj/Debug/debug.d | 87 + ZDBMS/BMS_MC/obj/Debug/debug.o | Bin 0 -> 29656 bytes ZDBMS/BMS_MC/obj/Debug/subdir.mk | 21 + .../BMS_MC/obj/Peripheral/src/ch32l103_adc.d | 85 + .../BMS_MC/obj/Peripheral/src/ch32l103_adc.o | Bin 0 -> 98632 bytes .../BMS_MC/obj/Peripheral/src/ch32l103_bkp.d | 85 + .../BMS_MC/obj/Peripheral/src/ch32l103_bkp.o | Bin 0 -> 27512 bytes .../BMS_MC/obj/Peripheral/src/ch32l103_can.d | 85 + .../BMS_MC/obj/Peripheral/src/ch32l103_can.o | Bin 0 -> 119588 bytes .../BMS_MC/obj/Peripheral/src/ch32l103_crc.d | 85 + .../BMS_MC/obj/Peripheral/src/ch32l103_crc.o | Bin 0 -> 17776 bytes .../obj/Peripheral/src/ch32l103_dbgmcu.d | 85 + .../obj/Peripheral/src/ch32l103_dbgmcu.o | Bin 0 -> 18100 bytes .../BMS_MC/obj/Peripheral/src/ch32l103_dma.d | 85 + .../BMS_MC/obj/Peripheral/src/ch32l103_dma.o | Bin 0 -> 28892 bytes .../BMS_MC/obj/Peripheral/src/ch32l103_exti.d | 85 + .../BMS_MC/obj/Peripheral/src/ch32l103_exti.o | Bin 0 -> 23708 bytes .../obj/Peripheral/src/ch32l103_flash.d | 85 + .../obj/Peripheral/src/ch32l103_flash.o | Bin 0 -> 86436 bytes .../BMS_MC/obj/Peripheral/src/ch32l103_gpio.d | 85 + .../BMS_MC/obj/Peripheral/src/ch32l103_gpio.o | Bin 0 -> 64856 bytes .../BMS_MC/obj/Peripheral/src/ch32l103_i2c.d | 85 + .../BMS_MC/obj/Peripheral/src/ch32l103_i2c.o | Bin 0 -> 65536 bytes .../BMS_MC/obj/Peripheral/src/ch32l103_iwdg.d | 85 + .../BMS_MC/obj/Peripheral/src/ch32l103_iwdg.o | Bin 0 -> 18324 bytes .../obj/Peripheral/src/ch32l103_lptim.d | 85 + .../obj/Peripheral/src/ch32l103_lptim.o | Bin 0 -> 32232 bytes .../BMS_MC/obj/Peripheral/src/ch32l103_misc.d | 85 + .../BMS_MC/obj/Peripheral/src/ch32l103_misc.o | Bin 0 -> 22064 bytes .../BMS_MC/obj/Peripheral/src/ch32l103_opa.d | 85 + .../BMS_MC/obj/Peripheral/src/ch32l103_opa.o | Bin 0 -> 41552 bytes .../BMS_MC/obj/Peripheral/src/ch32l103_pwr.d | 85 + .../BMS_MC/obj/Peripheral/src/ch32l103_pwr.o | Bin 0 -> 45916 bytes .../BMS_MC/obj/Peripheral/src/ch32l103_rcc.d | 85 + .../BMS_MC/obj/Peripheral/src/ch32l103_rcc.o | Bin 0 -> 66596 bytes .../BMS_MC/obj/Peripheral/src/ch32l103_rtc.d | 85 + .../BMS_MC/obj/Peripheral/src/ch32l103_rtc.o | Bin 0 -> 32496 bytes .../BMS_MC/obj/Peripheral/src/ch32l103_spi.d | 85 + .../BMS_MC/obj/Peripheral/src/ch32l103_spi.o | Bin 0 -> 43060 bytes .../BMS_MC/obj/Peripheral/src/ch32l103_tim.d | 85 + .../BMS_MC/obj/Peripheral/src/ch32l103_tim.o | Bin 0 -> 179704 bytes .../obj/Peripheral/src/ch32l103_usart.d | 85 + .../obj/Peripheral/src/ch32l103_usart.o | Bin 0 -> 61312 bytes .../BMS_MC/obj/Peripheral/src/ch32l103_wwdg.d | 85 + .../BMS_MC/obj/Peripheral/src/ch32l103_wwdg.o | Bin 0 -> 20532 bytes ZDBMS/BMS_MC/obj/Peripheral/src/subdir.mk | 81 + ZDBMS/BMS_MC/obj/Startup/startup_ch32l103.d | 1 + ZDBMS/BMS_MC/obj/Startup/startup_ch32l103.o | Bin 0 -> 8160 bytes ZDBMS/BMS_MC/obj/Startup/subdir.mk | 21 + ZDBMS/BMS_MC/obj/User/ch32l103_it.d | 87 + ZDBMS/BMS_MC/obj/User/ch32l103_it.o | Bin 0 -> 14868 bytes ZDBMS/BMS_MC/obj/User/main.d | 84 + ZDBMS/BMS_MC/obj/User/main.o | Bin 0 -> 14908 bytes ZDBMS/BMS_MC/obj/User/subdir.mk | 27 + ZDBMS/BMS_MC/obj/User/system_ch32l103.d | 85 + ZDBMS/BMS_MC/obj/User/system_ch32l103.o | Bin 0 -> 22400 bytes ZDBMS/BMS_MC/obj/makefile | 75 + ZDBMS/BMS_MC/obj/objects.mk | 9 + ZDBMS/BMS_MC/obj/sources.mk | 31 + 258 files changed, 67746 insertions(+) create mode 100644 ZDBMS/BMS_CC/.cproject create mode 100644 ZDBMS/BMS_CC/.project create mode 100644 ZDBMS/BMS_CC/.settings/language.settings.xml create mode 100644 ZDBMS/BMS_CC/.template create mode 100644 ZDBMS/BMS_CC/BMS_CC.launch create mode 100644 ZDBMS/BMS_CC/BMS_CC.wvproj create mode 100644 ZDBMS/BMS_CC/Core/core_riscv.c create mode 100644 ZDBMS/BMS_CC/Core/core_riscv.h create mode 100644 ZDBMS/BMS_CC/Debug/debug.c create mode 100644 ZDBMS/BMS_CC/Debug/debug.h create mode 100644 ZDBMS/BMS_CC/Ld/Link.ld create mode 100644 ZDBMS/BMS_CC/Peripheral/inc/ch32l103.h create mode 100644 ZDBMS/BMS_CC/Peripheral/inc/ch32l103_adc.h create mode 100644 ZDBMS/BMS_CC/Peripheral/inc/ch32l103_bkp.h create mode 100644 ZDBMS/BMS_CC/Peripheral/inc/ch32l103_can.h create mode 100644 ZDBMS/BMS_CC/Peripheral/inc/ch32l103_crc.h create mode 100644 ZDBMS/BMS_CC/Peripheral/inc/ch32l103_dbgmcu.h create mode 100644 ZDBMS/BMS_CC/Peripheral/inc/ch32l103_dma.h create mode 100644 ZDBMS/BMS_CC/Peripheral/inc/ch32l103_exti.h create mode 100644 ZDBMS/BMS_CC/Peripheral/inc/ch32l103_flash.h create mode 100644 ZDBMS/BMS_CC/Peripheral/inc/ch32l103_gpio.h create mode 100644 ZDBMS/BMS_CC/Peripheral/inc/ch32l103_i2c.h create mode 100644 ZDBMS/BMS_CC/Peripheral/inc/ch32l103_iwdg.h create mode 100644 ZDBMS/BMS_CC/Peripheral/inc/ch32l103_lptim.h create mode 100644 ZDBMS/BMS_CC/Peripheral/inc/ch32l103_misc.h create mode 100644 ZDBMS/BMS_CC/Peripheral/inc/ch32l103_opa.h create mode 100644 ZDBMS/BMS_CC/Peripheral/inc/ch32l103_pwr.h create mode 100644 ZDBMS/BMS_CC/Peripheral/inc/ch32l103_rcc.h create mode 100644 ZDBMS/BMS_CC/Peripheral/inc/ch32l103_rtc.h create mode 100644 ZDBMS/BMS_CC/Peripheral/inc/ch32l103_spi.h create mode 100644 ZDBMS/BMS_CC/Peripheral/inc/ch32l103_tim.h create mode 100644 ZDBMS/BMS_CC/Peripheral/inc/ch32l103_usart.h create mode 100644 ZDBMS/BMS_CC/Peripheral/inc/ch32l103_usb.h create mode 100644 ZDBMS/BMS_CC/Peripheral/inc/ch32l103_usbpd.h create mode 100644 ZDBMS/BMS_CC/Peripheral/inc/ch32l103_wwdg.h create mode 100644 ZDBMS/BMS_CC/Peripheral/src/ch32l103_adc.c create mode 100644 ZDBMS/BMS_CC/Peripheral/src/ch32l103_bkp.c create mode 100644 ZDBMS/BMS_CC/Peripheral/src/ch32l103_can.c create mode 100644 ZDBMS/BMS_CC/Peripheral/src/ch32l103_crc.c create mode 100644 ZDBMS/BMS_CC/Peripheral/src/ch32l103_dbgmcu.c create mode 100644 ZDBMS/BMS_CC/Peripheral/src/ch32l103_dma.c create mode 100644 ZDBMS/BMS_CC/Peripheral/src/ch32l103_exti.c create mode 100644 ZDBMS/BMS_CC/Peripheral/src/ch32l103_flash.c create mode 100644 ZDBMS/BMS_CC/Peripheral/src/ch32l103_gpio.c create mode 100644 ZDBMS/BMS_CC/Peripheral/src/ch32l103_i2c.c create mode 100644 ZDBMS/BMS_CC/Peripheral/src/ch32l103_iwdg.c create mode 100644 ZDBMS/BMS_CC/Peripheral/src/ch32l103_lptim.c create mode 100644 ZDBMS/BMS_CC/Peripheral/src/ch32l103_misc.c create mode 100644 ZDBMS/BMS_CC/Peripheral/src/ch32l103_opa.c create mode 100644 ZDBMS/BMS_CC/Peripheral/src/ch32l103_pwr.c create mode 100644 ZDBMS/BMS_CC/Peripheral/src/ch32l103_rcc.c create mode 100644 ZDBMS/BMS_CC/Peripheral/src/ch32l103_rtc.c create mode 100644 ZDBMS/BMS_CC/Peripheral/src/ch32l103_spi.c create mode 100644 ZDBMS/BMS_CC/Peripheral/src/ch32l103_tim.c create mode 100644 ZDBMS/BMS_CC/Peripheral/src/ch32l103_usart.c create mode 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org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + 1595986042669 + + 22 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-*.wvproj + + + + diff --git a/ZDBMS/BMS_CC/.settings/language.settings.xml b/ZDBMS/BMS_CC/.settings/language.settings.xml new file mode 100644 index 0000000..d15ddd3 --- /dev/null +++ b/ZDBMS/BMS_CC/.settings/language.settings.xml @@ -0,0 +1,14 @@ + + + + + + + + + + + + + + diff --git a/ZDBMS/BMS_CC/.template b/ZDBMS/BMS_CC/.template new file mode 100644 index 0000000..eefacb7 --- /dev/null +++ b/ZDBMS/BMS_CC/.template @@ -0,0 +1,17 @@ +Mcu Type=CH32L10x +Address=0x08000000 +Target Path=obj/BMS_CC.hex +Erase All=true +Program=true +Verify=true +Reset=true + +Vendor=WCH +Link=WCH-Link +Toolchain=RISC-V +Series=CH32L103 +MCU=CH32L103C8T6 +Description=Website: https://www.wch.cn/products/CH32L103.html?\nROM(byte): 64K, SRAM(byte): 20K, CHIP PINS: 48, GPIO PORTS: 37.\nCH32L103 is an industrial-grade low-power general purpose microcontroller based on Highland Barley RISC-V core design. The CH32L103 has built-in USB and PD PHY, support PDUSB, including USB Host host and USB Device device function, USB PD and type C fast charge function, built-in low power timer, It provides a set of OPA operation amplifier, 3 sets of CMP voltage comparators, 4 sets of USART serial ports, 2 I2C interfaces, 2 SPI interfaces, 1 set of CAN interfaces, multiple sets of timers, 12-bit ADC, 10 Touchkeys and other peripheral resources. + +PeripheralVersion=1.4 + diff --git a/ZDBMS/BMS_CC/BMS_CC.launch b/ZDBMS/BMS_CC/BMS_CC.launch new file mode 100644 index 0000000..f27e1cf --- /dev/null +++ b/ZDBMS/BMS_CC/BMS_CC.launch @@ -0,0 +1,61 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/ZDBMS/BMS_CC/BMS_CC.wvproj b/ZDBMS/BMS_CC/BMS_CC.wvproj new file mode 100644 index 0000000..603c784 --- /dev/null +++ b/ZDBMS/BMS_CC/BMS_CC.wvproj @@ -0,0 +1 @@ +⿷K<#6+03寑\p宬繌 vr桲潤5ぃrT縼卪JYi_脢+Oo7立=2潑à11;D,Lu猏O9拸;8糫Н縺琡:愧砵;玦(籊J$_帊瀒獌璸N1糠0徘翀>廣`)hsmv:8㎜Q焩${G穂 7灮羦N*b#{璳崅嵕ry痘盝,瑵op \ No newline at end of file diff --git a/ZDBMS/BMS_CC/Core/core_riscv.c b/ZDBMS/BMS_CC/Core/core_riscv.c new file mode 100644 index 0000000..d7d416d --- /dev/null +++ b/ZDBMS/BMS_CC/Core/core_riscv.c @@ -0,0 +1,306 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : core_riscv.c + * Author : WCH + * Version : V1.0.0 + * Date : 2023/11/11 + * Description : RISC-V V4 Core Peripheral Access Layer Source File for CH32L103 + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#include + +/* define compiler specific symbols */ +#if defined ( __CC_ARM ) + #define __ASM __asm /* asm keyword for ARM Compiler */ + #define __INLINE __inline /* inline keyword for ARM Compiler */ + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /* asm keyword for IAR Compiler */ + #define __INLINE inline /* inline keyword for IAR Compiler. Only avaiable in High optimization mode */ + +#elif defined ( __GNUC__ ) + #define __ASM __asm /* asm keyword for GNU Compiler */ + #define __INLINE inline /* inline keyword for GNU Compiler */ + +#elif defined ( __TASKING__ ) + #define __ASM __asm /* asm keyword for TASKING Compiler */ + #define __INLINE inline /* inline keyword for TASKING Compiler */ + +#endif + + + +/********************************************************************* + * @fn __get_MSTATUS + * + * @brief Return the Machine Status Register + * + * @return mstatus value + */ +uint32_t __get_MSTATUS(void) +{ + uint32_t result; + + __ASM volatile ( "csrr %0," "mstatus" : "=r" (result) ); + return (result); +} + +/********************************************************************* + * @fn __set_MSTATUS + * + * @brief Set the Machine Status Register + * + * @param value - set mstatus value + * + * @return none + */ +void __set_MSTATUS(uint32_t value) +{ + __ASM volatile ("csrw mstatus, %0" : : "r" (value) ); +} + +/********************************************************************* + * @fn __get_MISA + * + * @brief Return the Machine ISA Register + * + * @return misa value + */ +uint32_t __get_MISA(void) +{ + uint32_t result; + + __ASM volatile ( "csrr %0," "misa" : "=r" (result) ); + return (result); +} + +/********************************************************************* + * @fn __set_MISA + * + * @brief Set the Machine ISA Register + * + * @param value - set misa value + * + * @return none + */ +void __set_MISA(uint32_t value) +{ + __ASM volatile ("csrw misa, %0" : : "r" (value) ); +} + +/********************************************************************* + * @fn __get_MTVEC + * + * @brief Return the Machine Trap-Vector Base-Address Register + * + * @return mtvec value + */ +uint32_t __get_MTVEC(void) +{ + uint32_t result; + + __ASM volatile ( "csrr %0," "mtvec" : "=r" (result) ); + return (result); +} + +/********************************************************************* + * @fn __set_MTVEC + * + * @brief Set the Machine Trap-Vector Base-Address Register + * + * @param value - set mtvec value + * + * @return none + */ +void __set_MTVEC(uint32_t value) +{ + __ASM volatile ("csrw mtvec, %0" : : "r" (value) ); +} + +/********************************************************************* + * @fn __get_MSCRATCH + * + * @brief Return the Machine Seratch Register + * + * @return mscratch value + */ +uint32_t __get_MSCRATCH(void) +{ + uint32_t result; + + __ASM volatile ( "csrr %0," "mscratch" : "=r" (result) ); + return (result); +} + +/********************************************************************* + * @fn __set_MSCRATCH + * + * @brief Set the Machine Seratch Register + * + * @param value - set mscratch value + * + * @return none + */ +void __set_MSCRATCH(uint32_t value) +{ + __ASM volatile ("csrw mscratch, %0" : : "r" (value) ); +} + +/********************************************************************* + * @fn __get_MEPC + * + * @brief Return the Machine Exception Program Register + * + * @return mepc value + */ +uint32_t __get_MEPC(void) +{ + uint32_t result; + + __ASM volatile ( "csrr %0," "mepc" : "=r" (result) ); + return (result); +} + +/********************************************************************* + * @fn __set_MEPC + * + * @brief Set the Machine Exception Program Register + * + * @return mepc value + */ +void __set_MEPC(uint32_t value) +{ + __ASM volatile ("csrw mepc, %0" : : "r" (value) ); +} + +/********************************************************************* + * @fn __get_MCAUSE + * + * @brief Return the Machine Cause Register + * + * @return mcause value + */ +uint32_t __get_MCAUSE(void) +{ + uint32_t result; + + __ASM volatile ( "csrr %0," "mcause" : "=r" (result) ); + return (result); +} + +/********************************************************************* + * @fn __set_MEPC + * + * @brief Set the Machine Cause Register + * + * @return mcause value + */ +void __set_MCAUSE(uint32_t value) +{ + __ASM volatile ("csrw mcause, %0" : : "r" (value) ); +} + +/********************************************************************* + * @fn __get_MTVAL + * + * @brief Return the Machine Trap Value Register + * + * @return mtval value + */ +uint32_t __get_MTVAL(void) +{ + uint32_t result; + + __ASM volatile ( "csrr %0," "mtval" : "=r" (result) ); + return (result); +} + +/********************************************************************* + * @fn __set_MTVAL + * + * @brief Set the Machine Trap Value Register + * + * @return mtval value + */ +void __set_MTVAL(uint32_t value) +{ + __ASM volatile ("csrw mtval, %0" : : "r" (value) ); +} + +/********************************************************************* + * @fn __get_MVENDORID + * + * @brief Return Vendor ID Register + * + * @return mvendorid value + */ +uint32_t __get_MVENDORID(void) +{ + uint32_t result; + + __ASM volatile ( "csrr %0," "mvendorid" : "=r" (result) ); + return (result); +} + +/********************************************************************* + * @fn __get_MARCHID + * + * @brief Return Machine Architecture ID Register + * + * @return marchid value + */ +uint32_t __get_MARCHID(void) +{ + uint32_t result; + + __ASM volatile ( "csrr %0," "marchid" : "=r" (result) ); + return (result); +} + +/********************************************************************* + * @fn __get_MIMPID + * + * @brief Return Machine Implementation ID Register + * + * @return mimpid value + */ +uint32_t __get_MIMPID(void) +{ + uint32_t result; + + __ASM volatile ( "csrr %0," "mimpid" : "=r" (result) ); + return (result); +} + +/********************************************************************* + * @fn __get_MHARTID + * + * @brief Return Hart ID Register + * + * @return mhartid value + */ +uint32_t __get_MHARTID(void) +{ + uint32_t result; + + __ASM volatile ( "csrr %0," "mhartid" : "=r" (result) ); + return (result); +} + +/********************************************************************* + * @fn __get_SP + * + * @brief Return SP Register + * + * @return SP value + */ +uint32_t __get_SP(void) +{ + uint32_t result; + + __ASM volatile ( "mv %0," "sp" : "=r"(result) : ); + return (result); +} + diff --git a/ZDBMS/BMS_CC/Core/core_riscv.h b/ZDBMS/BMS_CC/Core/core_riscv.h new file mode 100644 index 0000000..46c433c --- /dev/null +++ b/ZDBMS/BMS_CC/Core/core_riscv.h @@ -0,0 +1,585 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : core_riscv.h + * Author : WCH + * Version : V1.0.0 + * Date : 2023/12/26 + * Description : RISC-V V4 Core Peripheral Access Layer Header File for CH32L103 + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#ifndef __CORE_RISCV_H__ +#define __CORE_RISCV_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/* IO definitions */ +#ifdef __cplusplus + #define __I volatile /* defines 'read only' permissions */ +#else + #define __I volatile const /* defines 'read only' permissions */ +#endif +#define __O volatile /* defines 'write only' permissions */ +#define __IO volatile /* defines 'read / write' permissions */ + + +typedef __I uint64_t vuc64; /* Read Only */ +typedef __I uint32_t vuc32; /* Read Only */ +typedef __I uint16_t vuc16; /* Read Only */ +typedef __I uint8_t vuc8; /* Read Only */ + +typedef const uint64_t uc64; /* Read Only */ +typedef const uint32_t uc32; /* Read Only */ +typedef const uint16_t uc16; /* Read Only */ +typedef const uint8_t uc8; /* Read Only */ + +typedef __I int64_t vsc64; /* Read Only */ +typedef __I int32_t vsc32; /* Read Only */ +typedef __I int16_t vsc16; /* Read Only */ +typedef __I int8_t vsc8; /* Read Only */ + +typedef const int64_t sc64; /* Read Only */ +typedef const int32_t sc32; /* Read Only */ +typedef const int16_t sc16; /* Read Only */ +typedef const int8_t sc8; /* Read Only */ + +typedef __IO uint64_t vu64; +typedef __IO uint32_t vu32; +typedef __IO uint16_t vu16; +typedef __IO uint8_t vu8; + +typedef uint64_t u64; +typedef uint32_t u32; +typedef uint16_t u16; +typedef uint8_t u8; + +typedef __IO int64_t vs64; +typedef __IO int32_t vs32; +typedef __IO int16_t vs16; +typedef __IO int8_t vs8; + +typedef int64_t s64; +typedef int32_t s32; +typedef int16_t s16; +typedef int8_t s8; + +typedef enum {NoREADY = 0, READY = !NoREADY} ErrorStatus; + +typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState; + +typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus; + +#define RV_STATIC_INLINE static inline + +/* memory mapped structure for Program Fast Interrupt Controller (PFIC) */ +typedef struct{ + __I uint32_t ISR[8]; + __I uint32_t IPR[8]; + __IO uint32_t ITHRESDR; + __IO uint32_t RESERVED; + __IO uint32_t CFGR; + __I uint32_t GISR; + __IO uint8_t VTFIDR[4]; + uint8_t RESERVED0[12]; + __IO uint32_t VTFADDR[4]; + uint8_t RESERVED1[0x90]; + __O uint32_t IENR[8]; + uint8_t RESERVED2[0x60]; + __O uint32_t IRER[8]; + uint8_t RESERVED3[0x60]; + __O uint32_t IPSR[8]; + uint8_t RESERVED4[0x60]; + __O uint32_t IPRR[8]; + uint8_t RESERVED5[0x60]; + __IO uint32_t IACTR[8]; + uint8_t RESERVED6[0xE0]; + __IO uint8_t IPRIOR[256]; + uint8_t RESERVED7[0x810]; + __IO uint32_t SCTLR; +}PFIC_Type; + +/* memory mapped structure for SysTick */ +typedef struct +{ + __IO uint32_t CTLR; + __IO uint32_t SR; + __IO uint64_t CNT; + __IO uint64_t CMP; +}SysTick_Type; + + +#define PFIC ((PFIC_Type *) 0xE000E000) +#define NVIC PFIC +#define NVIC_KEY1 ((uint32_t)0xFA050000) +#define NVIC_KEY2 ((uint32_t)0xBCAF0000) +#define NVIC_KEY3 ((uint32_t)0xBEEF0000) +#define SysTick ((SysTick_Type *) 0xE000F000) + + +/********************************************************************* + * @fn __enable_irq + * + * @brief Enable Global Interrupt + * + * @return none + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE void __enable_irq() +{ + __asm volatile ("csrs 0x800, %0" : : "r" (0x88) ); +} + +/********************************************************************* + * @fn __disable_irq + * + * @brief Disable Global Interrupt + * + * @return none + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE void __disable_irq() +{ + __asm volatile ("csrc 0x800, %0" : : "r" (0x88) ); +} + +/********************************************************************* + * @fn __NOP + * + * @brief nop + * + * @return none + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE void __NOP() +{ + __asm volatile ("nop"); +} + +/********************************************************************* + * @fn NVIC_EnableIRQ + * + * @brief Disable Interrupt + * + * @param IRQn - Interrupt Numbers + * + * @return none + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ + NVIC->IENR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); +} + +/********************************************************************* + * @fn NVIC_DisableIRQ + * + * @brief Disable Interrupt + * + * @param IRQn - Interrupt Numbers + * + * @return none + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->IRER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); +} + +/********************************************************************* + * @fn NVIC_GetStatusIRQ + * + * @brief Get Interrupt Enable State + * + * @param IRQn - Interrupt Numbers + * + * @return 1 - Interrupt Pending Enable + * 0 - Interrupt Pending Disable + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE uint32_t NVIC_GetStatusIRQ(IRQn_Type IRQn) +{ + return((uint32_t) ((NVIC->ISR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); +} + +/********************************************************************* + * @fn NVIC_GetPendingIRQ + * + * @brief Get Interrupt Pending State + * + * @param IRQn - Interrupt Numbers + * + * @return 1 - Interrupt Pending Enable + * 0 - Interrupt Pending Disable + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t) ((NVIC->IPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); +} + +/********************************************************************* + * @fn NVIC_SetPendingIRQ + * + * @brief Set Interrupt Pending + * + * @param IRQn - Interrupt Numbers + * + * @return none + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->IPSR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); +} + +/********************************************************************* + * @fn NVIC_ClearPendingIRQ + * + * @brief Clear Interrupt Pending + * + * @param IRQn - Interrupt Numbers + * + * @return none + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->IPRR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); +} + +/********************************************************************* + * @fn NVIC_GetActive + * + * @brief Get Interrupt Active State + * + * @param IRQn - Interrupt Numbers + * + * @return 1 - Interrupt Active + * 0 - Interrupt No Active + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) +{ + return((uint32_t)((NVIC->IACTR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); +} + +/********************************************************************* + * @fn NVIC_SetPriority + * + * @brief Set Interrupt Priority + * + * @param IRQn - Interrupt Numbers + * interrupt nesting enable(CSR-0x804 bit1 = 1) + * priority - bit[7] - Preemption Priority + * bit[6:5] - Sub priority + * bit[4:0] - Reserve + * interrupt nesting disable(CSR-0x804 bit1 = 0) + * priority - bit[7:5] - Sub priority + * bit[4:0] - Reserve + * + * @return none + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint8_t priority) +{ + NVIC->IPRIOR[(uint32_t)(IRQn)] = priority; +} + +/********************************************************************* + * @fn __WFI + * + * @brief Wait for Interrupt + * + * @return none + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE void __WFI(void) +{ + NVIC->SCTLR &= ~(1<<3); // wfi + asm volatile ("wfi"); +} + +/********************************************************************* + * @fn _SEV + * + * @brief Set Event + * + * @return none + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE void _SEV(void) +{ + uint32_t t; + + t = NVIC->SCTLR; + NVIC->SCTLR |= (1<<3)|(1<<5); + NVIC->SCTLR = (NVIC->SCTLR & ~(1<<5)) | ( t & (1<<5)); +} + +/********************************************************************* + * @fn _WFE + * + * @brief Wait for Events + * + * @return none + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE void _WFE(void) +{ + NVIC->SCTLR |= (1<<3); + asm volatile ("wfi"); +} + +/********************************************************************* + * @fn __WFE + * + * @brief Wait for Events + * + * @return none + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE void __WFE(void) +{ + _SEV(); + _WFE(); + _WFE(); +} + +/********************************************************************* + * @fn SetVTFIRQ + * + * @brief Set VTF Interrupt + * + * @param addr - VTF interrupt service function base address. + * IRQn - Interrupt Numbers + * num - VTF Interrupt Numbers + * NewState - DISABLE or ENABLE + * + * @return none + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE void SetVTFIRQ(uint32_t addr, IRQn_Type IRQn, uint8_t num, FunctionalState NewState) +{ + if(num > 3) return ; + + if (NewState != DISABLE) + { + NVIC->VTFIDR[num] = IRQn; + NVIC->VTFADDR[num] = ((addr&0xFFFFFFFE)|0x1); + } + else + { + NVIC->VTFIDR[num] = IRQn; + NVIC->VTFADDR[num] = ((addr&0xFFFFFFFE)&(~0x1)); + } +} + +/********************************************************************* + * @fn NVIC_SystemReset + * + * @brief Initiate a system reset request + * + * @return none + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE void NVIC_SystemReset(void) +{ + NVIC->CFGR = NVIC_KEY3|(1<<7); +} + +/********************************************************************* + * @fn __AMOADD_W + * + * @brief Atomic Add with 32bit value + * Atomically ADD 32bit value with value in memory using amoadd.d. + * + * @param addr - Address pointer to data, address need to be 4byte aligned + * value - value to be ADDed + * + * @return return memory value + add value + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE int32_t __AMOADD_W(volatile int32_t *addr, int32_t value) +{ + int32_t result; + + __asm volatile ("amoadd.w %0, %2, %1" : \ + "=r"(result), "+A"(*addr) : "r"(value) : "memory"); + return *addr; +} + +/********************************************************************* + * @fn __AMOAND_W + * + * @brief Atomic And with 32bit value + * Atomically AND 32bit value with value in memory using amoand.d. + * + * @param addr - Address pointer to data, address need to be 4byte aligned + * value - value to be ANDed + * + * @return return memory value & and value + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE int32_t __AMOAND_W(volatile int32_t *addr, int32_t value) +{ + int32_t result; + + __asm volatile ("amoand.w %0, %2, %1" : \ + "=r"(result), "+A"(*addr) : "r"(value) : "memory"); + return *addr; +} + +/********************************************************************* + * @fn __AMOMAX_W + * + * @brief Atomic signed MAX with 32bit value + * Atomically signed max compare 32bit value with value in memory using amomax.d. + * + * @param addr - Address pointer to data, address need to be 4byte aligned + * value - value to be compared + * + * @return the bigger value + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE int32_t __AMOMAX_W(volatile int32_t *addr, int32_t value) +{ + int32_t result; + + __asm volatile ("amomax.w %0, %2, %1" : \ + "=r"(result), "+A"(*addr) : "r"(value) : "memory"); + return *addr; +} + +/********************************************************************* + * @fn __AMOMAXU_W + * + * @brief Atomic unsigned MAX with 32bit value + * Atomically unsigned max compare 32bit value with value in memory using amomaxu.d. + * + * @param addr - Address pointer to data, address need to be 4byte aligned + * value - value to be compared + * + * @return return the bigger value + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE uint32_t __AMOMAXU_W(volatile uint32_t *addr, uint32_t value) +{ + uint32_t result; + + __asm volatile ("amomaxu.w %0, %2, %1" : \ + "=r"(result), "+A"(*addr) : "r"(value) : "memory"); + return *addr; +} + +/********************************************************************* + * @fn __AMOMIN_W + * + * @brief Atomic signed MIN with 32bit value + * Atomically signed min compare 32bit value with value in memory using amomin.d. + * + * @param addr - Address pointer to data, address need to be 4byte aligned + * value - value to be compared + * + * @return the smaller value + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE int32_t __AMOMIN_W(volatile int32_t *addr, int32_t value) +{ + int32_t result; + + __asm volatile ("amomin.w %0, %2, %1" : \ + "=r"(result), "+A"(*addr) : "r"(value) : "memory"); + return *addr; +} + +/********************************************************************* + * @fn __AMOMINU_W + * + * @brief Atomic unsigned MIN with 32bit value + * Atomically unsigned min compare 32bit value with value in memory using amominu.d. + * + * @param addr - Address pointer to data, address need to be 4byte aligned + * value - value to be compared + * + * @return the smaller value + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE uint32_t __AMOMINU_W(volatile uint32_t *addr, uint32_t value) +{ + uint32_t result; + + __asm volatile ("amominu.w %0, %2, %1" : \ + "=r"(result), "+A"(*addr) : "r"(value) : "memory"); + return *addr; +} + +/********************************************************************* + * @fn __AMOOR_W + * + * @brief Atomic OR with 32bit value + * Atomically OR 32bit value with value in memory using amoor.d. + * + * @param addr - Address pointer to data, address need to be 4byte aligned + * value - value to be ORed + * + * @return return memory value | and value + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE int32_t __AMOOR_W(volatile int32_t *addr, int32_t value) +{ + int32_t result; + + __asm volatile ("amoor.w %0, %2, %1" : \ + "=r"(result), "+A"(*addr) : "r"(value) : "memory"); + return *addr; +} + +/********************************************************************* + * @fn __AMOSWAP_W + * + * @brief Atomically swap new 32bit value into memory using amoswap.d. + * + * @param addr - Address pointer to data, address need to be 4byte aligned + * newval - New value to be stored into the address + * + * @return return the original value in memory + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE uint32_t __AMOSWAP_W(volatile uint32_t *addr, uint32_t newval) +{ + uint32_t result; + + __asm volatile ("amoswap.w %0, %2, %1" : \ + "=r"(result), "+A"(*addr) : "r"(newval) : "memory"); + return result; +} + +/********************************************************************* + * @fn __AMOXOR_W + * + * @brief Atomic XOR with 32bit value + * Atomically XOR 32bit value with value in memory using amoxor.d. + * + * @param addr - Address pointer to data, address need to be 4byte aligned + * value - value to be XORed + * + * @return return memory value ^ and value + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE int32_t __AMOXOR_W(volatile int32_t *addr, int32_t value) +{ + int32_t result; + + __asm volatile ("amoxor.w %0, %2, %1" : \ + "=r"(result), "+A"(*addr) : "r"(value) : "memory"); + return *addr; +} + +/* Core_Exported_Functions */ +extern uint32_t __get_MSTATUS(void); +extern void __set_MSTATUS(uint32_t value); +extern uint32_t __get_MISA(void); +extern void __set_MISA(uint32_t value); +extern uint32_t __get_MTVEC(void); +extern void __set_MTVEC(uint32_t value); +extern uint32_t __get_MSCRATCH(void); +extern void __set_MSCRATCH(uint32_t value); +extern uint32_t __get_MEPC(void); +extern void __set_MEPC(uint32_t value); +extern uint32_t __get_MCAUSE(void); +extern void __set_MCAUSE(uint32_t value); +extern uint32_t __get_MTVAL(void); +extern void __set_MTVAL(uint32_t value); +extern uint32_t __get_MVENDORID(void); +extern uint32_t __get_MARCHID(void); +extern uint32_t __get_MIMPID(void); +extern uint32_t __get_MHARTID(void); +extern uint32_t __get_SP(void); + +#ifdef __cplusplus +} +#endif + +#endif + + + + + diff --git a/ZDBMS/BMS_CC/Debug/debug.c b/ZDBMS/BMS_CC/Debug/debug.c new file mode 100644 index 0000000..7643334 --- /dev/null +++ b/ZDBMS/BMS_CC/Debug/debug.c @@ -0,0 +1,192 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : debug.c + * Author : WCH + * Version : V1.0.0 + * Date : 2023/07/08 + * Description : This file contains all the functions prototypes for UART + * Printf , Delay functions. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#include "debug.h" + +static uint16_t p_us = 0; +static uint16_t p_ms = 0; +/********************************************************************* + * @fn Delay_Init + * + * @brief Initializes Delay Funcation. + * + * @return none + */ +void Delay_Init(void) +{ + p_us = SystemCoreClock / 8000; + p_ms = (uint16_t)p_us * 1; +} + +/********************************************************************* + * @fn Delay_Us + * + * @brief Microsecond Delay Time. + * + * @param n - Microsecond number. + * + * @return None + */ +void Delay_Us(uint32_t n) +{ + uint32_t i; + + SysTick->SR &= ~(1 << 0); + i = (uint32_t)(n * p_us)/1000; + + SysTick->CMP = i; + SysTick->CTLR |= (1 << 4); + SysTick->CTLR |= (1 << 5) | (1 << 0); + + while((SysTick->SR & (1 << 0)) != (1 << 0)); + SysTick->CTLR &= ~(1 << 0); +} + +/********************************************************************* + * @fn Delay_Ms + * + * @brief Millisecond Delay Time. + * + * @param n - Millisecond number. + * + * @return None + */ +void Delay_Ms(uint32_t n) +{ + uint32_t i; + + SysTick->SR &= ~(1 << 0); + i = (uint32_t)n * p_ms; + + SysTick->CMP = i; + SysTick->CTLR |= (1 << 4); + SysTick->CTLR |= (1 << 5) | (1 << 0); + + while((SysTick->SR & (1 << 0)) != (1 << 0)); + SysTick->CTLR &= ~(1 << 0); +} + +/********************************************************************* + * @fn USART_Printf_Init + * + * @brief Initializes the USARTx peripheral. + * + * @param baudrate - USART communication baud rate. + * + * @return None + */ +void USART_Printf_Init(uint32_t baudrate) +{ + GPIO_InitTypeDef GPIO_InitStructure; + USART_InitTypeDef USART_InitStructure; + +#if(DEBUG == DEBUG_UART1) + RCC_PB2PeriphClockCmd(RCC_PB2Periph_USART1 | RCC_PB2Periph_GPIOA, ENABLE); + + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_9; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP; + GPIO_Init(GPIOA, &GPIO_InitStructure); + +#elif(DEBUG == DEBUG_UART2) + RCC_PB1PeriphClockCmd(RCC_PB1Periph_USART2, ENABLE); + RCC_PB2PeriphClockCmd(RCC_PB2Periph_GPIOA, ENABLE); + + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP; + GPIO_Init(GPIOA, &GPIO_InitStructure); + +#elif(DEBUG == DEBUG_UART3) + RCC_PB1PeriphClockCmd(RCC_PB1Periph_USART3, ENABLE); + RCC_PB2PeriphClockCmd(RCC_PB2Periph_GPIOB, ENABLE); + + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_10; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP; + GPIO_Init(GPIOB, &GPIO_InitStructure); + +#endif + + USART_InitStructure.USART_BaudRate = baudrate; + USART_InitStructure.USART_WordLength = USART_WordLength_8b; + USART_InitStructure.USART_StopBits = USART_StopBits_1; + USART_InitStructure.USART_Parity = USART_Parity_No; + USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None; + USART_InitStructure.USART_Mode = USART_Mode_Tx; + +#if(DEBUG == DEBUG_UART1) + USART_Init(USART1, &USART_InitStructure); + USART_Cmd(USART1, ENABLE); + +#elif(DEBUG == DEBUG_UART2) + USART_Init(USART2, &USART_InitStructure); + USART_Cmd(USART2, ENABLE); + +#elif(DEBUG == DEBUG_UART3) + USART_Init(USART3, &USART_InitStructure); + USART_Cmd(USART3, ENABLE); + +#endif +} + +/********************************************************************* + * @fn _write + * + * @brief Support Printf Function + * + * @param *buf - UART send Data. + * size - Data length + * + * @return size: Data length + */ +__attribute__((used)) +int _write(int fd, char *buf, int size) +{ + int i; + + for(i = 0; i < size; i++){ +#if(DEBUG == DEBUG_UART1) + while(USART_GetFlagStatus(USART1, USART_FLAG_TC) == RESET); + USART_SendData(USART1, *buf++); +#elif(DEBUG == DEBUG_UART2) + while(USART_GetFlagStatus(USART2, USART_FLAG_TC) == RESET); + USART_SendData(USART2, *buf++); +#elif(DEBUG == DEBUG_UART3) + while(USART_GetFlagStatus(USART3, USART_FLAG_TC) == RESET); + USART_SendData(USART3, *buf++); +#endif + } + + return size; +} + +/********************************************************************* + * @fn _sbrk + * + * @brief Change the spatial position of data segment. + * + * @return size: Data length + */ +__attribute__((used)) +void *_sbrk(ptrdiff_t incr) +{ + extern char _end[]; + extern char _heap_end[]; + static char *curbrk = _end; + + if ((curbrk + incr < _end) || (curbrk + incr > _heap_end)) + return NULL - 1; + + curbrk += incr; + return curbrk - incr; +} diff --git a/ZDBMS/BMS_CC/Debug/debug.h b/ZDBMS/BMS_CC/Debug/debug.h new file mode 100644 index 0000000..db1175d --- /dev/null +++ b/ZDBMS/BMS_CC/Debug/debug.h @@ -0,0 +1,54 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : debug.h + * Author : WCH + * Version : V1.0.0 + * Date : 2023/11/06 + * Description : This file contains all the functions prototypes for UART + * Printf , Delay functions. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#ifndef __DEBUG_H +#define __DEBUG_H + +#include "stdio.h" +#include "ch32l103.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* UART Printf Definition */ +#define DEBUG_UART1 1 +#define DEBUG_UART2 2 +#define DEBUG_UART3 3 + +/* DEBUG UATR Definition */ +#ifndef DEBUG +#define DEBUG DEBUG_UART1 +#endif + +extern uint32_t OPA_Trim; +extern uint16_t ADC_Trim; +extern uint32_t TS_Val; +extern uint32_t CHIPID; +extern uint16_t USBPD_CFG; + +void Delay_Init(void); +void Delay_Us(uint32_t n); +void Delay_Ms(uint32_t n); +void USART_Printf_Init(uint32_t baudrate); + +#if(DEBUG) + #define PRINT(format, ...) printf(format, ##__VA_ARGS__) +#else + #define PRINT(X...) +#endif + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/ZDBMS/BMS_CC/Ld/Link.ld b/ZDBMS/BMS_CC/Ld/Link.ld new file mode 100644 index 0000000..8825ecf --- /dev/null +++ b/ZDBMS/BMS_CC/Ld/Link.ld @@ -0,0 +1 @@ +ENTRY( _start ) __stack_size = 2048; PROVIDE( _stack_size = __stack_size ); MEMORY { FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 64K RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 20K } SECTIONS { .init : { _sinit = .; . = ALIGN(4); KEEP(*(SORT_NONE(.init))) . = ALIGN(4); _einit = .; } >FLASH AT>FLASH .vector : { *(.vector); . = ALIGN(64); } >FLASH AT>FLASH .text : { . = ALIGN(4); *(.text) *(.text.*) *(.rodata) *(.rodata*) *(.gnu.linkonce.t.*) . = ALIGN(4); } >FLASH AT>FLASH .fini : { KEEP(*(SORT_NONE(.fini))) . = ALIGN(4); } >FLASH AT>FLASH PROVIDE( _etext = . ); PROVIDE( _eitcm = . ); .preinit_array : { PROVIDE_HIDDEN (__preinit_array_start = .); KEEP (*(.preinit_array)) PROVIDE_HIDDEN (__preinit_array_end = .); } >FLASH AT>FLASH .init_array : { PROVIDE_HIDDEN (__init_array_start = .); KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors)) PROVIDE_HIDDEN (__init_array_end = .); } >FLASH AT>FLASH .fini_array : { PROVIDE_HIDDEN (__fini_array_start = .); KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*))) KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors)) PROVIDE_HIDDEN (__fini_array_end = .); } >FLASH AT>FLASH .ctors : { /* gcc uses crtbegin.o to find the start of the constructors, so we make sure it is first. Because this is a wildcard, it doesn't matter if the user does not actually link against crtbegin.o; the linker won't look for a file to match a wildcard. The wildcard also means that it doesn't matter which directory crtbegin.o is in. */ KEEP (*crtbegin.o(.ctors)) KEEP (*crtbegin?.o(.ctors)) /* We don't want to include the .ctor section from the crtend.o file until after the sorted ctors. The .ctor section from the crtend file contains the end of ctors marker and it must be last */ KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors)) KEEP (*(SORT(.ctors.*))) KEEP (*(.ctors)) } >FLASH AT>FLASH .dtors : { KEEP (*crtbegin.o(.dtors)) KEEP (*crtbegin?.o(.dtors)) KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors)) KEEP (*(SORT(.dtors.*))) KEEP (*(.dtors)) } >FLASH AT>FLASH .dalign : { . = ALIGN(4); PROVIDE(_data_vma = .); } >RAM AT>FLASH .dlalign : { . = ALIGN(4); PROVIDE(_data_lma = .); } >FLASH AT>FLASH .data : { *(.gnu.linkonce.r.*) *(.data .data.*) *(.gnu.linkonce.d.*) . = ALIGN(8); PROVIDE( __global_pointer$ = . + 0x800 ); *(.sdata .sdata.*) *(.sdata2.*) *(.gnu.linkonce.s.*) . = ALIGN(8); *(.srodata.cst16) *(.srodata.cst8) *(.srodata.cst4) *(.srodata.cst2) *(.srodata .srodata.*) . = ALIGN(4); PROVIDE( _edata = .); } >RAM AT>FLASH .bss : { . = ALIGN(4); PROVIDE( _sbss = .); *(.sbss*) *(.gnu.linkonce.sb.*) *(.bss*) *(.gnu.linkonce.b.*) *(COMMON*) . = ALIGN(4); PROVIDE( _ebss = .); } >RAM AT>FLASH PROVIDE( _end = _ebss); PROVIDE( end = . ); .stack ORIGIN(RAM) + LENGTH(RAM) - __stack_size : { PROVIDE( _heap_end = . ); . = ALIGN(4); PROVIDE(_susrstack = . ); . = . + __stack_size; PROVIDE( _eusrstack = .); } >RAM } \ No newline at end of file diff --git a/ZDBMS/BMS_CC/Peripheral/inc/ch32l103.h b/ZDBMS/BMS_CC/Peripheral/inc/ch32l103.h new file mode 100644 index 0000000..11e21fc --- /dev/null +++ b/ZDBMS/BMS_CC/Peripheral/inc/ch32l103.h @@ -0,0 +1,4759 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32l103.h + * Author : WCH + * Version : V1.0.1 + * Date : 2025/01/08 + * Description : CH32L103 Device Peripheral Access Layer Header File. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#ifndef __CH32L103_H +#define __CH32L103_H + +#ifdef __cplusplus +extern "C" { +#endif + +#ifndef HSE_VALUE +#define HSE_VALUE ((uint32_t)8000000) /* Value of the External oscillator in Hz */ +#endif + +/* In the following line adjust the External High Speed oscillator (HSE) Startup Timeout value */ +#define HSE_STARTUP_TIMEOUT ((uint16_t)0x1000) /* Time out for HSE start up */ + +#define HSI_VALUE ((uint32_t)8000000) /* Value of the Internal oscillator in Hz */ + +#define HSI_LP_VALUE ((uint32_t)1000000) /* Value of the Internal oscillator in Hz for low power mode */ + +/* Standard Peripheral Library version number */ +#define __CH32L103_STDPERIPH_VERSION_MAIN (0x01) /* [15:8] main version */ +#define __CH32L103_STDPERIPH_VERSION_SUB (0x04) /* [7:0] sub version */ +#define __CH32L103_STDPERIPH_VERSION ((__CH32L103_STDPERIPH_VERSION_MAIN << 8)\ + |(__CH32L103_STDPERIPH_VERSION_SUB << 0)) + +/* Interrupt Number Definition, according to the selected device */ +typedef enum IRQn +{ + /****** RISC-V Processor Exceptions Numbers *******************************************************/ + NonMaskableInt_IRQn = 2, /* Non Maskable Interrupt */ + EXC_IRQn = 3, /* Exception Interrupt */ + Ecall_M_Mode_IRQn = 5, /* Ecall M Mode Interrupt */ + Ecall_U_Mode_IRQn = 8, /* Ecall U Mode Interrupt */ + Break_Point_IRQn = 9, /* Break Point Interrupt */ + SysTick_IRQn = 12, /* System timer Interrupt */ + Software_IRQn = 14, /* Software Interrupt */ + + /****** RISC-V specific Interrupt Numbers *********************************************************/ + WWDG_IRQn = 16, /* Window WatchDog Interrupt */ + PVD_IRQn = 17, /* PVD through EXTI Line detection Interrupt */ + TAMPER_IRQn = 18, /* Tamper Interrupt */ + RTC_IRQn = 19, /* RTC global Interrupt */ + FLASH_IRQn = 20, /* FLASH global Interrupt */ + RCC_IRQn = 21, /* RCC global Interrupt */ + EXTI0_IRQn = 22, /* EXTI Line0 Interrupt */ + EXTI1_IRQn = 23, /* EXTI Line1 Interrupt */ + EXTI2_IRQn = 24, /* EXTI Line2 Interrupt */ + EXTI3_IRQn = 25, /* EXTI Line3 Interrupt */ + EXTI4_IRQn = 26, /* EXTI Line4 Interrupt */ + DMA1_Channel1_IRQn = 27, /* DMA1 Channel 1 global Interrupt */ + DMA1_Channel2_IRQn = 28, /* DMA1 Channel 2 global Interrupt */ + DMA1_Channel3_IRQn = 29, /* DMA1 Channel 3 global Interrupt */ + DMA1_Channel4_IRQn = 30, /* DMA1 Channel 4 global Interrupt */ + DMA1_Channel5_IRQn = 31, /* DMA1 Channel 5 global Interrupt */ + DMA1_Channel6_IRQn = 32, /* DMA1 Channel 6 global Interrupt */ + DMA1_Channel7_IRQn = 33, /* DMA1 Channel 7 global Interrupt */ + ADC_IRQn = 34, /* ADC1 global Interrupt */ + USB_HP_CAN1_TX_IRQn = 35, /* USB Device High Priority or CAN1 TX Interrupts */ + USB_LP_CAN1_RX0_IRQn = 36, /* USB Device Low Priority or CAN1 RX0 Interrupts */ + CAN1_RX1_IRQn = 37, /* CAN1 RX1 Interrupt */ + CAN1_SCE_IRQn = 38, /* CAN1 SCE Interrupt */ + EXTI9_5_IRQn = 39, /* External Line[9:5] Interrupts */ + TIM1_BRK_IRQn = 40, /* TIM1 Break Interrupt */ + TIM1_UP_IRQn = 41, /* TIM1 Update Interrupt */ + TIM1_TRG_COM_IRQn = 42, /* TIM1 Trigger and Commutation Interrupt */ + TIM1_CC_IRQn = 43, /* TIM1 Capture Compare Interrupt */ + TIM2_IRQn = 44, /* TIM2 global Interrupt */ + TIM3_IRQn = 45, /* TIM3 global Interrupt */ + TIM4_IRQn = 46, /* TIM4 global Interrupt */ + I2C1_EV_IRQn = 47, /* I2C1 Event Interrupt */ + I2C1_ER_IRQn = 48, /* I2C1 Error Interrupt */ + I2C2_EV_IRQn = 49, /* I2C2 Event Interrupt */ + I2C2_ER_IRQn = 50, /* I2C2 Error Interrupt */ + SPI1_IRQn = 51, /* SPI1 global Interrupt */ + SPI2_IRQn = 52, /* SPI2 global Interrupt */ + USART1_IRQn = 53, /* USART1 global Interrupt */ + USART2_IRQn = 54, /* USART2 global Interrupt */ + USART3_IRQn = 55, /* USART3 global Interrupt */ + EXTI15_10_IRQn = 56, /* External Line[15:10] Interrupts */ + RTCAlarm_IRQn = 57, /* RTC Alarm through EXTI Line Interrupt */ + LPTIMWakeUp_IRQn = 58, /* LPTIM WakeUp Interrupt */ + USBFS_IRQn = 59, /* USBFS global Interrupt */ + USBFSWakeUp_IRQn = 60, /* USBFS WakeUp Interrupt */ + USART4_IRQn = 61, /* USART4 global Interrupt */ + DMA1_Channel8_IRQn = 62, /* DMA1 Channel 8 global Interrupt */ + LPTIM_IRQn = 63, /* LPTIM global Interrupt */ + OPA_IRQn = 64, /* OPA global Interrupt */ + USBPD_IRQn = 65, /* USBPD global Interrupt */ + + USBPDWakeUp_IRQn = 67, /* USBPD WakeUp Interrupt */ + CMPWakeUp_IRQn = 68, /* CMP WakeUp Interrupt */ + +} IRQn_Type; + +#define HardFault_IRQn EXC_IRQn +#define ADC1_2_IRQn ADC_IRQn +#define SysTicK_IRQn SysTick_IRQn + +#include +#include "core_riscv.h" +#include "system_ch32l103.h" + +#define HSI_Value HSI_VALUE +#define HSE_Value HSE_VALUE +#define HSEStartUp_TimeOut HSE_STARTUP_TIMEOUT + +/* Analog to Digital Converter */ +typedef struct +{ + __IO uint32_t STATR; + __IO uint32_t CTLR1; + __IO uint32_t CTLR2; + __IO uint32_t SAMPTR1; + __IO uint32_t SAMPTR2; + __IO uint32_t IOFR1; + __IO uint32_t IOFR2; + __IO uint32_t IOFR3; + __IO uint32_t IOFR4; + __IO uint32_t WDHTR; + __IO uint32_t WDLTR; + __IO uint32_t RSQR1; + __IO uint32_t RSQR2; + __IO uint32_t RSQR3; + __IO uint32_t ISQR; + __IO uint32_t IDATAR1; + __IO uint32_t IDATAR2; + __IO uint32_t IDATAR3; + __IO uint32_t IDATAR4; + __IO uint32_t RDATAR; + __IO uint32_t CFG; +} ADC_TypeDef; + +/* Backup Registers */ +typedef struct +{ + uint32_t RESERVED0; + __IO uint16_t DATAR1; + uint16_t RESERVED1; + __IO uint16_t DATAR2; + uint16_t RESERVED2; + __IO uint16_t DATAR3; + uint16_t RESERVED3; + __IO uint16_t DATAR4; + uint16_t RESERVED4; + __IO uint16_t DATAR5; + uint16_t RESERVED5; + __IO uint16_t DATAR6; + uint16_t RESERVED6; + __IO uint16_t DATAR7; + uint16_t RESERVED7; + __IO uint16_t DATAR8; + uint16_t RESERVED8; + __IO uint16_t DATAR9; + uint16_t RESERVED9; + __IO uint16_t DATAR10; + uint16_t RESERVED10; + __IO uint16_t OCTLR; + uint16_t RESERVED11; + __IO uint16_t TPCTLR; + uint16_t RESERVED12; + __IO uint16_t TPCSR; + uint16_t RESERVED13; +} BKP_TypeDef; + +/* Controller Area Network TxMailBox */ +typedef struct +{ + __IO uint32_t TXMIR; + __IO uint32_t TXMDTR; + __IO uint32_t TXMDLR; + __IO uint32_t TXMDHR; +} CAN_TxMailBox_TypeDef; + +/* Controller Area Network FIFOMailBox */ +typedef struct +{ + __IO uint32_t RXMIR; + __IO uint32_t RXMDTR; + __IO uint32_t RXMDLR; + __IO uint32_t RXMDHR; +} CAN_FIFOMailBox_TypeDef; + +/* Controller Area Network FilterRegister */ +typedef struct +{ + __IO uint32_t FR1; + __IO uint32_t FR2; +} CAN_FilterRegister_TypeDef; + +/* Controller Area Network */ +typedef struct +{ + __IO uint32_t CTLR; + __IO uint32_t STATR; + __IO uint32_t TSTATR; + __IO uint32_t RFIFO0; + __IO uint32_t RFIFO1; + __IO uint32_t INTENR; + __IO uint32_t ERRSR; + __IO uint32_t BTIMR; + __IO uint32_t TTCTLR; + __IO uint32_t TTCNT; + __IO uint32_t TERR_CNT; + __IO uint32_t CANFD_CR; + __IO uint32_t CANFD_BTR; + __IO uint32_t CANFD_TDCT; + __IO uint32_t CANFD_PSR; + __IO uint32_t CANFD_DMA_T[3]; + __IO uint32_t CANFD_DMA_R[2]; + uint32_t RESERVED0[76]; + CAN_TxMailBox_TypeDef sTxMailBox[3]; + CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; + uint32_t RESERVED1[12]; + __IO uint32_t FCTLR; + __IO uint32_t FMCFGR; + uint32_t RESERVED2; + __IO uint32_t FSCFGR; + uint32_t RESERVED3; + __IO uint32_t FAFIFOR; + uint32_t RESERVED4; + __IO uint32_t FWR; + uint32_t RESERVED5[8]; + CAN_FilterRegister_TypeDef sFilterRegister[14]; +} CAN_TypeDef; + +/* CRC Calculation Unit */ +typedef struct +{ + __IO uint32_t DATAR; + __IO uint8_t IDATAR; + uint8_t RESERVED0; + uint16_t RESERVED1; + __IO uint32_t CTLR; +} CRC_TypeDef; + +/* DMA Channel Controller */ +typedef struct +{ + __IO uint32_t CFGR; + __IO uint32_t CNTR; + __IO uint32_t PADDR; + __IO uint32_t MADDR; +} DMA_Channel_TypeDef; + +/* DMA Controller */ +typedef struct +{ + __IO uint32_t INTFR; + __IO uint32_t INTFCR; +} DMA_TypeDef; + +/* External Interrupt/Event Controller */ +typedef struct +{ + __IO uint32_t INTENR; + __IO uint32_t EVENR; + __IO uint32_t RTENR; + __IO uint32_t FTENR; + __IO uint32_t SWIEVR; + __IO uint32_t INTFR; +} EXTI_TypeDef; + +/* FLASH Registers */ +typedef struct +{ + __IO uint32_t ACTLR; + __IO uint32_t KEYR; + __IO uint32_t OBKEYR; + __IO uint32_t STATR; + __IO uint32_t CTLR; + __IO uint32_t ADDR; + __IO uint32_t RESERVED; + __IO uint32_t OBR; + __IO uint32_t WPR; + __IO uint32_t MODEKEYR; +} FLASH_TypeDef; + +/* Option Bytes Registers */ +typedef struct +{ + __IO uint16_t RDPR; + __IO uint16_t USER; + __IO uint16_t Data0; + __IO uint16_t Data1; + __IO uint16_t WRPR0; + __IO uint16_t WRPR1; + __IO uint16_t WRPR2; + __IO uint16_t WRPR3; +} OB_TypeDef; + +/* General Purpose I/O */ +typedef struct +{ + __IO uint32_t CFGLR; + __IO uint32_t CFGHR; + __IO uint32_t INDR; + __IO uint32_t OUTDR; + __IO uint32_t BSHR; + __IO uint32_t BCR; + __IO uint32_t LCKR; +} GPIO_TypeDef; + +/* Alternate Function I/O */ +typedef struct +{ + __IO uint32_t ECR; + __IO uint32_t PCFR1; + __IO uint32_t EXTICR[4]; + __IO uint32_t CR; + __IO uint32_t PCFR2; +} AFIO_TypeDef; + +/* Inter Integrated Circuit Interface */ +typedef struct +{ + __IO uint16_t CTLR1; + uint16_t RESERVED0; + __IO uint16_t CTLR2; + uint16_t RESERVED1; + __IO uint16_t OADDR1; + uint16_t RESERVED2; + __IO uint16_t OADDR2; + uint16_t RESERVED3; + __IO uint16_t DATAR; + uint16_t RESERVED4; + __IO uint16_t STAR1; + uint16_t RESERVED5; + __IO uint16_t STAR2; + uint16_t RESERVED6; + __IO uint16_t CKCFGR; + uint16_t RESERVED7; + __IO uint16_t RTR; + uint16_t RESERVED8; +} I2C_TypeDef; + +/* Independent WatchDog */ +typedef struct +{ + __IO uint32_t CTLR; + __IO uint32_t PSCR; + __IO uint32_t RLDR; + __IO uint32_t STATR; +} IWDG_TypeDef; + +/* Power Control */ +typedef struct +{ + __IO uint32_t CTLR; + __IO uint32_t CSR; +} PWR_TypeDef; + +/* Reset and Clock Control */ +typedef struct +{ + __IO uint32_t CTLR; + __IO uint32_t CFGR0; + __IO uint32_t INTR; + __IO uint32_t PB2PRSTR; + __IO uint32_t PB1PRSTR; + __IO uint32_t HBPCENR; + __IO uint32_t PB2PCENR; + __IO uint32_t PB1PCENR; + __IO uint32_t BDCTLR; + __IO uint32_t RSTSCKR; + __IO uint32_t HBRSTR; +} RCC_TypeDef; + +/* Real-Time Clock */ +typedef struct +{ + __IO uint16_t CTLRH; + uint16_t RESERVED0; + __IO uint16_t CTLRL; + uint16_t RESERVED1; + __IO uint16_t PSCRH; + uint16_t RESERVED2; + __IO uint16_t PSCRL; + uint16_t RESERVED3; + __IO uint16_t DIVH; + uint16_t RESERVED4; + __IO uint16_t DIVL; + uint16_t RESERVED5; + __IO uint16_t CNTH; + uint16_t RESERVED6; + __IO uint16_t CNTL; + uint16_t RESERVED7; + __IO uint16_t ALRMH; + uint16_t RESERVED8; + __IO uint16_t ALRML; + uint16_t RESERVED9; +} RTC_TypeDef; + +/* Serial Peripheral Interface */ +typedef struct +{ + __IO uint16_t CTLR1; + uint16_t RESERVED0; + __IO uint16_t CTLR2; + uint16_t RESERVED1; + __IO uint16_t STATR; + uint16_t RESERVED2; + __IO uint16_t DATAR; + uint16_t RESERVED3; + __IO uint16_t CRCR; + uint16_t RESERVED4; + __IO uint16_t RCRCR; + uint16_t RESERVED5; + __IO uint16_t TCRCR; + uint16_t RESERVED6; + uint32_t RESERVED7; + uint32_t RESERVED8; + __IO uint16_t HSCR; + uint16_t RESERVED9; +} SPI_TypeDef; + +/* TIM */ +typedef struct +{ + __IO uint16_t CTLR1; + uint16_t RESERVED0; + __IO uint16_t CTLR2; + uint16_t RESERVED1; + __IO uint16_t SMCFGR; + uint16_t RESERVED2; + __IO uint16_t DMAINTENR; + uint16_t RESERVED3; + __IO uint16_t INTFR; + uint16_t RESERVED4; + __IO uint16_t SWEVGR; + uint16_t RESERVED5; + __IO uint16_t CHCTLR1; + uint16_t RESERVED6; + __IO uint16_t CHCTLR2; + uint16_t RESERVED7; + __IO uint16_t CCER; + uint16_t RESERVED8; + union + { + __IO uint32_t CNT_TIM4; + struct + { + __IO uint16_t CNT; + uint16_t RESERVED9; + }; + }; + __IO uint16_t PSC; + uint16_t RESERVED10; + union + { + __IO uint32_t ATRLR_TIM4; + struct + { + __IO uint16_t ATRLR; + uint16_t RESERVED11; + }; + }; + __IO uint16_t RPTCR; + uint16_t RESERVED12; + union + { + __IO uint32_t CH1CVR_TIM4; + + __IO uint32_t CH1CVR; + }; + union + { + __IO uint32_t CH2CVR_TIM4; + + __IO uint32_t CH2CVR; + }; + union + { + __IO uint32_t CH3CVR_TIM4; + + __IO uint32_t CH3CVR; + }; + union + { + __IO uint32_t CH4CVR_TIM4; + + __IO uint32_t CH4CVR; + }; + __IO uint16_t BDTR; + uint16_t RESERVED13; + __IO uint16_t DMACFGR; + uint16_t RESERVED14; + __IO uint32_t DMAADR; +} TIM_TypeDef; + +/* Universal Synchronous Asynchronous Receiver Transmitter */ +typedef struct +{ + __IO uint16_t STATR; + uint16_t RESERVED0; + __IO uint16_t DATAR; + uint16_t RESERVED1; + __IO uint16_t BRR; + uint16_t RESERVED2; + __IO uint16_t CTLR1; + uint16_t RESERVED3; + __IO uint16_t CTLR2; + uint16_t RESERVED4; + __IO uint16_t CTLR3; + uint16_t RESERVED5; + __IO uint16_t GPR; + uint16_t RESERVED6; +} USART_TypeDef; + +/* Window WatchDog */ +typedef struct +{ + __IO uint32_t CTLR; + __IO uint32_t CFGR; + __IO uint32_t STATR; +} WWDG_TypeDef; + +/* Enhanced Registers */ +typedef struct +{ + __IO uint32_t EXTEN_CTR; +} EXTEN_TypeDef; + +/* OPA Registers */ +typedef struct +{ + __IO uint16_t CFGR1; + __IO uint16_t CFGR2; + __IO uint32_t CTLR1; + __IO uint32_t CTLR2; + __IO uint32_t RESERVED0; + __IO uint32_t RESERVED1; + __IO uint32_t OPCMKEY; +} OPA_TypeDef; + +/* LPTIM Registers */ +typedef struct +{ + __IO uint32_t ISR; + __IO uint32_t ICR; + __IO uint32_t IER; + __IO uint32_t CFGR; + __IO uint32_t CR; + __IO uint16_t CMP; + uint16_t RESERVED0; + __IO uint16_t ARR; + uint16_t RESERVED1; + __IO uint16_t CNT; + uint16_t RESERVED2; +} LPTIM_TypeDef; + +/* PD Registers */ +typedef struct +{ + union + { + __IO uint32_t USBPD_CONFIG; + struct + { + __IO uint16_t CONFIG; + __IO uint16_t BMC_CLK_CNT; + }; + }; + union + { + __IO uint32_t USBPD_CONTROL; + struct + { + union + { + __IO uint16_t R16_CONTROL; + struct + { + __IO uint8_t CONTROL; + __IO uint8_t TX_SEL; + }; + }; + __IO uint16_t BMC_TX_SZ; + }; + }; + union + { + __IO uint32_t USBPD_STATUS; + struct + { + union + { + __IO uint16_t R16_STATUS; + struct + { + __IO uint8_t DATA_BUF; + __IO uint8_t STATUS; + }; + }; + __IO uint16_t BMC_BYTE_CNT; + }; + }; + union + { + __IO uint32_t USBPD_PORT; + struct + { + __IO uint16_t PORT_CC1; + __IO uint16_t PORT_CC2; + }; + }; + union + { + __IO uint32_t USBPD_DMA; + struct + { + __IO uint16_t DMA; + __IO uint16_t RESERVED; + }; + }; +} USBPD_TypeDef; + +/* USBFS Registers */ +typedef struct +{ + __IO uint8_t BASE_CTRL; + __IO uint8_t UDEV_CTRL; + __IO uint8_t INT_EN; + __IO uint8_t DEV_ADDR; + __IO uint8_t Reserve0; + __IO uint8_t MIS_ST; + __IO uint8_t INT_FG; + __IO uint8_t INT_ST; + __IO uint32_t RX_LEN; + __IO uint8_t UEP4_1_MOD; + __IO uint8_t UEP2_3_MOD; + __IO uint8_t UEP5_6_MOD; + __IO uint8_t UEP7_MOD; + __IO uint32_t UEP0_DMA; + __IO uint32_t UEP1_DMA; + __IO uint32_t UEP2_DMA; + __IO uint32_t UEP3_DMA; + __IO uint32_t UEP4_DMA; + __IO uint32_t UEP5_DMA; + __IO uint32_t UEP6_DMA; + __IO uint32_t UEP7_DMA; + __IO uint16_t UEP0_TX_LEN; + union{ + __IO uint16_t UEP0_CTRL; + struct{ + __IO uint8_t UEP0_TX_CTRL; + __IO uint8_t UEP0_RX_CTRL; + }; + }; + __IO uint16_t UEP1_TX_LEN; + union{ + __IO uint16_t UEP1_CTRL; + struct{ + __IO uint8_t UEP1_TX_CTRL; + __IO uint8_t UEP1_RX_CTRL; + }; + }; + __IO uint16_t UEP2_TX_LEN; + union{ + __IO uint16_t UEP2_CTRL; + struct{ + __IO uint8_t UEP2_TX_CTRL; + __IO uint8_t UEP2_RX_CTRL; + }; + }; + __IO uint16_t UEP3_TX_LEN; + union{ + __IO uint16_t UEP3_CTRL; + struct{ + __IO uint8_t UEP3_TX_CTRL; + __IO uint8_t UEP3_RX_CTRL; + }; + }; + __IO uint16_t UEP4_TX_LEN; + union{ + __IO uint16_t UEP4_CTRL; + struct{ + __IO uint8_t UEP4_TX_CTRL; + __IO uint8_t UEP4_RX_CTRL; + }; + }; + __IO uint16_t UEP5_TX_LEN; + union{ + __IO uint16_t UEP5_CTRL; + struct{ + __IO uint8_t UEP5_TX_CTRL; + __IO uint8_t UEP5_RX_CTRL; + }; + }; + __IO uint16_t UEP6_TX_LEN; + union{ + __IO uint16_t UEP6_CTRL; + struct{ + __IO uint8_t UEP6_TX_CTRL; + __IO uint8_t UEP6_RX_CTRL; + }; + }; + __IO uint16_t UEP7_TX_LEN; + union{ + __IO uint16_t UEP7_CTRL; + struct{ + __IO uint8_t UEP7_TX_CTRL; + __IO uint8_t UEP7_RX_CTRL; + }; + }; + __IO uint32_t Reserve1; + __IO uint32_t OTG_CR; + __IO uint32_t OTG_SR; +} USBFSD_TypeDef; + +typedef struct +{ + __IO uint8_t BASE_CTRL; + __IO uint8_t HOST_CTRL; + __IO uint8_t INT_EN; + __IO uint8_t DEV_ADDR; + __IO uint8_t Reserve0; + __IO uint8_t MIS_ST; + __IO uint8_t INT_FG; + __IO uint8_t INT_ST; + __IO uint16_t RX_LEN; + __IO uint16_t Reserve1; + __IO uint8_t Reserve2; + __IO uint8_t HOST_EP_MOD; + __IO uint16_t Reserve3; + __IO uint32_t Reserve4; + __IO uint32_t Reserve5; + __IO uint32_t HOST_RX_DMA; + __IO uint32_t HOST_TX_DMA; + __IO uint32_t Reserve6; + __IO uint32_t Reserve7; + __IO uint32_t Reserve8; + __IO uint32_t Reserve9; + __IO uint32_t Reserve10; + __IO uint16_t Reserve11; + __IO uint16_t HOST_SETUP; + __IO uint8_t HOST_EP_PID; + __IO uint8_t Reserve12; + __IO uint8_t Reserve13; + __IO uint8_t HOST_RX_CTRL; + __IO uint16_t HOST_TX_LEN; + __IO uint8_t HOST_TX_CTRL; + __IO uint8_t Reserve14; + __IO uint32_t Reserve15; + __IO uint32_t Reserve16; + __IO uint32_t Reserve17; + __IO uint32_t Reserve18; + __IO uint32_t Reserve19; + __IO uint32_t OTG_CR; + __IO uint32_t OTG_SR; +} USBFSH_TypeDef; + +/* Peripheral memory map */ +#define FLASH_BASE ((uint32_t)0x08000000) /* FLASH base address in the alias region */ +#define SRAM_BASE ((uint32_t)0x20000000) /* SRAM base address in the alias region */ +#define PERIPH_BASE ((uint32_t)0x40000000) /* Peripheral base address in the alias region */ + +#define PB1PERIPH_BASE (PERIPH_BASE) +#define PB2PERIPH_BASE (PERIPH_BASE + 0x10000) +#define HBPERIPH_BASE (PERIPH_BASE + 0x20000) + +#define TIM2_BASE (PB1PERIPH_BASE + 0x0000) +#define TIM3_BASE (PB1PERIPH_BASE + 0x0400) +#define TIM4_BASE (PB1PERIPH_BASE + 0x0800) +#define RTC_BASE (PB1PERIPH_BASE + 0x2800) +#define WWDG_BASE (PB1PERIPH_BASE + 0x2C00) +#define IWDG_BASE (PB1PERIPH_BASE + 0x3000) +#define SPI2_BASE (PB1PERIPH_BASE + 0x3800) +#define USART2_BASE (PB1PERIPH_BASE + 0x4400) +#define USART3_BASE (PB1PERIPH_BASE + 0x4800) +#define USART4_BASE (PB1PERIPH_BASE + 0x4C00) +#define I2C1_BASE (PB1PERIPH_BASE + 0x5400) +#define I2C2_BASE (PB1PERIPH_BASE + 0x5800) +#define CAN1_BASE (PB1PERIPH_BASE + 0x6400) +#define BKP_BASE (PB1PERIPH_BASE + 0x6C00) +#define PWR_BASE (PB1PERIPH_BASE + 0x7000) +#define LPTIM_BASE (PB1PERIPH_BASE + 0x7C00) + +#define AFIO_BASE (PB2PERIPH_BASE + 0x0000) +#define EXTI_BASE (PB2PERIPH_BASE + 0x0400) +#define GPIOA_BASE (PB2PERIPH_BASE + 0x0800) +#define GPIOB_BASE (PB2PERIPH_BASE + 0x0C00) +#define GPIOC_BASE (PB2PERIPH_BASE + 0x1000) +#define GPIOD_BASE (PB2PERIPH_BASE + 0x1400) +#define ADC1_BASE (PB2PERIPH_BASE + 0x2400) +#define TIM1_BASE (PB2PERIPH_BASE + 0x2C00) +#define SPI1_BASE (PB2PERIPH_BASE + 0x3000) +#define USART1_BASE (PB2PERIPH_BASE + 0x3800) + +#define DMA1_BASE (HBPERIPH_BASE + 0x0000) +#define DMA1_Channel1_BASE (HBPERIPH_BASE + 0x0008) +#define DMA1_Channel2_BASE (HBPERIPH_BASE + 0x001C) +#define DMA1_Channel3_BASE (HBPERIPH_BASE + 0x0030) +#define DMA1_Channel4_BASE (HBPERIPH_BASE + 0x0044) +#define DMA1_Channel5_BASE (HBPERIPH_BASE + 0x0058) +#define DMA1_Channel6_BASE (HBPERIPH_BASE + 0x006C) +#define DMA1_Channel7_BASE (HBPERIPH_BASE + 0x0080) +#define DMA1_Channel8_BASE (HBPERIPH_BASE + 0x0094) +#define RCC_BASE (HBPERIPH_BASE + 0x1000) +#define FLASH_R_BASE (HBPERIPH_BASE + 0x2000) +#define CRC_BASE (HBPERIPH_BASE + 0x3000) +#define EXTEN_BASE (HBPERIPH_BASE + 0x3800) +#define OPA_BASE (HBPERIPH_BASE + 0x6000) +#define USBPD_BASE (HBPERIPH_BASE + 0x7000) + +#define USBFS_BASE ((uint32_t)0x50000000) + +#define OB_BASE ((uint32_t)0x1FFFF800) + +#define TS_BASE ((uint32_t)0x1FFFF720) +#define OPA_TRIM_BASE ((uint32_t)0x1FFFF724) +#define ADC_TRIM_BASE ((uint32_t)0x1FFFF728) +#define HSI_LP_TRIM_BASE ((uint32_t)0x1FFFF72A) +#define CHIPID_BASE ((uint32_t)0x1FFFF704) +#define USBPD_CFG_BASE ((uint32_t)0x1FFFF730) + +/* Peripheral declaration */ +#define TIM2 ((TIM_TypeDef *)TIM2_BASE) +#define TIM3 ((TIM_TypeDef *)TIM3_BASE) +#define TIM4 ((TIM_TypeDef *)TIM4_BASE) +#define RTC ((RTC_TypeDef *)RTC_BASE) +#define WWDG ((WWDG_TypeDef *)WWDG_BASE) +#define IWDG ((IWDG_TypeDef *)IWDG_BASE) +#define SPI2 ((SPI_TypeDef *)SPI2_BASE) +#define USART2 ((USART_TypeDef *)USART2_BASE) +#define USART3 ((USART_TypeDef *)USART3_BASE) +#define USART4 ((USART_TypeDef *)USART4_BASE) +#define I2C1 ((I2C_TypeDef *)I2C1_BASE) +#define I2C2 ((I2C_TypeDef *)I2C2_BASE) +#define CAN1 ((CAN_TypeDef *)CAN1_BASE) +#define BKP ((BKP_TypeDef *)BKP_BASE) +#define PWR ((PWR_TypeDef *)PWR_BASE) +#define LPTIM ((LPTIM_TypeDef *)LPTIM_BASE) + +#define AFIO ((AFIO_TypeDef *)AFIO_BASE) +#define EXTI ((EXTI_TypeDef *)EXTI_BASE) +#define GPIOA ((GPIO_TypeDef *)GPIOA_BASE) +#define GPIOB ((GPIO_TypeDef *)GPIOB_BASE) +#define GPIOC ((GPIO_TypeDef *)GPIOC_BASE) +#define GPIOD ((GPIO_TypeDef *)GPIOD_BASE) +#define ADC1 ((ADC_TypeDef *)ADC1_BASE) +#define TKey1 ((ADC_TypeDef *)ADC1_BASE) +#define TIM1 ((TIM_TypeDef *)TIM1_BASE) +#define SPI1 ((SPI_TypeDef *)SPI1_BASE) +#define USART1 ((USART_TypeDef *)USART1_BASE) + +#define DMA1 ((DMA_TypeDef *)DMA1_BASE) +#define DMA1_Channel1 ((DMA_Channel_TypeDef *)DMA1_Channel1_BASE) +#define DMA1_Channel2 ((DMA_Channel_TypeDef *)DMA1_Channel2_BASE) +#define DMA1_Channel3 ((DMA_Channel_TypeDef *)DMA1_Channel3_BASE) +#define DMA1_Channel4 ((DMA_Channel_TypeDef *)DMA1_Channel4_BASE) +#define DMA1_Channel5 ((DMA_Channel_TypeDef *)DMA1_Channel5_BASE) +#define DMA1_Channel6 ((DMA_Channel_TypeDef *)DMA1_Channel6_BASE) +#define DMA1_Channel7 ((DMA_Channel_TypeDef *)DMA1_Channel7_BASE) +#define DMA1_Channel8 ((DMA_Channel_TypeDef *)DMA1_Channel8_BASE) +#define RCC ((RCC_TypeDef *)RCC_BASE) +#define FLASH ((FLASH_TypeDef *)FLASH_R_BASE) +#define CRC ((CRC_TypeDef *)CRC_BASE) +#define USBFSD ((USBFSD_TypeDef *)USBFS_BASE) +#define USBFSH ((USBFSH_TypeDef *)USBFS_BASE) +#define EXTEN ((EXTEN_TypeDef *)EXTEN_BASE) +#define OPA ((OPA_TypeDef *)OPA_BASE) +#define USBPD ((USBPD_TypeDef *)USBPD_BASE) + +#define OB ((OB_TypeDef *)OB_BASE) + + +/******************************************************************************/ +/* Peripheral Registers Bits Definition */ +/******************************************************************************/ + +/******************************************************************************/ +/* Analog to Digital Converter */ +/******************************************************************************/ + +/******************** Bit definition for ADC_STATR register ********************/ +#define ADC_AWD ((uint8_t)0x01) /* Analog watchdog flag */ +#define ADC_EOC ((uint8_t)0x02) /* End of conversion */ +#define ADC_JEOC ((uint8_t)0x04) /* Injected channel end of conversion */ +#define ADC_JSTRT ((uint8_t)0x08) /* Injected channel Start flag */ +#define ADC_STRT ((uint8_t)0x10) /* Regular channel Start flag */ + +/******************* Bit definition for ADC_CTLR1 register ********************/ +#define ADC_AWDCH ((uint32_t)0x0000001F) /* AWDCH[4:0] bits (Analog watchdog channel select bits) */ +#define ADC_AWDCH_0 ((uint32_t)0x00000001) /* Bit 0 */ +#define ADC_AWDCH_1 ((uint32_t)0x00000002) /* Bit 1 */ +#define ADC_AWDCH_2 ((uint32_t)0x00000004) /* Bit 2 */ +#define ADC_AWDCH_3 ((uint32_t)0x00000008) /* Bit 3 */ +#define ADC_AWDCH_4 ((uint32_t)0x00000010) /* Bit 4 */ + +#define ADC_EOCIE ((uint32_t)0x00000020) /* Interrupt enable for EOC */ +#define ADC_AWDIE ((uint32_t)0x00000040) /* Analog Watchdog interrupt enable */ +#define ADC_JEOCIE ((uint32_t)0x00000080) /* Interrupt enable for injected channels */ +#define ADC_SCAN ((uint32_t)0x00000100) /* Scan mode */ +#define ADC_AWDSGL ((uint32_t)0x00000200) /* Enable the watchdog on a single channel in scan mode */ +#define ADC_JAUTO ((uint32_t)0x00000400) /* Automatic injected group conversion */ +#define ADC_DISCEN ((uint32_t)0x00000800) /* Discontinuous mode on regular channels */ +#define ADC_JDISCEN ((uint32_t)0x00001000) /* Discontinuous mode on injected channels */ +#define ADC_RDISCEN ADC_DISCEN + +#define ADC_DISCNUM ((uint32_t)0x0000E000) /* DISCNUM[2:0] bits (Discontinuous mode channel count) */ +#define ADC_DISCNUM_0 ((uint32_t)0x00002000) /* Bit 0 */ +#define ADC_DISCNUM_1 ((uint32_t)0x00004000) /* Bit 1 */ +#define ADC_DISCNUM_2 ((uint32_t)0x00008000) /* Bit 2 */ + +#define ADC_JAWDEN ((uint32_t)0x00400000) /* Analog watchdog enable on injected channels */ +#define ADC_AWDEN ((uint32_t)0x00800000) /* Analog watchdog enable on regular channels */ + +#define ADC_TKENABLE ((uint32_t)0x01000000) +#define ADC_TK1TUNE ((uint32_t)0x02000000) +#define ADC_BUFEN ((uint32_t)0x04000000) + +#define ADC_PGA ((uint32_t)0x18000000) /* PGA[1:0] bits */ +#define ADC_PGA_0 ((uint32_t)0x08000000) +#define ADC_PGA_1 ((uint32_t)0x10000000) + +/******************* Bit definition for ADC_CTLR2 register ********************/ +#define ADC_ADON ((uint32_t)0x00000001) /* A/D Converter ON / OFF */ +#define ADC_CONT ((uint32_t)0x00000002) /* Continuous Conversion */ +#define ADC_CAL ((uint32_t)0x00000004) /* A/D Calibration */ +#define ADC_RSTCAL ((uint32_t)0x00000008) /* Reset Calibration */ +#define ADC_DMA ((uint32_t)0x00000100) /* Direct Memory access mode */ +#define ADC_ALIGN ((uint32_t)0x00000800) /* Data Alignment */ + +#define ADC_JEXTSEL ((uint32_t)0x00007000) /* JEXTSEL[2:0] bits (External event select for injected group) */ +#define ADC_JEXTSEL_0 ((uint32_t)0x00001000) /* Bit 0 */ +#define ADC_JEXTSEL_1 ((uint32_t)0x00002000) /* Bit 1 */ +#define ADC_JEXTSEL_2 ((uint32_t)0x00004000) /* Bit 2 */ + +#define ADC_JEXTTRIG ((uint32_t)0x00008000) /* External Trigger Conversion mode for injected channels */ + +#define ADC_EXTSEL ((uint32_t)0x000E0000) /* EXTSEL[2:0] bits (External Event Select for regular group) */ +#define ADC_EXTSEL_0 ((uint32_t)0x00020000) /* Bit 0 */ +#define ADC_EXTSEL_1 ((uint32_t)0x00040000) /* Bit 1 */ +#define ADC_EXTSEL_2 ((uint32_t)0x00080000) /* Bit 2 */ + +#define ADC_EXTTRIG ((uint32_t)0x00100000) /* External Trigger Conversion mode for regular channels */ +#define ADC_JSWSTART ((uint32_t)0x00200000) /* Start Conversion of injected channels */ +#define ADC_RSWSTART ((uint32_t)0x00400000) /* Start Conversion of regular channels */ +#define ADC_TSVREFE ((uint32_t)0x00800000) /* Temperature Sensor and VREFINT Enable */ + +/****************** Bit definition for ADC_SAMPTR1 register *******************/ +#define ADC_SMP16 ((uint32_t)0x001C0000) /* SMP16[2:0] bits (Channel 16 Sample time selection) */ +#define ADC_SMP16_0 ((uint32_t)0x00040000) /* Bit 0 */ +#define ADC_SMP16_1 ((uint32_t)0x00080000) /* Bit 1 */ +#define ADC_SMP16_2 ((uint32_t)0x00100000) /* Bit 2 */ + +#define ADC_SMP17 ((uint32_t)0x00E00000) /* SMP17[2:0] bits (Channel 17 Sample time selection) */ +#define ADC_SMP17_0 ((uint32_t)0x00200000) /* Bit 0 */ +#define ADC_SMP17_1 ((uint32_t)0x00400000) /* Bit 1 */ +#define ADC_SMP17_2 ((uint32_t)0x00800000) /* Bit 2 */ + +#define ADC_SMP18 ((uint32_t)0x07000000) /* SMP18[2:0] bits (Channel 18 Sample time selection) */ +#define ADC_SMP18_0 ((uint32_t)0x01000000) /* Bit 0 */ +#define ADC_SMP18_1 ((uint32_t)0x02000000) /* Bit 1 */ +#define ADC_SMP18_2 ((uint32_t)0x04000000) /* Bit 2 */ + +/****************** Bit definition for ADC_SAMPTR2 register *******************/ +#define ADC_SMP0 ((uint32_t)0x00000007) /* SMP0[2:0] bits (Channel 0 Sample time selection) */ +#define ADC_SMP0_0 ((uint32_t)0x00000001) /* Bit 0 */ +#define ADC_SMP0_1 ((uint32_t)0x00000002) /* Bit 1 */ +#define ADC_SMP0_2 ((uint32_t)0x00000004) /* Bit 2 */ + +#define ADC_SMP1 ((uint32_t)0x00000038) /* SMP1[2:0] bits (Channel 1 Sample time selection) */ +#define ADC_SMP1_0 ((uint32_t)0x00000008) /* Bit 0 */ +#define ADC_SMP1_1 ((uint32_t)0x00000010) /* Bit 1 */ +#define ADC_SMP1_2 ((uint32_t)0x00000020) /* Bit 2 */ + +#define ADC_SMP2 ((uint32_t)0x000001C0) /* SMP2[2:0] bits (Channel 2 Sample time selection) */ +#define ADC_SMP2_0 ((uint32_t)0x00000040) /* Bit 0 */ +#define ADC_SMP2_1 ((uint32_t)0x00000080) /* Bit 1 */ +#define ADC_SMP2_2 ((uint32_t)0x00000100) /* Bit 2 */ + +#define ADC_SMP3 ((uint32_t)0x00000E00) /* SMP3[2:0] bits (Channel 3 Sample time selection) */ +#define ADC_SMP3_0 ((uint32_t)0x00000200) /* Bit 0 */ +#define ADC_SMP3_1 ((uint32_t)0x00000400) /* Bit 1 */ +#define ADC_SMP3_2 ((uint32_t)0x00000800) /* Bit 2 */ + +#define ADC_SMP4 ((uint32_t)0x00007000) /* SMP4[2:0] bits (Channel 4 Sample time selection) */ +#define ADC_SMP4_0 ((uint32_t)0x00001000) /* Bit 0 */ +#define ADC_SMP4_1 ((uint32_t)0x00002000) /* Bit 1 */ +#define ADC_SMP4_2 ((uint32_t)0x00004000) /* Bit 2 */ + +#define ADC_SMP5 ((uint32_t)0x00038000) /* SMP5[2:0] bits (Channel 5 Sample time selection) */ +#define ADC_SMP5_0 ((uint32_t)0x00008000) /* Bit 0 */ +#define ADC_SMP5_1 ((uint32_t)0x00010000) /* Bit 1 */ +#define ADC_SMP5_2 ((uint32_t)0x00020000) /* Bit 2 */ + +#define ADC_SMP6 ((uint32_t)0x001C0000) /* SMP6[2:0] bits (Channel 6 Sample time selection) */ +#define ADC_SMP6_0 ((uint32_t)0x00040000) /* Bit 0 */ +#define ADC_SMP6_1 ((uint32_t)0x00080000) /* Bit 1 */ +#define ADC_SMP6_2 ((uint32_t)0x00100000) /* Bit 2 */ + +#define ADC_SMP7 ((uint32_t)0x00E00000) /* SMP7[2:0] bits (Channel 7 Sample time selection) */ +#define ADC_SMP7_0 ((uint32_t)0x00200000) /* Bit 0 */ +#define ADC_SMP7_1 ((uint32_t)0x00400000) /* Bit 1 */ +#define ADC_SMP7_2 ((uint32_t)0x00800000) /* Bit 2 */ + +#define ADC_SMP8 ((uint32_t)0x07000000) /* SMP8[2:0] bits (Channel 8 Sample time selection) */ +#define ADC_SMP8_0 ((uint32_t)0x01000000) /* Bit 0 */ +#define ADC_SMP8_1 ((uint32_t)0x02000000) /* Bit 1 */ +#define ADC_SMP8_2 ((uint32_t)0x04000000) /* Bit 2 */ + +#define ADC_SMP9 ((uint32_t)0x38000000) /* SMP9[2:0] bits (Channel 9 Sample time selection) */ +#define ADC_SMP9_0 ((uint32_t)0x08000000) /* Bit 0 */ +#define ADC_SMP9_1 ((uint32_t)0x10000000) /* Bit 1 */ +#define ADC_SMP9_2 ((uint32_t)0x20000000) /* Bit 2 */ + +/****************** Bit definition for ADC_IOFR1 register *******************/ +#define ADC_JOFFSET1 ((uint16_t)0x0FFF) /* Data offset for injected channel 1 */ + +/****************** Bit definition for ADC_IOFR2 register *******************/ +#define ADC_JOFFSET2 ((uint16_t)0x0FFF) /* Data offset for injected channel 2 */ + +/****************** Bit definition for ADC_IOFR3 register *******************/ +#define ADC_JOFFSET3 ((uint16_t)0x0FFF) /* Data offset for injected channel 3 */ + +/****************** Bit definition for ADC_IOFR4 register *******************/ +#define ADC_JOFFSET4 ((uint16_t)0x0FFF) /* Data offset for injected channel 4 */ + +/******************* Bit definition for ADC_WDHTR register ********************/ +#define ADC_HT ((uint16_t)0x0FFF) /* Analog watchdog high threshold */ + +/******************* Bit definition for ADC_WDLTR register ********************/ +#define ADC_LT ((uint16_t)0x0FFF) /* Analog watchdog low threshold */ + +/******************* Bit definition for ADC_RSQR1 register *******************/ +#define ADC_SQ13 ((uint32_t)0x0000001F) /* SQ13[4:0] bits (13th conversion in regular sequence) */ +#define ADC_SQ13_0 ((uint32_t)0x00000001) /* Bit 0 */ +#define ADC_SQ13_1 ((uint32_t)0x00000002) /* Bit 1 */ +#define ADC_SQ13_2 ((uint32_t)0x00000004) /* Bit 2 */ +#define ADC_SQ13_3 ((uint32_t)0x00000008) /* Bit 3 */ +#define ADC_SQ13_4 ((uint32_t)0x00000010) /* Bit 4 */ + +#define ADC_SQ14 ((uint32_t)0x000003E0) /* SQ14[4:0] bits (14th conversion in regular sequence) */ +#define ADC_SQ14_0 ((uint32_t)0x00000020) /* Bit 0 */ +#define ADC_SQ14_1 ((uint32_t)0x00000040) /* Bit 1 */ +#define ADC_SQ14_2 ((uint32_t)0x00000080) /* Bit 2 */ +#define ADC_SQ14_3 ((uint32_t)0x00000100) /* Bit 3 */ +#define ADC_SQ14_4 ((uint32_t)0x00000200) /* Bit 4 */ + +#define ADC_SQ15 ((uint32_t)0x00007C00) /* SQ15[4:0] bits (15th conversion in regular sequence) */ +#define ADC_SQ15_0 ((uint32_t)0x00000400) /* Bit 0 */ +#define ADC_SQ15_1 ((uint32_t)0x00000800) /* Bit 1 */ +#define ADC_SQ15_2 ((uint32_t)0x00001000) /* Bit 2 */ +#define ADC_SQ15_3 ((uint32_t)0x00002000) /* Bit 3 */ +#define ADC_SQ15_4 ((uint32_t)0x00004000) /* Bit 4 */ + +#define ADC_SQ16 ((uint32_t)0x000F8000) /* SQ16[4:0] bits (16th conversion in regular sequence) */ +#define ADC_SQ16_0 ((uint32_t)0x00008000) /* Bit 0 */ +#define ADC_SQ16_1 ((uint32_t)0x00010000) /* Bit 1 */ +#define ADC_SQ16_2 ((uint32_t)0x00020000) /* Bit 2 */ +#define ADC_SQ16_3 ((uint32_t)0x00040000) /* Bit 3 */ +#define ADC_SQ16_4 ((uint32_t)0x00080000) /* Bit 4 */ + +#define ADC_L ((uint32_t)0x00F00000) /* L[3:0] bits (Regular channel sequence length) */ +#define ADC_L_0 ((uint32_t)0x00100000) /* Bit 0 */ +#define ADC_L_1 ((uint32_t)0x00200000) /* Bit 1 */ +#define ADC_L_2 ((uint32_t)0x00400000) /* Bit 2 */ +#define ADC_L_3 ((uint32_t)0x00800000) /* Bit 3 */ + +/******************* Bit definition for ADC_RSQR2 register *******************/ +#define ADC_SQ7 ((uint32_t)0x0000001F) /* SQ7[4:0] bits (7th conversion in regular sequence) */ +#define ADC_SQ7_0 ((uint32_t)0x00000001) /* Bit 0 */ +#define ADC_SQ7_1 ((uint32_t)0x00000002) /* Bit 1 */ +#define ADC_SQ7_2 ((uint32_t)0x00000004) /* Bit 2 */ +#define ADC_SQ7_3 ((uint32_t)0x00000008) /* Bit 3 */ +#define ADC_SQ7_4 ((uint32_t)0x00000010) /* Bit 4 */ + +#define ADC_SQ8 ((uint32_t)0x000003E0) /* SQ8[4:0] bits (8th conversion in regular sequence) */ +#define ADC_SQ8_0 ((uint32_t)0x00000020) /* Bit 0 */ +#define ADC_SQ8_1 ((uint32_t)0x00000040) /* Bit 1 */ +#define ADC_SQ8_2 ((uint32_t)0x00000080) /* Bit 2 */ +#define ADC_SQ8_3 ((uint32_t)0x00000100) /* Bit 3 */ +#define ADC_SQ8_4 ((uint32_t)0x00000200) /* Bit 4 */ + +#define ADC_SQ9 ((uint32_t)0x00007C00) /* SQ9[4:0] bits (9th conversion in regular sequence) */ +#define ADC_SQ9_0 ((uint32_t)0x00000400) /* Bit 0 */ +#define ADC_SQ9_1 ((uint32_t)0x00000800) /* Bit 1 */ +#define ADC_SQ9_2 ((uint32_t)0x00001000) /* Bit 2 */ +#define ADC_SQ9_3 ((uint32_t)0x00002000) /* Bit 3 */ +#define ADC_SQ9_4 ((uint32_t)0x00004000) /* Bit 4 */ + +#define ADC_SQ10 ((uint32_t)0x000F8000) /* SQ10[4:0] bits (10th conversion in regular sequence) */ +#define ADC_SQ10_0 ((uint32_t)0x00008000) /* Bit 0 */ +#define ADC_SQ10_1 ((uint32_t)0x00010000) /* Bit 1 */ +#define ADC_SQ10_2 ((uint32_t)0x00020000) /* Bit 2 */ +#define ADC_SQ10_3 ((uint32_t)0x00040000) /* Bit 3 */ +#define ADC_SQ10_4 ((uint32_t)0x00080000) /* Bit 4 */ + +#define ADC_SQ11 ((uint32_t)0x01F00000) /* SQ11[4:0] bits (11th conversion in regular sequence) */ +#define ADC_SQ11_0 ((uint32_t)0x00100000) /* Bit 0 */ +#define ADC_SQ11_1 ((uint32_t)0x00200000) /* Bit 1 */ +#define ADC_SQ11_2 ((uint32_t)0x00400000) /* Bit 2 */ +#define ADC_SQ11_3 ((uint32_t)0x00800000) /* Bit 3 */ +#define ADC_SQ11_4 ((uint32_t)0x01000000) /* Bit 4 */ + +#define ADC_SQ12 ((uint32_t)0x3E000000) /* SQ12[4:0] bits (12th conversion in regular sequence) */ +#define ADC_SQ12_0 ((uint32_t)0x02000000) /* Bit 0 */ +#define ADC_SQ12_1 ((uint32_t)0x04000000) /* Bit 1 */ +#define ADC_SQ12_2 ((uint32_t)0x08000000) /* Bit 2 */ +#define ADC_SQ12_3 ((uint32_t)0x10000000) /* Bit 3 */ +#define ADC_SQ12_4 ((uint32_t)0x20000000) /* Bit 4 */ + +/******************* Bit definition for ADC_RSQR3 register *******************/ +#define ADC_SQ1 ((uint32_t)0x0000001F) /* SQ1[4:0] bits (1st conversion in regular sequence) */ +#define ADC_SQ1_0 ((uint32_t)0x00000001) /* Bit 0 */ +#define ADC_SQ1_1 ((uint32_t)0x00000002) /* Bit 1 */ +#define ADC_SQ1_2 ((uint32_t)0x00000004) /* Bit 2 */ +#define ADC_SQ1_3 ((uint32_t)0x00000008) /* Bit 3 */ +#define ADC_SQ1_4 ((uint32_t)0x00000010) /* Bit 4 */ + +#define ADC_SQ2 ((uint32_t)0x000003E0) /* SQ2[4:0] bits (2nd conversion in regular sequence) */ +#define ADC_SQ2_0 ((uint32_t)0x00000020) /* Bit 0 */ +#define ADC_SQ2_1 ((uint32_t)0x00000040) /* Bit 1 */ +#define ADC_SQ2_2 ((uint32_t)0x00000080) /* Bit 2 */ +#define ADC_SQ2_3 ((uint32_t)0x00000100) /* Bit 3 */ +#define ADC_SQ2_4 ((uint32_t)0x00000200) /* Bit 4 */ + +#define ADC_SQ3 ((uint32_t)0x00007C00) /* SQ3[4:0] bits (3rd conversion in regular sequence) */ +#define ADC_SQ3_0 ((uint32_t)0x00000400) /* Bit 0 */ +#define ADC_SQ3_1 ((uint32_t)0x00000800) /* Bit 1 */ +#define ADC_SQ3_2 ((uint32_t)0x00001000) /* Bit 2 */ +#define ADC_SQ3_3 ((uint32_t)0x00002000) /* Bit 3 */ +#define ADC_SQ3_4 ((uint32_t)0x00004000) /* Bit 4 */ + +#define ADC_SQ4 ((uint32_t)0x000F8000) /* SQ4[4:0] bits (4th conversion in regular sequence) */ +#define ADC_SQ4_0 ((uint32_t)0x00008000) /* Bit 0 */ +#define ADC_SQ4_1 ((uint32_t)0x00010000) /* Bit 1 */ +#define ADC_SQ4_2 ((uint32_t)0x00020000) /* Bit 2 */ +#define ADC_SQ4_3 ((uint32_t)0x00040000) /* Bit 3 */ +#define ADC_SQ4_4 ((uint32_t)0x00080000) /* Bit 4 */ + +#define ADC_SQ5 ((uint32_t)0x01F00000) /* SQ5[4:0] bits (5th conversion in regular sequence) */ +#define ADC_SQ5_0 ((uint32_t)0x00100000) /* Bit 0 */ +#define ADC_SQ5_1 ((uint32_t)0x00200000) /* Bit 1 */ +#define ADC_SQ5_2 ((uint32_t)0x00400000) /* Bit 2 */ +#define ADC_SQ5_3 ((uint32_t)0x00800000) /* Bit 3 */ +#define ADC_SQ5_4 ((uint32_t)0x01000000) /* Bit 4 */ + +#define ADC_SQ6 ((uint32_t)0x3E000000) /* SQ6[4:0] bits (6th conversion in regular sequence) */ +#define ADC_SQ6_0 ((uint32_t)0x02000000) /* Bit 0 */ +#define ADC_SQ6_1 ((uint32_t)0x04000000) /* Bit 1 */ +#define ADC_SQ6_2 ((uint32_t)0x08000000) /* Bit 2 */ +#define ADC_SQ6_3 ((uint32_t)0x10000000) /* Bit 3 */ +#define ADC_SQ6_4 ((uint32_t)0x20000000) /* Bit 4 */ + +/******************* Bit definition for ADC_ISQR register *******************/ +#define ADC_JSQ1 ((uint32_t)0x0000001F) /* JSQ1[4:0] bits (1st conversion in injected sequence) */ +#define ADC_JSQ1_0 ((uint32_t)0x00000001) /* Bit 0 */ +#define ADC_JSQ1_1 ((uint32_t)0x00000002) /* Bit 1 */ +#define ADC_JSQ1_2 ((uint32_t)0x00000004) /* Bit 2 */ +#define ADC_JSQ1_3 ((uint32_t)0x00000008) /* Bit 3 */ +#define ADC_JSQ1_4 ((uint32_t)0x00000010) /* Bit 4 */ + +#define ADC_JSQ2 ((uint32_t)0x000003E0) /* JSQ2[4:0] bits (2nd conversion in injected sequence) */ +#define ADC_JSQ2_0 ((uint32_t)0x00000020) /* Bit 0 */ +#define ADC_JSQ2_1 ((uint32_t)0x00000040) /* Bit 1 */ +#define ADC_JSQ2_2 ((uint32_t)0x00000080) /* Bit 2 */ +#define ADC_JSQ2_3 ((uint32_t)0x00000100) /* Bit 3 */ +#define ADC_JSQ2_4 ((uint32_t)0x00000200) /* Bit 4 */ + +#define ADC_JSQ3 ((uint32_t)0x00007C00) /* JSQ3[4:0] bits (3rd conversion in injected sequence) */ +#define ADC_JSQ3_0 ((uint32_t)0x00000400) /* Bit 0 */ +#define ADC_JSQ3_1 ((uint32_t)0x00000800) /* Bit 1 */ +#define ADC_JSQ3_2 ((uint32_t)0x00001000) /* Bit 2 */ +#define ADC_JSQ3_3 ((uint32_t)0x00002000) /* Bit 3 */ +#define ADC_JSQ3_4 ((uint32_t)0x00004000) /* Bit 4 */ + +#define ADC_JSQ4 ((uint32_t)0x000F8000) /* JSQ4[4:0] bits (4th conversion in injected sequence) */ +#define ADC_JSQ4_0 ((uint32_t)0x00008000) /* Bit 0 */ +#define ADC_JSQ4_1 ((uint32_t)0x00010000) /* Bit 1 */ +#define ADC_JSQ4_2 ((uint32_t)0x00020000) /* Bit 2 */ +#define ADC_JSQ4_3 ((uint32_t)0x00040000) /* Bit 3 */ +#define ADC_JSQ4_4 ((uint32_t)0x00080000) /* Bit 4 */ + +#define ADC_JL ((uint32_t)0x00300000) /* JL[1:0] bits (Injected Sequence length) */ +#define ADC_JL_0 ((uint32_t)0x00100000) /* Bit 0 */ +#define ADC_JL_1 ((uint32_t)0x00200000) /* Bit 1 */ + +/******************* Bit definition for ADC_IDATAR1 register *******************/ +#define ADC_IDATAR1_JDATA ((uint16_t)0xFFFF) /* Injected data */ + +/******************* Bit definition for ADC_IDATAR2 register *******************/ +#define ADC_IDATAR2_JDATA ((uint16_t)0xFFFF) /* Injected data */ + +/******************* Bit definition for ADC_IDATAR3 register *******************/ +#define ADC_IDATAR3_JDATA ((uint16_t)0xFFFF) /* Injected data */ + +/******************* Bit definition for ADC_IDATAR4 register *******************/ +#define ADC_IDATAR4_JDATA ((uint16_t)0xFFFF) /* Injected data */ + +/******************** Bit definition for ADC_RDATAR register ********************/ +#define ADC_RDATAR_DATA ((uint32_t)0x0000FFFF) /* Regular data */ +/******************** Bit definition for ADC_CFG register ********************/ +#define ADC_BUFTRIM ((uint32_t)0x0000000F) /* BUFTRIM[3:0] bits */ +#define ADC_BUFTRIM_0 ((uint32_t)0x00000001) +#define ADC_BUFTRIM_1 ((uint32_t)0x00000002) +#define ADC_BUFTRIM_2 ((uint32_t)0x00000004) +#define ADC_BUFTRIM_3 ((uint32_t)0x00000008) + +#define ADC_AWDRST_EN ((uint32_t)0x00000010) +#define ADC_LP ((uint32_t)0x00000020) +#define ADC_FIFO_EN ((uint32_t)0x00000040) +#define ADC_DUTY_EN ((uint32_t)0x00000080) +#define ADC_TKEY_DRV_EN ((uint32_t)0x00000100) + +#define ADC_TKEY_DRV_OUTEN ((uint32_t)0x0007FE00) /* TKEY_DRV_OUTEN[9:0] bits */ +#define ADC_TKEY_DRV_OUTEN_0 ((uint32_t)0x00000200) +#define ADC_TKEY_DRV_OUTEN_1 ((uint32_t)0x00000400) +#define ADC_TKEY_DRV_OUTEN_2 ((uint32_t)0x00000800) +#define ADC_TKEY_DRV_OUTEN_3 ((uint32_t)0x00001000) +#define ADC_TKEY_DRV_OUTEN_4 ((uint32_t)0x00002000) +#define ADC_TKEY_DRV_OUTEN_5 ((uint32_t)0x00004000) +#define ADC_TKEY_DRV_OUTEN_6 ((uint32_t)0x00008000) +#define ADC_TKEY_DRV_OUTEN_7 ((uint32_t)0x00010000) +#define ADC_TKEY_DRV_OUTEN_8 ((uint32_t)0x00020000) +#define ADC_TKEY_DRV_OUTEN_9 ((uint32_t)0x00040000) + +#define ADC_TKEY_SEL ((uint32_t)0x00180000) /* TKEY_SEL[1:0] bits */ +#define ADC_TKEY_SEL_0 ((uint32_t)0x00080000) +#define ADC_TKEY_SEL_1 ((uint32_t)0x00080000) + +#define ADC_TKEY_WAKE_EN ((uint32_t)0x8FE00000) /* TKEY_WAKE_EN[9:0] bits */ +#define ADC_TKEY_WAKE_EN_0 ((uint32_t)0x00200000) +#define ADC_TKEY_WAKE_EN_1 ((uint32_t)0x00400000) +#define ADC_TKEY_WAKE_EN_2 ((uint32_t)0x00800000) +#define ADC_TKEY_WAKE_EN_3 ((uint32_t)0x01000000) +#define ADC_TKEY_WAKE_EN_4 ((uint32_t)0x02000000) +#define ADC_TKEY_WAKE_EN_5 ((uint32_t)0x04000000) +#define ADC_TKEY_WAKE_EN_6 ((uint32_t)0x08000000) +#define ADC_TKEY_WAKE_EN_7 ((uint32_t)0x10000000) +#define ADC_TKEY_WAKE_EN_8 ((uint32_t)0x20000000) +#define ADC_TKEY_WAKE_EN_9 ((uint32_t)0x40000000) + +/******************************************************************************/ +/* Backup registers */ +/******************************************************************************/ + +/******************* Bit definition for BKP_DATAR1 register ********************/ +#define BKP_DATAR1_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR2 register ********************/ +#define BKP_DATAR2_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR3 register ********************/ +#define BKP_DATAR3_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR4 register ********************/ +#define BKP_DATAR4_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR5 register ********************/ +#define BKP_DATAR5_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR6 register ********************/ +#define BKP_DATAR6_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR7 register ********************/ +#define BKP_DATAR7_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR8 register ********************/ +#define BKP_DATAR8_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR9 register ********************/ +#define BKP_DATAR9_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR10 register *******************/ +#define BKP_DATAR10_D ((uint16_t)0xFFFF) /* Backup data */ + +/****************** Bit definition for BKP_OCTLR register *******************/ +#define BKP_CAL ((uint16_t)0x007F) /* Calibration value */ +#define BKP_CCO ((uint16_t)0x0080) /* Calibration Clock Output */ +#define BKP_ASOE ((uint16_t)0x0100) /* Alarm or Second Output Enable */ +#define BKP_ASOS ((uint16_t)0x0200) /* Alarm or Second Output Selection */ + +/******************** Bit definition for BKP_TPCTLR register ********************/ +#define BKP_TPE ((uint8_t)0x01) /* TAMPER pin enable */ +#define BKP_TPAL ((uint8_t)0x02) /* TAMPER pin active level */ + +/******************* Bit definition for BKP_TPCSR register ********************/ +#define BKP_CTE ((uint16_t)0x0001) /* Clear Tamper event */ +#define BKP_CTI ((uint16_t)0x0002) /* Clear Tamper Interrupt */ +#define BKP_TPIE ((uint16_t)0x0004) /* TAMPER Pin interrupt enable */ +#define BKP_TEF ((uint16_t)0x0100) /* Tamper Event Flag */ +#define BKP_TIF ((uint16_t)0x0200) /* Tamper Interrupt Flag */ + +/******************************************************************************/ +/* Controller Area Network */ +/******************************************************************************/ + +/******************* Bit definition for CAN_CTLR register ********************/ +#define CAN_CTLR_INRQ ((uint32_t)0x00000001) /* Initialization Request */ +#define CAN_CTLR_SLEEP ((uint32_t)0x00000002) /* Sleep Mode Request */ +#define CAN_CTLR_TXFP ((uint32_t)0x00000004) /* Transmit FIFO Priority */ +#define CAN_CTLR_RFLM ((uint32_t)0x00000008) /* Receive FIFO Locked Mode */ +#define CAN_CTLR_NART ((uint32_t)0x00000010) /* No Automatic Retransmission */ +#define CAN_CTLR_AWUM ((uint32_t)0x00000020) /* Automatic Wakeup Mode */ +#define CAN_CTLR_ABOM ((uint32_t)0x00000040) /* Automatic Bus-Off Management */ +#define CAN_CTLR_TTCM ((uint32_t)0x00000080) /* Time Triggered Communication Mode */ +#define CAN_CTLR_RESET ((uint32_t)0x00008000) /* CAN software master reset */ +#define CAN_CTLR_DBF ((uint32_t)0x00010000) /* CAN controller operating state selection during debugging */ + +/******************* Bit definition for CAN_STATR register ********************/ +#define CAN_STATR_INAK ((uint16_t)0x0001) /* Initialization Acknowledge */ +#define CAN_STATR_SLAK ((uint16_t)0x0002) /* Sleep Acknowledge */ +#define CAN_STATR_ERRI ((uint16_t)0x0004) /* Error Interrupt */ +#define CAN_STATR_WKUI ((uint16_t)0x0008) /* Wakeup Interrupt */ +#define CAN_STATR_SLAKI ((uint16_t)0x0010) /* Sleep Acknowledge Interrupt */ +#define CAN_STATR_TXM ((uint16_t)0x0100) /* Transmit Mode */ +#define CAN_STATR_RXM ((uint16_t)0x0200) /* Receive Mode */ +#define CAN_STATR_SAMP ((uint16_t)0x0400) /* Last Sample Point */ +#define CAN_STATR_RX ((uint16_t)0x0800) /* CAN Rx Signal */ + +/******************* Bit definition for CAN_TSTATR register ********************/ +#define CAN_TSTATR_RQCP0 ((uint32_t)0x00000001) /* Request Completed Mailbox0 */ +#define CAN_TSTATR_TXOK0 ((uint32_t)0x00000002) /* Transmission OK of Mailbox0 */ +#define CAN_TSTATR_ALST0 ((uint32_t)0x00000004) /* Arbitration Lost for Mailbox0 */ +#define CAN_TSTATR_TERR0 ((uint32_t)0x00000008) /* Transmission Error of Mailbox0 */ +#define CAN_TSTATR_ABRQ0 ((uint32_t)0x00000080) /* Abort Request for Mailbox0 */ +#define CAN_TSTATR_RQCP1 ((uint32_t)0x00000100) /* Request Completed Mailbox1 */ +#define CAN_TSTATR_TXOK1 ((uint32_t)0x00000200) /* Transmission OK of Mailbox1 */ +#define CAN_TSTATR_ALST1 ((uint32_t)0x00000400) /* Arbitration Lost for Mailbox1 */ +#define CAN_TSTATR_TERR1 ((uint32_t)0x00000800) /* Transmission Error of Mailbox1 */ +#define CAN_TSTATR_ABRQ1 ((uint32_t)0x00008000) /* Abort Request for Mailbox 1 */ +#define CAN_TSTATR_RQCP2 ((uint32_t)0x00010000) /* Request Completed Mailbox2 */ +#define CAN_TSTATR_TXOK2 ((uint32_t)0x00020000) /* Transmission OK of Mailbox 2 */ +#define CAN_TSTATR_ALST2 ((uint32_t)0x00040000) /* Arbitration Lost for mailbox 2 */ +#define CAN_TSTATR_TERR2 ((uint32_t)0x00080000) /* Transmission Error of Mailbox 2 */ +#define CAN_TSTATR_ABRQ2 ((uint32_t)0x00800000) /* Abort Request for Mailbox 2 */ +#define CAN_TSTATR_CODE ((uint32_t)0x03000000) /* Mailbox Code */ + +#define CAN_TSTATR_TME ((uint32_t)0x1C000000) /* TME[2:0] bits */ +#define CAN_TSTATR_TME0 ((uint32_t)0x04000000) /* Transmit Mailbox 0 Empty */ +#define CAN_TSTATR_TME1 ((uint32_t)0x08000000) /* Transmit Mailbox 1 Empty */ +#define CAN_TSTATR_TME2 ((uint32_t)0x10000000) /* Transmit Mailbox 2 Empty */ + +#define CAN_TSTATR_LOW ((uint32_t)0xE0000000) /* LOW[2:0] bits */ +#define CAN_TSTATR_LOW0 ((uint32_t)0x20000000) /* Lowest Priority Flag for Mailbox 0 */ +#define CAN_TSTATR_LOW1 ((uint32_t)0x40000000) /* Lowest Priority Flag for Mailbox 1 */ +#define CAN_TSTATR_LOW2 ((uint32_t)0x80000000) /* Lowest Priority Flag for Mailbox 2 */ + +/******************* Bit definition for CAN_RFIFO0 register *******************/ +#define CAN_RFIFO0_FMP0 ((uint8_t)0x03) /* FIFO 0 Message Pending */ +#define CAN_RFIFO0_FULL0 ((uint8_t)0x08) /* FIFO 0 Full */ +#define CAN_RFIFO0_FOVR0 ((uint8_t)0x10) /* FIFO 0 Overrun */ +#define CAN_RFIFO0_RFOM0 ((uint8_t)0x20) /* Release FIFO 0 Output Mailbox */ + +/******************* Bit definition for CAN_RFIFO1 register *******************/ +#define CAN_RFIFO1_FMP1 ((uint8_t)0x03) /* FIFO 1 Message Pending */ +#define CAN_RFIFO1_FULL1 ((uint8_t)0x08) /* FIFO 1 Full */ +#define CAN_RFIFO1_FOVR1 ((uint8_t)0x10) /* FIFO 1 Overrun */ +#define CAN_RFIFO1_RFOM1 ((uint8_t)0x20) /* Release FIFO 1 Output Mailbox */ + +/******************** Bit definition for CAN_INTENR register *******************/ +#define CAN_INTENR_TMEIE ((uint32_t)0x00000001) /* Transmit Mailbox Empty Interrupt Enable */ +#define CAN_INTENR_FMPIE0 ((uint32_t)0x00000002) /* FIFO Message Pending Interrupt Enable */ +#define CAN_INTENR_FFIE0 ((uint32_t)0x00000004) /* FIFO Full Interrupt Enable */ +#define CAN_INTENR_FOVIE0 ((uint32_t)0x00000008) /* FIFO Overrun Interrupt Enable */ +#define CAN_INTENR_FMPIE1 ((uint32_t)0x00000010) /* FIFO Message Pending Interrupt Enable */ +#define CAN_INTENR_FFIE1 ((uint32_t)0x00000020) /* FIFO Full Interrupt Enable */ +#define CAN_INTENR_FOVIE1 ((uint32_t)0x00000040) /* FIFO Overrun Interrupt Enable */ +#define CAN_INTENR_EWGIE ((uint32_t)0x00000100) /* Error Warning Interrupt Enable */ +#define CAN_INTENR_EPVIE ((uint32_t)0x00000200) /* Error Passive Interrupt Enable */ +#define CAN_INTENR_BOFIE ((uint32_t)0x00000400) /* Bus-Off Interrupt Enable */ +#define CAN_INTENR_LECIE ((uint32_t)0x00000800) /* Last Error Code Interrupt Enable */ +#define CAN_INTENR_ERRIE ((uint32_t)0x00008000) /* Error Interrupt Enable */ +#define CAN_INTENR_WKUIE ((uint32_t)0x00010000) /* Wakeup Interrupt Enable */ +#define CAN_INTENR_SLKIE ((uint32_t)0x00020000) /* Sleep Interrupt Enable */ + +/******************** Bit definition for CAN_ERRSR register *******************/ +#define CAN_ERRSR_EWGF ((uint32_t)0x00000001) /* Error Warning Flag */ +#define CAN_ERRSR_EPVF ((uint32_t)0x00000002) /* Error Passive Flag */ +#define CAN_ERRSR_BOFF ((uint32_t)0x00000004) /* Bus-Off Flag */ + +#define CAN_ERRSR_LEC ((uint32_t)0x00000070) /* LEC[2:0] bits (Last Error Code) */ +#define CAN_ERRSR_LEC_0 ((uint32_t)0x00000010) /* Bit 0 */ +#define CAN_ERRSR_LEC_1 ((uint32_t)0x00000020) /* Bit 1 */ +#define CAN_ERRSR_LEC_2 ((uint32_t)0x00000040) /* Bit 2 */ + +#define CAN_ERRSR_TEC ((uint32_t)0x00FF0000) /* Least significant byte of the 9-bit Transmit Error Counter */ +#define CAN_ERRSR_REC ((uint32_t)0xFF000000) /* Receive Error Counter */ + +/******************* Bit definition for CAN_BTIMR register ********************/ +#define CAN_BTIMR_BRP ((uint32_t)0x000003FF) /* Baud Rate Prescaler */ +#define CAN_BTIMR_TS1 ((uint32_t)0x000F0000) /* Time Segment 1 */ +#define CAN_BTIMR_TS2 ((uint32_t)0x00700000) /* Time Segment 2 */ +#define CAN_BTIMR_SJW ((uint32_t)0x03000000) /* Resynchronization Jump Width */ +#define CAN_BTIMR_LBKM ((uint32_t)0x40000000) /* Loop Back Mode (Debug) */ +#define CAN_BTIMR_SILM ((uint32_t)0x80000000) /* Silent Mode */ + +/******************** Bit definition for CAN_TTCTLR register *******************/ +#define CAN_TTCTLR_TIMCMV ((uint32_t)0x0000FFFF) +#define CAN_TTCTLR_TIMRST ((uint32_t)0x00010000) +#define CAN_TTCTLR_MODE ((uint32_t)0x00020000) + +/******************** Bit definition for CAN_TTCNT register *******************/ +#define CAN_TTCNT ((uint32_t)0x0000FFFF) + +/******************** Bit definition for CAN_TERR_CNT register *******************/ +#define CAN_TERR_CNT ((uint32_t)0x000001FF) + +/******************** Bit definition for CANFD_CR register *******************/ +#define CANFD_CR_TX_FD ((uint32_t)0x00000001) +#define CANFD_CR_TX_BRS_B ((uint32_t)0x0000000E) +#define CANFD_CR_USER_ESI_B ((uint32_t)0x00000070) +#define CANFD_CR_RES_EXCEPT ((uint32_t)0x00000080) +#define CANFD_CR_CLAS_LONG_TS1 ((uint32_t)0x00000100) +#define CANFD_CR_RESTRICT_MODE ((uint32_t)0x00000200) + +/******************** Bit definition for CANFD_BTR register *******************/ +#define CANFD_BTR_BTR_SJW_FD ((uint32_t)0x0000000F) +#define CANFD_BTR_BTR_TS2_FD ((uint32_t)0x000000F0) +#define CANFD_BTR_BTR_TS1_FD ((uint32_t)0x00001F00) +#define CANFD_BTR_BTR_BRP_FD ((uint32_t)0x001F0000) +#define CANFD_BTR_BTR_TDCE ((uint32_t)0x00800000) + +/******************** Bit definition for CANFD_TDCT register *******************/ +#define CANFD_TDCT_TDCO ((uint32_t)0x0000003F) +#define CANFD_TDCT_TDC_FILTER ((uint32_t)0x00003F00) + +/******************** Bit definition for CANFD_PSR register *******************/ +#define CANFD_PSR_TDCV ((uint32_t)0x00FF0000) + +/******************** Bit definition for CAN_DMA_T0 register *******************/ +#define CANFD_DMA_T0 ((uint32_t)0x00007FFF) + +/******************** Bit definition for CAN_DMA_T1 register *******************/ +#define CANFD_DMA_T1 ((uint32_t)0x00007FFF) + +/******************** Bit definition for CAN_DMA_T2 register *******************/ +#define CANFD_DMA_T2 ((uint32_t)0x00007FFF) + +/******************** Bit definition for CAN_DMA_R0 register *******************/ +#define CANFD_DMA_R0 ((uint32_t)0x00007FFF) + +/******************** Bit definition for CAN_DMA_R1 register *******************/ +#define CANFD_DMA_R1 ((uint32_t)0x00007FFF) + +/****************** Bit definition for CAN_TXMI0R register ********************/ +#define CAN_TXMI0R_TXRQ ((uint32_t)0x00000001) /* Transmit Mailbox Request */ +#define CAN_TXMI0R_RTR ((uint32_t)0x00000002) /* Remote Transmission Request */ +#define CAN_TXMI0R_IDE ((uint32_t)0x00000004) /* Identifier Extension */ +#define CAN_TXMI0R_EXID ((uint32_t)0x001FFFF8) /* Extended Identifier */ +#define CAN_TXMI0R_STID ((uint32_t)0xFFE00000) /* Standard Identifier or Extended Identifier */ + +/****************** Bit definition for CAN_TXMDT0R register *******************/ +#define CAN_TXMDT0R_DLC ((uint32_t)0x0000000F) /* Data Length Code */ +#define CAN_TXMDT0R_TGT ((uint32_t)0x00000100) /* Transmit Global Time */ +#define CAN_TXMDT0R_TIME ((uint32_t)0xFFFF0000) /* Message Time Stamp */ + +/****************** Bit definition for CAN_TXMDL0R register *******************/ +#define CAN_TXMDL0R_DATA0 ((uint32_t)0x000000FF) /* Data byte 0 */ +#define CAN_TXMDL0R_DATA1 ((uint32_t)0x0000FF00) /* Data byte 1 */ +#define CAN_TXMDL0R_DATA2 ((uint32_t)0x00FF0000) /* Data byte 2 */ +#define CAN_TXMDL0R_DATA3 ((uint32_t)0xFF000000) /* Data byte 3 */ + +/****************** Bit definition for CAN_TXMDH0R register *******************/ +#define CAN_TXMDH0R_DATA4 ((uint32_t)0x000000FF) /* Data byte 4 */ +#define CAN_TXMDH0R_DATA5 ((uint32_t)0x0000FF00) /* Data byte 5 */ +#define CAN_TXMDH0R_DATA6 ((uint32_t)0x00FF0000) /* Data byte 6 */ +#define CAN_TXMDH0R_DATA7 ((uint32_t)0xFF000000) /* Data byte 7 */ + +/******************* Bit definition for CAN_TXMI1R register *******************/ +#define CAN_TXMI1R_TXRQ ((uint32_t)0x00000001) /* Transmit Mailbox Request */ +#define CAN_TXMI1R_RTR ((uint32_t)0x00000002) /* Remote Transmission Request */ +#define CAN_TXMI1R_IDE ((uint32_t)0x00000004) /* Identifier Extension */ +#define CAN_TXMI1R_EXID ((uint32_t)0x001FFFF8) /* Extended Identifier */ +#define CAN_TXMI1R_STID ((uint32_t)0xFFE00000) /* Standard Identifier or Extended Identifier */ + +/******************* Bit definition for CAN_TXMDT1R register ******************/ +#define CAN_TXMDT1R_DLC ((uint32_t)0x0000000F) /* Data Length Code */ +#define CAN_TXMDT1R_TGT ((uint32_t)0x00000100) /* Transmit Global Time */ +#define CAN_TXMDT1R_TIME ((uint32_t)0xFFFF0000) /* Message Time Stamp */ + +/******************* Bit definition for CAN_TXMDL1R register ******************/ +#define CAN_TXMDL1R_DATA0 ((uint32_t)0x000000FF) /* Data byte 0 */ +#define CAN_TXMDL1R_DATA1 ((uint32_t)0x0000FF00) /* Data byte 1 */ +#define CAN_TXMDL1R_DATA2 ((uint32_t)0x00FF0000) /* Data byte 2 */ +#define CAN_TXMDL1R_DATA3 ((uint32_t)0xFF000000) /* Data byte 3 */ + +/******************* Bit definition for CAN_TXMDH1R register ******************/ +#define CAN_TXMDH1R_DATA4 ((uint32_t)0x000000FF) /* Data byte 4 */ +#define CAN_TXMDH1R_DATA5 ((uint32_t)0x0000FF00) /* Data byte 5 */ +#define CAN_TXMDH1R_DATA6 ((uint32_t)0x00FF0000) /* Data byte 6 */ +#define CAN_TXMDH1R_DATA7 ((uint32_t)0xFF000000) /* Data byte 7 */ + +/******************* Bit definition for CAN_TXMI2R register *******************/ +#define CAN_TXMI2R_TXRQ ((uint32_t)0x00000001) /* Transmit Mailbox Request */ +#define CAN_TXMI2R_RTR ((uint32_t)0x00000002) /* Remote Transmission Request */ +#define CAN_TXMI2R_IDE ((uint32_t)0x00000004) /* Identifier Extension */ +#define CAN_TXMI2R_EXID ((uint32_t)0x001FFFF8) /* Extended identifier */ +#define CAN_TXMI2R_STID ((uint32_t)0xFFE00000) /* Standard Identifier or Extended Identifier */ + +/******************* Bit definition for CAN_TXMDT2R register ******************/ +#define CAN_TXMDT2R_DLC ((uint32_t)0x0000000F) /* Data Length Code */ +#define CAN_TXMDT2R_TGT ((uint32_t)0x00000100) /* Transmit Global Time */ +#define CAN_TXMDT2R_TIME ((uint32_t)0xFFFF0000) /* Message Time Stamp */ + +/******************* Bit definition for CAN_TXMDL2R register ******************/ +#define CAN_TXMDL2R_DATA0 ((uint32_t)0x000000FF) /* Data byte 0 */ +#define CAN_TXMDL2R_DATA1 ((uint32_t)0x0000FF00) /* Data byte 1 */ +#define CAN_TXMDL2R_DATA2 ((uint32_t)0x00FF0000) /* Data byte 2 */ +#define CAN_TXMDL2R_DATA3 ((uint32_t)0xFF000000) /* Data byte 3 */ + +/******************* Bit definition for CAN_TXMDH2R register ******************/ +#define CAN_TXMDH2R_DATA4 ((uint32_t)0x000000FF) /* Data byte 4 */ +#define CAN_TXMDH2R_DATA5 ((uint32_t)0x0000FF00) /* Data byte 5 */ +#define CAN_TXMDH2R_DATA6 ((uint32_t)0x00FF0000) /* Data byte 6 */ +#define CAN_TXMDH2R_DATA7 ((uint32_t)0xFF000000) /* Data byte 7 */ + +/******************* Bit definition for CAN_RXMI0R register *******************/ +#define CAN_RXMIOR_FDF ((uint32_t)0x00000001) +#define CAN_RXMI0R_RTR ((uint32_t)0x00000002) /* Remote Transmission Request */ +#define CAN_RXMI0R_IDE ((uint32_t)0x00000004) /* Identifier Extension */ +#define CAN_RXMI0R_EXID ((uint32_t)0x001FFFF8) /* Extended Identifier */ +#define CAN_RXMI0R_STID ((uint32_t)0xFFE00000) /* Standard Identifier or Extended Identifier */ + +/******************* Bit definition for CAN_RXMDT0R register ******************/ +#define CAN_RXMDT0R_DLC ((uint32_t)0x0000000F) /* Data Length Code */ +#define CAN_RXMDT0R_BRS ((uint32_t)0x00000010) +#define CAN_RXMDT0R_ESI ((uint32_t)0x00000020) +#define CAN_RXMDH0R_RES ((uint32_t)0x00000100) +#define CAN_RXMDT0R_FMI ((uint32_t)0x0000FF00) /* Filter Match Index */ +#define CAN_RXMDT0R_TIME ((uint32_t)0xFFFF0000) /* Message Time Stamp */ + +/******************* Bit definition for CAN_RXMDL0R register ******************/ +#define CAN_RXMDL0R_DATA0 ((uint32_t)0x000000FF) /* Data byte 0 */ +#define CAN_RXMDL0R_DATA1 ((uint32_t)0x0000FF00) /* Data byte 1 */ +#define CAN_RXMDL0R_DATA2 ((uint32_t)0x00FF0000) /* Data byte 2 */ +#define CAN_RXMDL0R_DATA3 ((uint32_t)0xFF000000) /* Data byte 3 */ + +/******************* Bit definition for CAN_RXMDH0R register ******************/ +#define CAN_RXMDH0R_DATA4 ((uint32_t)0x000000FF) /* Data byte 4 */ +#define CAN_RXMDH0R_DATA5 ((uint32_t)0x0000FF00) /* Data byte 5 */ +#define CAN_RXMDH0R_DATA6 ((uint32_t)0x00FF0000) /* Data byte 6 */ +#define CAN_RXMDH0R_DATA7 ((uint32_t)0xFF000000) /* Data byte 7 */ + +/******************* Bit definition for CAN_RXMI1R register *******************/ +#define CAN_RXMI1R_FDF ((uint32_t)0x00000001) +#define CAN_RXMI1R_RTR ((uint32_t)0x00000002) /* Remote Transmission Request */ +#define CAN_RXMI1R_IDE ((uint32_t)0x00000004) /* Identifier Extension */ +#define CAN_RXMI1R_EXID ((uint32_t)0x001FFFF8) /* Extended identifier */ +#define CAN_RXMI1R_STID ((uint32_t)0xFFE00000) /* Standard Identifier or Extended Identifier */ + +/******************* Bit definition for CAN_RXMDT1R register ******************/ +#define CAN_RXMDT1R_DLC ((uint32_t)0x0000000F) /* Data Length Code */ +#define CAN_RXMDT1R_BRS ((uint32_t)0x00000010) +#define CAN_RXMDT1R_ESI ((uint32_t)0x00000020) +#define CAN_RXMDH1R_RES ((uint32_t)0x00000100) +#define CAN_RXMDT1R_FMI ((uint32_t)0x0000FF00) /* Filter Match Index */ +#define CAN_RXMDT1R_TIME ((uint32_t)0xFFFF0000) /* Message Time Stamp */ + +/******************* Bit definition for CAN_RXMDL1R register ******************/ +#define CAN_RXMDL1R_DATA0 ((uint32_t)0x000000FF) /* Data byte 0 */ +#define CAN_RXMDL1R_DATA1 ((uint32_t)0x0000FF00) /* Data byte 1 */ +#define CAN_RXMDL1R_DATA2 ((uint32_t)0x00FF0000) /* Data byte 2 */ +#define CAN_RXMDL1R_DATA3 ((uint32_t)0xFF000000) /* Data byte 3 */ + +/******************* Bit definition for CAN_RXMDH1R register ******************/ +#define CAN_RXMDH1R_DATA4 ((uint32_t)0x000000FF) /* Data byte 4 */ +#define CAN_RXMDH1R_DATA5 ((uint32_t)0x0000FF00) /* Data byte 5 */ +#define CAN_RXMDH1R_DATA6 ((uint32_t)0x00FF0000) /* Data byte 6 */ +#define CAN_RXMDH1R_DATA7 ((uint32_t)0xFF000000) /* Data byte 7 */ + +/******************* Bit definition for CAN_FCTLR register ********************/ +#define CAN_FCTLR_FINIT ((uint8_t)0x01) /* Filter Init Mode */ + +/******************* Bit definition for CAN_FMCFGR register *******************/ +#define CAN_FMCFGR_FBM ((uint32_t)0x00003FFF) /* Filter Mode */ +#define CAN_FMCFGR_FBM0 ((uint32_t)0x00000001) /* Filter Init Mode bit 0 */ +#define CAN_FMCFGR_FBM1 ((uint32_t)0x00000002) /* Filter Init Mode bit 1 */ +#define CAN_FMCFGR_FBM2 ((uint32_t)0x00000004) /* Filter Init Mode bit 2 */ +#define CAN_FMCFGR_FBM3 ((uint32_t)0x00000008) /* Filter Init Mode bit 3 */ +#define CAN_FMCFGR_FBM4 ((uint32_t)0x00000010) /* Filter Init Mode bit 4 */ +#define CAN_FMCFGR_FBM5 ((uint32_t)0x00000020) /* Filter Init Mode bit 5 */ +#define CAN_FMCFGR_FBM6 ((uint32_t)0x00000040) /* Filter Init Mode bit 6 */ +#define CAN_FMCFGR_FBM7 ((uint32_t)0x00000080) /* Filter Init Mode bit 7 */ +#define CAN_FMCFGR_FBM8 ((uint32_t)0x00000100) /* Filter Init Mode bit 8 */ +#define CAN_FMCFGR_FBM9 ((uint32_t)0x00000200) /* Filter Init Mode bit 9 */ +#define CAN_FMCFGR_FBM10 ((uint32_t)0x00000400) /* Filter Init Mode bit 10 */ +#define CAN_FMCFGR_FBM11 ((uint32_t)0x00000800) /* Filter Init Mode bit 11 */ +#define CAN_FMCFGR_FBM12 ((uint32_t)0x00001000) /* Filter Init Mode bit 12 */ +#define CAN_FMCFGR_FBM13 ((uint32_t)0x00002000) /* Filter Init Mode bit 13 */ +#define CAN_FMCFGR_FBM14 ((uint32_t)0x00004000) /* Filter Init Mode bit 14 */ +#define CAN_FMCFGR_FBM15 ((uint32_t)0x00008000) /* Filter Init Mode bit 15 */ +#define CAN_FMCFGR_FBM16 ((uint32_t)0x00010000) /* Filter Init Mode bit 16 */ +#define CAN_FMCFGR_FBM17 ((uint32_t)0x00020000) /* Filter Init Mode bit 17 */ +#define CAN_FMCFGR_FBM18 ((uint32_t)0x00040000) /* Filter Init Mode bit 18 */ +#define CAN_FMCFGR_FBM19 ((uint32_t)0x00080000) /* Filter Init Mode bit 19 */ +#define CAN_FMCFGR_FBM20 ((uint32_t)0x00100000) /* Filter Init Mode bit 20 */ +#define CAN_FMCFGR_FBM21 ((uint32_t)0x00200000) /* Filter Init Mode bit 21 */ +#define CAN_FMCFGR_FBM22 ((uint32_t)0x00400000) /* Filter Init Mode bit 22 */ +#define CAN_FMCFGR_FBM23 ((uint32_t)0x00800000) /* Filter Init Mode bit 23 */ +#define CAN_FMCFGR_FBM24 ((uint32_t)0x01000000) /* Filter Init Mode bit 24 */ +#define CAN_FMCFGR_FBM25 ((uint32_t)0x02000000) /* Filter Init Mode bit 25 */ +#define CAN_FMCFGR_FBM26 ((uint32_t)0x04000000) /* Filter Init Mode bit 26 */ +#define CAN_FMCFGR_FBM27 ((uint32_t)0x08000000) /* Filter Init Mode bit 27 */ + +/******************* Bit definition for CAN_FSCFGR register *******************/ +#define CAN_FSCFGR_FSC ((uint32_t)0x00003FFF) /* Filter Scale Configuration */ +#define CAN_FSCFGR_FSC0 ((uint32_t)0x00000001) /* Filter Scale Configuration bit 0 */ +#define CAN_FSCFGR_FSC1 ((uint32_t)0x00000002) /* Filter Scale Configuration bit 1 */ +#define CAN_FSCFGR_FSC2 ((uint32_t)0x00000004) /* Filter Scale Configuration bit 2 */ +#define CAN_FSCFGR_FSC3 ((uint32_t)0x00000008) /* Filter Scale Configuration bit 3 */ +#define CAN_FSCFGR_FSC4 ((uint32_t)0x00000010) /* Filter Scale Configuration bit 4 */ +#define CAN_FSCFGR_FSC5 ((uint32_t)0x00000020) /* Filter Scale Configuration bit 5 */ +#define CAN_FSCFGR_FSC6 ((uint32_t)0x00000040) /* Filter Scale Configuration bit 6 */ +#define CAN_FSCFGR_FSC7 ((uint32_t)0x00000080) /* Filter Scale Configuration bit 7 */ +#define CAN_FSCFGR_FSC8 ((uint32_t)0x00000100) /* Filter Scale Configuration bit 8 */ +#define CAN_FSCFGR_FSC9 ((uint32_t)0x00000200) /* Filter Scale Configuration bit 9 */ +#define CAN_FSCFGR_FSC10 ((uint32_t)0x00000400) /* Filter Scale Configuration bit 10 */ +#define CAN_FSCFGR_FSC11 ((uint32_t)0x00000800) /* Filter Scale Configuration bit 11 */ +#define CAN_FSCFGR_FSC12 ((uint32_t)0x00001000) /* Filter Scale Configuration bit 12 */ +#define CAN_FSCFGR_FSC13 ((uint32_t)0x00002000) /* Filter Scale Configuration bit 13 */ +#define CAN_FSCFGR_FSC14 ((uint32_t)0x00004000) /* Filter Scale Configuration bit 14 */ +#define CAN_FSCFGR_FSC15 ((uint32_t)0x00008000) /* Filter Scale Configuration bit 15 */ +#define CAN_FSCFGR_FSC16 ((uint32_t)0x00010000) /* Filter Scale Configuration bit 16 */ +#define CAN_FSCFGR_FSC17 ((uint32_t)0x00020000) /* Filter Scale Configuration bit 17 */ +#define CAN_FSCFGR_FSC18 ((uint32_t)0x00040000) /* Filter Scale Configuration bit 18 */ +#define CAN_FSCFGR_FSC19 ((uint32_t)0x00080000) /* Filter Scale Configuration bit 19 */ +#define CAN_FSCFGR_FSC20 ((uint32_t)0x00100000) /* Filter Scale Configuration bit 20 */ +#define CAN_FSCFGR_FSC21 ((uint32_t)0x00200000) /* Filter Scale Configuration bit 21 */ +#define CAN_FSCFGR_FSC22 ((uint32_t)0x00400000) /* Filter Scale Configuration bit 22 */ +#define CAN_FSCFGR_FSC23 ((uint32_t)0x00800000) /* Filter Scale Configuration bit 23 */ +#define CAN_FSCFGR_FSC24 ((uint32_t)0x01000000) /* Filter Scale Configuration bit 24 */ +#define CAN_FSCFGR_FSC25 ((uint32_t)0x02000000) /* Filter Scale Configuration bit 25 */ +#define CAN_FSCFGR_FSC26 ((uint32_t)0x04000000) /* Filter Scale Configuration bit 26 */ +#define CAN_FSCFGR_FSC27 ((uint32_t)0x08000000) /* Filter Scale Configuration bit 27 */ + +/****************** Bit definition for CAN_FAFIFOR register *******************/ +#define CAN_FAFIFOR_FFA ((uint32_t)0x00003FFF) /* Filter FIFO Assignment */ +#define CAN_FAFIFOR_FFA0 ((uint32_t)0x00000001) /* Filter FIFO Assignment for Filter 0 */ +#define CAN_FAFIFOR_FFA1 ((uint32_t)0x00000002) /* Filter FIFO Assignment for Filter 1 */ +#define CAN_FAFIFOR_FFA2 ((uint32_t)0x00000004) /* Filter FIFO Assignment for Filter 2 */ +#define CAN_FAFIFOR_FFA3 ((uint32_t)0x00000008) /* Filter FIFO Assignment for Filter 3 */ +#define CAN_FAFIFOR_FFA4 ((uint32_t)0x00000010) /* Filter FIFO Assignment for Filter 4 */ +#define CAN_FAFIFOR_FFA5 ((uint32_t)0x00000020) /* Filter FIFO Assignment for Filter 5 */ +#define CAN_FAFIFOR_FFA6 ((uint32_t)0x00000040) /* Filter FIFO Assignment for Filter 6 */ +#define CAN_FAFIFOR_FFA7 ((uint32_t)0x00000080) /* Filter FIFO Assignment for Filter 7 */ +#define CAN_FAFIFOR_FFA8 ((uint32_t)0x00000100) /* Filter FIFO Assignment for Filter 8 */ +#define CAN_FAFIFOR_FFA9 ((uint32_t)0x00000200) /* Filter FIFO Assignment for Filter 9 */ +#define CAN_FAFIFOR_FFA10 ((uint32_t)0x00000400) /* Filter FIFO Assignment for Filter 10 */ +#define CAN_FAFIFOR_FFA11 ((uint32_t)0x00000800) /* Filter FIFO Assignment for Filter 11 */ +#define CAN_FAFIFOR_FFA12 ((uint32_t)0x00001000) /* Filter FIFO Assignment for Filter 12 */ +#define CAN_FAFIFOR_FFA13 ((uint32_t)0x00002000) /* Filter FIFO Assignment for Filter 13 */ +#define CAN_FAFIFOR_FFA14 ((uint32_t)0x00004000) /* Filter FIFO Assignment for Filter 14 */ +#define CAN_FAFIFOR_FFA15 ((uint32_t)0x00008000) /* Filter FIFO Assignment for Filter 15 */ +#define CAN_FAFIFOR_FFA16 ((uint32_t)0x00010000) /* Filter FIFO Assignment for Filter 16 */ +#define CAN_FAFIFOR_FFA17 ((uint32_t)0x00020000) /* Filter FIFO Assignment for Filter 17 */ +#define CAN_FAFIFOR_FFA18 ((uint32_t)0x00040000) /* Filter FIFO Assignment for Filter 18 */ +#define CAN_FAFIFOR_FFA19 ((uint32_t)0x00080000) /* Filter FIFO Assignment for Filter 19 */ +#define CAN_FAFIFOR_FFA20 ((uint32_t)0x00100000) /* Filter FIFO Assignment for Filter 20 */ +#define CAN_FAFIFOR_FFA21 ((uint32_t)0x00200000) /* Filter FIFO Assignment for Filter 21 */ +#define CAN_FAFIFOR_FFA22 ((uint32_t)0x00400000) /* Filter FIFO Assignment for Filter 22 */ +#define CAN_FAFIFOR_FFA23 ((uint32_t)0x00800000) /* Filter FIFO Assignment for Filter 23 */ +#define CAN_FAFIFOR_FFA24 ((uint32_t)0x01000000) /* Filter FIFO Assignment for Filter 24 */ +#define CAN_FAFIFOR_FFA25 ((uint32_t)0x02000000) /* Filter FIFO Assignment for Filter 25 */ +#define CAN_FAFIFOR_FFA26 ((uint32_t)0x04000000) /* Filter FIFO Assignment for Filter 26 */ +#define CAN_FAFIFOR_FFA27 ((uint32_t)0x08000000) /* Filter FIFO Assignment for Filter 27 */ + +/******************* Bit definition for CAN_FWR register *******************/ +#define CAN_FWR_FACT ((uint32_t)0x00003FFF) /* Filter Active */ +#define CAN_FWR_FACT0 ((uint32_t)0x00000001) /* Filter 0 Active */ +#define CAN_FWR_FACT1 ((uint32_t)0x00000002) /* Filter 1 Active */ +#define CAN_FWR_FACT2 ((uint32_t)0x00000004) /* Filter 2 Active */ +#define CAN_FWR_FACT3 ((uint32_t)0x00000008) /* Filter 3 Active */ +#define CAN_FWR_FACT4 ((uint32_t)0x00000010) /* Filter 4 Active */ +#define CAN_FWR_FACT5 ((uint32_t)0x00000020) /* Filter 5 Active */ +#define CAN_FWR_FACT6 ((uint32_t)0x00000040) /* Filter 6 Active */ +#define CAN_FWR_FACT7 ((uint32_t)0x00000080) /* Filter 7 Active */ +#define CAN_FWR_FACT8 ((uint32_t)0x00000100) /* Filter 8 Active */ +#define CAN_FWR_FACT9 ((uint32_t)0x00000200) /* Filter 9 Active */ +#define CAN_FWR_FACT10 ((uint32_t)0x00000400) /* Filter 10 Active */ +#define CAN_FWR_FACT11 ((uint32_t)0x00000800) /* Filter 11 Active */ +#define CAN_FWR_FACT12 ((uint32_t)0x00001000) /* Filter 12 Active */ +#define CAN_FWR_FACT13 ((uint32_t)0x00002000) /* Filter 13 Active */ +#define CAN_FWR_FACT14 ((uint32_t)0x00004000) /* Filter 14 Active */ +#define CAN_FWR_FACT15 ((uint32_t)0x00008000) /* Filter 15 Active */ +#define CAN_FWR_FACT16 ((uint32_t)0x00010000) /* Filter 16 Active */ +#define CAN_FWR_FACT17 ((uint32_t)0x00020000) /* Filter 17 Active */ +#define CAN_FWR_FACT18 ((uint32_t)0x00040000) /* Filter 18 Active */ +#define CAN_FWR_FACT19 ((uint32_t)0x00080000) /* Filter 19 Active */ +#define CAN_FWR_FACT20 ((uint32_t)0x00100000) /* Filter 20 Active */ +#define CAN_FWR_FACT21 ((uint32_t)0x00200000) /* Filter 21 Active */ +#define CAN_FWR_FACT22 ((uint32_t)0x00400000) /* Filter 22 Active */ +#define CAN_FWR_FACT23 ((uint32_t)0x00800000) /* Filter 23 Active */ +#define CAN_FWR_FACT24 ((uint32_t)0x01000000) /* Filter 24 Active */ +#define CAN_FWR_FACT25 ((uint32_t)0x02000000) /* Filter 25 Active */ +#define CAN_FWR_FACT26 ((uint32_t)0x04000000) /* Filter 26 Active */ +#define CAN_FWR_FACT27 ((uint32_t)0x08000000) /* Filter 27 Active */ + +/******************* Bit definition for CAN_F0R1 register *******************/ +#define CAN_F0R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F0R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F0R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F0R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F0R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F0R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F0R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F0R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F0R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F0R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F0R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F0R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F0R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F0R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F0R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F0R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F0R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F0R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F0R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F0R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F0R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F0R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F0R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F0R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F0R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F0R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F0R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F0R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F0R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F0R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F0R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F0R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F1R1 register *******************/ +#define CAN_F1R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F1R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F1R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F1R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F1R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F1R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F1R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F1R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F1R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F1R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F1R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F1R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F1R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F1R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F1R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F1R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F1R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F1R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F1R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F1R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F1R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F1R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F1R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F1R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F1R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F1R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F1R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F1R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F1R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F1R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F1R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F1R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F2R1 register *******************/ +#define CAN_F2R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F2R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F2R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F2R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F2R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F2R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F2R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F2R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F2R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F2R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F2R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F2R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F2R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F2R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F2R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F2R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F2R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F2R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F2R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F2R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F2R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F2R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F2R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F2R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F2R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F2R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F2R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F2R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F2R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F2R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F2R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F2R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F3R1 register *******************/ +#define CAN_F3R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F3R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F3R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F3R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F3R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F3R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F3R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F3R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F3R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F3R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F3R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F3R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F3R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F3R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F3R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F3R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F3R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F3R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F3R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F3R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F3R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F3R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F3R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F3R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F3R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F3R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F3R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F3R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F3R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F3R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F3R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F3R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F4R1 register *******************/ +#define CAN_F4R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F4R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F4R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F4R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F4R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F4R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F4R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F4R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F4R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F4R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F4R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F4R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F4R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F4R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F4R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F4R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F4R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F4R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F4R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F4R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F4R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F4R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F4R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F4R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F4R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F4R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F4R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F4R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F4R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F4R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F4R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F4R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F5R1 register *******************/ +#define CAN_F5R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F5R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F5R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F5R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F5R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F5R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F5R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F5R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F5R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F5R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F5R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F5R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F5R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F5R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F5R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F5R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F5R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F5R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F5R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F5R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F5R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F5R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F5R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F5R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F5R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F5R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F5R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F5R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F5R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F5R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F5R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F5R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F6R1 register *******************/ +#define CAN_F6R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F6R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F6R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F6R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F6R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F6R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F6R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F6R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F6R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F6R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F6R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F6R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F6R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F6R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F6R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F6R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F6R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F6R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F6R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F6R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F6R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F6R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F6R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F6R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F6R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F6R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F6R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F6R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F6R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F6R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F6R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F6R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F7R1 register *******************/ +#define CAN_F7R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F7R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F7R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F7R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F7R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F7R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F7R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F7R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F7R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F7R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F7R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F7R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F7R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F7R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F7R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F7R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F7R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F7R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F7R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F7R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F7R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F7R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F7R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F7R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F7R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F7R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F7R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F7R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F7R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F7R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F7R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F7R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F8R1 register *******************/ +#define CAN_F8R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F8R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F8R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F8R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F8R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F8R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F8R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F8R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F8R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F8R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F8R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F8R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F8R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F8R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F8R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F8R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F8R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F8R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F8R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F8R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F8R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F8R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F8R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F8R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F8R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F8R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F8R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F8R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F8R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F8R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F8R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F8R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F9R1 register *******************/ +#define CAN_F9R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F9R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F9R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F9R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F9R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F9R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F9R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F9R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F9R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F9R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F9R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F9R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F9R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F9R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F9R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F9R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F9R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F9R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F9R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F9R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F9R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F9R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F9R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F9R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F9R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F9R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F9R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F9R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F9R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F9R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F9R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F9R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F10R1 register ******************/ +#define CAN_F10R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F10R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F10R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F10R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F10R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F10R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F10R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F10R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F10R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F10R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F10R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F10R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F10R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F10R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F10R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F10R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F10R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F10R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F10R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F10R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F10R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F10R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F10R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F10R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F10R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F10R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F10R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F10R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F10R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F10R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F10R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F10R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F11R1 register ******************/ +#define CAN_F11R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F11R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F11R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F11R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F11R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F11R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F11R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F11R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F11R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F11R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F11R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F11R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F11R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F11R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F11R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F11R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F11R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F11R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F11R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F11R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F11R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F11R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F11R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F11R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F11R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F11R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F11R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F11R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F11R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F11R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F11R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F11R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F12R1 register ******************/ +#define CAN_F12R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F12R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F12R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F12R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F12R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F12R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F12R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F12R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F12R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F12R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F12R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F12R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F12R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F12R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F12R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F12R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F12R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F12R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F12R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F12R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F12R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F12R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F12R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F12R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F12R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F12R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F12R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F12R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F12R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F12R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F12R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F12R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F13R1 register ******************/ +#define CAN_F13R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F13R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F13R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F13R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F13R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F13R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F13R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F13R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F13R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F13R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F13R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F13R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F13R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F13R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F13R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F13R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F13R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F13R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F13R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F13R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F13R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F13R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F13R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F13R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F13R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F13R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F13R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F13R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F13R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F13R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F13R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F13R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F0R2 register *******************/ +#define CAN_F0R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F0R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F0R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F0R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F0R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F0R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F0R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F0R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F0R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F0R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F0R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F0R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F0R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F0R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F0R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F0R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F0R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F0R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F0R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F0R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F0R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F0R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F0R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F0R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F0R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F0R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F0R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F0R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F0R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F0R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F0R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F0R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F1R2 register *******************/ +#define CAN_F1R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F1R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F1R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F1R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F1R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F1R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F1R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F1R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F1R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F1R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F1R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F1R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F1R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F1R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F1R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F1R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F1R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F1R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F1R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F1R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F1R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F1R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F1R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F1R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F1R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F1R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F1R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F1R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F1R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F1R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F1R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F1R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F2R2 register *******************/ +#define CAN_F2R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F2R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F2R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F2R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F2R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F2R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F2R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F2R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F2R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F2R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F2R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F2R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F2R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F2R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F2R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F2R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F2R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F2R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F2R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F2R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F2R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F2R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F2R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F2R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F2R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F2R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F2R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F2R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F2R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F2R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F2R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F2R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F3R2 register *******************/ +#define CAN_F3R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F3R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F3R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F3R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F3R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F3R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F3R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F3R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F3R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F3R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F3R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F3R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F3R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F3R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F3R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F3R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F3R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F3R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F3R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F3R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F3R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F3R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F3R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F3R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F3R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F3R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F3R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F3R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F3R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F3R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F3R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F3R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F4R2 register *******************/ +#define CAN_F4R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F4R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F4R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F4R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F4R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F4R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F4R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F4R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F4R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F4R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F4R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F4R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F4R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F4R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F4R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F4R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F4R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F4R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F4R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F4R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F4R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F4R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F4R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F4R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F4R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F4R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F4R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F4R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F4R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F4R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F4R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F4R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F5R2 register *******************/ +#define CAN_F5R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F5R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F5R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F5R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F5R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F5R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F5R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F5R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F5R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F5R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F5R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F5R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F5R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F5R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F5R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F5R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F5R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F5R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F5R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F5R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F5R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F5R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F5R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F5R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F5R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F5R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F5R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F5R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F5R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F5R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F5R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F5R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F6R2 register *******************/ +#define CAN_F6R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F6R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F6R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F6R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F6R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F6R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F6R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F6R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F6R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F6R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F6R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F6R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F6R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F6R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F6R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F6R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F6R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F6R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F6R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F6R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F6R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F6R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F6R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F6R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F6R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F6R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F6R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F6R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F6R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F6R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F6R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F6R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F7R2 register *******************/ +#define CAN_F7R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F7R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F7R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F7R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F7R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F7R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F7R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F7R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F7R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F7R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F7R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F7R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F7R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F7R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F7R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F7R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F7R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F7R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F7R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F7R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F7R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F7R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F7R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F7R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F7R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F7R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F7R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F7R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F7R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F7R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F7R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F7R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F8R2 register *******************/ +#define CAN_F8R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F8R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F8R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F8R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F8R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F8R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F8R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F8R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F8R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F8R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F8R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F8R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F8R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F8R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F8R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F8R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F8R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F8R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F8R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F8R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F8R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F8R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F8R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F8R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F8R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F8R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F8R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F8R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F8R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F8R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F8R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F8R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F9R2 register *******************/ +#define CAN_F9R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F9R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F9R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F9R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F9R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F9R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F9R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F9R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F9R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F9R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F9R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F9R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F9R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F9R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F9R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F9R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F9R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F9R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F9R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F9R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F9R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F9R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F9R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F9R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F9R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F9R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F9R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F9R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F9R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F9R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F9R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F9R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F10R2 register ******************/ +#define CAN_F10R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F10R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F10R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F10R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F10R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F10R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F10R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F10R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F10R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F10R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F10R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F10R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F10R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F10R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F10R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F10R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F10R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F10R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F10R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F10R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F10R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F10R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F10R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F10R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F10R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F10R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F10R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F10R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F10R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F10R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F10R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F10R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F11R2 register ******************/ +#define CAN_F11R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F11R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F11R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F11R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F11R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F11R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F11R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F11R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F11R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F11R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F11R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F11R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F11R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F11R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F11R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F11R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F11R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F11R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F11R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F11R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F11R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F11R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F11R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F11R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F11R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F11R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F11R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F11R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F11R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F11R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F11R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F11R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F12R2 register ******************/ +#define CAN_F12R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F12R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F12R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F12R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F12R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F12R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F12R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F12R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F12R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F12R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F12R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F12R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F12R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F12R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F12R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F12R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F12R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F12R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F12R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F12R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F12R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F12R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F12R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F12R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F12R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F12R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F12R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F12R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F12R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F12R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F12R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F12R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F13R2 register ******************/ +#define CAN_F13R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F13R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F13R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F13R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F13R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F13R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F13R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F13R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F13R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F13R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F13R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F13R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F13R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F13R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F13R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F13R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F13R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F13R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F13R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F13R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F13R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F13R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F13R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F13R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F13R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F13R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F13R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F13R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F13R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F13R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F13R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F13R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************************************************************************/ +/* CRC Calculation Unit */ +/******************************************************************************/ + +/******************* Bit definition for CRC_DATAR register *********************/ +#define CRC_DATAR_DR ((uint32_t)0xFFFFFFFF) /* Data register bits */ + +/******************* Bit definition for CRC_IDATAR register ********************/ +#define CRC_IDR_IDATAR ((uint8_t)0xFF) /* General-purpose 8-bit data register bits */ + +/******************** Bit definition for CRC_CTLR register ********************/ +#define CRC_CTLR_RESET ((uint8_t)0x01) /* RESET bit */ + +/******************************************************************************/ +/* DMA Controller */ +/******************************************************************************/ + +/******************* Bit definition for DMA_INTFR register ********************/ +#define DMA_GIF1 ((uint32_t)0x00000001) /* Channel 1 Global interrupt flag */ +#define DMA_TCIF1 ((uint32_t)0x00000002) /* Channel 1 Transfer Complete flag */ +#define DMA_HTIF1 ((uint32_t)0x00000004) /* Channel 1 Half Transfer flag */ +#define DMA_TEIF1 ((uint32_t)0x00000008) /* Channel 1 Transfer Error flag */ +#define DMA_GIF2 ((uint32_t)0x00000010) /* Channel 2 Global interrupt flag */ +#define DMA_TCIF2 ((uint32_t)0x00000020) /* Channel 2 Transfer Complete flag */ +#define DMA_HTIF2 ((uint32_t)0x00000040) /* Channel 2 Half Transfer flag */ +#define DMA_TEIF2 ((uint32_t)0x00000080) /* Channel 2 Transfer Error flag */ +#define DMA_GIF3 ((uint32_t)0x00000100) /* Channel 3 Global interrupt flag */ +#define DMA_TCIF3 ((uint32_t)0x00000200) /* Channel 3 Transfer Complete flag */ +#define DMA_HTIF3 ((uint32_t)0x00000400) /* Channel 3 Half Transfer flag */ +#define DMA_TEIF3 ((uint32_t)0x00000800) /* Channel 3 Transfer Error flag */ +#define DMA_GIF4 ((uint32_t)0x00001000) /* Channel 4 Global interrupt flag */ +#define DMA_TCIF4 ((uint32_t)0x00002000) /* Channel 4 Transfer Complete flag */ +#define DMA_HTIF4 ((uint32_t)0x00004000) /* Channel 4 Half Transfer flag */ +#define DMA_TEIF4 ((uint32_t)0x00008000) /* Channel 4 Transfer Error flag */ +#define DMA_GIF5 ((uint32_t)0x00010000) /* Channel 5 Global interrupt flag */ +#define DMA_TCIF5 ((uint32_t)0x00020000) /* Channel 5 Transfer Complete flag */ +#define DMA_HTIF5 ((uint32_t)0x00040000) /* Channel 5 Half Transfer flag */ +#define DMA_TEIF5 ((uint32_t)0x00080000) /* Channel 5 Transfer Error flag */ +#define DMA_GIF6 ((uint32_t)0x00100000) /* Channel 6 Global interrupt flag */ +#define DMA_TCIF6 ((uint32_t)0x00200000) /* Channel 6 Transfer Complete flag */ +#define DMA_HTIF6 ((uint32_t)0x00400000) /* Channel 6 Half Transfer flag */ +#define DMA_TEIF6 ((uint32_t)0x00800000) /* Channel 6 Transfer Error flag */ +#define DMA_GIF7 ((uint32_t)0x01000000) /* Channel 7 Global interrupt flag */ +#define DMA_TCIF7 ((uint32_t)0x02000000) /* Channel 7 Transfer Complete flag */ +#define DMA_HTIF7 ((uint32_t)0x04000000) /* Channel 7 Half Transfer flag */ +#define DMA_TEIF7 ((uint32_t)0x08000000) /* Channel 7 Transfer Error flag */ +#define DMA_GIF8 ((uint32_t)0x10000000) /* Channel 8 Global interrupt flag */ +#define DMA_TCIF8 ((uint32_t)0x20000000) /* Channel 8 Transfer Complete flag */ +#define DMA_HTIF8 ((uint32_t)0x40000000) /* Channel 8 Half Transfer flag */ +#define DMA_TEIF8 ((uint32_t)0x80000000) /* Channel 8 Transfer Error flag */ + +/******************* Bit definition for DMA_INTFCR register *******************/ +#define DMA_CGIF1 ((uint32_t)0x00000001) /* Channel 1 Global interrupt clear */ +#define DMA_CTCIF1 ((uint32_t)0x00000002) /* Channel 1 Transfer Complete clear */ +#define DMA_CHTIF1 ((uint32_t)0x00000004) /* Channel 1 Half Transfer clear */ +#define DMA_CTEIF1 ((uint32_t)0x00000008) /* Channel 1 Transfer Error clear */ +#define DMA_CGIF2 ((uint32_t)0x00000010) /* Channel 2 Global interrupt clear */ +#define DMA_CTCIF2 ((uint32_t)0x00000020) /* Channel 2 Transfer Complete clear */ +#define DMA_CHTIF2 ((uint32_t)0x00000040) /* Channel 2 Half Transfer clear */ +#define DMA_CTEIF2 ((uint32_t)0x00000080) /* Channel 2 Transfer Error clear */ +#define DMA_CGIF3 ((uint32_t)0x00000100) /* Channel 3 Global interrupt clear */ +#define DMA_CTCIF3 ((uint32_t)0x00000200) /* Channel 3 Transfer Complete clear */ +#define DMA_CHTIF3 ((uint32_t)0x00000400) /* Channel 3 Half Transfer clear */ +#define DMA_CTEIF3 ((uint32_t)0x00000800) /* Channel 3 Transfer Error clear */ +#define DMA_CGIF4 ((uint32_t)0x00001000) /* Channel 4 Global interrupt clear */ +#define DMA_CTCIF4 ((uint32_t)0x00002000) /* Channel 4 Transfer Complete clear */ +#define DMA_CHTIF4 ((uint32_t)0x00004000) /* Channel 4 Half Transfer clear */ +#define DMA_CTEIF4 ((uint32_t)0x00008000) /* Channel 4 Transfer Error clear */ +#define DMA_CGIF5 ((uint32_t)0x00010000) /* Channel 5 Global interrupt clear */ +#define DMA_CTCIF5 ((uint32_t)0x00020000) /* Channel 5 Transfer Complete clear */ +#define DMA_CHTIF5 ((uint32_t)0x00040000) /* Channel 5 Half Transfer clear */ +#define DMA_CTEIF5 ((uint32_t)0x00080000) /* Channel 5 Transfer Error clear */ +#define DMA_CGIF6 ((uint32_t)0x00100000) /* Channel 6 Global interrupt clear */ +#define DMA_CTCIF6 ((uint32_t)0x00200000) /* Channel 6 Transfer Complete clear */ +#define DMA_CHTIF6 ((uint32_t)0x00400000) /* Channel 6 Half Transfer clear */ +#define DMA_CTEIF6 ((uint32_t)0x00800000) /* Channel 6 Transfer Error clear */ +#define DMA_CGIF7 ((uint32_t)0x01000000) /* Channel 7 Global interrupt clear */ +#define DMA_CTCIF7 ((uint32_t)0x02000000) /* Channel 7 Transfer Complete clear */ +#define DMA_CHTIF7 ((uint32_t)0x04000000) /* Channel 7 Half Transfer clear */ +#define DMA_CTEIF7 ((uint32_t)0x08000000) /* Channel 7 Transfer Error clear */ +#define DMA_CGIF8 ((uint32_t)0x10000000) /* Channel 8 Global interrupt clear */ +#define DMA_CTCIF8 ((uint32_t)0x20000000) /* Channel 8 Transfer Complete clear */ +#define DMA_CHTIF8 ((uint32_t)0x40000000) /* Channel 8 Half Transfer clear */ +#define DMA_CTEIF8 ((uint32_t)0x80000000) /* Channel 8 Transfer Error clear */ + +/******************* Bit definition for DMA_CFGR1 register *******************/ +#define DMA_CFGR1_EN ((uint16_t)0x0001) /* Channel enable*/ +#define DMA_CFGR1_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */ +#define DMA_CFGR1_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */ +#define DMA_CFGR1_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */ +#define DMA_CFGR1_DIR ((uint16_t)0x0010) /* Data transfer direction */ +#define DMA_CFGR1_CIRC ((uint16_t)0x0020) /* Circular mode */ +#define DMA_CFGR1_PINC ((uint16_t)0x0040) /* Peripheral increment mode */ +#define DMA_CFGR1_MINC ((uint16_t)0x0080) /* Memory increment mode */ + +#define DMA_CFGR1_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CFGR1_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */ +#define DMA_CFGR1_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */ + +#define DMA_CFGR1_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */ +#define DMA_CFGR1_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */ +#define DMA_CFGR1_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */ + +#define DMA_CFGR1_PL ((uint16_t)0x3000) /* PL[1:0] bits(Channel Priority level) */ +#define DMA_CFGR1_PL_0 ((uint16_t)0x1000) /* Bit 0 */ +#define DMA_CFGR1_PL_1 ((uint16_t)0x2000) /* Bit 1 */ + +#define DMA_CFGR1_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode */ + +/******************* Bit definition for DMA_CFGR2 register *******************/ +#define DMA_CFGR2_EN ((uint16_t)0x0001) /* Channel enable */ +#define DMA_CFGR2_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */ +#define DMA_CFGR2_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */ +#define DMA_CFGR2_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */ +#define DMA_CFGR2_DIR ((uint16_t)0x0010) /* Data transfer direction */ +#define DMA_CFGR2_CIRC ((uint16_t)0x0020) /* Circular mode */ +#define DMA_CFGR2_PINC ((uint16_t)0x0040) /* Peripheral increment mode */ +#define DMA_CFGR2_MINC ((uint16_t)0x0080) /* Memory increment mode */ + +#define DMA_CFGR2_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CFGR2_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */ +#define DMA_CFGR2_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */ + +#define DMA_CFGR2_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */ +#define DMA_CFGR2_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */ +#define DMA_CFGR2_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */ + +#define DMA_CFGR2_PL ((uint16_t)0x3000) /* PL[1:0] bits (Channel Priority level) */ +#define DMA_CFGR2_PL_0 ((uint16_t)0x1000) /* Bit 0 */ +#define DMA_CFGR2_PL_1 ((uint16_t)0x2000) /* Bit 1 */ + +#define DMA_CFGR2_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode */ + +/******************* Bit definition for DMA_CFGR3 register *******************/ +#define DMA_CFGR3_EN ((uint16_t)0x0001) /* Channel enable */ +#define DMA_CFGR3_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */ +#define DMA_CFGR3_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */ +#define DMA_CFGR3_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */ +#define DMA_CFGR3_DIR ((uint16_t)0x0010) /* Data transfer direction */ +#define DMA_CFGR3_CIRC ((uint16_t)0x0020) /* Circular mode */ +#define DMA_CFGR3_PINC ((uint16_t)0x0040) /* Peripheral increment mode */ +#define DMA_CFGR3_MINC ((uint16_t)0x0080) /* Memory increment mode */ + +#define DMA_CFGR3_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CFGR3_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */ +#define DMA_CFGR3_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */ + +#define DMA_CFGR3_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */ +#define DMA_CFGR3_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */ +#define DMA_CFGR3_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */ + +#define DMA_CFGR3_PL ((uint16_t)0x3000) /* PL[1:0] bits (Channel Priority level) */ +#define DMA_CFGR3_PL_0 ((uint16_t)0x1000) /* Bit 0 */ +#define DMA_CFGR3_PL_1 ((uint16_t)0x2000) /* Bit 1 */ + +#define DMA_CFGR3_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode */ + +/******************* Bit definition for DMA_CFG4 register *******************/ +#define DMA_CFG4_EN ((uint16_t)0x0001) /* Channel enable */ +#define DMA_CFG4_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */ +#define DMA_CFG4_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */ +#define DMA_CFG4_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */ +#define DMA_CFG4_DIR ((uint16_t)0x0010) /* Data transfer direction */ +#define DMA_CFG4_CIRC ((uint16_t)0x0020) /* Circular mode */ +#define DMA_CFG4_PINC ((uint16_t)0x0040) /* Peripheral increment mode */ +#define DMA_CFG4_MINC ((uint16_t)0x0080) /* Memory increment mode */ + +#define DMA_CFG4_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CFG4_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */ +#define DMA_CFG4_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */ + +#define DMA_CFG4_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */ +#define DMA_CFG4_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */ +#define DMA_CFG4_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */ + +#define DMA_CFG4_PL ((uint16_t)0x3000) /* PL[1:0] bits (Channel Priority level) */ +#define DMA_CFG4_PL_0 ((uint16_t)0x1000) /* Bit 0 */ +#define DMA_CFG4_PL_1 ((uint16_t)0x2000) /* Bit 1 */ + +#define DMA_CFG4_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode */ + +/****************** Bit definition for DMA_CFG5 register *******************/ +#define DMA_CFG5_EN ((uint16_t)0x0001) /* Channel enable */ +#define DMA_CFG5_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */ +#define DMA_CFG5_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */ +#define DMA_CFG5_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */ +#define DMA_CFG5_DIR ((uint16_t)0x0010) /* Data transfer direction */ +#define DMA_CFG5_CIRC ((uint16_t)0x0020) /* Circular mode */ +#define DMA_CFG5_PINC ((uint16_t)0x0040) /* Peripheral increment mode */ +#define DMA_CFG5_MINC ((uint16_t)0x0080) /* Memory increment mode */ + +#define DMA_CFG5_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CFG5_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */ +#define DMA_CFG5_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */ + +#define DMA_CFG5_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */ +#define DMA_CFG5_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */ +#define DMA_CFG5_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */ + +#define DMA_CFG5_PL ((uint16_t)0x3000) /* PL[1:0] bits (Channel Priority level) */ +#define DMA_CFG5_PL_0 ((uint16_t)0x1000) /* Bit 0 */ +#define DMA_CFG5_PL_1 ((uint16_t)0x2000) /* Bit 1 */ + +#define DMA_CFG5_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode enable */ + +/******************* Bit definition for DMA_CFG6 register *******************/ +#define DMA_CFG6_EN ((uint16_t)0x0001) /* Channel enable */ +#define DMA_CFG6_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */ +#define DMA_CFG6_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */ +#define DMA_CFG6_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */ +#define DMA_CFG6_DIR ((uint16_t)0x0010) /* Data transfer direction */ +#define DMA_CFG6_CIRC ((uint16_t)0x0020) /* Circular mode */ +#define DMA_CFG6_PINC ((uint16_t)0x0040) /* Peripheral increment mode */ +#define DMA_CFG6_MINC ((uint16_t)0x0080) /* Memory increment mode */ + +#define DMA_CFG6_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CFG6_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */ +#define DMA_CFG6_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */ + +#define DMA_CFG6_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */ +#define DMA_CFG6_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */ +#define DMA_CFG6_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */ + +#define DMA_CFG6_PL ((uint16_t)0x3000) /* PL[1:0] bits (Channel Priority level) */ +#define DMA_CFG6_PL_0 ((uint16_t)0x1000) /* Bit 0 */ +#define DMA_CFG6_PL_1 ((uint16_t)0x2000) /* Bit 1 */ + +#define DMA_CFG6_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode */ + +/******************* Bit definition for DMA_CFG7 register *******************/ +#define DMA_CFG7_EN ((uint16_t)0x0001) /* Channel enable */ +#define DMA_CFG7_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */ +#define DMA_CFG7_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */ +#define DMA_CFG7_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */ +#define DMA_CFG7_DIR ((uint16_t)0x0010) /* Data transfer direction */ +#define DMA_CFG7_CIRC ((uint16_t)0x0020) /* Circular mode */ +#define DMA_CFG7_PINC ((uint16_t)0x0040) /* Peripheral increment mode */ +#define DMA_CFG7_MINC ((uint16_t)0x0080) /* Memory increment mode */ + +#define DMA_CFG7_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CFG7_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */ +#define DMA_CFG7_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */ + +#define DMA_CFG7_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */ +#define DMA_CFG7_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */ +#define DMA_CFG7_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */ + +#define DMA_CFG7_PL ((uint16_t)0x3000) /* PL[1:0] bits (Channel Priority level) */ +#define DMA_CFG7_PL_0 ((uint16_t)0x1000) /* Bit 0 */ +#define DMA_CFG7_PL_1 ((uint16_t)0x2000) /* Bit 1 */ + +#define DMA_CFG7_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode enable */ + +/****************** Bit definition for DMA_CNTR1 register ******************/ +#define DMA_CNTR1_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */ + +/****************** Bit definition for DMA_CNTR2 register ******************/ +#define DMA_CNTR2_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */ + +/****************** Bit definition for DMA_CNTR3 register ******************/ +#define DMA_CNTR3_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */ + +/****************** Bit definition for DMA_CNTR4 register ******************/ +#define DMA_CNTR4_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */ + +/****************** Bit definition for DMA_CNTR5 register ******************/ +#define DMA_CNTR5_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */ + +/****************** Bit definition for DMA_CNTR6 register ******************/ +#define DMA_CNTR6_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */ + +/****************** Bit definition for DMA_CNTR7 register ******************/ +#define DMA_CNTR7_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */ + +/****************** Bit definition for DMA_CNTR8 register ******************/ +#define DMA_CNTR8_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */ + +/****************** Bit definition for DMA_PADDR1 register *******************/ +#define DMA_PADDR1_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */ + +/****************** Bit definition for DMA_PADDR2 register *******************/ +#define DMA_PADDR2_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */ + +/****************** Bit definition for DMA_PADDR3 register *******************/ +#define DMA_PADDR3_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */ + +/****************** Bit definition for DMA_PADDR4 register *******************/ +#define DMA_PADDR4_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */ + +/****************** Bit definition for DMA_PADDR5 register *******************/ +#define DMA_PADDR5_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */ + +/****************** Bit definition for DMA_PADDR6 register *******************/ +#define DMA_PADDR6_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */ + +/****************** Bit definition for DMA_PADDR7 register *******************/ +#define DMA_PADDR7_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */ + +/****************** Bit definition for DMA_PADDR8 register *******************/ +#define DMA_PADDR8_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */ + +/****************** Bit definition for DMA_MADDR1 register *******************/ +#define DMA_MADDR1_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */ + +/****************** Bit definition for DMA_MADDR2 register *******************/ +#define DMA_MADDR2_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */ + +/****************** Bit definition for DMA_MADDR3 register *******************/ +#define DMA_MADDR3_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */ + +/****************** Bit definition for DMA_MADDR4 register *******************/ +#define DMA_MADDR4_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */ + +/****************** Bit definition for DMA_MADDR5 register *******************/ +#define DMA_MADDR5_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */ + +/****************** Bit definition for DMA_MADDR6 register *******************/ +#define DMA_MADDR6_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */ + +/****************** Bit definition for DMA_MADDR7 register *******************/ +#define DMA_MADDR7_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */ + +/****************** Bit definition for DMA_MADDR8 register *******************/ +#define DMA_MADDR8_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */ + +/******************************************************************************/ +/* External Interrupt/Event Controller */ +/******************************************************************************/ + +/******************* Bit definition for EXTI_INTENR register *******************/ +#define EXTI_INTENR_MR0 ((uint32_t)0x00000001) /* Interrupt Mask on line 0 */ +#define EXTI_INTENR_MR1 ((uint32_t)0x00000002) /* Interrupt Mask on line 1 */ +#define EXTI_INTENR_MR2 ((uint32_t)0x00000004) /* Interrupt Mask on line 2 */ +#define EXTI_INTENR_MR3 ((uint32_t)0x00000008) /* Interrupt Mask on line 3 */ +#define EXTI_INTENR_MR4 ((uint32_t)0x00000010) /* Interrupt Mask on line 4 */ +#define EXTI_INTENR_MR5 ((uint32_t)0x00000020) /* Interrupt Mask on line 5 */ +#define EXTI_INTENR_MR6 ((uint32_t)0x00000040) /* Interrupt Mask on line 6 */ +#define EXTI_INTENR_MR7 ((uint32_t)0x00000080) /* Interrupt Mask on line 7 */ +#define EXTI_INTENR_MR8 ((uint32_t)0x00000100) /* Interrupt Mask on line 8 */ +#define EXTI_INTENR_MR9 ((uint32_t)0x00000200) /* Interrupt Mask on line 9 */ +#define EXTI_INTENR_MR10 ((uint32_t)0x00000400) /* Interrupt Mask on line 10 */ +#define EXTI_INTENR_MR11 ((uint32_t)0x00000800) /* Interrupt Mask on line 11 */ +#define EXTI_INTENR_MR12 ((uint32_t)0x00001000) /* Interrupt Mask on line 12 */ +#define EXTI_INTENR_MR13 ((uint32_t)0x00002000) /* Interrupt Mask on line 13 */ +#define EXTI_INTENR_MR14 ((uint32_t)0x00004000) /* Interrupt Mask on line 14 */ +#define EXTI_INTENR_MR15 ((uint32_t)0x00008000) /* Interrupt Mask on line 15 */ +#define EXTI_INTENR_MR16 ((uint32_t)0x00010000) /* Interrupt Mask on line 16 */ +#define EXTI_INTENR_MR17 ((uint32_t)0x00020000) /* Interrupt Mask on line 17 */ +#define EXTI_INTENR_MR18 ((uint32_t)0x00040000) /* Interrupt Mask on line 18 */ +#define EXTI_INTENR_MR19 ((uint32_t)0x00080000) /* Interrupt Mask on line 19 */ +#define EXTI_INTENR_MR20 ((uint32_t)0x00100000) /* Interrupt Mask on line 20 */ +#define EXTI_INTENR_MR21 ((uint32_t)0x00200000) /* Interrupt Mask on line 21 */ +#define EXTI_INTENR_MR22 ((uint32_t)0x00400000) /* Interrupt Mask on line 22 */ + +/******************* Bit definition for EXTI_EVENR register *******************/ +#define EXTI_EVENR_MR0 ((uint32_t)0x00000001) /* Event Mask on line 0 */ +#define EXTI_EVENR_MR1 ((uint32_t)0x00000002) /* Event Mask on line 1 */ +#define EXTI_EVENR_MR2 ((uint32_t)0x00000004) /* Event Mask on line 2 */ +#define EXTI_EVENR_MR3 ((uint32_t)0x00000008) /* Event Mask on line 3 */ +#define EXTI_EVENR_MR4 ((uint32_t)0x00000010) /* Event Mask on line 4 */ +#define EXTI_EVENR_MR5 ((uint32_t)0x00000020) /* Event Mask on line 5 */ +#define EXTI_EVENR_MR6 ((uint32_t)0x00000040) /* Event Mask on line 6 */ +#define EXTI_EVENR_MR7 ((uint32_t)0x00000080) /* Event Mask on line 7 */ +#define EXTI_EVENR_MR8 ((uint32_t)0x00000100) /* Event Mask on line 8 */ +#define EXTI_EVENR_MR9 ((uint32_t)0x00000200) /* Event Mask on line 9 */ +#define EXTI_EVENR_MR10 ((uint32_t)0x00000400) /* Event Mask on line 10 */ +#define EXTI_EVENR_MR11 ((uint32_t)0x00000800) /* Event Mask on line 11 */ +#define EXTI_EVENR_MR12 ((uint32_t)0x00001000) /* Event Mask on line 12 */ +#define EXTI_EVENR_MR13 ((uint32_t)0x00002000) /* Event Mask on line 13 */ +#define EXTI_EVENR_MR14 ((uint32_t)0x00004000) /* Event Mask on line 14 */ +#define EXTI_EVENR_MR15 ((uint32_t)0x00008000) /* Event Mask on line 15 */ +#define EXTI_EVENR_MR16 ((uint32_t)0x00010000) /* Event Mask on line 16 */ +#define EXTI_EVENR_MR17 ((uint32_t)0x00020000) /* Event Mask on line 17 */ +#define EXTI_EVENR_MR18 ((uint32_t)0x00040000) /* Event Mask on line 18 */ +#define EXTI_EVENR_MR19 ((uint32_t)0x00080000) /* Event Mask on line 19 */ +#define EXTI_EVENR_MR20 ((uint32_t)0x00100000) /* Event Mask on line 20 */ +#define EXTI_EVENR_MR21 ((uint32_t)0x00200000) /* Event Mask on line 21 */ +#define EXTI_EVENR_MR22 ((uint32_t)0x00400000) /* Event Mask on line 22 */ + +/****************** Bit definition for EXTI_RTENR register *******************/ +#define EXTI_RTENR_TR0 ((uint32_t)0x00000001) /* Rising trigger event configuration bit of line 0 */ +#define EXTI_RTENR_TR1 ((uint32_t)0x00000002) /* Rising trigger event configuration bit of line 1 */ +#define EXTI_RTENR_TR2 ((uint32_t)0x00000004) /* Rising trigger event configuration bit of line 2 */ +#define EXTI_RTENR_TR3 ((uint32_t)0x00000008) /* Rising trigger event configuration bit of line 3 */ +#define EXTI_RTENR_TR4 ((uint32_t)0x00000010) /* Rising trigger event configuration bit of line 4 */ +#define EXTI_RTENR_TR5 ((uint32_t)0x00000020) /* Rising trigger event configuration bit of line 5 */ +#define EXTI_RTENR_TR6 ((uint32_t)0x00000040) /* Rising trigger event configuration bit of line 6 */ +#define EXTI_RTENR_TR7 ((uint32_t)0x00000080) /* Rising trigger event configuration bit of line 7 */ +#define EXTI_RTENR_TR8 ((uint32_t)0x00000100) /* Rising trigger event configuration bit of line 8 */ +#define EXTI_RTENR_TR9 ((uint32_t)0x00000200) /* Rising trigger event configuration bit of line 9 */ +#define EXTI_RTENR_TR10 ((uint32_t)0x00000400) /* Rising trigger event configuration bit of line 10 */ +#define EXTI_RTENR_TR11 ((uint32_t)0x00000800) /* Rising trigger event configuration bit of line 11 */ +#define EXTI_RTENR_TR12 ((uint32_t)0x00001000) /* Rising trigger event configuration bit of line 12 */ +#define EXTI_RTENR_TR13 ((uint32_t)0x00002000) /* Rising trigger event configuration bit of line 13 */ +#define EXTI_RTENR_TR14 ((uint32_t)0x00004000) /* Rising trigger event configuration bit of line 14 */ +#define EXTI_RTENR_TR15 ((uint32_t)0x00008000) /* Rising trigger event configuration bit of line 15 */ +#define EXTI_RTENR_TR16 ((uint32_t)0x00010000) /* Rising trigger event configuration bit of line 16 */ +#define EXTI_RTENR_TR17 ((uint32_t)0x00020000) /* Rising trigger event configuration bit of line 17 */ +#define EXTI_RTENR_TR18 ((uint32_t)0x00040000) /* Rising trigger event configuration bit of line 18 */ +#define EXTI_RTENR_TR19 ((uint32_t)0x00080000) /* Rising trigger event configuration bit of line 19 */ +#define EXTI_RTENR_TR20 ((uint32_t)0x00100000) /* Rising trigger event configuration bit of line 20 */ +#define EXTI_RTENR_TR21 ((uint32_t)0x00200000) /* Rising trigger event configuration bit of line 21 */ +#define EXTI_RTENR_TR22 ((uint32_t)0x00400000) /* Rising trigger event configuration bit of line 22 */ + +/****************** Bit definition for EXTI_FTENR register *******************/ +#define EXTI_FTENR_TR0 ((uint32_t)0x00000001) /* Falling trigger event configuration bit of line 0 */ +#define EXTI_FTENR_TR1 ((uint32_t)0x00000002) /* Falling trigger event configuration bit of line 1 */ +#define EXTI_FTENR_TR2 ((uint32_t)0x00000004) /* Falling trigger event configuration bit of line 2 */ +#define EXTI_FTENR_TR3 ((uint32_t)0x00000008) /* Falling trigger event configuration bit of line 3 */ +#define EXTI_FTENR_TR4 ((uint32_t)0x00000010) /* Falling trigger event configuration bit of line 4 */ +#define EXTI_FTENR_TR5 ((uint32_t)0x00000020) /* Falling trigger event configuration bit of line 5 */ +#define EXTI_FTENR_TR6 ((uint32_t)0x00000040) /* Falling trigger event configuration bit of line 6 */ +#define EXTI_FTENR_TR7 ((uint32_t)0x00000080) /* Falling trigger event configuration bit of line 7 */ +#define EXTI_FTENR_TR8 ((uint32_t)0x00000100) /* Falling trigger event configuration bit of line 8 */ +#define EXTI_FTENR_TR9 ((uint32_t)0x00000200) /* Falling trigger event configuration bit of line 9 */ +#define EXTI_FTENR_TR10 ((uint32_t)0x00000400) /* Falling trigger event configuration bit of line 10 */ +#define EXTI_FTENR_TR11 ((uint32_t)0x00000800) /* Falling trigger event configuration bit of line 11 */ +#define EXTI_FTENR_TR12 ((uint32_t)0x00001000) /* Falling trigger event configuration bit of line 12 */ +#define EXTI_FTENR_TR13 ((uint32_t)0x00002000) /* Falling trigger event configuration bit of line 13 */ +#define EXTI_FTENR_TR14 ((uint32_t)0x00004000) /* Falling trigger event configuration bit of line 14 */ +#define EXTI_FTENR_TR15 ((uint32_t)0x00008000) /* Falling trigger event configuration bit of line 15 */ +#define EXTI_FTENR_TR16 ((uint32_t)0x00010000) /* Falling trigger event configuration bit of line 16 */ +#define EXTI_FTENR_TR17 ((uint32_t)0x00020000) /* Falling trigger event configuration bit of line 17 */ +#define EXTI_FTENR_TR18 ((uint32_t)0x00040000) /* Falling trigger event configuration bit of line 18 */ +#define EXTI_FTENR_TR19 ((uint32_t)0x00080000) /* Falling trigger event configuration bit of line 19 */ +#define EXTI_FTENR_TR20 ((uint32_t)0x00100000) /* Falling trigger event configuration bit of line 20 */ +#define EXTI_FTENR_TR21 ((uint32_t)0x00200000) /* Falling trigger event configuration bit of line 21 */ +#define EXTI_FTENR_TR22 ((uint32_t)0x00400000) /* Falling trigger event configuration bit of line 22 */ + +/****************** Bit definition for EXTI_SWIEVR register ******************/ +#define EXTI_SWIEVR_SWIEVR0 ((uint32_t)0x00000001) /* Software Interrupt on line 0 */ +#define EXTI_SWIEVR_SWIEVR1 ((uint32_t)0x00000002) /* Software Interrupt on line 1 */ +#define EXTI_SWIEVR_SWIEVR2 ((uint32_t)0x00000004) /* Software Interrupt on line 2 */ +#define EXTI_SWIEVR_SWIEVR3 ((uint32_t)0x00000008) /* Software Interrupt on line 3 */ +#define EXTI_SWIEVR_SWIEVR4 ((uint32_t)0x00000010) /* Software Interrupt on line 4 */ +#define EXTI_SWIEVR_SWIEVR5 ((uint32_t)0x00000020) /* Software Interrupt on line 5 */ +#define EXTI_SWIEVR_SWIEVR6 ((uint32_t)0x00000040) /* Software Interrupt on line 6 */ +#define EXTI_SWIEVR_SWIEVR7 ((uint32_t)0x00000080) /* Software Interrupt on line 7 */ +#define EXTI_SWIEVR_SWIEVR8 ((uint32_t)0x00000100) /* Software Interrupt on line 8 */ +#define EXTI_SWIEVR_SWIEVR9 ((uint32_t)0x00000200) /* Software Interrupt on line 9 */ +#define EXTI_SWIEVR_SWIEVR10 ((uint32_t)0x00000400) /* Software Interrupt on line 10 */ +#define EXTI_SWIEVR_SWIEVR11 ((uint32_t)0x00000800) /* Software Interrupt on line 11 */ +#define EXTI_SWIEVR_SWIEVR12 ((uint32_t)0x00001000) /* Software Interrupt on line 12 */ +#define EXTI_SWIEVR_SWIEVR13 ((uint32_t)0x00002000) /* Software Interrupt on line 13 */ +#define EXTI_SWIEVR_SWIEVR14 ((uint32_t)0x00004000) /* Software Interrupt on line 14 */ +#define EXTI_SWIEVR_SWIEVR15 ((uint32_t)0x00008000) /* Software Interrupt on line 15 */ +#define EXTI_SWIEVR_SWIEVR16 ((uint32_t)0x00010000) /* Software Interrupt on line 16 */ +#define EXTI_SWIEVR_SWIEVR17 ((uint32_t)0x00020000) /* Software Interrupt on line 17 */ +#define EXTI_SWIEVR_SWIEVR18 ((uint32_t)0x00040000) /* Software Interrupt on line 18 */ +#define EXTI_SWIEVR_SWIEVR19 ((uint32_t)0x00080000) /* Software Interrupt on line 19 */ +#define EXTI_SWIEVR_SWIEVR20 ((uint32_t)0x00100000) /* Software Interrupt on line 20 */ +#define EXTI_SWIEVR_SWIEVR21 ((uint32_t)0x00200000) /* Software Interrupt on line 21 */ +#define EXTI_SWIEVR_SWIEVR22 ((uint32_t)0x00400000) /* Software Interrupt on line 22 */ + +/******************* Bit definition for EXTI_INTFR register ********************/ +#define EXTI_INTF_INTF0 ((uint32_t)0x00000001) /* Pending bit for line 0 */ +#define EXTI_INTF_INTF1 ((uint32_t)0x00000002) /* Pending bit for line 1 */ +#define EXTI_INTF_INTF2 ((uint32_t)0x00000004) /* Pending bit for line 2 */ +#define EXTI_INTF_INTF3 ((uint32_t)0x00000008) /* Pending bit for line 3 */ +#define EXTI_INTF_INTF4 ((uint32_t)0x00000010) /* Pending bit for line 4 */ +#define EXTI_INTF_INTF5 ((uint32_t)0x00000020) /* Pending bit for line 5 */ +#define EXTI_INTF_INTF6 ((uint32_t)0x00000040) /* Pending bit for line 6 */ +#define EXTI_INTF_INTF7 ((uint32_t)0x00000080) /* Pending bit for line 7 */ +#define EXTI_INTF_INTF8 ((uint32_t)0x00000100) /* Pending bit for line 8 */ +#define EXTI_INTF_INTF9 ((uint32_t)0x00000200) /* Pending bit for line 9 */ +#define EXTI_INTF_INTF10 ((uint32_t)0x00000400) /* Pending bit for line 10 */ +#define EXTI_INTF_INTF11 ((uint32_t)0x00000800) /* Pending bit for line 11 */ +#define EXTI_INTF_INTF12 ((uint32_t)0x00001000) /* Pending bit for line 12 */ +#define EXTI_INTF_INTF13 ((uint32_t)0x00002000) /* Pending bit for line 13 */ +#define EXTI_INTF_INTF14 ((uint32_t)0x00004000) /* Pending bit for line 14 */ +#define EXTI_INTF_INTF15 ((uint32_t)0x00008000) /* Pending bit for line 15 */ +#define EXTI_INTF_INTF16 ((uint32_t)0x00010000) /* Pending bit for line 16 */ +#define EXTI_INTF_INTF17 ((uint32_t)0x00020000) /* Pending bit for line 17 */ +#define EXTI_INTF_INTF18 ((uint32_t)0x00040000) /* Pending bit for line 18 */ +#define EXTI_INTF_INTF19 ((uint32_t)0x00080000) /* Pending bit for line 19 */ +#define EXTI_INTF_INTF20 ((uint32_t)0x00100000) /* Pending bit for line 20 */ +#define EXTI_INTF_INTF21 ((uint32_t)0x00200000) /* Pending bit for line 21 */ +#define EXTI_INTF_INTF22 ((uint32_t)0x00400000) /* Pending bit for line 22 */ + +/******************************************************************************/ +/* FLASH and Option Bytes Registers */ +/******************************************************************************/ + +/******************* Bit definition for FLASH_ACTLR register ******************/ +#define FLASH_ACTLR_LATENCY ((uint8_t)0x03) /* LATENCY[1:0] bits (Latency) */ +#define FLASH_ACTLR_LATENCY_0 ((uint8_t)0x00) /* Bit 0 */ +#define FLASH_ACTLR_LATENCY_1 ((uint8_t)0x01) /* Bit 0 */ +#define FLASH_ACTLR_LATENCY_2 ((uint8_t)0x02) /* Bit 1 */ + +/****************** Bit definition for FLASH_KEYR register ******************/ +#define FLASH_KEYR_FKEYR ((uint32_t)0xFFFFFFFF) /* FPEC Key */ + +/***************** Bit definition for FLASH_OBKEYR register ****************/ +#define FLASH_OBKEYR_OBKEYR ((uint32_t)0xFFFFFFFF) /* Option Byte Key */ + +/****************** Bit definition for FLASH_STATR register *******************/ +#define FLASH_STATR_BSY ((uint8_t)0x01) /* Busy */ +#define FLASH_STATR_WRPRTERR ((uint8_t)0x10) /* Write Protection Error */ +#define FLASH_STATR_EOP ((uint8_t)0x20) /* End of operation */ +#define FLASH_STATR_FWAKE_FLAG ((uint8_t)0x40) +#define FLASH_STATR_TURBO ((uint8_t)0x80) + +/******************* Bit definition for FLASH_CTLR register *******************/ +#define FLASH_CTLR_PER ((uint32_t)0x00000002) /* Sector Erase 1K */ +#define FLASH_CTLR_MER ((uint32_t)0x00000004) /* Mass Erase */ +#define FLASH_CTLR_OBER ((uint32_t)0x00000020) /* Option Byte Erase */ +#define FLASH_CTLR_STRT ((uint32_t)0x00000040) /* Start */ +#define FLASH_CTLR_LOCK ((uint32_t)0x00000080) /* Lock */ +#define FLASH_CTLR_OBWRE ((uint32_t)0x00000200) /* Option Bytes Write Enable */ +#define FLASH_CTLR_ERRIE ((uint32_t)0x00000400) /* Error Interrupt Enable */ +#define FLASH_CTLR_EOPIE ((uint32_t)0x00001000) /* End of operation interrupt enable */ +#define FLASH_CTLR_FWAKEIE ((uint32_t)0x00002000) +#define FLASH_CTLR_FLOCK ((uint32_t)0x00008000) /* Fast Lock */ +#define FLASH_CTLR_FTPG ((uint32_t)0x00010000) /* Page Programming 256Byte */ +#define FLASH_CTLR_FTER ((uint32_t)0x00020000) /* Page Erase 256Byte */ +#define FLASH_CTLR_BUFLOAD ((uint32_t)0x00040000) +#define FLASH_CTLR_BUFRST ((uint32_t)0x00080000) +#define FLASH_CTLR_BER32 ((uint32_t)0x00800000) /* Block Erase 32K */ + +/******************* Bit definition for FLASH_ADDR register *******************/ +#define FLASH_ADDR_FAR ((uint32_t)0xFFFFFFFF) /* Flash Address */ + +/****************** Bit definition for FLASH_OBR register *******************/ +#define FLASH_OBR_OBERR ((uint32_t)0x00000001) /* Option Byte Error */ +#define FLASH_OBR_RDPRT ((uint32_t)0x00000002) /* Read protection */ + +#define FLASH_OBR_USER ((uint32_t)0x000000FC) /* User Option Bytes */ +#define FLASH_OBR_iWDG_SW ((uint32_t)0x00000004) /* WDG_SW */ +#define FLASH_OBR_STOP_nRST ((uint32_t)0x00000008) /* nRST_STOP */ +#define FLASH_OBR_STANDY_nRST ((uint32_t)0x00000010) /* nRST_STDBY */ +#define FLASH_OBR_CFGCANM ((uint32_t)0x00000080) + +#define FLASH_OBR_DATA0 ((uint32_t)0x0003FC00) /* DATA0 */ +#define FLASH_OBR_DATA1 ((uint32_t)0x03FC0000) /* DATA1 */ + +/****************** Bit definition for FLASH_WPR register ******************/ +#define FLASH_WPR_WRP ((uint32_t)0xFFFFFFFF) /* Write Protect */ + +/****************** Bit definition for FLASH_OBR_MODEKEYR register ******************/ +#define FLASH_OBR_MODEKEYR ((uint32_t)0xFFFFFFFF) + +/****************** Bit definition for FLASH_RDPR register *******************/ +#define FLASH_RDPR_RDPR ((uint32_t)0x000000FF) /* Read protection option byte */ +#define FLASH_RDPR_nRDPR ((uint32_t)0x0000FF00) /* Read protection complemented option byte */ + +/****************** Bit definition for FLASH_USER register ******************/ +#define FLASH_USER_USER ((uint32_t)0x00FF0000) /* User option byte */ +#define FLASH_USER_nUSER ((uint32_t)0xFF000000) /* User complemented option byte */ + +/****************** Bit definition for FLASH_Data0 register *****************/ +#define FLASH_Data0_Data0 ((uint32_t)0x000000FF) /* User data storage option byte */ +#define FLASH_Data0_nData0 ((uint32_t)0x0000FF00) /* User data storage complemented option byte */ + +/****************** Bit definition for FLASH_Data1 register *****************/ +#define FLASH_Data1_Data1 ((uint32_t)0x00FF0000) /* User data storage option byte */ +#define FLASH_Data1_nData1 ((uint32_t)0xFF000000) /* User data storage complemented option byte */ + +/****************** Bit definition for FLASH_WRPR0 register ******************/ +#define FLASH_WRPR0_WRPR0 ((uint32_t)0x000000FF) /* Flash memory write protection option bytes */ +#define FLASH_WRPR0_nWRPR0 ((uint32_t)0x0000FF00) /* Flash memory write protection complemented option bytes */ + +/****************** Bit definition for FLASH_WRPR1 register ******************/ +#define FLASH_WRPR1_WRPR1 ((uint32_t)0x00FF0000) /* Flash memory write protection option bytes */ +#define FLASH_WRPR1_nWRPR1 ((uint32_t)0xFF000000) /* Flash memory write protection complemented option bytes */ + +/****************** Bit definition for FLASH_WRPR2 register ******************/ +#define FLASH_WRPR2_WRPR2 ((uint32_t)0x000000FF) /* Flash memory write protection option bytes */ +#define FLASH_WRPR2_nWRPR2 ((uint32_t)0x0000FF00) /* Flash memory write protection complemented option bytes */ + +/****************** Bit definition for FLASH_WRPR3 register ******************/ +#define FLASH_WRPR3_WRPR3 ((uint32_t)0x00FF0000) /* Flash memory write protection option bytes */ +#define FLASH_WRPR3_nWRPR3 ((uint32_t)0xFF000000) /* Flash memory write protection complemented option bytes */ + +/******************************************************************************/ +/* General Purpose and Alternate Function I/O */ +/******************************************************************************/ + +/******************* Bit definition for GPIO_CFGLR register *******************/ +#define GPIO_CFGLR_MODE ((uint32_t)0x33333333) /* Port x mode bits */ + +#define GPIO_CFGLR_MODE0 ((uint32_t)0x00000003) /* MODE0[1:0] bits (Port x mode bits, pin 0) */ +#define GPIO_CFGLR_MODE0_0 ((uint32_t)0x00000001) /* Bit 0 */ +#define GPIO_CFGLR_MODE0_1 ((uint32_t)0x00000002) /* Bit 1 */ + +#define GPIO_CFGLR_MODE1 ((uint32_t)0x00000030) /* MODE1[1:0] bits (Port x mode bits, pin 1) */ +#define GPIO_CFGLR_MODE1_0 ((uint32_t)0x00000010) /* Bit 0 */ +#define GPIO_CFGLR_MODE1_1 ((uint32_t)0x00000020) /* Bit 1 */ + +#define GPIO_CFGLR_MODE2 ((uint32_t)0x00000300) /* MODE2[1:0] bits (Port x mode bits, pin 2) */ +#define GPIO_CFGLR_MODE2_0 ((uint32_t)0x00000100) /* Bit 0 */ +#define GPIO_CFGLR_MODE2_1 ((uint32_t)0x00000200) /* Bit 1 */ + +#define GPIO_CFGLR_MODE3 ((uint32_t)0x00003000) /* MODE3[1:0] bits (Port x mode bits, pin 3) */ +#define GPIO_CFGLR_MODE3_0 ((uint32_t)0x00001000) /* Bit 0 */ +#define GPIO_CFGLR_MODE3_1 ((uint32_t)0x00002000) /* Bit 1 */ + +#define GPIO_CFGLR_MODE4 ((uint32_t)0x00030000) /* MODE4[1:0] bits (Port x mode bits, pin 4) */ +#define GPIO_CFGLR_MODE4_0 ((uint32_t)0x00010000) /* Bit 0 */ +#define GPIO_CFGLR_MODE4_1 ((uint32_t)0x00020000) /* Bit 1 */ + +#define GPIO_CFGLR_MODE5 ((uint32_t)0x00300000) /* MODE5[1:0] bits (Port x mode bits, pin 5) */ +#define GPIO_CFGLR_MODE5_0 ((uint32_t)0x00100000) /* Bit 0 */ +#define GPIO_CFGLR_MODE5_1 ((uint32_t)0x00200000) /* Bit 1 */ + +#define GPIO_CFGLR_MODE6 ((uint32_t)0x03000000) /* MODE6[1:0] bits (Port x mode bits, pin 6) */ +#define GPIO_CFGLR_MODE6_0 ((uint32_t)0x01000000) /* Bit 0 */ +#define GPIO_CFGLR_MODE6_1 ((uint32_t)0x02000000) /* Bit 1 */ + +#define GPIO_CFGLR_MODE7 ((uint32_t)0x30000000) /* MODE7[1:0] bits (Port x mode bits, pin 7) */ +#define GPIO_CFGLR_MODE7_0 ((uint32_t)0x10000000) /* Bit 0 */ +#define GPIO_CFGLR_MODE7_1 ((uint32_t)0x20000000) /* Bit 1 */ + +#define GPIO_CFGLR_CNF ((uint32_t)0xCCCCCCCC) /* Port x configuration bits */ + +#define GPIO_CFGLR_CNF0 ((uint32_t)0x0000000C) /* CNF0[1:0] bits (Port x configuration bits, pin 0) */ +#define GPIO_CFGLR_CNF0_0 ((uint32_t)0x00000004) /* Bit 0 */ +#define GPIO_CFGLR_CNF0_1 ((uint32_t)0x00000008) /* Bit 1 */ + +#define GPIO_CFGLR_CNF1 ((uint32_t)0x000000C0) /* CNF1[1:0] bits (Port x configuration bits, pin 1) */ +#define GPIO_CFGLR_CNF1_0 ((uint32_t)0x00000040) /* Bit 0 */ +#define GPIO_CFGLR_CNF1_1 ((uint32_t)0x00000080) /* Bit 1 */ + +#define GPIO_CFGLR_CNF2 ((uint32_t)0x00000C00) /* CNF2[1:0] bits (Port x configuration bits, pin 2) */ +#define GPIO_CFGLR_CNF2_0 ((uint32_t)0x00000400) /* Bit 0 */ +#define GPIO_CFGLR_CNF2_1 ((uint32_t)0x00000800) /* Bit 1 */ + +#define GPIO_CFGLR_CNF3 ((uint32_t)0x0000C000) /* CNF3[1:0] bits (Port x configuration bits, pin 3) */ +#define GPIO_CFGLR_CNF3_0 ((uint32_t)0x00004000) /* Bit 0 */ +#define GPIO_CFGLR_CNF3_1 ((uint32_t)0x00008000) /* Bit 1 */ + +#define GPIO_CFGLR_CNF4 ((uint32_t)0x000C0000) /* CNF4[1:0] bits (Port x configuration bits, pin 4) */ +#define GPIO_CFGLR_CNF4_0 ((uint32_t)0x00040000) /* Bit 0 */ +#define GPIO_CFGLR_CNF4_1 ((uint32_t)0x00080000) /* Bit 1 */ + +#define GPIO_CFGLR_CNF5 ((uint32_t)0x00C00000) /* CNF5[1:0] bits (Port x configuration bits, pin 5) */ +#define GPIO_CFGLR_CNF5_0 ((uint32_t)0x00400000) /* Bit 0 */ +#define GPIO_CFGLR_CNF5_1 ((uint32_t)0x00800000) /* Bit 1 */ + +#define GPIO_CFGLR_CNF6 ((uint32_t)0x0C000000) /* CNF6[1:0] bits (Port x configuration bits, pin 6) */ +#define GPIO_CFGLR_CNF6_0 ((uint32_t)0x04000000) /* Bit 0 */ +#define GPIO_CFGLR_CNF6_1 ((uint32_t)0x08000000) /* Bit 1 */ + +#define GPIO_CFGLR_CNF7 ((uint32_t)0xC0000000) /* CNF7[1:0] bits (Port x configuration bits, pin 7) */ +#define GPIO_CFGLR_CNF7_0 ((uint32_t)0x40000000) /* Bit 0 */ +#define GPIO_CFGLR_CNF7_1 ((uint32_t)0x80000000) /* Bit 1 */ + +/******************* Bit definition for GPIO_CFGHR register *******************/ +#define GPIO_CFGHR_MODE ((uint32_t)0x33333333) /* Port x mode bits */ + +#define GPIO_CFGHR_MODE8 ((uint32_t)0x00000003) /* MODE8[1:0] bits (Port x mode bits, pin 8) */ +#define GPIO_CFGHR_MODE8_0 ((uint32_t)0x00000001) /* Bit 0 */ +#define GPIO_CFGHR_MODE8_1 ((uint32_t)0x00000002) /* Bit 1 */ + +#define GPIO_CFGHR_MODE9 ((uint32_t)0x00000030) /* MODE9[1:0] bits (Port x mode bits, pin 9) */ +#define GPIO_CFGHR_MODE9_0 ((uint32_t)0x00000010) /* Bit 0 */ +#define GPIO_CFGHR_MODE9_1 ((uint32_t)0x00000020) /* Bit 1 */ + +#define GPIO_CFGHR_MODE10 ((uint32_t)0x00000300) /* MODE10[1:0] bits (Port x mode bits, pin 10) */ +#define GPIO_CFGHR_MODE10_0 ((uint32_t)0x00000100) /* Bit 0 */ +#define GPIO_CFGHR_MODE10_1 ((uint32_t)0x00000200) /* Bit 1 */ + +#define GPIO_CFGHR_MODE11 ((uint32_t)0x00003000) /* MODE11[1:0] bits (Port x mode bits, pin 11) */ +#define GPIO_CFGHR_MODE11_0 ((uint32_t)0x00001000) /* Bit 0 */ +#define GPIO_CFGHR_MODE11_1 ((uint32_t)0x00002000) /* Bit 1 */ + +#define GPIO_CFGHR_MODE12 ((uint32_t)0x00030000) /* MODE12[1:0] bits (Port x mode bits, pin 12) */ +#define GPIO_CFGHR_MODE12_0 ((uint32_t)0x00010000) /* Bit 0 */ +#define GPIO_CFGHR_MODE12_1 ((uint32_t)0x00020000) /* Bit 1 */ + +#define GPIO_CFGHR_MODE13 ((uint32_t)0x00300000) /* MODE13[1:0] bits (Port x mode bits, pin 13) */ +#define GPIO_CFGHR_MODE13_0 ((uint32_t)0x00100000) /* Bit 0 */ +#define GPIO_CFGHR_MODE13_1 ((uint32_t)0x00200000) /* Bit 1 */ + +#define GPIO_CFGHR_MODE14 ((uint32_t)0x03000000) /* MODE14[1:0] bits (Port x mode bits, pin 14) */ +#define GPIO_CFGHR_MODE14_0 ((uint32_t)0x01000000) /* Bit 0 */ +#define GPIO_CFGHR_MODE14_1 ((uint32_t)0x02000000) /* Bit 1 */ + +#define GPIO_CFGHR_MODE15 ((uint32_t)0x30000000) /* MODE15[1:0] bits (Port x mode bits, pin 15) */ +#define GPIO_CFGHR_MODE15_0 ((uint32_t)0x10000000) /* Bit 0 */ +#define GPIO_CFGHR_MODE15_1 ((uint32_t)0x20000000) /* Bit 1 */ + +#define GPIO_CFGHR_CNF ((uint32_t)0xCCCCCCCC) /* Port x configuration bits */ + +#define GPIO_CFGHR_CNF8 ((uint32_t)0x0000000C) /* CNF8[1:0] bits (Port x configuration bits, pin 8) */ +#define GPIO_CFGHR_CNF8_0 ((uint32_t)0x00000004) /* Bit 0 */ +#define GPIO_CFGHR_CNF8_1 ((uint32_t)0x00000008) /* Bit 1 */ + +#define GPIO_CFGHR_CNF9 ((uint32_t)0x000000C0) /* CNF9[1:0] bits (Port x configuration bits, pin 9) */ +#define GPIO_CFGHR_CNF9_0 ((uint32_t)0x00000040) /* Bit 0 */ +#define GPIO_CFGHR_CNF9_1 ((uint32_t)0x00000080) /* Bit 1 */ + +#define GPIO_CFGHR_CNF10 ((uint32_t)0x00000C00) /* CNF10[1:0] bits (Port x configuration bits, pin 10) */ +#define GPIO_CFGHR_CNF10_0 ((uint32_t)0x00000400) /* Bit 0 */ +#define GPIO_CFGHR_CNF10_1 ((uint32_t)0x00000800) /* Bit 1 */ + +#define GPIO_CFGHR_CNF11 ((uint32_t)0x0000C000) /* CNF11[1:0] bits (Port x configuration bits, pin 11) */ +#define GPIO_CFGHR_CNF11_0 ((uint32_t)0x00004000) /* Bit 0 */ +#define GPIO_CFGHR_CNF11_1 ((uint32_t)0x00008000) /* Bit 1 */ + +#define GPIO_CFGHR_CNF12 ((uint32_t)0x000C0000) /* CNF12[1:0] bits (Port x configuration bits, pin 12) */ +#define GPIO_CFGHR_CNF12_0 ((uint32_t)0x00040000) /* Bit 0 */ +#define GPIO_CFGHR_CNF12_1 ((uint32_t)0x00080000) /* Bit 1 */ + +#define GPIO_CFGHR_CNF13 ((uint32_t)0x00C00000) /* CNF13[1:0] bits (Port x configuration bits, pin 13) */ +#define GPIO_CFGHR_CNF13_0 ((uint32_t)0x00400000) /* Bit 0 */ +#define GPIO_CFGHR_CNF13_1 ((uint32_t)0x00800000) /* Bit 1 */ + +#define GPIO_CFGHR_CNF14 ((uint32_t)0x0C000000) /* CNF14[1:0] bits (Port x configuration bits, pin 14) */ +#define GPIO_CFGHR_CNF14_0 ((uint32_t)0x04000000) /* Bit 0 */ +#define GPIO_CFGHR_CNF14_1 ((uint32_t)0x08000000) /* Bit 1 */ + +#define GPIO_CFGHR_CNF15 ((uint32_t)0xC0000000) /* CNF15[1:0] bits (Port x configuration bits, pin 15) */ +#define GPIO_CFGHR_CNF15_0 ((uint32_t)0x40000000) /* Bit 0 */ +#define GPIO_CFGHR_CNF15_1 ((uint32_t)0x80000000) /* Bit 1 */ + +/******************* Bit definition for GPIO_INDR register *******************/ +#define GPIO_INDR_IDR0 ((uint16_t)0x0001) /* Port input data, bit 0 */ +#define GPIO_INDR_IDR1 ((uint16_t)0x0002) /* Port input data, bit 1 */ +#define GPIO_INDR_IDR2 ((uint16_t)0x0004) /* Port input data, bit 2 */ +#define GPIO_INDR_IDR3 ((uint16_t)0x0008) /* Port input data, bit 3 */ +#define GPIO_INDR_IDR4 ((uint16_t)0x0010) /* Port input data, bit 4 */ +#define GPIO_INDR_IDR5 ((uint16_t)0x0020) /* Port input data, bit 5 */ +#define GPIO_INDR_IDR6 ((uint16_t)0x0040) /* Port input data, bit 6 */ +#define GPIO_INDR_IDR7 ((uint16_t)0x0080) /* Port input data, bit 7 */ +#define GPIO_INDR_IDR8 ((uint16_t)0x0100) /* Port input data, bit 8 */ +#define GPIO_INDR_IDR9 ((uint16_t)0x0200) /* Port input data, bit 9 */ +#define GPIO_INDR_IDR10 ((uint16_t)0x0400) /* Port input data, bit 10 */ +#define GPIO_INDR_IDR11 ((uint16_t)0x0800) /* Port input data, bit 11 */ +#define GPIO_INDR_IDR12 ((uint16_t)0x1000) /* Port input data, bit 12 */ +#define GPIO_INDR_IDR13 ((uint16_t)0x2000) /* Port input data, bit 13 */ +#define GPIO_INDR_IDR14 ((uint16_t)0x4000) /* Port input data, bit 14 */ +#define GPIO_INDR_IDR15 ((uint16_t)0x8000) /* Port input data, bit 15 */ + +/******************* Bit definition for GPIO_OUTDR register *******************/ +#define GPIO_OUTDR_ODR0 ((uint16_t)0x0001) /* Port output data, bit 0 */ +#define GPIO_OUTDR_ODR1 ((uint16_t)0x0002) /* Port output data, bit 1 */ +#define GPIO_OUTDR_ODR2 ((uint16_t)0x0004) /* Port output data, bit 2 */ +#define GPIO_OUTDR_ODR3 ((uint16_t)0x0008) /* Port output data, bit 3 */ +#define GPIO_OUTDR_ODR4 ((uint16_t)0x0010) /* Port output data, bit 4 */ +#define GPIO_OUTDR_ODR5 ((uint16_t)0x0020) /* Port output data, bit 5 */ +#define GPIO_OUTDR_ODR6 ((uint16_t)0x0040) /* Port output data, bit 6 */ +#define GPIO_OUTDR_ODR7 ((uint16_t)0x0080) /* Port output data, bit 7 */ +#define GPIO_OUTDR_ODR8 ((uint16_t)0x0100) /* Port output data, bit 8 */ +#define GPIO_OUTDR_ODR9 ((uint16_t)0x0200) /* Port output data, bit 9 */ +#define GPIO_OUTDR_ODR10 ((uint16_t)0x0400) /* Port output data, bit 10 */ +#define GPIO_OUTDR_ODR11 ((uint16_t)0x0800) /* Port output data, bit 11 */ +#define GPIO_OUTDR_ODR12 ((uint16_t)0x1000) /* Port output data, bit 12 */ +#define GPIO_OUTDR_ODR13 ((uint16_t)0x2000) /* Port output data, bit 13 */ +#define GPIO_OUTDR_ODR14 ((uint16_t)0x4000) /* Port output data, bit 14 */ +#define GPIO_OUTDR_ODR15 ((uint16_t)0x8000) /* Port output data, bit 15 */ + +/****************** Bit definition for GPIO_BSHR register *******************/ +#define GPIO_BSHR_BS0 ((uint32_t)0x00000001) /* Port x Set bit 0 */ +#define GPIO_BSHR_BS1 ((uint32_t)0x00000002) /* Port x Set bit 1 */ +#define GPIO_BSHR_BS2 ((uint32_t)0x00000004) /* Port x Set bit 2 */ +#define GPIO_BSHR_BS3 ((uint32_t)0x00000008) /* Port x Set bit 3 */ +#define GPIO_BSHR_BS4 ((uint32_t)0x00000010) /* Port x Set bit 4 */ +#define GPIO_BSHR_BS5 ((uint32_t)0x00000020) /* Port x Set bit 5 */ +#define GPIO_BSHR_BS6 ((uint32_t)0x00000040) /* Port x Set bit 6 */ +#define GPIO_BSHR_BS7 ((uint32_t)0x00000080) /* Port x Set bit 7 */ +#define GPIO_BSHR_BS8 ((uint32_t)0x00000100) /* Port x Set bit 8 */ +#define GPIO_BSHR_BS9 ((uint32_t)0x00000200) /* Port x Set bit 9 */ +#define GPIO_BSHR_BS10 ((uint32_t)0x00000400) /* Port x Set bit 10 */ +#define GPIO_BSHR_BS11 ((uint32_t)0x00000800) /* Port x Set bit 11 */ +#define GPIO_BSHR_BS12 ((uint32_t)0x00001000) /* Port x Set bit 12 */ +#define GPIO_BSHR_BS13 ((uint32_t)0x00002000) /* Port x Set bit 13 */ +#define GPIO_BSHR_BS14 ((uint32_t)0x00004000) /* Port x Set bit 14 */ +#define GPIO_BSHR_BS15 ((uint32_t)0x00008000) /* Port x Set bit 15 */ + +#define GPIO_BSHR_BR0 ((uint32_t)0x00010000) /* Port x Reset bit 0 */ +#define GPIO_BSHR_BR1 ((uint32_t)0x00020000) /* Port x Reset bit 1 */ +#define GPIO_BSHR_BR2 ((uint32_t)0x00040000) /* Port x Reset bit 2 */ +#define GPIO_BSHR_BR3 ((uint32_t)0x00080000) /* Port x Reset bit 3 */ +#define GPIO_BSHR_BR4 ((uint32_t)0x00100000) /* Port x Reset bit 4 */ +#define GPIO_BSHR_BR5 ((uint32_t)0x00200000) /* Port x Reset bit 5 */ +#define GPIO_BSHR_BR6 ((uint32_t)0x00400000) /* Port x Reset bit 6 */ +#define GPIO_BSHR_BR7 ((uint32_t)0x00800000) /* Port x Reset bit 7 */ +#define GPIO_BSHR_BR8 ((uint32_t)0x01000000) /* Port x Reset bit 8 */ +#define GPIO_BSHR_BR9 ((uint32_t)0x02000000) /* Port x Reset bit 9 */ +#define GPIO_BSHR_BR10 ((uint32_t)0x04000000) /* Port x Reset bit 10 */ +#define GPIO_BSHR_BR11 ((uint32_t)0x08000000) /* Port x Reset bit 11 */ +#define GPIO_BSHR_BR12 ((uint32_t)0x10000000) /* Port x Reset bit 12 */ +#define GPIO_BSHR_BR13 ((uint32_t)0x20000000) /* Port x Reset bit 13 */ +#define GPIO_BSHR_BR14 ((uint32_t)0x40000000) /* Port x Reset bit 14 */ +#define GPIO_BSHR_BR15 ((uint32_t)0x80000000) /* Port x Reset bit 15 */ + +/******************* Bit definition for GPIO_BCR register *******************/ +#define GPIO_BCR_BR0 ((uint16_t)0x0001) /* Port x Reset bit 0 */ +#define GPIO_BCR_BR1 ((uint16_t)0x0002) /* Port x Reset bit 1 */ +#define GPIO_BCR_BR2 ((uint16_t)0x0004) /* Port x Reset bit 2 */ +#define GPIO_BCR_BR3 ((uint16_t)0x0008) /* Port x Reset bit 3 */ +#define GPIO_BCR_BR4 ((uint16_t)0x0010) /* Port x Reset bit 4 */ +#define GPIO_BCR_BR5 ((uint16_t)0x0020) /* Port x Reset bit 5 */ +#define GPIO_BCR_BR6 ((uint16_t)0x0040) /* Port x Reset bit 6 */ +#define GPIO_BCR_BR7 ((uint16_t)0x0080) /* Port x Reset bit 7 */ +#define GPIO_BCR_BR8 ((uint16_t)0x0100) /* Port x Reset bit 8 */ +#define GPIO_BCR_BR9 ((uint16_t)0x0200) /* Port x Reset bit 9 */ +#define GPIO_BCR_BR10 ((uint16_t)0x0400) /* Port x Reset bit 10 */ +#define GPIO_BCR_BR11 ((uint16_t)0x0800) /* Port x Reset bit 11 */ +#define GPIO_BCR_BR12 ((uint16_t)0x1000) /* Port x Reset bit 12 */ +#define GPIO_BCR_BR13 ((uint16_t)0x2000) /* Port x Reset bit 13 */ +#define GPIO_BCR_BR14 ((uint16_t)0x4000) /* Port x Reset bit 14 */ +#define GPIO_BCR_BR15 ((uint16_t)0x8000) /* Port x Reset bit 15 */ + +/****************** Bit definition for GPIO_LCKR register *******************/ +#define GPIO_LCK0 ((uint32_t)0x00000001) /* Port x Lock bit 0 */ +#define GPIO_LCK1 ((uint32_t)0x00000002) /* Port x Lock bit 1 */ +#define GPIO_LCK2 ((uint32_t)0x00000004) /* Port x Lock bit 2 */ +#define GPIO_LCK3 ((uint32_t)0x00000008) /* Port x Lock bit 3 */ +#define GPIO_LCK4 ((uint32_t)0x00000010) /* Port x Lock bit 4 */ +#define GPIO_LCK5 ((uint32_t)0x00000020) /* Port x Lock bit 5 */ +#define GPIO_LCK6 ((uint32_t)0x00000040) /* Port x Lock bit 6 */ +#define GPIO_LCK7 ((uint32_t)0x00000080) /* Port x Lock bit 7 */ +#define GPIO_LCK8 ((uint32_t)0x00000100) /* Port x Lock bit 8 */ +#define GPIO_LCK9 ((uint32_t)0x00000200) /* Port x Lock bit 9 */ +#define GPIO_LCK10 ((uint32_t)0x00000400) /* Port x Lock bit 10 */ +#define GPIO_LCK11 ((uint32_t)0x00000800) /* Port x Lock bit 11 */ +#define GPIO_LCK12 ((uint32_t)0x00001000) /* Port x Lock bit 12 */ +#define GPIO_LCK13 ((uint32_t)0x00002000) /* Port x Lock bit 13 */ +#define GPIO_LCK14 ((uint32_t)0x00004000) /* Port x Lock bit 14 */ +#define GPIO_LCK15 ((uint32_t)0x00008000) /* Port x Lock bit 15 */ +#define GPIO_LCKK ((uint32_t)0x00010000) /* Lock key */ + +/****************** Bit definition for AFIO_ECR register *******************/ +#define AFIO_ECR_PIN ((uint8_t)0x0F) /* PIN[3:0] bits (Pin selection) */ +#define AFIO_ECR_PIN_0 ((uint8_t)0x01) /* Bit 0 */ +#define AFIO_ECR_PIN_1 ((uint8_t)0x02) /* Bit 1 */ +#define AFIO_ECR_PIN_2 ((uint8_t)0x04) /* Bit 2 */ +#define AFIO_ECR_PIN_3 ((uint8_t)0x08) /* Bit 3 */ + +#define AFIO_ECR_PIN_PX0 ((uint8_t)0x00) /* Pin 0 selected */ +#define AFIO_ECR_PIN_PX1 ((uint8_t)0x01) /* Pin 1 selected */ +#define AFIO_ECR_PIN_PX2 ((uint8_t)0x02) /* Pin 2 selected */ +#define AFIO_ECR_PIN_PX3 ((uint8_t)0x03) /* Pin 3 selected */ +#define AFIO_ECR_PIN_PX4 ((uint8_t)0x04) /* Pin 4 selected */ +#define AFIO_ECR_PIN_PX5 ((uint8_t)0x05) /* Pin 5 selected */ +#define AFIO_ECR_PIN_PX6 ((uint8_t)0x06) /* Pin 6 selected */ +#define AFIO_ECR_PIN_PX7 ((uint8_t)0x07) /* Pin 7 selected */ +#define AFIO_ECR_PIN_PX8 ((uint8_t)0x08) /* Pin 8 selected */ +#define AFIO_ECR_PIN_PX9 ((uint8_t)0x09) /* Pin 9 selected */ +#define AFIO_ECR_PIN_PX10 ((uint8_t)0x0A) /* Pin 10 selected */ +#define AFIO_ECR_PIN_PX11 ((uint8_t)0x0B) /* Pin 11 selected */ +#define AFIO_ECR_PIN_PX12 ((uint8_t)0x0C) /* Pin 12 selected */ +#define AFIO_ECR_PIN_PX13 ((uint8_t)0x0D) /* Pin 13 selected */ +#define AFIO_ECR_PIN_PX14 ((uint8_t)0x0E) /* Pin 14 selected */ +#define AFIO_ECR_PIN_PX15 ((uint8_t)0x0F) /* Pin 15 selected */ + +#define AFIO_ECR_PORT ((uint8_t)0x70) /* PORT[2:0] bits (Port selection) */ +#define AFIO_ECR_PORT_0 ((uint8_t)0x10) /* Bit 0 */ +#define AFIO_ECR_PORT_1 ((uint8_t)0x20) /* Bit 1 */ +#define AFIO_ECR_PORT_2 ((uint8_t)0x40) /* Bit 2 */ + +#define AFIO_ECR_PORT_PA ((uint8_t)0x00) /* Port A selected */ +#define AFIO_ECR_PORT_PB ((uint8_t)0x10) /* Port B selected */ +#define AFIO_ECR_PORT_PC ((uint8_t)0x20) /* Port C selected */ +#define AFIO_ECR_PORT_PD ((uint8_t)0x30) /* Port D selected */ + +#define AFIO_ECR_EVOE ((uint8_t)0x80) /* Event Output Enable */ + +/****************** Bit definition for AFIO_PCFR1register *******************/ +#define AFIO_PCFR1_SPI1_RM ((uint32_t)0x00000001) /* SPI1 remapping */ +#define AFIO_PCFR1_I2C1_RM ((uint32_t)0x00000002) /* I2C1 remapping */ +#define AFIO_PCFR1_USART1_RM ((uint32_t)0x00000004) /* USART1 remapping */ +#define AFIO_PCFR1_USART2_RM ((uint32_t)0x00000008) /* USART2 remapping */ + +#define AFIO_PCFR1_USART3_RM ((uint32_t)0x00000030) /* USART3_RM[1:0] bits (USART3 remapping) */ +#define AFIO_PCFR1_USART3_RM_0 ((uint32_t)0x00000010) /* Bit 0 */ +#define AFIO_PCFR1_USART3_RM_1 ((uint32_t)0x00000020) /* Bit 1 */ + +#define AFIO_PCFR1_TIM1_RM ((uint32_t)0x000000C0) /* TIM1_RM[1:0] bits (TIM1 remapping) */ +#define AFIO_PCFR1_TIM1_RM_0 ((uint32_t)0x00000040) /* Bit 0 */ +#define AFIO_PCFR1_TIM1_RM_1 ((uint32_t)0x00000080) /* Bit 1 */ + +#define AFIO_PCFR1_TIM2_RM ((uint32_t)0x00000300) /* TIM2_RM[1:0] bits (TIM2 remapping) */ +#define AFIO_PCFR1_TIM2_RM_0 ((uint32_t)0x00000100) /* Bit 0 */ +#define AFIO_PCFR1_TIM2_RM_1 ((uint32_t)0x00000200) /* Bit 1 */ + +#define AFIO_PCFR1_TIM3_RM ((uint32_t)0x00000400) /* TIM3_RM bits (TIM3 remapping) */ + +#define AFIO_PCFR1_TIM4_RM ((uint32_t)0x00001000) /* TIM4_RM bit (TIM4 remapping) */ + +#define AFIO_PCFR1_CAN_RM ((uint32_t)0x00006000) /* CAN_RM[1:0] bits (CAN Alternate function remapping) */ +#define AFIO_PCFR1_CAN_RM_0 ((uint32_t)0x00002000) /* Bit 0 */ +#define AFIO_PCFR1_CAN_RM_1 ((uint32_t)0x00004000) /* Bit 1 */ + +#define AFIO_PCFR1_PD0PD1_RM ((uint32_t)0x00008000) /* Port D0/Port D1 mapping on OSC_IN/OSC_OUT */ +#define AFIO_PCFR1_PD01_RM AFIO_PCFR1_PD0PD1_RM + +#define AFIO_PCFR1_SW_CFG ((uint32_t)0x07000000) /* SW_CFG[2:0] bits (SDI configuration) */ +#define AFIO_PCFR1_SW_CFG_0 ((uint32_t)0x01000000) /* Bit 0 */ +#define AFIO_PCFR1_SW_CFG_1 ((uint32_t)0x02000000) /* Bit 1 */ +#define AFIO_PCFR1_SW_CFG_2 ((uint32_t)0x04000000) /* Bit 2 */ + +/***************** Bit definition for AFIO_EXTICR1 register *****************/ +#define AFIO_EXTICR1_EXTI0 ((uint16_t)0x000F) /* EXTI 0 configuration */ +#define AFIO_EXTICR1_EXTI1 ((uint16_t)0x00F0) /* EXTI 1 configuration */ +#define AFIO_EXTICR1_EXTI2 ((uint16_t)0x0F00) /* EXTI 2 configuration */ +#define AFIO_EXTICR1_EXTI3 ((uint16_t)0xF000) /* EXTI 3 configuration */ + +#define AFIO_EXTICR1_EXTI0_PA ((uint16_t)0x0000) /* PA[0] pin */ +#define AFIO_EXTICR1_EXTI0_PB ((uint16_t)0x0001) /* PB[0] pin */ +#define AFIO_EXTICR1_EXTI0_PC ((uint16_t)0x0002) /* PC[0] pin */ +#define AFIO_EXTICR1_EXTI0_PD ((uint16_t)0x0003) /* PD[0] pin */ + +#define AFIO_EXTICR1_EXTI1_PA ((uint16_t)0x0000) /* PA[1] pin */ +#define AFIO_EXTICR1_EXTI1_PB ((uint16_t)0x0010) /* PB[1] pin */ +#define AFIO_EXTICR1_EXTI1_PC ((uint16_t)0x0020) /* PC[1] pin */ +#define AFIO_EXTICR1_EXTI1_PD ((uint16_t)0x0030) /* PD[1] pin */ + +#define AFIO_EXTICR1_EXTI2_PA ((uint16_t)0x0000) /* PA[2] pin */ +#define AFIO_EXTICR1_EXTI2_PB ((uint16_t)0x0100) /* PB[2] pin */ +#define AFIO_EXTICR1_EXTI2_PC ((uint16_t)0x0200) /* PC[2] pin */ +#define AFIO_EXTICR1_EXTI2_PD ((uint16_t)0x0300) /* PD[2] pin */ + +#define AFIO_EXTICR1_EXTI3_PA ((uint16_t)0x0000) /* PA[3] pin */ +#define AFIO_EXTICR1_EXTI3_PB ((uint16_t)0x1000) /* PB[3] pin */ +#define AFIO_EXTICR1_EXTI3_PC ((uint16_t)0x2000) /* PC[3] pin */ +#define AFIO_EXTICR1_EXTI3_PD ((uint16_t)0x3000) /* PD[3] pin */ + +/***************** Bit definition for AFIO_EXTICR2 register *****************/ +#define AFIO_EXTICR2_EXTI4 ((uint16_t)0x000F) /* EXTI 4 configuration */ +#define AFIO_EXTICR2_EXTI5 ((uint16_t)0x00F0) /* EXTI 5 configuration */ +#define AFIO_EXTICR2_EXTI6 ((uint16_t)0x0F00) /* EXTI 6 configuration */ +#define AFIO_EXTICR2_EXTI7 ((uint16_t)0xF000) /* EXTI 7 configuration */ + +#define AFIO_EXTICR2_EXTI4_PA ((uint16_t)0x0000) /* PA[4] pin */ +#define AFIO_EXTICR2_EXTI4_PB ((uint16_t)0x0001) /* PB[4] pin */ +#define AFIO_EXTICR2_EXTI4_PC ((uint16_t)0x0002) /* PC[4] pin */ +#define AFIO_EXTICR2_EXTI4_PD ((uint16_t)0x0003) /* PD[4] pin */ + +#define AFIO_EXTICR2_EXTI5_PA ((uint16_t)0x0000) /* PA[5] pin */ +#define AFIO_EXTICR2_EXTI5_PB ((uint16_t)0x0010) /* PB[5] pin */ +#define AFIO_EXTICR2_EXTI5_PC ((uint16_t)0x0020) /* PC[5] pin */ +#define AFIO_EXTICR2_EXTI5_PD ((uint16_t)0x0030) /* PD[5] pin */ + +#define AFIO_EXTICR2_EXTI6_PA ((uint16_t)0x0000) /* PA[6] pin */ +#define AFIO_EXTICR2_EXTI6_PB ((uint16_t)0x0100) /* PB[6] pin */ +#define AFIO_EXTICR2_EXTI6_PC ((uint16_t)0x0200) /* PC[6] pin */ +#define AFIO_EXTICR2_EXTI6_PD ((uint16_t)0x0300) /* PD[6] pin */ + +#define AFIO_EXTICR2_EXTI7_PA ((uint16_t)0x0000) /* PA[7] pin */ +#define AFIO_EXTICR2_EXTI7_PB ((uint16_t)0x1000) /* PB[7] pin */ +#define AFIO_EXTICR2_EXTI7_PC ((uint16_t)0x2000) /* PC[7] pin */ +#define AFIO_EXTICR2_EXTI7_PD ((uint16_t)0x3000) /* PD[7] pin */ + +/***************** Bit definition for AFIO_EXTICR3 register *****************/ +#define AFIO_EXTICR3_EXTI8 ((uint16_t)0x000F) /* EXTI 8 configuration */ +#define AFIO_EXTICR3_EXTI9 ((uint16_t)0x00F0) /* EXTI 9 configuration */ +#define AFIO_EXTICR3_EXTI10 ((uint16_t)0x0F00) /* EXTI 10 configuration */ +#define AFIO_EXTICR3_EXTI11 ((uint16_t)0xF000) /* EXTI 11 configuration */ + +#define AFIO_EXTICR3_EXTI8_PA ((uint16_t)0x0000) /* PA[8] pin */ +#define AFIO_EXTICR3_EXTI8_PB ((uint16_t)0x0001) /* PB[8] pin */ +#define AFIO_EXTICR3_EXTI8_PC ((uint16_t)0x0002) /* PC[8] pin */ +#define AFIO_EXTICR3_EXTI8_PD ((uint16_t)0x0003) /* PD[8] pin */ + +#define AFIO_EXTICR3_EXTI9_PA ((uint16_t)0x0000) /* PA[9] pin */ +#define AFIO_EXTICR3_EXTI9_PB ((uint16_t)0x0010) /* PB[9] pin */ +#define AFIO_EXTICR3_EXTI9_PC ((uint16_t)0x0020) /* PC[9] pin */ +#define AFIO_EXTICR3_EXTI9_PD ((uint16_t)0x0030) /* PD[9] pin */ + +#define AFIO_EXTICR3_EXTI10_PA ((uint16_t)0x0000) /* PA[10] pin */ +#define AFIO_EXTICR3_EXTI10_PB ((uint16_t)0x0100) /* PB[10] pin */ +#define AFIO_EXTICR3_EXTI10_PC ((uint16_t)0x0200) /* PC[10] pin */ +#define AFIO_EXTICR3_EXTI10_PD ((uint16_t)0x0300) /* PD[10] pin */ + +#define AFIO_EXTICR3_EXTI11_PA ((uint16_t)0x0000) /* PA[11] pin */ +#define AFIO_EXTICR3_EXTI11_PB ((uint16_t)0x1000) /* PB[11] pin */ +#define AFIO_EXTICR3_EXTI11_PC ((uint16_t)0x2000) /* PC[11] pin */ +#define AFIO_EXTICR3_EXTI11_PD ((uint16_t)0x3000) /* PD[11] pin */ + +/***************** Bit definition for AFIO_EXTICR4 register *****************/ +#define AFIO_EXTICR4_EXTI12 ((uint16_t)0x000F) /* EXTI 12 configuration */ +#define AFIO_EXTICR4_EXTI13 ((uint16_t)0x00F0) /* EXTI 13 configuration */ +#define AFIO_EXTICR4_EXTI14 ((uint16_t)0x0F00) /* EXTI 14 configuration */ +#define AFIO_EXTICR4_EXTI15 ((uint16_t)0xF000) /* EXTI 15 configuration */ + +#define AFIO_EXTICR4_EXTI12_PA ((uint16_t)0x0000) /* PA[12] pin */ +#define AFIO_EXTICR4_EXTI12_PB ((uint16_t)0x0001) /* PB[12] pin */ +#define AFIO_EXTICR4_EXTI12_PC ((uint16_t)0x0002) /* PC[12] pin */ +#define AFIO_EXTICR4_EXTI12_PD ((uint16_t)0x0003) /* PD[12] pin */ + +#define AFIO_EXTICR4_EXTI13_PA ((uint16_t)0x0000) /* PA[13] pin */ +#define AFIO_EXTICR4_EXTI13_PB ((uint16_t)0x0010) /* PB[13] pin */ +#define AFIO_EXTICR4_EXTI13_PC ((uint16_t)0x0020) /* PC[13] pin */ +#define AFIO_EXTICR4_EXTI13_PD ((uint16_t)0x0030) /* PD[13] pin */ + +#define AFIO_EXTICR4_EXTI14_PA ((uint16_t)0x0000) /* PA[14] pin */ +#define AFIO_EXTICR4_EXTI14_PB ((uint16_t)0x0100) /* PB[14] pin */ +#define AFIO_EXTICR4_EXTI14_PC ((uint16_t)0x0200) /* PC[14] pin */ +#define AFIO_EXTICR4_EXTI14_PD ((uint16_t)0x0300) /* PD[14] pin */ + +#define AFIO_EXTICR4_EXTI15_PA ((uint16_t)0x0000) /* PA[15] pin */ +#define AFIO_EXTICR4_EXTI15_PB ((uint16_t)0x1000) /* PB[15] pin */ +#define AFIO_EXTICR4_EXTI15_PC ((uint16_t)0x2000) /* PC[15] pin */ +#define AFIO_EXTICR4_EXTI15_PD ((uint16_t)0x3000) /* PD[15] pin */ + +/***************** Bit definition for AFIO_CR register *****************/ +#define AFIO_CR_USBPD_IN_HVT ((uint32_t)0x00000200) +#define AFIO_CR_UPD_BC_VSRC ((uint32_t)0x00010000) +#define AFIO_CR_UDM_BC_VSRC ((uint32_t)0x00020000) +#define AFIO_CR_UPD_BC_CMPE ((uint32_t)0x00040000) +#define AFIO_CR_UDM_BC_CMPE ((uint32_t)0x00080000) +#define AFIO_CR_UPD_BC_CMPO ((uint32_t)0x00100000) +#define AFIO_CR_UDM_BC_CMPO ((uint32_t)0x00200000) + +/***************** Bit definition for AFIO_PCFR2 register *****************/ +#define AFIO_PCFR2_USART4_RM ((uint32_t)0x00010000) +#define AFIO_PCFR2_USART2_RM_H ((uint32_t)0x00040000) + +#define AFIO_PCFR2_USART1_RM_H ((uint32_t)0x00180000) +#define AFIO_PCFR2_USART1_RM_H_0 ((uint32_t)0x00080000) +#define AFIO_PCFR2_USART1_RM_H_1 ((uint32_t)0x00100000) + +#define AFIO_PCFR2_TIM2_RM_H ((uint32_t)0x00200000) +#define AFIO_PCFR2_TIM1_RM_H ((uint32_t)0x00400000) +#define AFIO_PCFR2_I2C_RM_H ((uint32_t)0x00800000) +#define AFIO_PCFR2_SPI1_RM_H ((uint32_t)0x01000000) +#define AFIO_PCFR2_LPTIM_RM ((uint32_t)0x02000000) + +/******************************************************************************/ +/* Independent WATCHDOG */ +/******************************************************************************/ + +/******************* Bit definition for IWDG_CTLR register ********************/ +#define IWDG_KEY ((uint16_t)0xFFFF) /* Key value (write only, read 0000h) */ + +/******************* Bit definition for IWDG_PSCR register ********************/ +#define IWDG_PR ((uint8_t)0x07) /* PR[2:0] (Prescaler divider) */ +#define IWDG_PR_0 ((uint8_t)0x01) /* Bit 0 */ +#define IWDG_PR_1 ((uint8_t)0x02) /* Bit 1 */ +#define IWDG_PR_2 ((uint8_t)0x04) /* Bit 2 */ + +/******************* Bit definition for IWDG_RLDR register *******************/ +#define IWDG_RL ((uint16_t)0x0FFF) /* Watchdog counter reload value */ + +/******************* Bit definition for IWDG_STATR register ********************/ +#define IWDG_PVU ((uint8_t)0x01) /* Watchdog prescaler value update */ +#define IWDG_RVU ((uint8_t)0x02) /* Watchdog counter reload value update */ + +/******************************************************************************/ +/* Inter-integrated Circuit Interface */ +/******************************************************************************/ + +/******************* Bit definition for I2C_CTLR1 register ********************/ +#define I2C_CTLR1_PE ((uint16_t)0x0001) /* Peripheral Enable */ +#define I2C_CTLR1_SMBUS ((uint16_t)0x0002) /* SMBus Mode */ +#define I2C_CTLR1_SMBTYPE ((uint16_t)0x0008) /* SMBus Type */ +#define I2C_CTLR1_ENARP ((uint16_t)0x0010) /* ARP Enable */ +#define I2C_CTLR1_ENPEC ((uint16_t)0x0020) /* PEC Enable */ +#define I2C_CTLR1_ENGC ((uint16_t)0x0040) /* General Call Enable */ +#define I2C_CTLR1_NOSTRETCH ((uint16_t)0x0080) /* Clock Stretching Disable (Slave mode) */ +#define I2C_CTLR1_START ((uint16_t)0x0100) /* Start Generation */ +#define I2C_CTLR1_STOP ((uint16_t)0x0200) /* Stop Generation */ +#define I2C_CTLR1_ACK ((uint16_t)0x0400) /* Acknowledge Enable */ +#define I2C_CTLR1_POS ((uint16_t)0x0800) /* Acknowledge/PEC Position (for data reception) */ +#define I2C_CTLR1_PEC ((uint16_t)0x1000) /* Packet Error Checking */ +#define I2C_CTLR1_ALERT ((uint16_t)0x2000) /* SMBus Alert */ +#define I2C_CTLR1_SWRST ((uint16_t)0x8000) /* Software Reset */ + +/******************* Bit definition for I2C_CTLR2 register ********************/ +#define I2C_CTLR2_FREQ ((uint16_t)0x003F) /* FREQ[5:0] bits (Peripheral Clock Frequency) */ +#define I2C_CTLR2_FREQ_0 ((uint16_t)0x0001) /* Bit 0 */ +#define I2C_CTLR2_FREQ_1 ((uint16_t)0x0002) /* Bit 1 */ +#define I2C_CTLR2_FREQ_2 ((uint16_t)0x0004) /* Bit 2 */ +#define I2C_CTLR2_FREQ_3 ((uint16_t)0x0008) /* Bit 3 */ +#define I2C_CTLR2_FREQ_4 ((uint16_t)0x0010) /* Bit 4 */ +#define I2C_CTLR2_FREQ_5 ((uint16_t)0x0020) /* Bit 5 */ + +#define I2C_CTLR2_ITERREN ((uint16_t)0x0100) /* Error Interrupt Enable */ +#define I2C_CTLR2_ITEVTEN ((uint16_t)0x0200) /* Event Interrupt Enable */ +#define I2C_CTLR2_ITBUFEN ((uint16_t)0x0400) /* Buffer Interrupt Enable */ +#define I2C_CTLR2_DMAEN ((uint16_t)0x0800) /* DMA Requests Enable */ +#define I2C_CTLR2_LAST ((uint16_t)0x1000) /* DMA Last Transfer */ + +/******************* Bit definition for I2C_OADDR1 register *******************/ +#define I2C_OADDR1_ADD1_7 ((uint16_t)0x00FE) /* Interface Address */ +#define I2C_OADDR1_ADD8_9 ((uint16_t)0x0300) /* Interface Address */ + +#define I2C_OADDR1_ADD0 ((uint16_t)0x0001) /* Bit 0 */ +#define I2C_OADDR1_ADD1 ((uint16_t)0x0002) /* Bit 1 */ +#define I2C_OADDR1_ADD2 ((uint16_t)0x0004) /* Bit 2 */ +#define I2C_OADDR1_ADD3 ((uint16_t)0x0008) /* Bit 3 */ +#define I2C_OADDR1_ADD4 ((uint16_t)0x0010) /* Bit 4 */ +#define I2C_OADDR1_ADD5 ((uint16_t)0x0020) /* Bit 5 */ +#define I2C_OADDR1_ADD6 ((uint16_t)0x0040) /* Bit 6 */ +#define I2C_OADDR1_ADD7 ((uint16_t)0x0080) /* Bit 7 */ +#define I2C_OADDR1_ADD8 ((uint16_t)0x0100) /* Bit 8 */ +#define I2C_OADDR1_ADD9 ((uint16_t)0x0200) /* Bit 9 */ + +#define I2C_OADDR1_ADDMODE ((uint16_t)0x8000) /* Addressing Mode (Slave mode) */ + +/******************* Bit definition for I2C_OADDR2 register *******************/ +#define I2C_OADDR2_ENDUAL ((uint8_t)0x01) /* Dual addressing mode enable */ +#define I2C_OADDR2_ADD2 ((uint8_t)0xFE) /* Interface address */ + +/******************** Bit definition for I2C_DATAR register ********************/ +#define I2C_DR_DATAR ((uint8_t)0xFF) /* 8-bit Data Register */ + +/******************* Bit definition for I2C_STAR1 register ********************/ +#define I2C_STAR1_SB ((uint16_t)0x0001) /* Start Bit (Master mode) */ +#define I2C_STAR1_ADDR ((uint16_t)0x0002) /* Address sent (master mode)/matched (slave mode) */ +#define I2C_STAR1_BTF ((uint16_t)0x0004) /* Byte Transfer Finished */ +#define I2C_STAR1_ADD10 ((uint16_t)0x0008) /* 10-bit header sent (Master mode) */ +#define I2C_STAR1_STOPF ((uint16_t)0x0010) /* Stop detection (Slave mode) */ +#define I2C_STAR1_RXNE ((uint16_t)0x0040) /* Data Register not Empty (receivers) */ +#define I2C_STAR1_TXE ((uint16_t)0x0080) /* Data Register Empty (transmitters) */ +#define I2C_STAR1_BERR ((uint16_t)0x0100) /* Bus Error */ +#define I2C_STAR1_ARLO ((uint16_t)0x0200) /* Arbitration Lost (master mode) */ +#define I2C_STAR1_AF ((uint16_t)0x0400) /* Acknowledge Failure */ +#define I2C_STAR1_OVR ((uint16_t)0x0800) /* Overrun/Underrun */ +#define I2C_STAR1_PECERR ((uint16_t)0x1000) /* PEC Error in reception */ +#define I2C_STAR1_TIMEOUT ((uint16_t)0x4000) /* Timeout or Tlow Error */ +#define I2C_STAR1_SMBALERT ((uint16_t)0x8000) /* SMBus Alert */ + +/******************* Bit definition for I2C_STAR2 register ********************/ +#define I2C_STAR2_MSL ((uint16_t)0x0001) /* Master/Slave */ +#define I2C_STAR2_BUSY ((uint16_t)0x0002) /* Bus Busy */ +#define I2C_STAR2_TRA ((uint16_t)0x0004) /* Transmitter/Receiver */ +#define I2C_STAR2_GENCALL ((uint16_t)0x0010) /* General Call Address (Slave mode) */ +#define I2C_STAR2_SMBDEFAULT ((uint16_t)0x0020) /* SMBus Device Default Address (Slave mode) */ +#define I2C_STAR2_SMBHOST ((uint16_t)0x0040) /* SMBus Host Header (Slave mode) */ +#define I2C_STAR2_DUALF ((uint16_t)0x0080) /* Dual Flag (Slave mode) */ +#define I2C_STAR2_PEC ((uint16_t)0xFF00) /* Packet Error Checking Register */ + +/******************* Bit definition for I2C_CKCFGR register ********************/ +#define I2C_CKCFGR_CCR ((uint16_t)0x0FFF) /* Clock Control Register in Fast/Standard mode (Master mode) */ +#define I2C_CKCFGR_DUTY ((uint16_t)0x4000) /* Fast Mode Duty Cycle */ +#define I2C_CKCFGR_FS ((uint16_t)0x8000) /* I2C Master Mode Selection */ + +/****************** Bit definition for I2C_RTR register *******************/ +#define I2C_RTR_TRISE ((uint8_t)0x3F) /* Maximum Rise Time in Fast/Standard mode (Master mode) */ + +/******************************************************************************/ +/* Power Control */ +/******************************************************************************/ + +/******************** Bit definition for PWR_CTLR register ********************/ +#define PWR_CTLR_LPDS ((uint16_t)0x0001) /* Low-Power Deepsleep */ +#define PWR_CTLR_PDDS ((uint16_t)0x0002) /* Power Down Deepsleep */ +#define PWR_CTLR_CWUF ((uint16_t)0x0004) /* Clear Wakeup Flag */ +#define PWR_CTLR_CSBF ((uint16_t)0x0008) /* Clear Standby Flag */ +#define PWR_CTLR_PVDE ((uint16_t)0x0010) /* Power Voltage Detector Enable */ + +#define PWR_CTLR_PLS ((uint16_t)0x00E0) /* PLS[2:0] bits (PVD Level Selection) */ +#define PWR_CTLR_PLS_0 ((uint16_t)0x0020) /* Bit 0 */ +#define PWR_CTLR_PLS_1 ((uint16_t)0x0040) /* Bit 1 */ +#define PWR_CTLR_PLS_2 ((uint16_t)0x0080) /* Bit 2 */ + +#define PWR_CTLR_PLS_MODE0 ((uint16_t)0x0000) /* PVD level 0 */ +#define PWR_CTLR_PLS_MODE1 ((uint16_t)0x0020) /* PVD level 1 */ +#define PWR_CTLR_PLS_MODE2 ((uint16_t)0x0040) /* PVD level 2 */ +#define PWR_CTLR_PLS_MODE3 ((uint16_t)0x0060) /* PVD level 3 */ +#define PWR_CTLR_PLS_MODE4 ((uint16_t)0x0080) /* PVD level 4 */ +#define PWR_CTLR_PLS_MODE5 ((uint16_t)0x00A0) /* PVD level 5 */ +#define PWR_CTLR_PLS_MODE6 ((uint16_t)0x00C0) /* PVD level 6 */ +#define PWR_CTLR_PLS_MODE7 ((uint16_t)0x00E0) /* PVD level 7 */ + +#define PWR_CTLR_DBP ((uint16_t)0x0100) /* Disable Backup Domain write protection */ + +#define PWR_CTLR_FLASH_LP_REG ((uint16_t)0x0200) + +#define PWR_CTLR_FLASH_LP ((uint16_t)0x0C00) /* FLASH_LP [1:0]*/ +#define PWR_CTLR_FLASH_LP_0 ((uint16_t)0x0400) +#define PWR_CTLR_FLASH_LP_1 ((uint16_t)0x0800) + +#define PWR_CTLR_AUTO_LDO_EC ((uint16_t)0x1000) +#define PWR_CTLR_LDO_EC ((uint16_t)0x2000) +#define PWR_CTLR_R2KSTY ((uint32_t)0x00010000) +#define PWR_CTLR_R18KSTY ((uint32_t)0x00020000) +#define PWR_CTLR_R2KVBAT ((uint32_t)0x00040000) +#define PWR_CTLR_R18KVBAT ((uint32_t)0x00080000) +#define PWR_RAMLV ((uint32_t)0x00100000) + +/******************* Bit definition for PWR_CSR register ********************/ +#define PWR_CSR_WUF ((uint16_t)0x0001) /* Wakeup Flag */ +#define PWR_CSR_SBF ((uint16_t)0x0002) /* Standby Flag */ +#define PWR_CSR_PVDO ((uint16_t)0x0004) /* PVD Output */ +#define PWR_CSR_EWUP ((uint16_t)0x0100) /* Enable WKUP pin */ + +/******************************************************************************/ +/* Reset and Clock Control */ +/******************************************************************************/ + +/******************** Bit definition for RCC_CTLR register ********************/ +#define RCC_HSION ((uint32_t)0x00000001) /* Internal High Speed clock enable */ +#define RCC_HSIRDY ((uint32_t)0x00000002) /* Internal High Speed clock ready flag */ +#define RCC_HSILP ((uint32_t)0x00000004) +#define RCC_HSITRIM ((uint32_t)0x000000F8) /* Internal High Speed clock trimming */ +#define RCC_HSICAL ((uint32_t)0x0000FF00) /* Internal High Speed clock Calibration */ +#define RCC_HSEON ((uint32_t)0x00010000) /* External High Speed clock enable */ +#define RCC_HSERDY ((uint32_t)0x00020000) /* External High Speed clock ready flag */ +#define RCC_HSEBYP ((uint32_t)0x00040000) /* External High Speed clock Bypass */ +#define RCC_CSSON ((uint32_t)0x00080000) /* Clock Security System enable */ +#define RCC_HSELP ((uint32_t)0x00100000) +#define RCC_PLLON ((uint32_t)0x01000000) /* PLL enable */ +#define RCC_PLLRDY ((uint32_t)0x02000000) /* PLL clock ready flag */ + +/******************* Bit definition for RCC_CFGR0 register *******************/ +#define RCC_SW ((uint32_t)0x00000003) /* SW[1:0] bits (System clock Switch) */ +#define RCC_SW_0 ((uint32_t)0x00000001) /* Bit 0 */ +#define RCC_SW_1 ((uint32_t)0x00000002) /* Bit 1 */ + +#define RCC_SW_HSI ((uint32_t)0x00000000) /* HSI selected as system clock */ +#define RCC_SW_HSE ((uint32_t)0x00000001) /* HSE selected as system clock */ +#define RCC_SW_PLL ((uint32_t)0x00000002) /* PLL selected as system clock */ + +#define RCC_SWS ((uint32_t)0x0000000C) /* SWS[1:0] bits (System Clock Switch Status) */ +#define RCC_SWS_0 ((uint32_t)0x00000004) /* Bit 0 */ +#define RCC_SWS_1 ((uint32_t)0x00000008) /* Bit 1 */ + +#define RCC_SWS_HSI ((uint32_t)0x00000000) /* HSI oscillator used as system clock */ +#define RCC_SWS_HSE ((uint32_t)0x00000004) /* HSE oscillator used as system clock */ +#define RCC_SWS_PLL ((uint32_t)0x00000008) /* PLL used as system clock */ + +#define RCC_HPRE ((uint32_t)0x000000F0) /* HPRE[3:0] bits (HB prescaler) */ +#define RCC_HPRE_0 ((uint32_t)0x00000010) /* Bit 0 */ +#define RCC_HPRE_1 ((uint32_t)0x00000020) /* Bit 1 */ +#define RCC_HPRE_2 ((uint32_t)0x00000040) /* Bit 2 */ +#define RCC_HPRE_3 ((uint32_t)0x00000080) /* Bit 3 */ + +#define RCC_HPRE_DIV1 ((uint32_t)0x00000000) /* SYSCLK not divided */ +#define RCC_HPRE_DIV2 ((uint32_t)0x00000080) /* SYSCLK divided by 2 */ +#define RCC_HPRE_DIV4 ((uint32_t)0x00000090) /* SYSCLK divided by 4 */ +#define RCC_HPRE_DIV8 ((uint32_t)0x000000A0) /* SYSCLK divided by 8 */ +#define RCC_HPRE_DIV16 ((uint32_t)0x000000B0) /* SYSCLK divided by 16 */ +#define RCC_HPRE_DIV64 ((uint32_t)0x000000C0) /* SYSCLK divided by 64 */ +#define RCC_HPRE_DIV128 ((uint32_t)0x000000D0) /* SYSCLK divided by 128 */ +#define RCC_HPRE_DIV256 ((uint32_t)0x000000E0) /* SYSCLK divided by 256 */ +#define RCC_HPRE_DIV512 ((uint32_t)0x000000F0) /* SYSCLK divided by 512 */ + +#define RCC_PPRE1 ((uint32_t)0x00000700) /* PRE1[2:0] bits (PB1 prescaler) */ +#define RCC_PPRE1_0 ((uint32_t)0x00000100) /* Bit 0 */ +#define RCC_PPRE1_1 ((uint32_t)0x00000200) /* Bit 1 */ +#define RCC_PPRE1_2 ((uint32_t)0x00000400) /* Bit 2 */ + +#define RCC_PPRE1_DIV1 ((uint32_t)0x00000000) /* PPRE1 not divided */ +#define RCC_PPRE1_DIV2 ((uint32_t)0x00000400) /* PPRE1 divided by 2 */ +#define RCC_PPRE1_DIV4 ((uint32_t)0x00000500) /* PPRE1 divided by 4 */ +#define RCC_PPRE1_DIV8 ((uint32_t)0x00000600) /* PPRE1 divided by 8 */ +#define RCC_PPRE1_DIV16 ((uint32_t)0x00000700) /* PPRE1 divided by 16 */ + +#define RCC_PPRE2 ((uint32_t)0x00003800) /* PRE2[2:0] bits (PB2 prescaler) */ +#define RCC_PPRE2_0 ((uint32_t)0x00000800) /* Bit 0 */ +#define RCC_PPRE2_1 ((uint32_t)0x00001000) /* Bit 1 */ +#define RCC_PPRE2_2 ((uint32_t)0x00002000) /* Bit 2 */ + +#define RCC_PPRE2_DIV1 ((uint32_t)0x00000000) /* PPRE2 not divided */ +#define RCC_PPRE2_DIV2 ((uint32_t)0x00002000) /* PPRE2 divided by 2 */ +#define RCC_PPRE2_DIV4 ((uint32_t)0x00002800) /* PPRE2 divided by 4 */ +#define RCC_PPRE2_DIV8 ((uint32_t)0x00003000) /* PPRE2 divided by 8 */ +#define RCC_PPRE2_DIV16 ((uint32_t)0x00003800) /* PPRE2 divided by 16 */ + +#define RCC_ADCPRE ((uint32_t)0x0000C000) /* ADCPRE[1:0] bits (ADC prescaler) */ +#define RCC_ADCPRE_0 ((uint32_t)0x00004000) /* Bit 0 */ +#define RCC_ADCPRE_1 ((uint32_t)0x00008000) /* Bit 1 */ + +#define RCC_ADCPRE_DIV2 ((uint32_t)0x00000000) /* ADCPRE divided by 2 */ +#define RCC_ADCPRE_DIV4 ((uint32_t)0x00004000) /* ADCPRE divided by 4 */ +#define RCC_ADCPRE_DIV6 ((uint32_t)0x00008000) /* ADCPRE divided by 6 */ +#define RCC_ADCPRE_DIV8 ((uint32_t)0x0000C000) /* ADCPRE divided by 8 */ + +#define RCC_PLLSRC ((uint32_t)0x00010000) /* PLL entry clock source */ + +#define RCC_PLLXTPRE ((uint32_t)0x00020000) /* HSE divider for PLL entry */ + +#define RCC_PLLMULL ((uint32_t)0x003C0000) /* PLLMUL[3:0] bits (PLL multiplication factor) */ +#define RCC_PLLMULL_0 ((uint32_t)0x00040000) /* Bit 0 */ +#define RCC_PLLMULL_1 ((uint32_t)0x00080000) /* Bit 1 */ +#define RCC_PLLMULL_2 ((uint32_t)0x00100000) /* Bit 2 */ +#define RCC_PLLMULL_3 ((uint32_t)0x00200000) /* Bit 3 */ + +#define RCC_PLLSRC_HSI_Div2 ((uint32_t)0x00000000) /* HSI clock divided by 2 selected as PLL entry clock source */ +#define RCC_PLLSRC_HSE ((uint32_t)0x00010000) /* HSE clock selected as PLL entry clock source */ + +#define RCC_PLLXTPRE_HSE ((uint32_t)0x00000000) /* HSE clock not divided for PLL entry */ +#define RCC_PLLXTPRE_HSE_Div2 ((uint32_t)0x00020000) /* HSE clock divided by 2 for PLL entry */ + +/* for other CH32L103 */ +#define RCC_PLLMULL2 ((uint32_t)0x00000000) /* PLL input clock*2 */ +#define RCC_PLLMULL3 ((uint32_t)0x00040000) /* PLL input clock*3 */ +#define RCC_PLLMULL4 ((uint32_t)0x00080000) /* PLL input clock*4 */ +#define RCC_PLLMULL5 ((uint32_t)0x000C0000) /* PLL input clock*5 */ +#define RCC_PLLMULL6 ((uint32_t)0x00100000) /* PLL input clock*6 */ +#define RCC_PLLMULL7 ((uint32_t)0x00140000) /* PLL input clock*7 */ +#define RCC_PLLMULL8 ((uint32_t)0x00180000) /* PLL input clock*8 */ +#define RCC_PLLMULL9 ((uint32_t)0x001C0000) /* PLL input clock*9 */ +#define RCC_PLLMULL10 ((uint32_t)0x00200000) /* PLL input clock10 */ +#define RCC_PLLMULL11 ((uint32_t)0x00240000) /* PLL input clock*11 */ +#define RCC_PLLMULL12 ((uint32_t)0x00280000) /* PLL input clock*12 */ +#define RCC_PLLMULL13 ((uint32_t)0x002C0000) /* PLL input clock*13 */ +#define RCC_PLLMULL14 ((uint32_t)0x00300000) /* PLL input clock*14 */ +#define RCC_PLLMULL15 ((uint32_t)0x00340000) /* PLL input clock*15 */ +#define RCC_PLLMULL16 ((uint32_t)0x00380000) /* PLL input clock*16 */ +#define RCC_PLLMULL18 ((uint32_t)0x003C0000) /* PLL input clock*18 */ + +#define RCC_CFGR0_USBPRE ((uint32_t)0x00C00000) /* USBPRE[1:0] bits*/ +#define RCC_USBPRE_0 ((uint32_t)0x00400000) /* Bit 0 */ +#define RCC_USBPRE_1 ((uint32_t)0x00800000) /* Bit 1 */ + +#define RCC_CFGR0_MCO ((uint32_t)0x07000000) /* MCO[2:0] bits (Microcontroller Clock Output) */ +#define RCC_MCO_0 ((uint32_t)0x01000000) /* Bit 0 */ +#define RCC_MCO_1 ((uint32_t)0x02000000) /* Bit 1 */ +#define RCC_MCO_2 ((uint32_t)0x04000000) /* Bit 2 */ + +#define RCC_MCO_NOCLOCK ((uint32_t)0x00000000) /* No clock */ +#define RCC_CFGR0_MCO_SYSCLK ((uint32_t)0x04000000) /* System clock selected as MCO source */ +#define RCC_CFGR0_MCO_HSI ((uint32_t)0x05000000) /* HSI clock selected as MCO source */ +#define RCC_CFGR0_MCO_HSE ((uint32_t)0x06000000) /* HSE clock selected as MCO source */ +#define RCC_CFGR0_MCO_PLL ((uint32_t)0x07000000) /* PLL clock divided by 2 selected as MCO source */ + +#define RCC_ADC_DUTY_CHG ((uint32_t)0x70000000) /* DUTY_CHG[2:0] bits */ +#define RCC_ADC_DUTY_CHG_0 ((uint32_t)0x10000000) +#define RCC_ADC_DUTY_CHG_1 ((uint32_t)0x20000000) +#define RCC_ADC_DUTY_CHG_2 ((uint32_t)0x40000000) + +#define RCC_ADC_PRE_ADJ ((uint32_t)0x80000000) + +/******************* Bit definition for RCC_INTR register ********************/ +#define RCC_LSIRDYF ((uint32_t)0x00000001) /* LSI Ready Interrupt flag */ +#define RCC_LSERDYF ((uint32_t)0x00000002) /* LSE Ready Interrupt flag */ +#define RCC_HSIRDYF ((uint32_t)0x00000004) /* HSI Ready Interrupt flag */ +#define RCC_HSERDYF ((uint32_t)0x00000008) /* HSE Ready Interrupt flag */ +#define RCC_PLLRDYF ((uint32_t)0x00000010) /* PLL Ready Interrupt flag */ +#define RCC_CSSF ((uint32_t)0x00000080) /* Clock Security System Interrupt flag */ +#define RCC_LSIRDYIE ((uint32_t)0x00000100) /* LSI Ready Interrupt Enable */ +#define RCC_LSERDYIE ((uint32_t)0x00000200) /* LSE Ready Interrupt Enable */ +#define RCC_HSIRDYIE ((uint32_t)0x00000400) /* HSI Ready Interrupt Enable */ +#define RCC_HSERDYIE ((uint32_t)0x00000800) /* HSE Ready Interrupt Enable */ +#define RCC_PLLRDYIE ((uint32_t)0x00001000) /* PLL Ready Interrupt Enable */ +#define RCC_LSIRDYC ((uint32_t)0x00010000) /* LSI Ready Interrupt Clear */ +#define RCC_LSERDYC ((uint32_t)0x00020000) /* LSE Ready Interrupt Clear */ +#define RCC_HSIRDYC ((uint32_t)0x00040000) /* HSI Ready Interrupt Clear */ +#define RCC_HSERDYC ((uint32_t)0x00080000) /* HSE Ready Interrupt Clear */ +#define RCC_PLLRDYC ((uint32_t)0x00100000) /* PLL Ready Interrupt Clear */ +#define RCC_CSSC ((uint32_t)0x00800000) /* Clock Security System Interrupt Clear */ + +/***************** Bit definition for RCC_PB2PRSTR register *****************/ +#define RCC_AFIORST ((uint32_t)0x00000001) /* Alternate Function I/O reset */ +#define RCC_IOPARST ((uint32_t)0x00000004) /* I/O port A reset */ +#define RCC_IOPBRST ((uint32_t)0x00000008) /* I/O port B reset */ +#define RCC_IOPCRST ((uint32_t)0x00000010) /* I/O port C reset */ +#define RCC_IOPDRST ((uint32_t)0x00000020) /* I/O port D reset */ +#define RCC_ADCRST ((uint32_t)0x00000200) /* ADC interface reset */ +#define RCC_TIM1RST ((uint32_t)0x00000800) /* TIM1 Timer reset */ +#define RCC_SPI1RST ((uint32_t)0x00001000) /* SPI 1 reset */ +#define RCC_USART1RST ((uint32_t)0x00004000) /* USART1 reset */ + +/***************** Bit definition for RCC_PB1PRSTR register *****************/ +#define RCC_TIM2RST ((uint32_t)0x00000001) /* Timer 2 reset */ +#define RCC_TIM3RST ((uint32_t)0x00000002) /* Timer 3 reset */ +#define RCC_TIM4RST ((uint32_t)0x00000004) +#define RCC_WWDGRST ((uint32_t)0x00000800) /* Window Watchdog reset */ +#define RCC_SPI2RST ((uint32_t)0x00004000) +#define RCC_USART2RST ((uint32_t)0x00020000) /* USART 2 reset */ +#define RCC_USART3RST ((uint32_t)0x00040000) /* USART 2 reset */ +#define RCC_USART4RST ((uint32_t)0x00080000) /* USART 2 reset */ +#define RCC_I2C1RST ((uint32_t)0x00200000) /* I2C 1 reset */ +#define RCC_I2C2RST ((uint32_t)0x00400000) /* I2C 1 reset */ +#define RCC_CANRST ((uint32_t)0x02000000) /* CAN reset */ +#define RCC_BKPRST ((uint32_t)0x08000000) /* Backup interface reset */ +#define RCC_PWRRST ((uint32_t)0x10000000) /* Power interface reset */ +#define RCC_LPTIMRST ((uint32_t)0x80000000) /* USB Device reset */ + +/****************** Bit definition for RCC_HBPCENR register ******************/ +#define RCC_DMAEN ((uint16_t)0x0001) /* DMA clock enable */ +#define RCC_SRAMEN ((uint16_t)0x0004) /* SRAM interface clock enable */ +#define RCC_CRCEN ((uint16_t)0x0040) /* CRC clock enable */ +#define RCC_USBFSEN ((uint16_t)0x1000) +#define RCC_USBPDEN ((uint32_t)0x00020000) + +/****************** Bit definition for RCC_PB2PCENR register *****************/ +#define RCC_AFIOEN ((uint32_t)0x00000001) /* Alternate Function I/O clock enable */ +#define RCC_IOPAEN ((uint32_t)0x00000004) /* I/O port A clock enable */ +#define RCC_IOPBEN ((uint32_t)0x00000008) /* I/O port B clock enable */ +#define RCC_IOPCEN ((uint32_t)0x00000010) /* I/O port C clock enable */ +#define RCC_IOPDEN ((uint32_t)0x00000020) /* I/O port D clock enable */ +#define RCC_ADCEN ((uint32_t)0x00000200) /* ADC interface clock enable */ +#define RCC_TIM1EN ((uint32_t)0x00000800) /* TIM1 Timer clock enable */ +#define RCC_SPI1EN ((uint32_t)0x00001000) /* SPI 1 clock enable */ +#define RCC_USART1EN ((uint32_t)0x00004000) /* USART1 clock enable */ + +/***************** Bit definition for RCC_PB1PCENR register ******************/ +#define RCC_TIM2EN ((uint32_t)0x00000001) /* Timer 2 clock enabled*/ +#define RCC_TIM3EN ((uint32_t)0x00000002) /* Timer 3 clock enable */ +#define RCC_TIM4EN ((uint32_t)0x00000004) +#define RCC_WWDGEN ((uint32_t)0x00000800) /* Window Watchdog clock enable */ +#define RCC_SPI2EN ((uint32_t)0x00004000) +#define RCC_USART2EN ((uint32_t)0x00020000) /* USART 2 clock enable */ +#define RCC_USART3EN ((uint32_t)0x00040000) /* USART 3 clock enable */ +#define RCC_USART4EN ((uint32_t)0x00080000) /* USART 4 clock enable */ +#define RCC_I2C1EN ((uint32_t)0x00200000) /* I2C 1 clock enable */ +#define RCC_I2C2EN ((uint32_t)0x00400000) /* I2C 2 clock enable */ +#define RCC_CANEN ((uint32_t)0x02000000) +#define RCC_BKPEN ((uint32_t)0x08000000) /* Backup interface clock enable */ +#define RCC_PWREN ((uint32_t)0x10000000) /* Power interface clock enable */ +#define RCC_LPTIMEN ((uint32_t)0x80000000) + +/******************* Bit definition for RCC_BDCTLR register *******************/ +#define RCC_LSEON ((uint32_t)0x00000001) /* External Low Speed oscillator enable */ +#define RCC_LSERDY ((uint32_t)0x00000002) /* External Low Speed oscillator Ready */ +#define RCC_LSEBYP ((uint32_t)0x00000004) /* External Low Speed oscillator Bypass */ + +#define RCC_RTCSEL ((uint32_t)0x00000300) /* RTCSEL[1:0] bits (RTC clock source selection) */ +#define RCC_RTCSEL_0 ((uint32_t)0x00000100) /* Bit 0 */ +#define RCC_RTCSEL_1 ((uint32_t)0x00000200) /* Bit 1 */ + +#define RCC_RTCEN ((uint32_t)0x00008000) /* RTC clock enable */ +#define RCC_BDRST ((uint32_t)0x00010000) /* Backup domain software reset */ + +/******************* Bit definition for RCC_RSTSCKR register ********************/ +#define RCC_LSION ((uint32_t)0x00000001) /* Internal Low Speed oscillator enable */ +#define RCC_LSIRDY ((uint32_t)0x00000002) /* Internal Low Speed oscillator Ready */ +#define RCC_RMVF ((uint32_t)0x01000000) /* Remove reset flag */ +#define RCC_PINRSTF ((uint32_t)0x04000000) /* PIN reset flag */ +#define RCC_PORRSTF ((uint32_t)0x08000000) /* POR/PDR reset flag */ +#define RCC_SFTRSTF ((uint32_t)0x10000000) /* Software Reset flag */ +#define RCC_IWDGRSTF ((uint32_t)0x20000000) /* Independent Watchdog reset flag */ +#define RCC_WWDGRSTF ((uint32_t)0x40000000) /* Window watchdog reset flag */ +#define RCC_LPWRRSTF ((uint32_t)0x80000000) /* Low-Power reset flag */ + +/******************************************************************************/ +/* Real-Time Clock */ +/******************************************************************************/ + +/******************* Bit definition for RTC_CTLRH register ********************/ +#define RTC_CTLRH_SECIE ((uint8_t)0x01) /* Second Interrupt Enable */ +#define RTC_CTLRH_ALRIE ((uint8_t)0x02) /* Alarm Interrupt Enable */ +#define RTC_CTLRH_OWIE ((uint8_t)0x04) /* OverfloW Interrupt Enable */ + +/******************* Bit definition for RTC_CTLRL register ********************/ +#define RTC_CTLRL_SECF ((uint8_t)0x01) /* Second Flag */ +#define RTC_CTLRL_ALRF ((uint8_t)0x02) /* Alarm Flag */ +#define RTC_CTLRL_OWF ((uint8_t)0x04) /* OverfloW Flag */ +#define RTC_CTLRL_RSF ((uint8_t)0x08) /* Registers Synchronized Flag */ +#define RTC_CTLRL_CNF ((uint8_t)0x10) /* Configuration Flag */ +#define RTC_CTLRL_RTOFF ((uint8_t)0x20) /* RTC operation OFF */ + +/******************* Bit definition for RTC_PSCRH register *******************/ +#define RTC_PSCRH_PRL ((uint16_t)0x000F) /* RTC Prescaler Reload Value High */ + +/******************* Bit definition for RTC_PRCRL register *******************/ +#define RTC_PRCRL_PRL ((uint16_t)0xFFFF) /* RTC Prescaler Reload Value Low */ + +/******************* Bit definition for RTC_DIVH register *******************/ +#define RTC_DIVH_RTC_DIV ((uint16_t)0x000F) /* RTC Clock Divider High */ + +/******************* Bit definition for RTC_DIVL register *******************/ +#define RTC_DIVL_RTC_DIV ((uint16_t)0xFFFF) /* RTC Clock Divider Low */ + +/******************* Bit definition for RTC_CNTH register *******************/ +#define RTC_CNTH_RTC_CNT ((uint16_t)0xFFFF) /* RTC Counter High */ + +/******************* Bit definition for RTC_CNTL register *******************/ +#define RTC_CNTL_RTC_CNT ((uint16_t)0xFFFF) /* RTC Counter Low */ + +/******************* Bit definition for RTC_ALRMH register *******************/ +#define RTC_ALRMH_RTC_ALRM ((uint16_t)0xFFFF) /* RTC Alarm High */ + +/******************* Bit definition for RTC_ALRML register *******************/ +#define RTC_ALRML_RTC_ALRM ((uint16_t)0xFFFF) /* RTC Alarm Low */ + +/******************************************************************************/ +/* Serial Peripheral Interface */ +/******************************************************************************/ + +/******************* Bit definition for SPI_CTLR1 register ********************/ +#define SPI_CTLR1_CPHA ((uint16_t)0x0001) /* Clock Phase */ +#define SPI_CTLR1_CPOL ((uint16_t)0x0002) /* Clock Polarity */ +#define SPI_CTLR1_MSTR ((uint16_t)0x0004) /* Master Selection */ + +#define SPI_CTLR1_BR ((uint16_t)0x0038) /* BR[2:0] bits (Baud Rate Control) */ +#define SPI_CTLR1_BR_0 ((uint16_t)0x0008) /* Bit 0 */ +#define SPI_CTLR1_BR_1 ((uint16_t)0x0010) /* Bit 1 */ +#define SPI_CTLR1_BR_2 ((uint16_t)0x0020) /* Bit 2 */ + +#define SPI_CTLR1_SPE ((uint16_t)0x0040) /* SPI Enable */ +#define SPI_CTLR1_LSBFIRST ((uint16_t)0x0080) /* Frame Format */ +#define SPI_CTLR1_SSI ((uint16_t)0x0100) /* Internal slave select */ +#define SPI_CTLR1_SSM ((uint16_t)0x0200) /* Software slave management */ +#define SPI_CTLR1_RXONLY ((uint16_t)0x0400) /* Receive only */ +#define SPI_CTLR1_DFF ((uint16_t)0x0800) /* Data Frame Format */ +#define SPI_CTLR1_CRCNEXT ((uint16_t)0x1000) /* Transmit CRC next */ +#define SPI_CTLR1_CRCEN ((uint16_t)0x2000) /* Hardware CRC calculation enable */ +#define SPI_CTLR1_BIDIOE ((uint16_t)0x4000) /* Output enable in bidirectional mode */ +#define SPI_CTLR1_BIDIMODE ((uint16_t)0x8000) /* Bidirectional data mode enable */ + +/******************* Bit definition for SPI_CTLR2 register ********************/ +#define SPI_CTLR2_RXDMAEN ((uint8_t)0x01) /* Rx Buffer DMA Enable */ +#define SPI_CTLR2_TXDMAEN ((uint8_t)0x02) /* Tx Buffer DMA Enable */ +#define SPI_CTLR2_SSOE ((uint8_t)0x04) /* SS Output Enable */ +#define SPI_CTLR2_ERRIE ((uint8_t)0x20) /* Error Interrupt Enable */ +#define SPI_CTLR2_RXNEIE ((uint8_t)0x40) /* RX buffer Not Empty Interrupt Enable */ +#define SPI_CTLR2_TXEIE ((uint8_t)0x80) /* Tx buffer Empty Interrupt Enable */ + +/******************** Bit definition for SPI_STATR register ********************/ +#define SPI_STATR_RXNE ((uint8_t)0x01) /* Receive buffer Not Empty */ +#define SPI_STATR_TXE ((uint8_t)0x02) /* Transmit buffer Empty */ +#define SPI_STATR_CRCERR ((uint8_t)0x10) /* CRC Error flag */ +#define SPI_STATR_MODF ((uint8_t)0x20) /* Mode fault */ +#define SPI_STATR_OVR ((uint8_t)0x40) /* Overrun flag */ +#define SPI_STATR_BSY ((uint8_t)0x80) /* Busy flag */ + +/******************** Bit definition for SPI_DATAR register ********************/ +#define SPI_DATAR_DR ((uint16_t)0xFFFF) /* Data Register */ + +/******************* Bit definition for SPI_CRCR register ******************/ +#define SPI_CRCR_CRCPOLY ((uint16_t)0xFFFF) /* CRC polynomial register */ + +/****************** Bit definition for SPI_RCRCR register ******************/ +#define SPI_RCRCR_RXCRC ((uint16_t)0xFFFF) /* Rx CRC Register */ + +/****************** Bit definition for SPI_TCRCR register ******************/ +#define SPI_TCRCR_TXCRC ((uint16_t)0xFFFF) /* Tx CRC Register */ + +/****************** Bit definition for SPI_HSCR register ******************/ +#define SPI_HSRXEN ((uint16_t)0x0001) + + +/******************************************************************************/ +/* TIM */ +/******************************************************************************/ + +/******************* Bit definition for TIM_CTLR1 register ********************/ +#define TIM_CEN ((uint16_t)0x0001) /* Counter enable */ +#define TIM_UDIS ((uint16_t)0x0002) /* Update disable */ +#define TIM_URS ((uint16_t)0x0004) /* Update request source */ +#define TIM_OPM ((uint16_t)0x0008) /* One pulse mode */ +#define TIM_DIR ((uint16_t)0x0010) /* Direction */ + +#define TIM_CMS ((uint16_t)0x0060) /* CMS[1:0] bits (Center-aligned mode selection) */ +#define TIM_CMS_0 ((uint16_t)0x0020) /* Bit 0 */ +#define TIM_CMS_1 ((uint16_t)0x0040) /* Bit 1 */ + +#define TIM_ARPE ((uint16_t)0x0080) /* Auto-reload preload enable */ + +#define TIM_CTLR1_CKD ((uint16_t)0x0300) /* CKD[1:0] bits (clock division) */ +#define TIM_CKD_0 ((uint16_t)0x0100) /* Bit 0 */ +#define TIM_CKD_1 ((uint16_t)0x0200) /* Bit 1 */ + +#define TIM_BKSEL ((uint16_t)0x1000) +#define TIM_TMR_CAP_OV_EN ((uint16_t)0x4000) +#define TIM_TMR_CAP_LVL_EN ((uint16_t)0x8000) + +/******************* Bit definition for TIM_CTLR2 register ********************/ +#define TIM_CCPC ((uint16_t)0x0001) /* Capture/Compare Preloaded Control */ +#define TIM_CCUS ((uint16_t)0x0004) /* Capture/Compare Control Update Selection */ +#define TIM_CCDS ((uint16_t)0x0008) /* Capture/Compare DMA Selection */ + +#define TIM_MMS ((uint16_t)0x0070) /* MMS[2:0] bits (Master Mode Selection) */ +#define TIM_MMS_0 ((uint16_t)0x0010) /* Bit 0 */ +#define TIM_MMS_1 ((uint16_t)0x0020) /* Bit 1 */ +#define TIM_MMS_2 ((uint16_t)0x0040) /* Bit 2 */ + +#define TIM_TI1S ((uint16_t)0x0080) /* TI1 Selection */ +#define TIM_OIS1 ((uint16_t)0x0100) /* Output Idle state 1 (OC1 output) */ +#define TIM_OIS1N ((uint16_t)0x0200) /* Output Idle state 1 (OC1N output) */ +#define TIM_OIS2 ((uint16_t)0x0400) /* Output Idle state 2 (OC2 output) */ +#define TIM_OIS2N ((uint16_t)0x0800) /* Output Idle state 2 (OC2N output) */ +#define TIM_OIS3 ((uint16_t)0x1000) /* Output Idle state 3 (OC3 output) */ +#define TIM_OIS3N ((uint16_t)0x2000) /* Output Idle state 3 (OC3N output) */ +#define TIM_OIS4 ((uint16_t)0x4000) /* Output Idle state 4 (OC4 output) */ + +/******************* Bit definition for TIM_SMCFGR register *******************/ +#define TIM_SMS ((uint16_t)0x0007) /* SMS[2:0] bits (Slave mode selection) */ +#define TIM_SMS_0 ((uint16_t)0x0001) /* Bit 0 */ +#define TIM_SMS_1 ((uint16_t)0x0002) /* Bit 1 */ +#define TIM_SMS_2 ((uint16_t)0x0004) /* Bit 2 */ + +#define TIM_TS ((uint16_t)0x0070) /* TS[2:0] bits (Trigger selection) */ +#define TIM_TS_0 ((uint16_t)0x0010) /* Bit 0 */ +#define TIM_TS_1 ((uint16_t)0x0020) /* Bit 1 */ +#define TIM_TS_2 ((uint16_t)0x0040) /* Bit 2 */ + +#define TIM_MSM ((uint16_t)0x0080) /* Master/slave mode */ + +#define TIM_ETF ((uint16_t)0x0F00) /* ETF[3:0] bits (External trigger filter) */ +#define TIM_ETF_0 ((uint16_t)0x0100) /* Bit 0 */ +#define TIM_ETF_1 ((uint16_t)0x0200) /* Bit 1 */ +#define TIM_ETF_2 ((uint16_t)0x0400) /* Bit 2 */ +#define TIM_ETF_3 ((uint16_t)0x0800) /* Bit 3 */ + +#define TIM_ETPS ((uint16_t)0x3000) /* ETPS[1:0] bits (External trigger prescaler) */ +#define TIM_ETPS_0 ((uint16_t)0x1000) /* Bit 0 */ +#define TIM_ETPS_1 ((uint16_t)0x2000) /* Bit 1 */ + +#define TIM_ECE ((uint16_t)0x4000) /* External clock enable */ +#define TIM_ETP ((uint16_t)0x8000) /* External trigger polarity */ + +/******************* Bit definition for TIM_DMAINTENR register *******************/ +#define TIM_UIE ((uint16_t)0x0001) /* Update interrupt enable */ +#define TIM_CC1IE ((uint16_t)0x0002) /* Capture/Compare 1 interrupt enable */ +#define TIM_CC2IE ((uint16_t)0x0004) /* Capture/Compare 2 interrupt enable */ +#define TIM_CC3IE ((uint16_t)0x0008) /* Capture/Compare 3 interrupt enable */ +#define TIM_CC4IE ((uint16_t)0x0010) /* Capture/Compare 4 interrupt enable */ +#define TIM_COMIE ((uint16_t)0x0020) /* COM interrupt enable */ +#define TIM_TIE ((uint16_t)0x0040) /* Trigger interrupt enable */ +#define TIM_BIE ((uint16_t)0x0080) /* Break interrupt enable */ +#define TIM_UDE ((uint16_t)0x0100) /* Update DMA request enable */ +#define TIM_CC1DE ((uint16_t)0x0200) /* Capture/Compare 1 DMA request enable */ +#define TIM_CC2DE ((uint16_t)0x0400) /* Capture/Compare 2 DMA request enable */ +#define TIM_CC3DE ((uint16_t)0x0800) /* Capture/Compare 3 DMA request enable */ +#define TIM_CC4DE ((uint16_t)0x1000) /* Capture/Compare 4 DMA request enable */ +#define TIM_COMDE ((uint16_t)0x2000) /* COM DMA request enable */ +#define TIM_TDE ((uint16_t)0x4000) /* Trigger DMA request enable */ + +/******************** Bit definition for TIM_INTFR register ********************/ +#define TIM_UIF ((uint16_t)0x0001) /* Update interrupt Flag */ +#define TIM_CC1IF ((uint16_t)0x0002) /* Capture/Compare 1 interrupt Flag */ +#define TIM_CC2IF ((uint16_t)0x0004) /* Capture/Compare 2 interrupt Flag */ +#define TIM_CC3IF ((uint16_t)0x0008) /* Capture/Compare 3 interrupt Flag */ +#define TIM_CC4IF ((uint16_t)0x0010) /* Capture/Compare 4 interrupt Flag */ +#define TIM_COMIF ((uint16_t)0x0020) /* COM interrupt Flag */ +#define TIM_TIF ((uint16_t)0x0040) /* Trigger interrupt Flag */ +#define TIM_BIF ((uint16_t)0x0080) /* Break interrupt Flag */ +#define TIM_CC1OF ((uint16_t)0x0200) /* Capture/Compare 1 Overcapture Flag */ +#define TIM_CC2OF ((uint16_t)0x0400) /* Capture/Compare 2 Overcapture Flag */ +#define TIM_CC3OF ((uint16_t)0x0800) /* Capture/Compare 3 Overcapture Flag */ +#define TIM_CC4OF ((uint16_t)0x1000) /* Capture/Compare 4 Overcapture Flag */ + +/******************* Bit definition for TIM_SWEVGR register ********************/ +#define TIM_UG ((uint8_t)0x01) /* Update Generation */ +#define TIM_CC1G ((uint8_t)0x02) /* Capture/Compare 1 Generation */ +#define TIM_CC2G ((uint8_t)0x04) /* Capture/Compare 2 Generation */ +#define TIM_CC3G ((uint8_t)0x08) /* Capture/Compare 3 Generation */ +#define TIM_CC4G ((uint8_t)0x10) /* Capture/Compare 4 Generation */ +#define TIM_COMG ((uint8_t)0x20) /* Capture/Compare Control Update Generation */ +#define TIM_TG ((uint8_t)0x40) /* Trigger Generation */ +#define TIM_BG ((uint8_t)0x80) /* Break Generation */ + +/****************** Bit definition for TIM_CHCTLR1 register *******************/ +#define TIM_CC1S ((uint16_t)0x0003) /* CC1S[1:0] bits (Capture/Compare 1 Selection) */ +#define TIM_CC1S_0 ((uint16_t)0x0001) /* Bit 0 */ +#define TIM_CC1S_1 ((uint16_t)0x0002) /* Bit 1 */ + +#define TIM_OC1FE ((uint16_t)0x0004) /* Output Compare 1 Fast enable */ +#define TIM_OC1PE ((uint16_t)0x0008) /* Output Compare 1 Preload enable */ + +#define TIM_OC1M ((uint16_t)0x0070) /* OC1M[2:0] bits (Output Compare 1 Mode) */ +#define TIM_OC1M_0 ((uint16_t)0x0010) /* Bit 0 */ +#define TIM_OC1M_1 ((uint16_t)0x0020) /* Bit 1 */ +#define TIM_OC1M_2 ((uint16_t)0x0040) /* Bit 2 */ + +#define TIM_OC1CE ((uint16_t)0x0080) /* Output Compare 1Clear Enable */ + +#define TIM_CC2S ((uint16_t)0x0300) /* CC2S[1:0] bits (Capture/Compare 2 Selection) */ +#define TIM_CC2S_0 ((uint16_t)0x0100) /* Bit 0 */ +#define TIM_CC2S_1 ((uint16_t)0x0200) /* Bit 1 */ + +#define TIM_OC2FE ((uint16_t)0x0400) /* Output Compare 2 Fast enable */ +#define TIM_OC2PE ((uint16_t)0x0800) /* Output Compare 2 Preload enable */ + +#define TIM_OC2M ((uint16_t)0x7000) /* OC2M[2:0] bits (Output Compare 2 Mode) */ +#define TIM_OC2M_0 ((uint16_t)0x1000) /* Bit 0 */ +#define TIM_OC2M_1 ((uint16_t)0x2000) /* Bit 1 */ +#define TIM_OC2M_2 ((uint16_t)0x4000) /* Bit 2 */ + +#define TIM_OC2CE ((uint16_t)0x8000) /* Output Compare 2 Clear Enable */ + +#define TIM_IC1PSC ((uint16_t)0x000C) /* IC1PSC[1:0] bits (Input Capture 1 Prescaler) */ +#define TIM_IC1PSC_0 ((uint16_t)0x0004) /* Bit 0 */ +#define TIM_IC1PSC_1 ((uint16_t)0x0008) /* Bit 1 */ + +#define TIM_IC1F ((uint16_t)0x00F0) /* IC1F[3:0] bits (Input Capture 1 Filter) */ +#define TIM_IC1F_0 ((uint16_t)0x0010) /* Bit 0 */ +#define TIM_IC1F_1 ((uint16_t)0x0020) /* Bit 1 */ +#define TIM_IC1F_2 ((uint16_t)0x0040) /* Bit 2 */ +#define TIM_IC1F_3 ((uint16_t)0x0080) /* Bit 3 */ + +#define TIM_IC2PSC ((uint16_t)0x0C00) /* IC2PSC[1:0] bits (Input Capture 2 Prescaler) */ +#define TIM_IC2PSC_0 ((uint16_t)0x0400) /* Bit 0 */ +#define TIM_IC2PSC_1 ((uint16_t)0x0800) /* Bit 1 */ + +#define TIM_IC2F ((uint16_t)0xF000) /* IC2F[3:0] bits (Input Capture 2 Filter) */ +#define TIM_IC2F_0 ((uint16_t)0x1000) /* Bit 0 */ +#define TIM_IC2F_1 ((uint16_t)0x2000) /* Bit 1 */ +#define TIM_IC2F_2 ((uint16_t)0x4000) /* Bit 2 */ +#define TIM_IC2F_3 ((uint16_t)0x8000) /* Bit 3 */ + +/****************** Bit definition for TIM_CHCTLR2 register *******************/ +#define TIM_CC3S ((uint16_t)0x0003) /* CC3S[1:0] bits (Capture/Compare 3 Selection) */ +#define TIM_CC3S_0 ((uint16_t)0x0001) /* Bit 0 */ +#define TIM_CC3S_1 ((uint16_t)0x0002) /* Bit 1 */ + +#define TIM_OC3FE ((uint16_t)0x0004) /* Output Compare 3 Fast enable */ +#define TIM_OC3PE ((uint16_t)0x0008) /* Output Compare 3 Preload enable */ + +#define TIM_OC3M ((uint16_t)0x0070) /* OC3M[2:0] bits (Output Compare 3 Mode) */ +#define TIM_OC3M_0 ((uint16_t)0x0010) /* Bit 0 */ +#define TIM_OC3M_1 ((uint16_t)0x0020) /* Bit 1 */ +#define TIM_OC3M_2 ((uint16_t)0x0040) /* Bit 2 */ + +#define TIM_OC3CE ((uint16_t)0x0080) /* Output Compare 3 Clear Enable */ + +#define TIM_CC4S ((uint16_t)0x0300) /* CC4S[1:0] bits (Capture/Compare 4 Selection) */ +#define TIM_CC4S_0 ((uint16_t)0x0100) /* Bit 0 */ +#define TIM_CC4S_1 ((uint16_t)0x0200) /* Bit 1 */ + +#define TIM_OC4FE ((uint16_t)0x0400) /* Output Compare 4 Fast enable */ +#define TIM_OC4PE ((uint16_t)0x0800) /* Output Compare 4 Preload enable */ + +#define TIM_OC4M ((uint16_t)0x7000) /* OC4M[2:0] bits (Output Compare 4 Mode) */ +#define TIM_OC4M_0 ((uint16_t)0x1000) /* Bit 0 */ +#define TIM_OC4M_1 ((uint16_t)0x2000) /* Bit 1 */ +#define TIM_OC4M_2 ((uint16_t)0x4000) /* Bit 2 */ + +#define TIM_OC4CE ((uint16_t)0x8000) /* Output Compare 4 Clear Enable */ + +#define TIM_IC3PSC ((uint16_t)0x000C) /* IC3PSC[1:0] bits (Input Capture 3 Prescaler) */ +#define TIM_IC3PSC_0 ((uint16_t)0x0004) /* Bit 0 */ +#define TIM_IC3PSC_1 ((uint16_t)0x0008) /* Bit 1 */ + +#define TIM_IC3F ((uint16_t)0x00F0) /* IC3F[3:0] bits (Input Capture 3 Filter) */ +#define TIM_IC3F_0 ((uint16_t)0x0010) /* Bit 0 */ +#define TIM_IC3F_1 ((uint16_t)0x0020) /* Bit 1 */ +#define TIM_IC3F_2 ((uint16_t)0x0040) /* Bit 2 */ +#define TIM_IC3F_3 ((uint16_t)0x0080) /* Bit 3 */ + +#define TIM_IC4PSC ((uint16_t)0x0C00) /* IC4PSC[1:0] bits (Input Capture 4 Prescaler) */ +#define TIM_IC4PSC_0 ((uint16_t)0x0400) /* Bit 0 */ +#define TIM_IC4PSC_1 ((uint16_t)0x0800) /* Bit 1 */ + +#define TIM_IC4F ((uint16_t)0xF000) /* IC4F[3:0] bits (Input Capture 4 Filter) */ +#define TIM_IC4F_0 ((uint16_t)0x1000) /* Bit 0 */ +#define TIM_IC4F_1 ((uint16_t)0x2000) /* Bit 1 */ +#define TIM_IC4F_2 ((uint16_t)0x4000) /* Bit 2 */ +#define TIM_IC4F_3 ((uint16_t)0x8000) /* Bit 3 */ + +/******************* Bit definition for TIM_CCER register *******************/ +#define TIM_CC1E ((uint16_t)0x0001) /* Capture/Compare 1 output enable */ +#define TIM_CC1P ((uint16_t)0x0002) /* Capture/Compare 1 output Polarity */ +#define TIM_CC1NE ((uint16_t)0x0004) /* Capture/Compare 1 Complementary output enable */ +#define TIM_CC1NP ((uint16_t)0x0008) /* Capture/Compare 1 Complementary output Polarity */ +#define TIM_CC2E ((uint16_t)0x0010) /* Capture/Compare 2 output enable */ +#define TIM_CC2P ((uint16_t)0x0020) /* Capture/Compare 2 output Polarity */ +#define TIM_CC2NE ((uint16_t)0x0040) /* Capture/Compare 2 Complementary output enable */ +#define TIM_CC2NP ((uint16_t)0x0080) /* Capture/Compare 2 Complementary output Polarity */ +#define TIM_CC3E ((uint16_t)0x0100) /* Capture/Compare 3 output enable */ +#define TIM_CC3P ((uint16_t)0x0200) /* Capture/Compare 3 output Polarity */ +#define TIM_CC3NE ((uint16_t)0x0400) /* Capture/Compare 3 Complementary output enable */ +#define TIM_CC3NP ((uint16_t)0x0800) /* Capture/Compare 3 Complementary output Polarity */ +#define TIM_CC4E ((uint16_t)0x1000) /* Capture/Compare 4 output enable */ +#define TIM_CC4P ((uint16_t)0x2000) /* Capture/Compare 4 output Polarity */ + +/******************* Bit definition for TIM_CNT register ********************/ +#define TIM_CNT ((uint16_t)0xFFFF) /* Counter Value */ + +#define TIM4_CNT ((uint32_t)0xFFFFFFFF) /* Counter Value */ + +/******************* Bit definition for TIM_PSC register ********************/ +#define TIM_PSC ((uint16_t)0xFFFF) /* Prescaler Value */ + +/******************* Bit definition for TIM_ATRLR register ********************/ +#define TIM_ARR ((uint16_t)0xFFFF) /* actual auto-reload Value */ + +/******************* Bit definition for TIM_RPTCR register ********************/ +#define TIM_REP ((uint8_t)0xFF) /* Repetition Counter Value */ + +/******************* Bit definition for TIM_CH1CVR register *******************/ +#define TIM_CCR1 ((uint16_t)0xFFFF) /* Capture/Compare 1 Value */ +#define TIM_LEVEL1 ((uint32_t)0x00010000) + +/******************* Bit definition for TIM_CH2CVR register *******************/ +#define TIM_CCR2 ((uint16_t)0xFFFF) /* Capture/Compare 2 Value */ +#define TIM_LEVEL2 ((uint32_t)0x00010000) + +/******************* Bit definition for TIM_CH3CVR register *******************/ +#define TIM_CCR3 ((uint16_t)0xFFFF) /* Capture/Compare 3 Value */ +#define TIM_LEVEL3 ((uint32_t)0x00010000) + +/******************* Bit definition for TIM_CH4CVR register *******************/ +#define TIM_CCR4 ((uint16_t)0xFFFF) /* Capture/Compare 4 Value */ +#define TIM_LEVEL4 ((uint32_t)0x00010000) + +/******************* Bit definition for TIM_BDTR register *******************/ +#define TIM_DTG ((uint16_t)0x00FF) /* DTG[0:7] bits (Dead-Time Generator set-up) */ +#define TIM_DTG_0 ((uint16_t)0x0001) /* Bit 0 */ +#define TIM_DTG_1 ((uint16_t)0x0002) /* Bit 1 */ +#define TIM_DTG_2 ((uint16_t)0x0004) /* Bit 2 */ +#define TIM_DTG_3 ((uint16_t)0x0008) /* Bit 3 */ +#define TIM_DTG_4 ((uint16_t)0x0010) /* Bit 4 */ +#define TIM_DTG_5 ((uint16_t)0x0020) /* Bit 5 */ +#define TIM_DTG_6 ((uint16_t)0x0040) /* Bit 6 */ +#define TIM_DTG_7 ((uint16_t)0x0080) /* Bit 7 */ + +#define TIM_LOCK ((uint16_t)0x0300) /* LOCK[1:0] bits (Lock Configuration) */ +#define TIM_LOCK_0 ((uint16_t)0x0100) /* Bit 0 */ +#define TIM_LOCK_1 ((uint16_t)0x0200) /* Bit 1 */ + +#define TIM_OSSI ((uint16_t)0x0400) /* Off-State Selection for Idle mode */ +#define TIM_OSSR ((uint16_t)0x0800) /* Off-State Selection for Run mode */ +#define TIM_BKE ((uint16_t)0x1000) /* Break enable */ +#define TIM_BKP ((uint16_t)0x2000) /* Break Polarity */ +#define TIM_AOE ((uint16_t)0x4000) /* Automatic Output enable */ +#define TIM_MOE ((uint16_t)0x8000) /* Main Output enable */ + +/******************* Bit definition for TIM_DMACFGR register ********************/ +#define TIM_DBA ((uint16_t)0x001F) /* DBA[4:0] bits (DMA Base Address) */ +#define TIM_DBA_0 ((uint16_t)0x0001) /* Bit 0 */ +#define TIM_DBA_1 ((uint16_t)0x0002) /* Bit 1 */ +#define TIM_DBA_2 ((uint16_t)0x0004) /* Bit 2 */ +#define TIM_DBA_3 ((uint16_t)0x0008) /* Bit 3 */ +#define TIM_DBA_4 ((uint16_t)0x0010) /* Bit 4 */ + +#define TIM_DBL ((uint16_t)0x1F00) /* DBL[4:0] bits (DMA Burst Length) */ +#define TIM_DBL_0 ((uint16_t)0x0100) /* Bit 0 */ +#define TIM_DBL_1 ((uint16_t)0x0200) /* Bit 1 */ +#define TIM_DBL_2 ((uint16_t)0x0400) /* Bit 2 */ +#define TIM_DBL_3 ((uint16_t)0x0800) /* Bit 3 */ +#define TIM_DBL_4 ((uint16_t)0x1000) /* Bit 4 */ + +/******************* Bit definition for TIM_DMAADR register *******************/ +#define TIM_DMAR_DMAB ((uint32_t)0xFFFFFFFF) /* DMA register for burst accesses */ + +/******************************************************************************/ +/* Universal Synchronous Asynchronous Receiver Transmitter */ +/******************************************************************************/ + +/******************* Bit definition for USART_STATR register *******************/ +#define USART_STATR_PE ((uint16_t)0x0001) /* Parity Error */ +#define USART_STATR_FE ((uint16_t)0x0002) /* Framing Error */ +#define USART_STATR_NE ((uint16_t)0x0004) /* Noise Error Flag */ +#define USART_STATR_ORE ((uint16_t)0x0008) /* OverRun Error */ +#define USART_STATR_IDLE ((uint16_t)0x0010) /* IDLE line detected */ +#define USART_STATR_RXNE ((uint16_t)0x0020) /* Read Data Register Not Empty */ +#define USART_STATR_TC ((uint16_t)0x0040) /* Transmission Complete */ +#define USART_STATR_TXE ((uint16_t)0x0080) /* Transmit Data Register Empty */ +#define USART_STATR_LBD ((uint16_t)0x0100) /* LIN Break Detection Flag */ +#define USART_STATR_CTS ((uint16_t)0x0200) /* CTS Flag */ + +/******************* Bit definition for USART_DATAR register *******************/ +#define USART_DATAR_DR ((uint16_t)0x01FF) /* Data value */ + +/****************** Bit definition for USART_BRR register *******************/ +#define USART_BRR_DIV_Fraction ((uint16_t)0x000F) /* Fraction of USARTDIV */ +#define USART_BRR_DIV_Mantissa ((uint16_t)0xFFF0) /* Mantissa of USARTDIV */ + +/****************** Bit definition for USART_CTLR1 register *******************/ +#define USART_CTLR1_SBK ((uint16_t)0x0001) /* Send Break */ +#define USART_CTLR1_RWU ((uint16_t)0x0002) /* Receiver wakeup */ +#define USART_CTLR1_RE ((uint16_t)0x0004) /* Receiver Enable */ +#define USART_CTLR1_TE ((uint16_t)0x0008) /* Transmitter Enable */ +#define USART_CTLR1_IDLEIE ((uint16_t)0x0010) /* IDLE Interrupt Enable */ +#define USART_CTLR1_RXNEIE ((uint16_t)0x0020) /* RXNE Interrupt Enable */ +#define USART_CTLR1_TCIE ((uint16_t)0x0040) /* Transmission Complete Interrupt Enable */ +#define USART_CTLR1_TXEIE ((uint16_t)0x0080) /* PE Interrupt Enable */ +#define USART_CTLR1_PEIE ((uint16_t)0x0100) /* PE Interrupt Enable */ +#define USART_CTLR1_PS ((uint16_t)0x0200) /* Parity Selection */ +#define USART_CTLR1_PCE ((uint16_t)0x0400) /* Parity Control Enable */ +#define USART_CTLR1_WAKE ((uint16_t)0x0800) /* Wakeup method */ +#define USART_CTLR1_M ((uint16_t)0x1000) /* Word length */ +#define USART_CTLR1_UE ((uint16_t)0x2000) /* USART Enable */ + +/****************** Bit definition for USART_CTLR2 register *******************/ +#define USART_CTLR2_ADD ((uint16_t)0x000F) /* Address of the USART node */ +#define USART_CTLR2_LBDL ((uint16_t)0x0020) /* LIN Break Detection Length */ +#define USART_CTLR2_LBDIE ((uint16_t)0x0040) /* LIN Break Detection Interrupt Enable */ +#define USART_CTLR2_LBCL ((uint16_t)0x0100) /* Last Bit Clock pulse */ +#define USART_CTLR2_CPHA ((uint16_t)0x0200) /* Clock Phase */ +#define USART_CTLR2_CPOL ((uint16_t)0x0400) /* Clock Polarity */ +#define USART_CTLR2_CLKEN ((uint16_t)0x0800) /* Clock Enable */ + +#define USART_CTLR2_STOP ((uint16_t)0x3000) /* STOP[1:0] bits (STOP bits) */ +#define USART_CTLR2_STOP_0 ((uint16_t)0x1000) /* Bit 0 */ +#define USART_CTLR2_STOP_1 ((uint16_t)0x2000) /* Bit 1 */ + +#define USART_CTLR2_LINEN ((uint16_t)0x4000) /* LIN mode enable */ + +/****************** Bit definition for USART_CTLR3 register *******************/ +#define USART_CTLR3_EIE ((uint16_t)0x0001) /* Error Interrupt Enable */ +#define USART_CTLR3_IREN ((uint16_t)0x0002) /* IrDA mode Enable */ +#define USART_CTLR3_IRLP ((uint16_t)0x0004) /* IrDA Low-Power */ +#define USART_CTLR3_HDSEL ((uint16_t)0x0008) /* Half-Duplex Selection */ +#define USART_CTLR3_NACK ((uint16_t)0x0010) /* Smartcard NACK enable */ +#define USART_CTLR3_SCEN ((uint16_t)0x0020) /* Smartcard mode enable */ +#define USART_CTLR3_DMAR ((uint16_t)0x0040) /* DMA Enable Receiver */ +#define USART_CTLR3_DMAT ((uint16_t)0x0080) /* DMA Enable Transmitter */ +#define USART_CTLR3_RTSE ((uint16_t)0x0100) /* RTS Enable */ +#define USART_CTLR3_CTSE ((uint16_t)0x0200) /* CTS Enable */ +#define USART_CTLR3_CTSIE ((uint16_t)0x0400) /* CTS Interrupt Enable */ + +/****************** Bit definition for USART_GPR register ******************/ +#define USART_GPR_PSC ((uint16_t)0x00FF) /* PSC[7:0] bits (Prescaler value) */ +#define USART_GPR_PSC_0 ((uint16_t)0x0001) /* Bit 0 */ +#define USART_GPR_PSC_1 ((uint16_t)0x0002) /* Bit 1 */ +#define USART_GPR_PSC_2 ((uint16_t)0x0004) /* Bit 2 */ +#define USART_GPR_PSC_3 ((uint16_t)0x0008) /* Bit 3 */ +#define USART_GPR_PSC_4 ((uint16_t)0x0010) /* Bit 4 */ +#define USART_GPR_PSC_5 ((uint16_t)0x0020) /* Bit 5 */ +#define USART_GPR_PSC_6 ((uint16_t)0x0040) /* Bit 6 */ +#define USART_GPR_PSC_7 ((uint16_t)0x0080) /* Bit 7 */ + +#define USART_GPR_GT ((uint16_t)0xFF00) /* Guard time value */ + +/******************************************************************************/ +/* Window WATCHDOG */ +/******************************************************************************/ + +/******************* Bit definition for WWDG_CTLR register ********************/ +#define WWDG_CTLR_T ((uint8_t)0x7F) /* T[6:0] bits (7-Bit counter (MSB to LSB)) */ +#define WWDG_CTLR_T0 ((uint8_t)0x01) /* Bit 0 */ +#define WWDG_CTLR_T1 ((uint8_t)0x02) /* Bit 1 */ +#define WWDG_CTLR_T2 ((uint8_t)0x04) /* Bit 2 */ +#define WWDG_CTLR_T3 ((uint8_t)0x08) /* Bit 3 */ +#define WWDG_CTLR_T4 ((uint8_t)0x10) /* Bit 4 */ +#define WWDG_CTLR_T5 ((uint8_t)0x20) /* Bit 5 */ +#define WWDG_CTLR_T6 ((uint8_t)0x40) /* Bit 6 */ + +#define WWDG_CTLR_WDGA ((uint8_t)0x80) /* Activation bit */ + +/******************* Bit definition for WWDG_CFGR register *******************/ +#define WWDG_CFGR_W ((uint16_t)0x007F) /* W[6:0] bits (7-bit window value) */ +#define WWDG_CFGR_W0 ((uint16_t)0x0001) /* Bit 0 */ +#define WWDG_CFGR_W1 ((uint16_t)0x0002) /* Bit 1 */ +#define WWDG_CFGR_W2 ((uint16_t)0x0004) /* Bit 2 */ +#define WWDG_CFGR_W3 ((uint16_t)0x0008) /* Bit 3 */ +#define WWDG_CFGR_W4 ((uint16_t)0x0010) /* Bit 4 */ +#define WWDG_CFGR_W5 ((uint16_t)0x0020) /* Bit 5 */ +#define WWDG_CFGR_W6 ((uint16_t)0x0040) /* Bit 6 */ + +#define WWDG_CFGR_WDGTB ((uint16_t)0x0180) /* WDGTB[1:0] bits (Timer Base) */ +#define WWDG_CFGR_WDGTB0 ((uint16_t)0x0080) /* Bit 0 */ +#define WWDG_CFGR_WDGTB1 ((uint16_t)0x0100) /* Bit 1 */ + +#define WWDG_CFGR_EWI ((uint16_t)0x0200) /* Early Wakeup Interrupt */ + +/******************* Bit definition for WWDG_STATR register ********************/ +#define WWDG_STATR_EWIF ((uint8_t)0x01) /* Early Wakeup Interrupt Flag */ + +/******************************************************************************/ +/* ENHANCED FUNNCTION */ +/******************************************************************************/ + +/**************************** Enhanced register *****************************/ +#define EXTEN_PLL_HSI_PRE ((uint32_t)0x00000010) /* Bit 4 */ +#define EXTEN_LOCKUP_EN ((uint32_t)0x00000040) /* Bit 5 */ +#define EXTEN_LOCKUP_RSTF ((uint32_t)0x00000080) /* Bit 7 */ + +#define EXTEN_ULLDO_TRIM ((uint32_t)0x00000700) /* ULLDO_TRIM[2:0] bits */ +#define EXTEN_ULLDO_TRIM0 ((uint32_t)0x00000100) /* Bit 0 */ +#define EXTEN_ULLDO_TRIM1 ((uint32_t)0x00000200) /* Bit 1 */ +#define EXTEN_ULLDO_TRIM2 ((uint32_t)0x00000400) /* Bit 2 */ + +#define EXTEN_LDO_TRIM ((uint32_t)0x00003000) /* LDO_TRIM[1:0] bits */ +#define EXTEN_LDO_TRIM0 ((uint32_t)0x00001000) /* Bit 0 */ +#define EXTEN_LDO_TRIM1 ((uint32_t)0x00002000) /* Bit 1 */ + +/******************************************************************************/ +/* DEBUG SUPPORT */ +/******************************************************************************/ +/******************* Bit definition for DBGMCU_DR register *******************/ +#define DBG_DEBUGMCU_SLEEP ((uint32_t)0x00000001) +#define DBG_DEBUGMCU_STOP ((uint32_t)0x00000002) +#define DBG_DEBUGMCU_STBY ((uint32_t)0x00000004) +#define DBG_DEBUGMCU_IWDG_STOP ((uint32_t)0x00000100) +#define DBG_DEBUGMCU_WWDG_STOP ((uint32_t)0x00000200) +#define DBG_DEBUGMCU_I2C1SMBUS_TOUT ((uint32_t)0x00000400) +#define DBG_DEBUGMCU_I2C2SMBUS_TOUT ((uint32_t)0x00000800) +#define DBG_DEBUGMCU_TIM1_STOP ((uint32_t)0x00001000) +#define DBG_DEBUGMCU_TIM2_STOP ((uint32_t)0x00002000) +#define DBG_DEBUGMCU_TIM3_STOP ((uint32_t)0x00004000) +#define DBG_DEBUGMCU_TIM4_STOP ((uint32_t)0x00008000) +#define DBG_DEBUGMCU_CAN_STOP ((uint32_t)0x00010000) + +/******************************************************************************/ +/* OPTICAL PARAMETER */ +/******************************************************************************/ + +/******************* Bit definition for OPA_CFGR1 register *******************/ +#define OPA_CFGR1_POLLEN ((uint32_t)0x00000001) +#define OPA_CFGR1_BKINEN ((uint32_t)0x00000004) +#define OPA_CFGR1_RSTEN ((uint32_t)0x00000010) +#define OPA_CFGR1_OPCMLOCK ((uint32_t)0x00000080) +#define OPA_CFGR1_IEOUT ((uint32_t)0x00000100) +#define OPA_CFGR1_IECNT ((uint32_t)0x00000400) +#define OPA_CFGR1_NMIEN ((uint32_t)0x00000800) +#define OPA_CFGR1_IFOUT ((uint32_t)0x00001000) +#define OPA_CFGR1_IFCNT ((uint32_t)0x00004000) + +/******************* Bit definition for OPA_CFGR2 register *******************/ +#define OPA_CFGR2_POLL_VLU ((uint32_t)0x000001FF) +#define OPA_CFGR2_POLL_NUM ((uint32_t)0x00000E00) +#define OPA_CFGR2_POLL_CNT ((uint32_t)0x00007000) + +/******************* Bit definition for OPA_CTLR1 register *******************/ +#define OPA_CTLR1_EN1 ((uint32_t)0x00000001) +#define OPA_CTLR1_MODE1 ((uint32_t)0x0000000E) +#define OPA_CTLR1_PSEL1 ((uint32_t)0x00000070) +#define OPA_CTLR1_FBEN1 ((uint32_t)0x00000080) +#define OPA_CTLR1_NSEL1 ((uint32_t)0x00000F00) +#define OPA_CTLR1_LP1 ((uint32_t)0x00001000) +#define OPA_CTLR1_INTRIMP ((uint32_t)0x00010000) +#define OPA_CTLR1_ITRIMP ((uint32_t)0x003E0000) +#define OPA_CTLR1_INTRIMN ((uint32_t)0x01000000) +#define OPA_CTLR1_ITRIMN ((uint32_t)0x3E000000) + +/******************* Bit definition for OPA_CTLR2 register *******************/ +#define OPA_CTLR2_EN1 ((uint32_t)0x00000001) +#define OPA_CTLR2_MODE1 ((uint32_t)0x00000006) +#define OPA_CTLR2_NSEL1 ((uint32_t)0x00000008) +#define OPA_CTLR2_PSEL1 ((uint32_t)0x00000010) +#define OPA_CTLR2_HYEN1 ((uint32_t)0x00000020) +#define OPA_CTLR2_LP1 ((uint32_t)0x00000040) +#define OPA_CTLR2_EN2 ((uint32_t)0x00000100) +#define OPA_CTLR2_MODE2 ((uint32_t)0x00000600) +#define OPA_CTLR2_NSEL2 ((uint32_t)0x00000800) +#define OPA_CTLR2_PSEL2 ((uint32_t)0x00001000) +#define OPA_CTLR2_HYEN2 ((uint32_t)0x00002000) +#define OPA_CTLR2_LP2 ((uint32_t)0x00004000) +#define OPA_CTLR2_EN3 ((uint32_t)0x00010000) +#define OPA_CTLR2_MODE3 ((uint32_t)0x00060000) +#define OPA_CTLR2_NSEL3 ((uint32_t)0x00080000) +#define OPA_CTLR2_PSEL3 ((uint32_t)0x00100000) +#define OPA_CTLR2_HYEN3 ((uint32_t)0x00200000) +#define OPA_CTLR2_LP3 ((uint32_t)0x00400000) + +#define OPA_CTLR2_WKUP_MD ((uint32_t)0x03000000) +#define OPA_CTLR2_WKUP_MD_0 ((uint32_t)0x01000000) +#define OPA_CTLR2_WKUP_MD_1 ((uint32_t)0x02000000) + +/******************* Bit definition for OPCMKEY register *******************/ +#define OPCM_KEY ((uint32_t)0xFFFFFFFF) + +/******************************************************************************/ +/* LOW POWER TIM */ +/******************************************************************************/ +/******************* Bit definition for LPTIM_ISR register *******************/ +#define LPTIM_ISR_CMPM ((uint32_t)0x00000001) +#define LPTIM_ISR_ARRM ((uint32_t)0x00000002) +#define LPTIM_ISR_EXTTRIG ((uint32_t)0x00000004) +#define LPTIM_ISR_CMPOK ((uint32_t)0x00000008) +#define LPTIM_ISR_ARROK ((uint32_t)0000000010) +#define LPTIM_ISR_UP ((uint32_t)0x00000020) +#define LPTIM_ISR_DOWN ((uint32_t)0x00000040) +#define LPTIM_ISR_DIRSYNC ((uint32_t)0x00000080) + +/******************* Bit definition for LPTIM_ICR register *******************/ +#define LPTIM_ICR_CMPMCF ((uint32_t)0x00000001) +#define LPTIM_ICR_ARRMCF ((uint32_t)0x00000002) +#define LPTIM_ICR_EXTTRIGCF ((uint32_t)0x00000004) +#define LPTIM_ICR_CMPOKCF ((uint32_t)0x00000008) +#define LPTIM_ICR_ARROKCF ((uint32_t)0x00000010) +#define LPTIM_ICR_UPCF ((uint32_t)0x00000020) +#define LPTIM_ICR_DOWNCF ((uint32_t)0x00000040) + +/******************* Bit definition for LPTIM_IER register *******************/ +#define LPTIM_IER_CMPMIE ((uint32_t)0x00000001) +#define LPTIM_IER_ARRMIE ((uint32_t)0x00000002) +#define LPTIM_IER_EXTTRIGIE ((uint32_t)0x00000004) +#define LPTIM_IER_CMPOKIE ((uint32_t)0x00000008) +#define LPTIM_IER_ARROKIE ((uint32_t)0x00000010) +#define LPTIM_IER_UPIE ((uint32_t)0x00000020) +#define LPTIM_IER_DOWNIE ((uint32_t)0x00000040) + +/******************* Bit definition for LPTIM_CFGR register *******************/ +#define LPTIM_CFGR_CKSEL ((uint32_t)0x00000001) +#define LPTIM_CFGR_CKPOL ((uint32_t)0x00000006) +#define LPTIM_CFGR_CKFLT ((uint32_t)0x00000018) +#define LPTIM_CFGR_TRGFLT ((uint32_t)0x000000C0) +#define LPTIM_CFGR_PRESC ((uint32_t)0x00000E00) +#define LPTIM_CFGR_TRIGSEL ((uint32_t)0x00006000) +#define LPTIM_CFGR_TRIGEN ((uint32_t)0x00060000) +#define LPTIM_CFGR_TIMOUT ((uint32_t)0x00080000) +#define LPTIM_CFGR_WAVE ((uint32_t)0x00100000) +#define LPTIM_CFGR_WAVPOL ((uint32_t)0x00200000) +#define LPTIM_CFGR_PRELOAD ((uint32_t)0x00400000) +#define LPTIM_CFGR_CONTMODE ((uint32_t)0x00800000) +#define LPTIM_CFGR_ENC ((uint32_t)0x01000000) +#define LPTIM_CFGR_CLKSEL ((uint32_t)0x06000000) +#define LPTIM_CFGR_FORCEPWM ((uint32_t)0x08000000) + +/******************* Bit definition for LPTIM_CR register *******************/ +#define LPTIM_CR_ENABLE ((uint32_t)0x00000001) +#define LPTIM_CR_SNGSTRT ((uint32_t)0x00000002) +#define LPTIM_CR_CNTSTRT ((uint32_t)0x00000004) +#define LPTIM_CR_OUTEN ((uint32_t)0x00000008) +#define LPTIM_CR_DIR_EXTEN ((uint32_t)0x00000010) + +/******************* Bit definition for LPTIM_CMP register *******************/ +#define LPTIM_CMP ((uint32_t)0x0000FFFF) + +/******************* Bit definition for LPTIM_ARR register *******************/ +#define LPTIM_ARR ((uint32_t)0x0000FFFF) + +/******************* Bit definition for LPTIM_CNT register *******************/ +#define LPTIM_COUNT ((uint32_t)0x0000FFFF) + +/******************************************************************************/ +/* TOUCH KEY */ +/******************************************************************************/ +/******************* Bit definition for TKEY_CHARGE register *******************/ +#define TKEY_CHGOFFSET ((uint32_t)0x000003FF) + +/******************* Bit definition for TKEY_ACT_DCG register *******************/ +#define TKEY_TKACTDCG ((uint32_t)0x000003FF) + +/******************* Bit definition for TKEY_DR register *******************/ +#define TKEY_DR ((uint32_t)0x0000FFFF) + +#include "ch32l103_conf.h" + +#ifdef __cplusplus +} +#endif + +#endif + diff --git a/ZDBMS/BMS_CC/Peripheral/inc/ch32l103_adc.h b/ZDBMS/BMS_CC/Peripheral/inc/ch32l103_adc.h new file mode 100644 index 0000000..7494a2c --- /dev/null +++ b/ZDBMS/BMS_CC/Peripheral/inc/ch32l103_adc.h @@ -0,0 +1,211 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32l103_adc.h + * Author : WCH + * Version : V1.0.0 + * Date : 2024/05/06 + * Description : This file contains all the functions prototypes for the + * ADC firmware library. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#ifndef __CH32L103_ADC_H +#define __CH32L103_ADC_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "ch32l103.h" + +/* ADC Init structure definition */ +typedef struct +{ + uint32_t ADC_Mode; /* Configures the ADC to operate in independent or + dual mode. + This parameter can be a value of @ref ADC_mode */ + + FunctionalState ADC_ScanConvMode; /* Specifies whether the conversion is performed in + Scan (multichannels) or Single (one channel) mode. + This parameter can be set to ENABLE or DISABLE */ + + FunctionalState ADC_ContinuousConvMode; /* Specifies whether the conversion is performed in + Continuous or Single mode. + This parameter can be set to ENABLE or DISABLE. */ + + uint32_t ADC_ExternalTrigConv; /* Defines the external trigger used to start the analog + to digital conversion of regular channels. This parameter + can be a value of @ref ADC_external_trigger_sources_for_regular_channels_conversion */ + + uint32_t ADC_DataAlign; /* Specifies whether the ADC data alignment is left or right. + This parameter can be a value of @ref ADC_data_align */ + + uint8_t ADC_NbrOfChannel; /* Specifies the number of ADC channels that will be converted + using the sequencer for regular channel group. + This parameter must range from 1 to 16. */ + + uint32_t ADC_OutputBuffer; /* Specifies whether the ADC channel output buffer is enabled or disabled. + This parameter can be a value of @ref ADC_OutputBuffer */ + + uint32_t ADC_Pga; /* Specifies the PGA gain multiple. + This parameter can be a value of @ref ADC_Pga */ +} ADC_InitTypeDef; + +/* ADC_mode */ +#define ADC_Mode_Independent ((uint32_t)0x00000000) +#define ADC_Mode_RegInjecSimult ((uint32_t)0x00010000) +#define ADC_Mode_RegSimult_AlterTrig ((uint32_t)0x00020000) +#define ADC_Mode_InjecSimult_FastInterl ((uint32_t)0x00030000) +#define ADC_Mode_InjecSimult_SlowInterl ((uint32_t)0x00040000) +#define ADC_Mode_InjecSimult ((uint32_t)0x00050000) +#define ADC_Mode_RegSimult ((uint32_t)0x00060000) +#define ADC_Mode_FastInterl ((uint32_t)0x00070000) +#define ADC_Mode_SlowInterl ((uint32_t)0x00080000) +#define ADC_Mode_AlterTrig ((uint32_t)0x00090000) + +/* ADC_external_trigger_sources_for_regular_channels_conversion */ +#define ADC_ExternalTrigConv_T1_CC1 ((uint32_t)0x00000000) +#define ADC_ExternalTrigConv_T1_CC2 ((uint32_t)0x00020000) +#define ADC_ExternalTrigConv_T1_CC3 ((uint32_t)0x00040000) +#define ADC_ExternalTrigConv_T2_CC2 ((uint32_t)0x00060000) +#define ADC_ExternalTrigConv_T3_TRGO ((uint32_t)0x00080000) +#define ADC_ExternalTrigConv_T4_CC4 ((uint32_t)0x000A0000) +#define ADC_ExternalTrigConv_Ext_IT11 ((uint32_t)0x000C0000) +#define ADC_ExternalTrigConv_None ((uint32_t)0x000E0000) + +/* ADC_data_align */ +#define ADC_DataAlign_Right ((uint32_t)0x00000000) +#define ADC_DataAlign_Left ((uint32_t)0x00000800) + +/* ADC_channels */ +#define ADC_Channel_0 ((uint8_t)0x00) +#define ADC_Channel_1 ((uint8_t)0x01) +#define ADC_Channel_2 ((uint8_t)0x02) +#define ADC_Channel_3 ((uint8_t)0x03) +#define ADC_Channel_4 ((uint8_t)0x04) +#define ADC_Channel_5 ((uint8_t)0x05) +#define ADC_Channel_6 ((uint8_t)0x06) +#define ADC_Channel_7 ((uint8_t)0x07) +#define ADC_Channel_8 ((uint8_t)0x08) +#define ADC_Channel_9 ((uint8_t)0x09) +#define ADC_Channel_16 ((uint8_t)0x10) +#define ADC_Channel_17 ((uint8_t)0x11) +#define ADC_Channel_18 ((uint8_t)0x12) +#define ADC_Channel_TempSensor ((uint8_t)ADC_Channel_16) +#define ADC_Channel_Vrefint ((uint8_t)ADC_Channel_17) +#define ADC_Channel_CalInternal ((uint8_t)ADC_Channel_18) + +/*ADC_output_buffer*/ +#define ADC_OutputBuffer_Enable ((uint32_t)0x04000000) +#define ADC_OutputBuffer_Disable ((uint32_t)0x00000000) + +/*ADC_pga*/ +#define ADC_Pga_1 ((uint32_t)0x00000000) +#define ADC_Pga_4 ((uint32_t)0x08000000) +#define ADC_Pga_16 ((uint32_t)0x10000000) +#define ADC_Pga_64 ((uint32_t)0x18000000) + +/* ADC_sampling_time */ +#define ADC_SampleTime_CyclesMode0 ((uint8_t)0x00) +#define ADC_SampleTime_CyclesMode1 ((uint8_t)0x01) +#define ADC_SampleTime_CyclesMode2 ((uint8_t)0x02) +#define ADC_SampleTime_CyclesMode3 ((uint8_t)0x03) +#define ADC_SampleTime_CyclesMode4 ((uint8_t)0x04) +#define ADC_SampleTime_CyclesMode5 ((uint8_t)0x05) +#define ADC_SampleTime_CyclesMode6 ((uint8_t)0x06) +#define ADC_SampleTime_CyclesMode7 ((uint8_t)0x07) + +/* ADC_external_trigger_sources_for_injected_channels_conversion */ +#define ADC_ExternalTrigInjecConv_T1_TRGO ((uint32_t)0x00000000) +#define ADC_ExternalTrigInjecConv_T1_CC4 ((uint32_t)0x00001000) +#define ADC_ExternalTrigInjecConv_T2_TRGO ((uint32_t)0x00002000) +#define ADC_ExternalTrigInjecConv_T2_CC1 ((uint32_t)0x00003000) +#define ADC_ExternalTrigInjecConv_T3_CC4 ((uint32_t)0x00004000) +#define ADC_ExternalTrigInjecConv_T4_TRGO ((uint32_t)0x00005000) +#define ADC_ExternalTrigInjecConv_Ext_IT15 ((uint32_t)0x00006000) +#define ADC_ExternalTrigInjecConv_None ((uint32_t)0x00007000) + +/* ADC_injected_channel_selection */ +#define ADC_InjectedChannel_1 ((uint8_t)0x14) +#define ADC_InjectedChannel_2 ((uint8_t)0x18) +#define ADC_InjectedChannel_3 ((uint8_t)0x1C) +#define ADC_InjectedChannel_4 ((uint8_t)0x20) + +/* ADC_analog_watchdog_selection */ +#define ADC_AnalogWatchdog_SingleRegEnable ((uint32_t)0x00800200) +#define ADC_AnalogWatchdog_SingleInjecEnable ((uint32_t)0x00400200) +#define ADC_AnalogWatchdog_SingleRegOrInjecEnable ((uint32_t)0x00C00200) +#define ADC_AnalogWatchdog_AllRegEnable ((uint32_t)0x00800000) +#define ADC_AnalogWatchdog_AllInjecEnable ((uint32_t)0x00400000) +#define ADC_AnalogWatchdog_AllRegAllInjecEnable ((uint32_t)0x00C00000) +#define ADC_AnalogWatchdog_None ((uint32_t)0x00000000) + +/* ADC_interrupts_definition */ +#define ADC_IT_EOC ((uint16_t)0x0220) +#define ADC_IT_AWD ((uint16_t)0x0140) +#define ADC_IT_JEOC ((uint16_t)0x0480) + +/* ADC_flags_definition */ +#define ADC_FLAG_AWD ((uint8_t)0x01) +#define ADC_FLAG_EOC ((uint8_t)0x02) +#define ADC_FLAG_JEOC ((uint8_t)0x04) +#define ADC_FLAG_JSTRT ((uint8_t)0x08) +#define ADC_FLAG_STRT ((uint8_t)0x10) + +/* ADC_Sample_mode_definition */ +#define ADC_Sample_NoOver_1M_Mode ((uint32_t)0x00000000) +#define ADC_Sample_Over_1M_Mode ((uint32_t)0x00000020) + + +void ADC_DeInit(ADC_TypeDef *ADCx); +void ADC_Init(ADC_TypeDef *ADCx, ADC_InitTypeDef *ADC_InitStruct); +void ADC_StructInit(ADC_InitTypeDef *ADC_InitStruct); +void ADC_Cmd(ADC_TypeDef *ADCx, FunctionalState NewState); +void ADC_DMACmd(ADC_TypeDef *ADCx, FunctionalState NewState); +void ADC_ITConfig(ADC_TypeDef *ADCx, uint16_t ADC_IT, FunctionalState NewState); +void ADC_ResetCalibration(ADC_TypeDef *ADCx); +FlagStatus ADC_GetResetCalibrationStatus(ADC_TypeDef *ADCx); +void ADC_StartCalibration(ADC_TypeDef *ADCx); +FlagStatus ADC_GetCalibrationStatus(ADC_TypeDef *ADCx); +void ADC_SoftwareStartConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState); +FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef *ADCx); +void ADC_DiscModeChannelCountConfig(ADC_TypeDef *ADCx, uint8_t Number); +void ADC_DiscModeCmd(ADC_TypeDef *ADCx, FunctionalState NewState); +void ADC_RegularChannelConfig(ADC_TypeDef *ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime); +void ADC_ExternalTrigConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState); +uint16_t ADC_GetConversionValue(ADC_TypeDef *ADCx); +uint32_t ADC_GetDualModeConversionValue(void); +void ADC_AutoInjectedConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState); +void ADC_InjectedDiscModeCmd(ADC_TypeDef *ADCx, FunctionalState NewState); +void ADC_ExternalTrigInjectedConvConfig(ADC_TypeDef *ADCx, uint32_t ADC_ExternalTrigInjecConv); +void ADC_ExternalTrigInjectedConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState); +void ADC_SoftwareStartInjectedConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState); +FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_TypeDef *ADCx); +void ADC_InjectedChannelConfig(ADC_TypeDef *ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime); +void ADC_InjectedSequencerLengthConfig(ADC_TypeDef *ADCx, uint8_t Length); +void ADC_SetInjectedOffset(ADC_TypeDef *ADCx, uint8_t ADC_InjectedChannel, uint16_t Offset); +uint16_t ADC_GetInjectedConversionValue(ADC_TypeDef *ADCx, uint8_t ADC_InjectedChannel); +void ADC_AnalogWatchdogCmd(ADC_TypeDef *ADCx, uint32_t ADC_AnalogWatchdog); +void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef *ADCx, uint16_t HighThreshold, uint16_t LowThreshold); +void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef *ADCx, uint8_t ADC_Channel); +void ADC_TempSensorVrefintCmd(FunctionalState NewState); +FlagStatus ADC_GetFlagStatus(ADC_TypeDef *ADCx, uint8_t ADC_FLAG); +void ADC_ClearFlag(ADC_TypeDef *ADCx, uint8_t ADC_FLAG); +ITStatus ADC_GetITStatus(ADC_TypeDef *ADCx, uint16_t ADC_IT); +void ADC_ClearITPendingBit(ADC_TypeDef *ADCx, uint16_t ADC_IT); +s32 TempSensor_Volt_To_Temper(s32 Value); +void ADC_BufferCmd(ADC_TypeDef *ADCx, FunctionalState NewState); +void ADC_TKey_ChannelxMulShieldCmd(ADC_TypeDef *ADCx, uint8_t ADC_Channel, FunctionalState NewState); +void ADC_TKey_MulShieldCmd(ADC_TypeDef *ADCx, FunctionalState NewState); +void ADC_DutyDelayCmd(ADC_TypeDef *ADCx, FunctionalState NewState); +void ADC_FIFO_Cmd(ADC_TypeDef *ADCx, FunctionalState NewState); +void ADC_Sample_ModeConfig(ADC_TypeDef *ADCx, uint32_t ADC_Sample_Mode); +void ADC_OffsetCalibrationConfig(ADC_TypeDef *ADCx); +void ADC_AnalogWatchdogResetCmd(ADC_TypeDef *ADCx, FunctionalState NewState); +int16_t Get_CalibrationValue(ADC_TypeDef *ADCx); +#ifdef __cplusplus +} +#endif + +#endif diff --git a/ZDBMS/BMS_CC/Peripheral/inc/ch32l103_bkp.h b/ZDBMS/BMS_CC/Peripheral/inc/ch32l103_bkp.h new file mode 100644 index 0000000..ccc57d4 --- /dev/null +++ b/ZDBMS/BMS_CC/Peripheral/inc/ch32l103_bkp.h @@ -0,0 +1,65 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32l103_bkp.h + * Author : WCH + * Version : V1.0.0 + * Date : 2023/07/08 + * Description : This file contains all the functions prototypes for the + * BKP firmware library. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#ifndef __CH32L103_BKP_H +#define __CH32L103_BKP_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "ch32l103.h" + +/* Tamper_Pin_active_level */ +#define BKP_TamperPinLevel_High ((uint16_t)0x0000) +#define BKP_TamperPinLevel_Low ((uint16_t)0x0001) + +/* RTC_output_source_to_output_on_the_Tamper_pin */ +#define BKP_RTCOutputSource_None ((uint16_t)0x0000) +#define BKP_RTCOutputSource_CalibClock ((uint16_t)0x0080) +#define BKP_RTCOutputSource_Alarm ((uint16_t)0x0100) +#define BKP_RTCOutputSource_Second ((uint16_t)0x0300) + +/* Data_Backup_Register */ +#define BKP_DR1 ((uint16_t)0x0004) +#define BKP_DR2 ((uint16_t)0x0008) +#define BKP_DR3 ((uint16_t)0x000C) +#define BKP_DR4 ((uint16_t)0x0010) +#define BKP_DR5 ((uint16_t)0x0014) +#define BKP_DR6 ((uint16_t)0x0018) +#define BKP_DR7 ((uint16_t)0x001C) +#define BKP_DR8 ((uint16_t)0x0020) +#define BKP_DR9 ((uint16_t)0x0024) +#define BKP_DR10 ((uint16_t)0x0028) +#define BKP_DR11 ((uint16_t)0x0040) +#define BKP_DR12 ((uint16_t)0x0044) +#define BKP_DR13 ((uint16_t)0x0048) + + +void BKP_DeInit(void); +void BKP_TamperPinLevelConfig(uint16_t BKP_TamperPinLevel); +void BKP_TamperPinCmd(FunctionalState NewState); +void BKP_ITConfig(FunctionalState NewState); +void BKP_RTCOutputConfig(uint16_t BKP_RTCOutputSource); +void BKP_SetRTCCalibrationValue(uint8_t CalibrationValue); +void BKP_WriteBackupRegister(uint16_t BKP_DR, uint16_t Data); +uint16_t BKP_ReadBackupRegister(uint16_t BKP_DR); +FlagStatus BKP_GetFlagStatus(void); +void BKP_ClearFlag(void); +ITStatus BKP_GetITStatus(void); +void BKP_ClearITPendingBit(void); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/ZDBMS/BMS_CC/Peripheral/inc/ch32l103_can.h b/ZDBMS/BMS_CC/Peripheral/inc/ch32l103_can.h new file mode 100644 index 0000000..0c0e313 --- /dev/null +++ b/ZDBMS/BMS_CC/Peripheral/inc/ch32l103_can.h @@ -0,0 +1,630 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32l103_can.h + * Author : WCH + * Version : V1.0.0 + * Date : 2023/07/08 + * Description : This file contains all the functions prototypes for the + * CAN firmware library. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#ifndef __CH32L103_CAN_H +#define __CH32L103_CAN_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "ch32l103.h" + +/* CAN init structure definition */ +typedef struct +{ + uint16_t CAN_Prescaler; /* Specifies the length of a time quantum. + It ranges from 1 to 1024. */ + + uint8_t CAN_Mode; /* Specifies the CAN operating mode. + This parameter can be a value of + @ref CAN_operating_mode */ + + uint8_t CAN_SJW; /* Specifies the maximum number of time quanta + the CAN hardware is allowed to lengthen or + shorten a bit to perform resynchronization. + This parameter can be a value of + @ref CAN_synchronisation_jump_width */ + + uint8_t CAN_BS1; /* Specifies the number of time quanta in Bit + Segment 1. This parameter can be a value of + @ref CAN_time_quantum_in_bit_segment_1 */ + + uint8_t CAN_BS2; /* Specifies the number of time quanta in Bit + Segment 2. + This parameter can be a value of + @ref CAN_time_quantum_in_bit_segment_2 */ + + FunctionalState CAN_TTCM; /* Enable or disable the time triggered + communication mode. This parameter can be set + either to ENABLE or DISABLE. */ + + FunctionalState CAN_ABOM; /* Enable or disable the automatic bus-off + management. This parameter can be set either + to ENABLE or DISABLE. */ + + FunctionalState CAN_AWUM; /* Enable or disable the automatic wake-up mode. + This parameter can be set either to ENABLE or + DISABLE. */ + + FunctionalState CAN_NART; /* Enable or disable the no-automatic + retransmission mode. This parameter can be + set either to ENABLE or DISABLE. */ + + FunctionalState CAN_RFLM; /* Enable or disable the Receive FIFO Locked mode. + This parameter can be set either to ENABLE + or DISABLE. */ + + FunctionalState CAN_TXFP; /* Enable or disable the transmit FIFO priority. + This parameter can be set either to ENABLE + or DISABLE. */ +} CAN_InitTypeDef; + +/* CAN filter init structure definition */ +typedef struct +{ + uint16_t CAN_FilterIdHigh; /* Specifies the filter identification number (MSBs for a 32-bit + configuration, first one for a 16-bit configuration). + This parameter can be a value between 0x0000 and 0xFFFF */ + + uint16_t CAN_FilterIdLow; /* Specifies the filter identification number (LSBs for a 32-bit + configuration, second one for a 16-bit configuration). + This parameter can be a value between 0x0000 and 0xFFFF */ + + uint16_t CAN_FilterMaskIdHigh; /* Specifies the filter mask number or identification number, + according to the mode (MSBs for a 32-bit configuration, + first one for a 16-bit configuration). + This parameter can be a value between 0x0000 and 0xFFFF */ + + uint16_t CAN_FilterMaskIdLow; /* Specifies the filter mask number or identification number, + according to the mode (LSBs for a 32-bit configuration, + second one for a 16-bit configuration). + This parameter can be a value between 0x0000 and 0xFFFF */ + + uint16_t CAN_FilterFIFOAssignment; /* Specifies the FIFO (0 or 1) which will be assigned to the filter. + This parameter can be a value of @ref CAN_filter_FIFO */ + + uint8_t CAN_FilterNumber; /* Specifies the filter which will be initialized. It ranges from 0 to 13. */ + + uint8_t CAN_FilterMode; /* Specifies the filter mode to be initialized. + This parameter can be a value of @ref CAN_filter_mode */ + + uint8_t CAN_FilterScale; /* Specifies the filter scale. + This parameter can be a value of @ref CAN_filter_scale */ + + FunctionalState CAN_FilterActivation; /* Enable or disable the filter. + This parameter can be set either to ENABLE or DISABLE. */ +} CAN_FilterInitTypeDef; + +/* CAN Tx message structure definition */ +typedef struct +{ + uint32_t StdId; /* Specifies the standard identifier. + This parameter can be a value between 0 to 0x7FF. */ + + uint32_t ExtId; /* Specifies the extended identifier. + This parameter can be a value between 0 to 0x1FFFFFFF. */ + + uint8_t IDE; /* Specifies the type of identifier for the message that + will be transmitted. This parameter can be a value + of @ref CAN_identifier_type */ + + uint8_t RTR; /* Specifies the type of frame for the message that will + be transmitted. This parameter can be a value of + @ref CAN_remote_transmission_request */ + + uint8_t DLC; /* Specifies the length of the frame that will be + transmitted. This parameter can be a value between + 0 to 8 */ + + uint8_t Data[8]; /* Contains the data to be transmitted. It ranges from 0 + to 0xFF. */ +} CanTxMsg; + +/* CAN Rx message structure definition */ +typedef struct +{ + uint32_t StdId; /* Specifies the standard identifier. + This parameter can be a value between 0 to 0x7FF. */ + + uint32_t ExtId; /* Specifies the extended identifier. + This parameter can be a value between 0 to 0x1FFFFFFF. */ + + uint8_t IDE; /* Specifies the type of identifier for the message that + will be received. This parameter can be a value of + @ref CAN_identifier_type */ + + uint8_t RTR; /* Specifies the type of frame for the received message. + This parameter can be a value of + @ref CAN_remote_transmission_request */ + + uint8_t DLC; /* Specifies the length of the frame that will be received. + This parameter can be a value between 0 to 8 */ + + uint8_t Data[8]; /* Contains the data to be received. It ranges from 0 to + 0xFF. */ + + uint8_t FMI; /* Specifies the index of the filter the message stored in + the mailbox passes through. This parameter can be a + value between 0 to 0xFF */ +} CanRxMsg; + +/* CANFD init structure definition */ +typedef struct +{ + uint16_t CANFD_Prescaler; /* Specifies the length of a time quantum. + It ranges from 1 to 32. */ + + uint8_t CANFD_Mode; /* Specifies the CAN operating mode. + This parameter can be a value of + @ref CAN_operating_mode */ + + uint8_t CANFD_SJW; /* Specifies the maximum number of time quanta + the CAN hardware is allowed to lengthen or + shorten a bit to perform resynchronization. + This parameter can be a value of + @ref CANFD_synchronisation_jump_width */ + + uint8_t CANFD_BS1; /* Specifies the number of time quanta in Bit + Segment 1. This parameter can be a value of + @ref CANFD_time_quantum_in_bit_segment_1 */ + + uint8_t CANFD_BS2; /* Specifies the number of time quanta in Bit + Segment 2. + This parameter can be a value of + @ref CANFD_time_quantum_in_bit_segment_2 */ + + uint8_t CANFD_TDC_FILTER; /* Specifies the number of time quanta in Bit Segment + Minimum delay of internal delay counter. + It ranges from 0 to 63. */ + + uint8_t CANFD_TDC0; /* Specifies the number of time quanta in Bit Segment + transmission delay compensation offset. + It ranges from 0 to 63. */ + + FunctionalState CANFD_TDCE; /* Enable or disable transmission delay compensation offset. + This parameter can be set either to ENABLE or DISABLE. */ + + FunctionalState CANFD_TTCM; /* Enable or disable the time triggered + communication mode. This parameter can be set + either to ENABLE or DISABLE. */ + + FunctionalState CANFD_ABOM; /* Enable or disable the automatic bus-off + management. This parameter can be set either + to ENABLE or DISABLE. */ + + FunctionalState CANFD_AWUM; /* Enable or disable the automatic wake-up mode. + This parameter can be set either to ENABLE or + DISABLE. */ + + FunctionalState CANFD_NART; /* Enable or disable the no-automatic + retransmission mode. This parameter can be + set either to ENABLE or DISABLE. */ + + FunctionalState CANFD_TXFP; /* Enable or disable the transmit FIFO priority. + This parameter can be set either to ENABLE + or DISABLE. */ + + FunctionalState CANFD_RES_Error; /* Enable or disable the RES bit can generate error . + This parameter can be set either to ENABLE + or DISABLE. */ + + FunctionalState CANFD_ESI_Auto_TXM0; /* Enable or disable the ESI bit auto mode for Tx mailbox 0. + This parameter can be set either to ENABLE + or DISABLE. */ + + FunctionalState CANFD_ESI_Auto_TXM1; /* Enable or disable the ESI bit auto mode for Tx mailbox 1. + This parameter can be set either to ENABLE + or DISABLE. */ + + FunctionalState CANFD_ESI_Auto_TXM2; /* Enable or disable the ESI bit auto mode for Tx mailbox 2. + This parameter can be set either to ENABLE + or DISABLE. */ + + FunctionalState CANFD_BRS_TXM0; /* Enable or disable the BRS bit speed switch for Tx mailbox 0. + This parameter can be set either to ENABLE + or DISABLE. */ + + FunctionalState CANFD_BRS_TXM1; /* Enable or disable the BRS bit speed switch for Tx mailbox 1. + This parameter can be set either to ENABLE + or DISABLE. */ + + FunctionalState CANFD_BRS_TXM2; /* Enable or disable the BRS bit speed switch for Tx mailbox 2. + This parameter can be set either to ENABLE + or DISABLE. */ +} CANFD_InitTypeDef; + +/* CANFD Tx message structure definition */ +typedef struct +{ + uint32_t StdId; /* Specifies the standard identifier. + This parameter can be a value between 0 to 0x7FF. */ + + uint32_t ExtId; /* Specifies the extended identifier. + This parameter can be a value between 0 to 0x1FFFFFFF. */ + + uint8_t Data[64]; /* Contains the data to be transmitted. It ranges from 0 + to 0xFF. */ + + uint8_t IDE; /* Specifies the type of identifier for the message that + will be transmitted. This parameter can be a value + of @ref CAN_identifier_type */ + + uint8_t RTR; /* Specifies the type of frame for the message that will + be transmitted. This parameter can be a value of + @ref CAN_remote_transmission_request */ + + uint8_t DLC; /* Specifies the length of the frame that will be + transmitted. + This parameter can be a value of + @ref CANFD_data_length_code */ +} CanFDTxMsg; + +/* CANFD Rx message structure definition */ +typedef struct +{ + uint32_t StdId; /* Specifies the standard identifier. + This parameter can be a value between 0 to 0x7FF. */ + + uint32_t ExtId; /* Specifies the extended identifier. + This parameter can be a value between 0 to 0x1FFFFFFF. */ + + uint8_t Data[64]; /* Contains the data to be received. It ranges from 0 to + 0xFF. */ + + uint8_t IDE; /* Specifies the type of identifier for the message that + will be received. This parameter can be a value of + @ref CAN_identifier_type */ + + uint8_t RTR; /* Specifies the type of frame for the received message. + This parameter can be a value of + @ref CAN_remote_transmission_request */ + + uint8_t DLC; /* Specifies the length of the frame that will be received. + This parameter can be a value of + 0, 1, 2, 3, 4, 5, 6, 7, 8, 12, 16, 20, 24, 32, 48, 64 */ + + uint8_t BRS; /* Specifies the length of the frame that will be received. + This parameter can be a value of + @ref CANFD_data_length_code */ + + uint8_t ESI; /* Specifies the length of the frame that will be received. + This parameter can be a value of + @ref CANFD_data_length_code */ + + uint8_t RES; /* Specifies the length of the frame that will be received. + This parameter can be a value of + @ref CANFD_data_length_code */ + + uint8_t FMI; /* Specifies the index of the filter the message stored in + the mailbox passes through. This parameter can be a + value between 0 to 0xFF */ +} CanFDRxMsg; + +/* CAN_sleep_constants */ +#define CAN_InitStatus_Failed ((uint8_t)0x00) /* CAN initialization failed */ +#define CAN_InitStatus_Success ((uint8_t)0x01) /* CAN initialization OK */ + +/* CAN_Mode */ +#define CAN_Mode_Normal ((uint8_t)0x00) /* normal mode */ +#define CAN_Mode_LoopBack ((uint8_t)0x01) /* loopback mode */ +#define CAN_Mode_Silent ((uint8_t)0x02) /* silent mode */ +#define CAN_Mode_Silent_LoopBack ((uint8_t)0x03) /* loopback combined with silent mode */ + +/* CAN_Operating_Mode */ +#define CAN_OperatingMode_Initialization ((uint8_t)0x00) /* Initialization mode */ +#define CAN_OperatingMode_Normal ((uint8_t)0x01) /* Normal mode */ +#define CAN_OperatingMode_Sleep ((uint8_t)0x02) /* sleep mode */ + +/* CAN_Mode_Status */ +#define CAN_ModeStatus_Failed ((uint8_t)0x00) /* CAN entering the specific mode failed */ +#define CAN_ModeStatus_Success ((uint8_t)!CAN_ModeStatus_Failed) /* CAN entering the specific mode Succeed */ + +/* CAN_synchronisation_jump_width */ +#define CAN_SJW_1tq ((uint8_t)0x00) /* 1 time quantum */ +#define CAN_SJW_2tq ((uint8_t)0x01) /* 2 time quantum */ +#define CAN_SJW_3tq ((uint8_t)0x02) /* 3 time quantum */ +#define CAN_SJW_4tq ((uint8_t)0x03) /* 4 time quantum */ + +/* CAN_time_quantum_in_bit_segment_1 */ +#define CAN_BS1_1tq ((uint8_t)0x00) /* 1 time quantum */ +#define CAN_BS1_2tq ((uint8_t)0x01) /* 2 time quantum */ +#define CAN_BS1_3tq ((uint8_t)0x02) /* 3 time quantum */ +#define CAN_BS1_4tq ((uint8_t)0x03) /* 4 time quantum */ +#define CAN_BS1_5tq ((uint8_t)0x04) /* 5 time quantum */ +#define CAN_BS1_6tq ((uint8_t)0x05) /* 6 time quantum */ +#define CAN_BS1_7tq ((uint8_t)0x06) /* 7 time quantum */ +#define CAN_BS1_8tq ((uint8_t)0x07) /* 8 time quantum */ +#define CAN_BS1_9tq ((uint8_t)0x08) /* 9 time quantum */ +#define CAN_BS1_10tq ((uint8_t)0x09) /* 10 time quantum */ +#define CAN_BS1_11tq ((uint8_t)0x0A) /* 11 time quantum */ +#define CAN_BS1_12tq ((uint8_t)0x0B) /* 12 time quantum */ +#define CAN_BS1_13tq ((uint8_t)0x0C) /* 13 time quantum */ +#define CAN_BS1_14tq ((uint8_t)0x0D) /* 14 time quantum */ +#define CAN_BS1_15tq ((uint8_t)0x0E) /* 15 time quantum */ +#define CAN_BS1_16tq ((uint8_t)0x0F) /* 16 time quantum */ + +/* CAN_time_quantum_in_bit_segment_2 */ +#define CAN_BS2_1tq ((uint8_t)0x00) /* 1 time quantum */ +#define CAN_BS2_2tq ((uint8_t)0x01) /* 2 time quantum */ +#define CAN_BS2_3tq ((uint8_t)0x02) /* 3 time quantum */ +#define CAN_BS2_4tq ((uint8_t)0x03) /* 4 time quantum */ +#define CAN_BS2_5tq ((uint8_t)0x04) /* 5 time quantum */ +#define CAN_BS2_6tq ((uint8_t)0x05) /* 6 time quantum */ +#define CAN_BS2_7tq ((uint8_t)0x06) /* 7 time quantum */ +#define CAN_BS2_8tq ((uint8_t)0x07) /* 8 time quantum */ + +/* CAN_filter_mode */ +#define CAN_FilterMode_IdMask ((uint8_t)0x00) /* identifier/mask mode */ +#define CAN_FilterMode_IdList ((uint8_t)0x01) /* identifier list mode */ + +/* CAN_filter_scale */ +#define CAN_FilterScale_16bit ((uint8_t)0x00) /* Two 16-bit filters */ +#define CAN_FilterScale_32bit ((uint8_t)0x01) /* One 32-bit filter */ + +/* CAN_filter_FIFO */ +#define CAN_Filter_FIFO0 ((uint8_t)0x00) /* Filter FIFO 0 assignment for filter x */ +#define CAN_Filter_FIFO1 ((uint8_t)0x01) /* Filter FIFO 1 assignment for filter x */ + +/* CAN_identifier_type */ +#define CAN_Id_Standard ((uint32_t)0x00000000) /* Standard Id */ +#define CAN_Id_Extended ((uint32_t)0x00000004) /* Extended Id */ + +/* CAN_remote_transmission_request */ +#define CAN_RTR_Data ((uint32_t)0x00000000) /* Data frame */ +#define CAN_RTR_Remote ((uint32_t)0x00000002) /* Remote frame */ + +/* CAN_transmit_constants */ +#define CAN_TxStatus_Failed ((uint8_t)0x00) /* CAN transmission failed */ +#define CAN_TxStatus_Ok ((uint8_t)0x01) /* CAN transmission succeeded */ +#define CAN_TxStatus_Pending ((uint8_t)0x02) /* CAN transmission pending */ +#define CAN_TxStatus_NoMailBox ((uint8_t)0x04) /* CAN cell did not provide an empty mailbox */ + +/* CAN_receive_FIFO_number_constants */ +#define CAN_FIFO0 ((uint8_t)0x00) /* CAN FIFO 0 used to receive */ +#define CAN_FIFO1 ((uint8_t)0x01) /* CAN FIFO 1 used to receive */ + +/* CAN_sleep_constants */ +#define CAN_Sleep_Failed ((uint8_t)0x00) /* CAN did not enter the sleep mode */ +#define CAN_Sleep_Ok ((uint8_t)0x01) /* CAN entered the sleep mode */ + +/* CAN_wake_up_constants */ +#define CAN_WakeUp_Failed ((uint8_t)0x00) /* CAN did not leave the sleep mode */ +#define CAN_WakeUp_Ok ((uint8_t)0x01) /* CAN leaved the sleep mode */ + +/* CAN_Error_Code_constants */ +#define CAN_ErrorCode_NoErr ((uint8_t)0x00) /* No Error */ +#define CAN_ErrorCode_StuffErr ((uint8_t)0x10) /* Stuff Error */ +#define CAN_ErrorCode_FormErr ((uint8_t)0x20) /* Form Error */ +#define CAN_ErrorCode_ACKErr ((uint8_t)0x30) /* Acknowledgment Error */ +#define CAN_ErrorCode_BitRecessiveErr ((uint8_t)0x40) /* Bit Recessive Error */ +#define CAN_ErrorCode_BitDominantErr ((uint8_t)0x50) /* Bit Dominant Error */ +#define CAN_ErrorCode_CRCErr ((uint8_t)0x60) /* CRC Error */ +#define CAN_ErrorCode_SoftwareSetErr ((uint8_t)0x70) /* Software Set Error */ + +/* CAN_flags */ +/* Transmit Flags */ +/* If the flag is 0x3XXXXXXX, it means that it can be used with CAN_GetFlagStatus() + * and CAN_ClearFlag() functions. + * If the flag is 0x1XXXXXXX, it means that it can only be used with CAN_GetFlagStatus() function. +*/ +#define CAN_FLAG_RQCP0 ((uint32_t)0x38000001) /* Request MailBox0 Flag */ +#define CAN_FLAG_RQCP1 ((uint32_t)0x38000100) /* Request MailBox1 Flag */ +#define CAN_FLAG_RQCP2 ((uint32_t)0x38010000) /* Request MailBox2 Flag */ + +/* Receive Flags */ +#define CAN_FLAG_FMP0 ((uint32_t)0x12000003) /* FIFO 0 Message Pending Flag */ +#define CAN_FLAG_FF0 ((uint32_t)0x32000008) /* FIFO 0 Full Flag */ +#define CAN_FLAG_FOV0 ((uint32_t)0x32000010) /* FIFO 0 Overrun Flag */ +#define CAN_FLAG_FMP1 ((uint32_t)0x14000003) /* FIFO 1 Message Pending Flag */ +#define CAN_FLAG_FF1 ((uint32_t)0x34000008) /* FIFO 1 Full Flag */ +#define CAN_FLAG_FOV1 ((uint32_t)0x34000010) /* FIFO 1 Overrun Flag */ + +/* Operating Mode Flags */ +#define CAN_FLAG_WKU ((uint32_t)0x31000008) /* Wake up Flag */ +#define CAN_FLAG_SLAK ((uint32_t)0x31000012) /* Sleep acknowledge Flag */ +/* Note: + *When SLAK intterupt is disabled (SLKIE=0), no polling on SLAKI is possible. + *In this case the SLAK bit can be polled. +*/ + + +/* Error Flags */ +#define CAN_FLAG_EWG ((uint32_t)0x10F00001) /* Error Warning Flag */ +#define CAN_FLAG_EPV ((uint32_t)0x10F00002) /* Error Passive Flag */ +#define CAN_FLAG_BOF ((uint32_t)0x10F00004) /* Bus-Off Flag */ +#define CAN_FLAG_LEC ((uint32_t)0x30F00070) /* Last error code Flag */ + +/* CAN_interrupts */ +#define CAN_IT_TME ((uint32_t)0x00000001) /* Transmit mailbox empty Interrupt*/ + +/* Receive Interrupts */ +#define CAN_IT_FMP0 ((uint32_t)0x00000002) /* FIFO 0 message pending Interrupt*/ +#define CAN_IT_FF0 ((uint32_t)0x00000004) /* FIFO 0 full Interrupt*/ +#define CAN_IT_FOV0 ((uint32_t)0x00000008) /* FIFO 0 overrun Interrupt*/ +#define CAN_IT_FMP1 ((uint32_t)0x00000010) /* FIFO 1 message pending Interrupt*/ +#define CAN_IT_FF1 ((uint32_t)0x00000020) /* FIFO 1 full Interrupt*/ +#define CAN_IT_FOV1 ((uint32_t)0x00000040) /* FIFO 1 overrun Interrupt*/ + +/* Operating Mode Interrupts */ +#define CAN_IT_WKU ((uint32_t)0x00010000) /* Wake-up Interrupt*/ +#define CAN_IT_SLK ((uint32_t)0x00020000) /* Sleep acknowledge Interrupt*/ + +/* Error Interrupts */ +#define CAN_IT_EWG ((uint32_t)0x00000100) /* Error warning Interrupt*/ +#define CAN_IT_EPV ((uint32_t)0x00000200) /* Error passive Interrupt*/ +#define CAN_IT_BOF ((uint32_t)0x00000400) /* Bus-off Interrupt*/ +#define CAN_IT_LEC ((uint32_t)0x00000800) /* Last error code Interrupt*/ +#define CAN_IT_ERR ((uint32_t)0x00008000) /* Error Interrupt*/ + +/* Flags named as Interrupts : kept only for FW compatibility */ +#define CAN_IT_RQCP0 CAN_IT_TME +#define CAN_IT_RQCP1 CAN_IT_TME +#define CAN_IT_RQCP2 CAN_IT_TME + +/* CAN_Legacy */ +#define CANINITFAILED CAN_InitStatus_Failed +#define CANINITOK CAN_InitStatus_Success +#define CAN_FilterFIFO0 CAN_Filter_FIFO0 +#define CAN_FilterFIFO1 CAN_Filter_FIFO1 +#define CAN_ID_STD CAN_Id_Standard +#define CAN_ID_EXT CAN_Id_Extended +#define CAN_RTR_DATA CAN_RTR_Data +#define CAN_RTR_REMOTE CAN_RTR_Remote +#define CANTXFAILE CAN_TxStatus_Failed +#define CANTXOK CAN_TxStatus_Ok +#define CANTXPENDING CAN_TxStatus_Pending +#define CAN_NO_MB CAN_TxStatus_NoMailBox +#define CANSLEEPFAILED CAN_Sleep_Failed +#define CANSLEEPOK CAN_Sleep_Ok +#define CANWAKEUPFAILED CAN_WakeUp_Failed +#define CANWAKEUPOK CAN_WakeUp_Ok + +/* CAN_BS1_Mode */ +#define CAN_BS1_4bit ((uint32_t)0x00000000) +#define CAN_BS1_6bit ((uint32_t)0x00000100) + +/* CANFD_data_length_code */ +#define CANFD_DLC_BYTES_0 ((uint32_t)0x0000) /* 0 bytes data field */ +#define CANFD_DLC_BYTES_1 ((uint32_t)0x0001) /* 1 bytes data field */ +#define CANFD_DLC_BYTES_2 ((uint32_t)0x0002) /* 2 bytes data field */ +#define CANFD_DLC_BYTES_3 ((uint32_t)0x0003) /* 3 bytes data field */ +#define CANFD_DLC_BYTES_4 ((uint32_t)0x0004) /* 4 bytes data field */ +#define CANFD_DLC_BYTES_5 ((uint32_t)0x0005) /* 5 bytes data field */ +#define CANFD_DLC_BYTES_6 ((uint32_t)0x0006) /* 6 bytes data field */ +#define CANFD_DLC_BYTES_7 ((uint32_t)0x0007) /* 7 bytes data field */ +#define CANFD_DLC_BYTES_8 ((uint32_t)0x0008) /* 8 bytes data field */ +#define CANFD_DLC_BYTES_12 ((uint32_t)0x0009) /* 12 bytes data field */ +#define CANFD_DLC_BYTES_16 ((uint32_t)0x000A) /* 16 bytes data field */ +#define CANFD_DLC_BYTES_20 ((uint32_t)0x000B) /* 20 bytes data field */ +#define CANFD_DLC_BYTES_24 ((uint32_t)0x000C) /* 24 bytes data field */ +#define CANFD_DLC_BYTES_32 ((uint32_t)0x000D) /* 32 bytes data field */ +#define CANFD_DLC_BYTES_48 ((uint32_t)0x000E) /* 48 bytes data field */ +#define CANFD_DLC_BYTES_64 ((uint32_t)0x000F) /* 64 bytes data field */ + +/* CANFD_synchronisation_jump_width */ +#define CANFD_SJW_1tq ((uint8_t)0x00) /* 1 time quantum */ +#define CANFD_SJW_2tq ((uint8_t)0x01) /* 2 time quantum */ +#define CANFD_SJW_3tq ((uint8_t)0x02) /* 3 time quantum */ +#define CANFD_SJW_4tq ((uint8_t)0x03) /* 4 time quantum */ +#define CANFD_SJW_5tq ((uint8_t)0x04) /* 5 time quantum */ +#define CANFD_SJW_6tq ((uint8_t)0x05) /* 6 time quantum */ +#define CANFD_SJW_7tq ((uint8_t)0x06) /* 7 time quantum */ +#define CANFD_SJW_8tq ((uint8_t)0x07) /* 8 time quantum */ +#define CANFD_SJW_9tq ((uint8_t)0x08) /* 9 time quantum */ +#define CANFD_SJW_10tq ((uint8_t)0x09) /* 10 time quantum */ +#define CANFD_SJW_11tq ((uint8_t)0x0A) /* 11 time quantum */ +#define CANFD_SJW_12tq ((uint8_t)0x0B) /* 12 time quantum */ +#define CANFD_SJW_13tq ((uint8_t)0x0C) /* 13 time quantum */ +#define CANFD_SJW_14tq ((uint8_t)0x0D) /* 14 time quantum */ +#define CANFD_SJW_15tq ((uint8_t)0x0E) /* 15 time quantum */ +#define CANFD_SJW_16tq ((uint8_t)0x0F) /* 16 time quantum */ + +/* CANFD_time_quantum_in_bit_segment_1 */ +#define CANFD_BS1_1tq ((uint8_t)0x00) /* 1 time quantum */ +#define CANFD_BS1_2tq ((uint8_t)0x01) /* 2 time quantum */ +#define CANFD_BS1_3tq ((uint8_t)0x02) /* 3 time quantum */ +#define CANFD_BS1_4tq ((uint8_t)0x03) /* 4 time quantum */ +#define CANFD_BS1_5tq ((uint8_t)0x04) /* 5 time quantum */ +#define CANFD_BS1_6tq ((uint8_t)0x05) /* 6 time quantum */ +#define CANFD_BS1_7tq ((uint8_t)0x06) /* 7 time quantum */ +#define CANFD_BS1_8tq ((uint8_t)0x07) /* 8 time quantum */ +#define CANFD_BS1_9tq ((uint8_t)0x08) /* 9 time quantum */ +#define CANFD_BS1_10tq ((uint8_t)0x09) /* 10 time quantum */ +#define CANFD_BS1_11tq ((uint8_t)0x0A) /* 11 time quantum */ +#define CANFD_BS1_12tq ((uint8_t)0x0B) /* 12 time quantum */ +#define CANFD_BS1_13tq ((uint8_t)0x0C) /* 13 time quantum */ +#define CANFD_BS1_14tq ((uint8_t)0x0D) /* 14 time quantum */ +#define CANFD_BS1_15tq ((uint8_t)0x0E) /* 15 time quantum */ +#define CANFD_BS1_16tq ((uint8_t)0x0F) /* 16 time quantum */ +#define CANFD_BS1_17tq ((uint8_t)0x10) /* 17 time quantum */ +#define CANFD_BS1_18tq ((uint8_t)0x11) /* 18 time quantum */ +#define CANFD_BS1_19tq ((uint8_t)0x12) /* 19 time quantum */ +#define CANFD_BS1_20tq ((uint8_t)0x13) /* 20 time quantum */ +#define CANFD_BS1_21tq ((uint8_t)0x14) /* 21 time quantum */ +#define CANFD_BS1_22tq ((uint8_t)0x15) /* 22 time quantum */ +#define CANFD_BS1_23tq ((uint8_t)0x16) /* 23 time quantum */ +#define CANFD_BS1_24tq ((uint8_t)0x17) /* 24 time quantum */ +#define CANFD_BS1_25tq ((uint8_t)0x18) /* 25 time quantum */ +#define CANFD_BS1_26tq ((uint8_t)0x19) /* 26 time quantum */ +#define CANFD_BS1_27tq ((uint8_t)0x1A) /* 27 time quantum */ +#define CANFD_BS1_28tq ((uint8_t)0x1B) /* 28 time quantum */ +#define CANFD_BS1_29tq ((uint8_t)0x1C) /* 29 time quantum */ +#define CANFD_BS1_30tq ((uint8_t)0x1D) /* 30 time quantum */ +#define CANFD_BS1_31tq ((uint8_t)0x1E) /* 31 time quantum */ +#define CANFD_BS1_32tq ((uint8_t)0x1F) /* 32 time quantum */ + +/* CANFD_time_quantum_in_bit_segment_2 */ +#define CANFD_BS2_1tq ((uint8_t)0x00) /* 1 time quantum */ +#define CANFD_BS2_2tq ((uint8_t)0x01) /* 2 time quantum */ +#define CANFD_BS2_3tq ((uint8_t)0x02) /* 3 time quantum */ +#define CANFD_BS2_4tq ((uint8_t)0x03) /* 4 time quantum */ +#define CANFD_BS2_5tq ((uint8_t)0x04) /* 5 time quantum */ +#define CANFD_BS2_6tq ((uint8_t)0x05) /* 6 time quantum */ +#define CANFD_BS2_7tq ((uint8_t)0x06) /* 7 time quantum */ +#define CANFD_BS2_8tq ((uint8_t)0x07) /* 8 time quantum */ +#define CANFD_BS2_9tq ((uint8_t)0x08) /* 9 time quantum */ +#define CANFD_BS2_10tq ((uint8_t)0x09) /* 10 time quantum */ +#define CANFD_BS2_11tq ((uint8_t)0x0A) /* 11 time quantum */ +#define CANFD_BS2_12tq ((uint8_t)0x0B) /* 12 time quantum */ +#define CANFD_BS2_13tq ((uint8_t)0x0C) /* 13 time quantum */ +#define CANFD_BS2_14tq ((uint8_t)0x0D) /* 14 time quantum */ +#define CANFD_BS2_15tq ((uint8_t)0x0E) /* 15 time quantum */ +#define CANFD_BS2_16tq ((uint8_t)0x0F) /* 16 time quantum */ + +/* CAN_Transmit_Mailbox_number_constants */ +#define CAN_Transmit_Mailbox0 ((uint8_t)0x00) +#define CAN_Transmit_Mailbox1 ((uint8_t)0x01) +#define CAN_Transmit_Mailbox2 ((uint8_t)0x02) + + +void CAN_DeInit(CAN_TypeDef *CANx); +uint8_t CAN_Init(CAN_TypeDef *CANx, CAN_InitTypeDef *CAN_InitStruct); +void CAN_FilterInit(CAN_FilterInitTypeDef *CAN_FilterInitStruct); +void CAN_StructInit(CAN_InitTypeDef *CAN_InitStruct); +void CAN_SlaveStartBank(uint8_t CAN_BankNumber); +void CAN_DBGFreeze(CAN_TypeDef *CANx, FunctionalState NewState); +void CAN_TTComModeCmd(CAN_TypeDef *CANx, FunctionalState NewState); +uint8_t CAN_Transmit(CAN_TypeDef *CANx, CanTxMsg *TxMessage); +uint8_t CAN_TransmitStatus(CAN_TypeDef *CANx, uint8_t TransmitMailbox); +void CAN_CancelTransmit(CAN_TypeDef *CANx, uint8_t Mailbox); +void CAN_Receive(CAN_TypeDef *CANx, uint8_t FIFONumber, CanRxMsg *RxMessage); +void CAN_FIFORelease(CAN_TypeDef *CANx, uint8_t FIFONumber); +uint8_t CAN_MessagePending(CAN_TypeDef *CANx, uint8_t FIFONumber); +uint8_t CAN_OperatingModeRequest(CAN_TypeDef *CANx, uint8_t CAN_OperatingMode); +uint8_t CAN_Sleep(CAN_TypeDef *CANx); +uint8_t CAN_WakeUp(CAN_TypeDef *CANx); +uint8_t CAN_GetLastErrorCode(CAN_TypeDef *CANx); +uint8_t CAN_GetReceiveErrorCounter(CAN_TypeDef *CANx); +uint8_t CAN_GetLSBTransmitErrorCounter(CAN_TypeDef *CANx); +void CAN_ITConfig(CAN_TypeDef *CANx, uint32_t CAN_IT, FunctionalState NewState); +FlagStatus CAN_GetFlagStatus(CAN_TypeDef *CANx, uint32_t CAN_FLAG); +void CAN_ClearFlag(CAN_TypeDef *CANx, uint32_t CAN_FLAG); +ITStatus CAN_GetITStatus(CAN_TypeDef *CANx, uint32_t CAN_IT); +void CAN_ClearITPendingBit(CAN_TypeDef *CANx, uint32_t CAN_IT); +void CAN_BS1_ModeConfig(CAN_TypeDef* CANx, uint32_t CAN_BS1_Mode, uint8_t CAN_BS1_tq); +void CAN_BusOff_ErrCntConfig(CAN_TypeDef *CANx, uint8_t BusOff_ErrCnt); +void CANFD_Restrict_ModeCmd(CAN_TypeDef *CANx, FunctionalState NewState); +uint8_t CANFD_Init(CAN_TypeDef *CANx, CANFD_InitTypeDef *CANFD_InitStruct); +void CANFD_StructInit(CANFD_InitTypeDef *CANFD_InitStruct); +uint8_t CANFD_Transmit(CAN_TypeDef *CANx, CanFDTxMsg *TxMessage); +ErrorStatus CANFD_Receive(CAN_TypeDef *CANx, uint8_t FIFONumber, CanFDRxMsg *RxMessage); +uint8_t CANFD_GetTransmitDelayOffsetVal(CAN_TypeDef *CANx); +void CANFD_TransmitMailbox_DMAAdr(CAN_TypeDef *CANx, uint8_t MailboxNumber, uint32_t Address); +void CANFD_ReceiveFIFO_DMAAdr(CAN_TypeDef *CANx, uint8_t FIFONumber, uint32_t Address); + + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/ZDBMS/BMS_CC/Peripheral/inc/ch32l103_crc.h b/ZDBMS/BMS_CC/Peripheral/inc/ch32l103_crc.h new file mode 100644 index 0000000..114754c --- /dev/null +++ b/ZDBMS/BMS_CC/Peripheral/inc/ch32l103_crc.h @@ -0,0 +1,33 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32l103_crc.h + * Author : WCH + * Version : V1.0.0 + * Date : 2023/07/08 + * Description : This file contains all the functions prototypes for the + * CRC firmware library. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#ifndef __CH32L103_CRC_H +#define __CH32L103_CRC_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "ch32l103.h" + +void CRC_ResetDR(void); +uint32_t CRC_CalcCRC(uint32_t Data); +uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength); +uint32_t CRC_GetCRC(void); +void CRC_SetIDRegister(uint8_t IDValue); +uint8_t CRC_GetIDRegister(void); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/ZDBMS/BMS_CC/Peripheral/inc/ch32l103_dbgmcu.h b/ZDBMS/BMS_CC/Peripheral/inc/ch32l103_dbgmcu.h new file mode 100644 index 0000000..4797b18 --- /dev/null +++ b/ZDBMS/BMS_CC/Peripheral/inc/ch32l103_dbgmcu.h @@ -0,0 +1,46 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32l103_dbgmcu.h + * Author : WCH + * Version : V1.0.0 + * Date : 2023/07/08 + * Description : This file contains all the functions prototypes for the + * DBGMCU firmware library. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#ifndef __CH32L103_DBGMCU_H +#define __CH32L103_DBGMCU_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "ch32l103.h" + +#define DBGMCU_SLEEP ((uint32_t)0x00000001) +#define DBGMCU_STOP ((uint32_t)0x00000002) +#define DBGMCU_STANDBY ((uint32_t)0x00000004) +#define DBGMCU_IWDG_STOP ((uint32_t)0x00000100) +#define DBGMCU_WWDG_STOP ((uint32_t)0x00000200) +#define DBGMCU_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00000400) +#define DBGMCU_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00000800) +#define DBGMCU_TIM1_STOP ((uint32_t)0x00001000) +#define DBGMCU_TIM2_STOP ((uint32_t)0x00002000) +#define DBGMCU_TIM3_STOP ((uint32_t)0x00004000) +#define DBGMCU_TIM4_STOP ((uint32_t)0x00008000) +#define DBGMCU_CAN1_STOP ((uint32_t)0x00100000) + + +uint32_t DBGMCU_GetREVID(void); +uint32_t DBGMCU_GetDEVID(void); +uint32_t __get_DEBUG_CR(void); +void __set_DEBUG_CR(uint32_t value); +void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState); +uint32_t DBGMCU_GetCHIPID( void ); +#ifdef __cplusplus +} +#endif + +#endif diff --git a/ZDBMS/BMS_CC/Peripheral/inc/ch32l103_dma.h b/ZDBMS/BMS_CC/Peripheral/inc/ch32l103_dma.h new file mode 100644 index 0000000..7042b81 --- /dev/null +++ b/ZDBMS/BMS_CC/Peripheral/inc/ch32l103_dma.h @@ -0,0 +1,184 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32l103_dma.h + * Author : WCH + * Version : V1.0.0 + * Date : 2023/07/08 + * Description : This file contains all the functions prototypes for the + * DMA firmware library. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#ifndef __CH32L103_DMA_H +#define __CH32L103_DMA_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "ch32l103.h" + +/* DMA Init structure definition */ +typedef struct +{ + uint32_t DMA_PeripheralBaseAddr; /* Specifies the peripheral base address for DMAy Channelx. */ + + uint32_t DMA_MemoryBaseAddr; /* Specifies the memory base address for DMAy Channelx. */ + + uint32_t DMA_DIR; /* Specifies if the peripheral is the source or destination. + This parameter can be a value of @ref DMA_data_transfer_direction */ + + uint32_t DMA_BufferSize; /* Specifies the buffer size, in data unit, of the specified Channel. + The data unit is equal to the configuration set in DMA_PeripheralDataSize + or DMA_MemoryDataSize members depending in the transfer direction. */ + + uint32_t DMA_PeripheralInc; /* Specifies whether the Peripheral address register is incremented or not. + This parameter can be a value of @ref DMA_peripheral_incremented_mode */ + + uint32_t DMA_MemoryInc; /* Specifies whether the memory address register is incremented or not. + This parameter can be a value of @ref DMA_memory_incremented_mode */ + + uint32_t DMA_PeripheralDataSize; /* Specifies the Peripheral data width. + This parameter can be a value of @ref DMA_peripheral_data_size */ + + uint32_t DMA_MemoryDataSize; /* Specifies the Memory data width. + This parameter can be a value of @ref DMA_memory_data_size */ + + uint32_t DMA_Mode; /* Specifies the operation mode of the DMAy Channelx. + This parameter can be a value of @ref DMA_circular_normal_mode. + @note: The circular buffer mode cannot be used if the memory-to-memory + data transfer is configured on the selected Channel */ + + uint32_t DMA_Priority; /* Specifies the software priority for the DMAy Channelx. + This parameter can be a value of @ref DMA_priority_level */ + + uint32_t DMA_M2M; /* Specifies if the DMAy Channelx will be used in memory-to-memory transfer. + This parameter can be a value of @ref DMA_memory_to_memory */ +} DMA_InitTypeDef; + +/* DMA_data_transfer_direction */ +#define DMA_DIR_PeripheralDST ((uint32_t)0x00000010) +#define DMA_DIR_PeripheralSRC ((uint32_t)0x00000000) + +/* DMA_peripheral_incremented_mode */ +#define DMA_PeripheralInc_Enable ((uint32_t)0x00000040) +#define DMA_PeripheralInc_Disable ((uint32_t)0x00000000) + +/* DMA_memory_incremented_mode */ +#define DMA_MemoryInc_Enable ((uint32_t)0x00000080) +#define DMA_MemoryInc_Disable ((uint32_t)0x00000000) + +/* DMA_peripheral_data_size */ +#define DMA_PeripheralDataSize_Byte ((uint32_t)0x00000000) +#define DMA_PeripheralDataSize_HalfWord ((uint32_t)0x00000100) +#define DMA_PeripheralDataSize_Word ((uint32_t)0x00000200) + +/* DMA_memory_data_size */ +#define DMA_MemoryDataSize_Byte ((uint32_t)0x00000000) +#define DMA_MemoryDataSize_HalfWord ((uint32_t)0x00000400) +#define DMA_MemoryDataSize_Word ((uint32_t)0x00000800) + +/* DMA_circular_normal_mode */ +#define DMA_Mode_Circular ((uint32_t)0x00000020) +#define DMA_Mode_Normal ((uint32_t)0x00000000) + +/* DMA_priority_level */ +#define DMA_Priority_VeryHigh ((uint32_t)0x00003000) +#define DMA_Priority_High ((uint32_t)0x00002000) +#define DMA_Priority_Medium ((uint32_t)0x00001000) +#define DMA_Priority_Low ((uint32_t)0x00000000) + +/* DMA_memory_to_memory */ +#define DMA_M2M_Enable ((uint32_t)0x00004000) +#define DMA_M2M_Disable ((uint32_t)0x00000000) + +/* DMA_interrupts_definition */ +#define DMA_IT_TC ((uint32_t)0x00000002) +#define DMA_IT_HT ((uint32_t)0x00000004) +#define DMA_IT_TE ((uint32_t)0x00000008) + +#define DMA1_IT_GL1 ((uint32_t)0x00000001) +#define DMA1_IT_TC1 ((uint32_t)0x00000002) +#define DMA1_IT_HT1 ((uint32_t)0x00000004) +#define DMA1_IT_TE1 ((uint32_t)0x00000008) +#define DMA1_IT_GL2 ((uint32_t)0x00000010) +#define DMA1_IT_TC2 ((uint32_t)0x00000020) +#define DMA1_IT_HT2 ((uint32_t)0x00000040) +#define DMA1_IT_TE2 ((uint32_t)0x00000080) +#define DMA1_IT_GL3 ((uint32_t)0x00000100) +#define DMA1_IT_TC3 ((uint32_t)0x00000200) +#define DMA1_IT_HT3 ((uint32_t)0x00000400) +#define DMA1_IT_TE3 ((uint32_t)0x00000800) +#define DMA1_IT_GL4 ((uint32_t)0x00001000) +#define DMA1_IT_TC4 ((uint32_t)0x00002000) +#define DMA1_IT_HT4 ((uint32_t)0x00004000) +#define DMA1_IT_TE4 ((uint32_t)0x00008000) +#define DMA1_IT_GL5 ((uint32_t)0x00010000) +#define DMA1_IT_TC5 ((uint32_t)0x00020000) +#define DMA1_IT_HT5 ((uint32_t)0x00040000) +#define DMA1_IT_TE5 ((uint32_t)0x00080000) +#define DMA1_IT_GL6 ((uint32_t)0x00100000) +#define DMA1_IT_TC6 ((uint32_t)0x00200000) +#define DMA1_IT_HT6 ((uint32_t)0x00400000) +#define DMA1_IT_TE6 ((uint32_t)0x00800000) +#define DMA1_IT_GL7 ((uint32_t)0x01000000) +#define DMA1_IT_TC7 ((uint32_t)0x02000000) +#define DMA1_IT_HT7 ((uint32_t)0x04000000) +#define DMA1_IT_TE7 ((uint32_t)0x08000000) +#define DMA1_IT_GL8 ((uint32_t)0x10000000) +#define DMA1_IT_TC8 ((uint32_t)0x20000000) +#define DMA1_IT_HT8 ((uint32_t)0x40000000) +#define DMA1_IT_TE8 ((uint32_t)0x80000000) + +/* DMA_flags_definition */ +#define DMA1_FLAG_GL1 ((uint32_t)0x00000001) +#define DMA1_FLAG_TC1 ((uint32_t)0x00000002) +#define DMA1_FLAG_HT1 ((uint32_t)0x00000004) +#define DMA1_FLAG_TE1 ((uint32_t)0x00000008) +#define DMA1_FLAG_GL2 ((uint32_t)0x00000010) +#define DMA1_FLAG_TC2 ((uint32_t)0x00000020) +#define DMA1_FLAG_HT2 ((uint32_t)0x00000040) +#define DMA1_FLAG_TE2 ((uint32_t)0x00000080) +#define DMA1_FLAG_GL3 ((uint32_t)0x00000100) +#define DMA1_FLAG_TC3 ((uint32_t)0x00000200) +#define DMA1_FLAG_HT3 ((uint32_t)0x00000400) +#define DMA1_FLAG_TE3 ((uint32_t)0x00000800) +#define DMA1_FLAG_GL4 ((uint32_t)0x00001000) +#define DMA1_FLAG_TC4 ((uint32_t)0x00002000) +#define DMA1_FLAG_HT4 ((uint32_t)0x00004000) +#define DMA1_FLAG_TE4 ((uint32_t)0x00008000) +#define DMA1_FLAG_GL5 ((uint32_t)0x00010000) +#define DMA1_FLAG_TC5 ((uint32_t)0x00020000) +#define DMA1_FLAG_HT5 ((uint32_t)0x00040000) +#define DMA1_FLAG_TE5 ((uint32_t)0x00080000) +#define DMA1_FLAG_GL6 ((uint32_t)0x00100000) +#define DMA1_FLAG_TC6 ((uint32_t)0x00200000) +#define DMA1_FLAG_HT6 ((uint32_t)0x00400000) +#define DMA1_FLAG_TE6 ((uint32_t)0x00800000) +#define DMA1_FLAG_GL7 ((uint32_t)0x01000000) +#define DMA1_FLAG_TC7 ((uint32_t)0x02000000) +#define DMA1_FLAG_HT7 ((uint32_t)0x04000000) +#define DMA1_FLAG_TE7 ((uint32_t)0x08000000) +#define DMA1_FLAG_GL8 ((uint32_t)0x10000000) +#define DMA1_FLAG_TC8 ((uint32_t)0x20000000) +#define DMA1_FLAG_HT8 ((uint32_t)0x40000000) +#define DMA1_FLAG_TE8 ((uint32_t)0x80000000) + +void DMA_DeInit(DMA_Channel_TypeDef *DMAy_Channelx); +void DMA_Init(DMA_Channel_TypeDef *DMAy_Channelx, DMA_InitTypeDef *DMA_InitStruct); +void DMA_StructInit(DMA_InitTypeDef *DMA_InitStruct); +void DMA_Cmd(DMA_Channel_TypeDef *DMAy_Channelx, FunctionalState NewState); +void DMA_ITConfig(DMA_Channel_TypeDef *DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState); +void DMA_SetCurrDataCounter(DMA_Channel_TypeDef *DMAy_Channelx, uint16_t DataNumber); +uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef *DMAy_Channelx); +FlagStatus DMA_GetFlagStatus(uint32_t DMAy_FLAG); +void DMA_ClearFlag(uint32_t DMAy_FLAG); +ITStatus DMA_GetITStatus(uint32_t DMAy_IT); +void DMA_ClearITPendingBit(uint32_t DMAy_IT); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/ZDBMS/BMS_CC/Peripheral/inc/ch32l103_exti.h b/ZDBMS/BMS_CC/Peripheral/inc/ch32l103_exti.h new file mode 100644 index 0000000..058a195 --- /dev/null +++ b/ZDBMS/BMS_CC/Peripheral/inc/ch32l103_exti.h @@ -0,0 +1,90 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32l103_exti.h + * Author : WCH + * Version : V1.0.0 + * Date : 2024/05/06 + * Description : This file contains all the functions prototypes for the + * EXTI firmware library. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#ifndef __CH32L103_EXTI_H +#define __CH32L103_EXTI_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "ch32l103.h" + +/* EXTI mode enumeration */ +typedef enum +{ + EXTI_Mode_Interrupt = 0x00, + EXTI_Mode_Event = 0x04 +} EXTIMode_TypeDef; + +/* EXTI Trigger enumeration */ +typedef enum +{ + EXTI_Trigger_Rising = 0x08, + EXTI_Trigger_Falling = 0x0C, + EXTI_Trigger_Rising_Falling = 0x10 +} EXTITrigger_TypeDef; + +/* EXTI Init Structure definition */ +typedef struct +{ + uint32_t EXTI_Line; /* Specifies the EXTI lines to be enabled or disabled. + This parameter can be any combination of @ref EXTI_Lines */ + + EXTIMode_TypeDef EXTI_Mode; /* Specifies the mode for the EXTI lines. + This parameter can be a value of @ref EXTIMode_TypeDef */ + + EXTITrigger_TypeDef EXTI_Trigger; /* Specifies the trigger signal active edge for the EXTI lines. + This parameter can be a value of @ref EXTIMode_TypeDef */ + + FunctionalState EXTI_LineCmd; /* Specifies the new state of the selected EXTI lines. + This parameter can be set either to ENABLE or DISABLE */ +} EXTI_InitTypeDef; + +/* EXTI_Lines */ +#define EXTI_Line0 ((uint32_t)0x00001) /* External interrupt line 0 */ +#define EXTI_Line1 ((uint32_t)0x00002) /* External interrupt line 1 */ +#define EXTI_Line2 ((uint32_t)0x00004) /* External interrupt line 2 */ +#define EXTI_Line3 ((uint32_t)0x00008) /* External interrupt line 3 */ +#define EXTI_Line4 ((uint32_t)0x00010) /* External interrupt line 4 */ +#define EXTI_Line5 ((uint32_t)0x00020) /* External interrupt line 5 */ +#define EXTI_Line6 ((uint32_t)0x00040) /* External interrupt line 6 */ +#define EXTI_Line7 ((uint32_t)0x00080) /* External interrupt line 7 */ +#define EXTI_Line8 ((uint32_t)0x00100) /* External interrupt line 8 */ +#define EXTI_Line9 ((uint32_t)0x00200) /* External interrupt line 9 */ +#define EXTI_Line10 ((uint32_t)0x00400) /* External interrupt line 10 */ +#define EXTI_Line11 ((uint32_t)0x00800) /* External interrupt line 11 */ +#define EXTI_Line12 ((uint32_t)0x01000) /* External interrupt line 12 */ +#define EXTI_Line13 ((uint32_t)0x02000) /* External interrupt line 13 */ +#define EXTI_Line14 ((uint32_t)0x04000) /* External interrupt line 14 */ +#define EXTI_Line15 ((uint32_t)0x08000) /* External interrupt line 15 */ +#define EXTI_Line16 ((uint32_t)0x10000) /* External interrupt line 16 Connected to the PVD Output */ +#define EXTI_Line17 ((uint32_t)0x20000) /* External interrupt line 17 Connected to the RTC Alarm event */ +#define EXTI_Line19 ((uint32_t)0x80000) /* External interrupt line 19 Connected to the USBPD Wakeup event */ +#define EXTI_Line20 ((uint32_t)0x100000) /* External interrupt line 20 Connected to the USBFS Wakeup event */ +#define EXTI_Line21 ((uint32_t)0x200000) /* External interrupt line 21 Connected to the LPTIM Wakeup event */ +#define EXTI_Line22 ((uint32_t)0x400000) /* External interrupt line 22 Connected to the COMP Wakeup event */ + +void EXTI_DeInit(void); +void EXTI_Init(EXTI_InitTypeDef *EXTI_InitStruct); +void EXTI_StructInit(EXTI_InitTypeDef *EXTI_InitStruct); +void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line); +FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line); +void EXTI_ClearFlag(uint32_t EXTI_Line); +ITStatus EXTI_GetITStatus(uint32_t EXTI_Line); +void EXTI_ClearITPendingBit(uint32_t EXTI_Line); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/ZDBMS/BMS_CC/Peripheral/inc/ch32l103_flash.h b/ZDBMS/BMS_CC/Peripheral/inc/ch32l103_flash.h new file mode 100644 index 0000000..bda3664 --- /dev/null +++ b/ZDBMS/BMS_CC/Peripheral/inc/ch32l103_flash.h @@ -0,0 +1,142 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32l103_flash.h + * Author : WCH + * Version : V1.0.0 + * Date : 2023/07/08 + * Description : This file contains all the functions prototypes for the FLASH + * firmware library. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#ifndef __CH32L103_FLASH_H +#define __CH32L103_FLASH_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "ch32l103.h" + +/* FLASH Status */ +typedef enum +{ + FLASH_BUSY = 1, + FLASH_ERROR_PG, + FLASH_ERROR_WRP, + FLASH_COMPLETE, + FLASH_TIMEOUT, + FLASH_RDP, + FLASH_OP_RANGE_ERROR = 0xFD, + FLASH_ALIGN_ERROR = 0xFE, + FLASH_ADR_RANGE_ERROR = 0xFF, +} FLASH_Status; + +/* Flash_Latency */ +#define FLASH_Latency_0 ((uint32_t)0x00000000) /* FLASH Zero Latency cycle */ +#define FLASH_Latency_1 ((uint32_t)0x00000001) /* FLASH One Latency cycle */ +#define FLASH_Latency_2 ((uint32_t)0x00000002) /* FLASH Two Latency cycle */ + +/* Write Protect 1Sectors = 2KB */ +#define FLASH_WRProt_Sectors0 ((uint32_t)0x00000001) /* Write protection of sector 0 */ +#define FLASH_WRProt_Sectors1 ((uint32_t)0x00000002) /* Write protection of sector 1 */ +#define FLASH_WRProt_Sectors2 ((uint32_t)0x00000004) /* Write protection of sector 2 */ +#define FLASH_WRProt_Sectors3 ((uint32_t)0x00000008) /* Write protection of sector 3 */ +#define FLASH_WRProt_Sectors4 ((uint32_t)0x00000010) /* Write protection of sector 4 */ +#define FLASH_WRProt_Sectors5 ((uint32_t)0x00000020) /* Write protection of sector 5 */ +#define FLASH_WRProt_Sectors6 ((uint32_t)0x00000040) /* Write protection of sector 6 */ +#define FLASH_WRProt_Sectors7 ((uint32_t)0x00000080) /* Write protection of sector 7 */ +#define FLASH_WRProt_Sectors8 ((uint32_t)0x00000100) /* Write protection of sector 8 */ +#define FLASH_WRProt_Sectors9 ((uint32_t)0x00000200) /* Write protection of sector 9 */ +#define FLASH_WRProt_Sectors10 ((uint32_t)0x00000400) /* Write protection of sector 10 */ +#define FLASH_WRProt_Sectors11 ((uint32_t)0x00000800) /* Write protection of sector 11 */ +#define FLASH_WRProt_Sectors12 ((uint32_t)0x00001000) /* Write protection of sector 12 */ +#define FLASH_WRProt_Sectors13 ((uint32_t)0x00002000) /* Write protection of sector 13 */ +#define FLASH_WRProt_Sectors14 ((uint32_t)0x00004000) /* Write protection of sector 14 */ +#define FLASH_WRProt_Sectors15 ((uint32_t)0x00008000) /* Write protection of sector 15 */ +#define FLASH_WRProt_Sectors16 ((uint32_t)0x00010000) /* Write protection of sector 16 */ +#define FLASH_WRProt_Sectors17 ((uint32_t)0x00020000) /* Write protection of sector 17 */ +#define FLASH_WRProt_Sectors18 ((uint32_t)0x00040000) /* Write protection of sector 18 */ +#define FLASH_WRProt_Sectors19 ((uint32_t)0x00080000) /* Write protection of sector 19 */ +#define FLASH_WRProt_Sectors20 ((uint32_t)0x00100000) /* Write protection of sector 20 */ +#define FLASH_WRProt_Sectors21 ((uint32_t)0x00200000) /* Write protection of sector 21 */ +#define FLASH_WRProt_Sectors22 ((uint32_t)0x00400000) /* Write protection of sector 22 */ +#define FLASH_WRProt_Sectors23 ((uint32_t)0x00800000) /* Write protection of sector 23 */ +#define FLASH_WRProt_Sectors24 ((uint32_t)0x01000000) /* Write protection of sector 24 */ +#define FLASH_WRProt_Sectors25 ((uint32_t)0x02000000) /* Write protection of sector 25 */ +#define FLASH_WRProt_Sectors26 ((uint32_t)0x04000000) /* Write protection of sector 26 */ +#define FLASH_WRProt_Sectors27 ((uint32_t)0x08000000) /* Write protection of sector 27 */ +#define FLASH_WRProt_Sectors28 ((uint32_t)0x10000000) /* Write protection of sector 28 */ +#define FLASH_WRProt_Sectors29 ((uint32_t)0x20000000) /* Write protection of sector 29 */ +#define FLASH_WRProt_Sectors30 ((uint32_t)0x40000000) /* Write protection of sector 30 */ +#define FLASH_WRProt_Sectors31 ((uint32_t)0x80000000) /* Write protection of sector 31 */ + +#define FLASH_WRProt_AllSectors ((uint32_t)0xFFFFFFFF) /* Write protection of all Sectors */ + +/* Option_Bytes_IWatchdog */ +#define OB_IWDG_SW ((uint16_t)0x0001) /* Software IWDG selected */ +#define OB_IWDG_HW ((uint16_t)0x0000) /* Hardware IWDG selected */ + +/* Option_Bytes_nRST_STOP */ +#define OB_STOP_NoRST ((uint16_t)0x0002) /* No reset generated when entering in STOP */ +#define OB_STOP_RST ((uint16_t)0x0000) /* Reset generated when entering in STOP */ + +/* Option_Bytes_nRST_STDBY */ +#define OB_STDBY_NoRST ((uint16_t)0x0004) /* No reset generated when entering in STANDBY */ +#define OB_STDBY_RST ((uint16_t)0x0000) /* Reset generated when entering in STANDBY */ + +/* Option_Bytes_OB_CAN_BusOff_MODE */ +#define OB_CAN_BusOff_MODE1 ((uint16_t)0x0020) /* Bus off recovery mode1 */ +#define OB_CAN_BusOff_MODE2 ((uint16_t)0x0000) /* Bus off recovery mode2 */ + +/* FLASH_Interrupts */ +#define FLASH_IT_ERROR ((uint32_t)0x00000400) /* FPEC error interrupt source */ +#define FLASH_IT_EOP ((uint32_t)0x00001000) /* End of FLASH Operation Interrupt source */ +#define FLASH_IT_BANK1_ERROR FLASH_IT_ERROR /* FPEC BANK1 error interrupt source */ +#define FLASH_IT_BANK1_EOP FLASH_IT_EOP /* End of FLASH BANK1 Operation Interrupt source */ + +/* FLASH_Flags */ +#define FLASH_FLAG_BSY ((uint32_t)0x00000001) /* FLASH Busy flag */ +#define FLASH_FLAG_WRPRTERR ((uint32_t)0x00000010) /* FLASH Write protected error flag */ +#define FLASH_FLAG_EOP ((uint32_t)0x00000020) /* FLASH End of Operation flag */ +#define FLASH_FLAG_WAKE_UP ((uint32_t)0x00000040) /* FLASH Wake up of Operation flag */ +#define FLASH_FLAG_OPTERR ((uint32_t)0x00000001) /* FLASH Option Byte error flag */ + +#define FLASH_FLAG_BANK1_BSY FLASH_FLAG_BSY /* FLASH BANK1 Busy flag*/ +#define FLASH_FLAG_BANK1_EOP FLASH_FLAG_EOP /* FLASH BANK1 End of Operation flag */ +#define FLASH_FLAG_BANK1_WRPRTERR FLASH_FLAG_WRPRTERR /* FLASH BANK1 Write protected error flag */ + +/*Functions used for all devices*/ +void FLASH_SetLatency(uint32_t FLASH_Latency); +void FLASH_Unlock(void); +void FLASH_Lock(void); +FLASH_Status FLASH_ErasePage(uint32_t Page_Address); +FLASH_Status FLASH_EraseAllPages(void); +FLASH_Status FLASH_EraseOptionBytes(void); +FLASH_Status FLASH_EnableWriteProtection(uint32_t FLASH_Pages); +FLASH_Status FLASH_EnableReadOutProtection(void); +FLASH_Status FLASH_UserOptionByteConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY, uint8_t OB_RST); +uint32_t FLASH_GetUserOptionByte(void); +uint32_t FLASH_GetWriteProtectionOptionByte(void); +FlagStatus FLASH_GetReadOutProtectionStatus(void); +void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState); +FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG); +void FLASH_ClearFlag(uint32_t FLASH_FLAG); +FLASH_Status FLASH_GetStatus(void); +FLASH_Status FLASH_WaitForLastOperation(uint32_t Timeout); +void FLASH_Unlock_Fast(void); +void FLASH_Lock_Fast(void); +void FLASH_BufReset(void); +void FLASH_BufLoad(uint32_t Address, uint32_t Data0); +void FLASH_ErasePage_Fast(uint32_t Page_Address); +void FLASH_EraseBlock_32K_Fast(uint32_t Block_Address); +void FLASH_ProgramPage_Fast(uint32_t Page_Address); +FLASH_Status FLASH_ROM_ERASE(uint32_t StartAddr, uint32_t Length); +FLASH_Status FLASH_ROM_WRITE(uint32_t StartAddr, uint32_t *pbuf, uint32_t Length); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/ZDBMS/BMS_CC/Peripheral/inc/ch32l103_gpio.h b/ZDBMS/BMS_CC/Peripheral/inc/ch32l103_gpio.h new file mode 100644 index 0000000..810bf66 --- /dev/null +++ b/ZDBMS/BMS_CC/Peripheral/inc/ch32l103_gpio.h @@ -0,0 +1,178 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32l103_gpio.h + * Author : WCH + * Version : V1.0.0 + * Date : 2024/03/01 + * Description : This file contains all the functions prototypes for the + * GPIO firmware library. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#ifndef __CH32L103_GPIO_H +#define __CH32L103_GPIO_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "ch32l103.h" + +/* Output Maximum frequency selection */ +typedef enum +{ + GPIO_Speed_10MHz = 1, + GPIO_Speed_2MHz, + GPIO_Speed_50MHz +} GPIOSpeed_TypeDef; + +/* Configuration Mode enumeration */ +typedef enum +{ + GPIO_Mode_AIN = 0x0, + GPIO_Mode_IN_FLOATING = 0x04, + GPIO_Mode_IPD = 0x28, + GPIO_Mode_IPU = 0x48, + GPIO_Mode_Out_OD = 0x14, + GPIO_Mode_Out_PP = 0x10, + GPIO_Mode_AF_OD = 0x1C, + GPIO_Mode_AF_PP = 0x18 +} GPIOMode_TypeDef; + +/* GPIO Init structure definition */ +typedef struct +{ + uint16_t GPIO_Pin; /* Specifies the GPIO pins to be configured. + This parameter can be any value of @ref GPIO_pins_define */ + + GPIOSpeed_TypeDef GPIO_Speed; /* Specifies the speed for the selected pins. + This parameter can be a value of @ref GPIOSpeed_TypeDef */ + + GPIOMode_TypeDef GPIO_Mode; /* Specifies the operating mode for the selected pins. + This parameter can be a value of @ref GPIOMode_TypeDef */ +} GPIO_InitTypeDef; + +/* Bit_SET and Bit_RESET enumeration */ +typedef enum +{ + Bit_RESET = 0, + Bit_SET +} BitAction; + +/* GPIO_pins_define */ +#define GPIO_Pin_0 ((uint16_t)0x0001) /* Pin 0 selected */ +#define GPIO_Pin_1 ((uint16_t)0x0002) /* Pin 1 selected */ +#define GPIO_Pin_2 ((uint16_t)0x0004) /* Pin 2 selected */ +#define GPIO_Pin_3 ((uint16_t)0x0008) /* Pin 3 selected */ +#define GPIO_Pin_4 ((uint16_t)0x0010) /* Pin 4 selected */ +#define GPIO_Pin_5 ((uint16_t)0x0020) /* Pin 5 selected */ +#define GPIO_Pin_6 ((uint16_t)0x0040) /* Pin 6 selected */ +#define GPIO_Pin_7 ((uint16_t)0x0080) /* Pin 7 selected */ +#define GPIO_Pin_8 ((uint16_t)0x0100) /* Pin 8 selected */ +#define GPIO_Pin_9 ((uint16_t)0x0200) /* Pin 9 selected */ +#define GPIO_Pin_10 ((uint16_t)0x0400) /* Pin 10 selected */ +#define GPIO_Pin_11 ((uint16_t)0x0800) /* Pin 11 selected */ +#define GPIO_Pin_12 ((uint16_t)0x1000) /* Pin 12 selected */ +#define GPIO_Pin_13 ((uint16_t)0x2000) /* Pin 13 selected */ +#define GPIO_Pin_14 ((uint16_t)0x4000) /* Pin 14 selected */ +#define GPIO_Pin_15 ((uint16_t)0x8000) /* Pin 15 selected */ +#define GPIO_Pin_All ((uint16_t)0xFFFF) /* All pins selected */ + +/* GPIO_Remap_define */ +//bit[31:30] = 11b - PCFR1-bit[15-0] and PCFR2-bit[26:16] +/* bit[29:27] = 000b */ +#define GPIO_PartialRemap1_SPI1 ((uint32_t)0xC0000001) /* SPI1 Partial1 Alternate Function mapping */ +#define GPIO_PartialRemap2_SPI1 ((uint32_t)0xC1000000) /* SPI1 Partial2 Alternate Function mapping */ +#define GPIO_FullRemap_SPI1 ((uint32_t)0xC1000001) /* SPI1 Full Alternate Function mapping */ +/* bit[29:27] = 001b */ +#define GPIO_PartialRemap1_I2C1 ((uint32_t)0xC8800000) /* I2C1 Partial1 Alternate Function mapping */ +#define GPIO_FullRemap_I2C1 ((uint32_t)0xC8800002) /* I2C1 Full Alternate Function mapping */ +/* bit[29:27] = 010b */ +#define GPIO_PartialRemap1_USART1 ((uint32_t)0xD0000004) /* USART1 Partial1 Alternate Function mapping */ +#define GPIO_PartialRemap2_USART1 ((uint32_t)0xD0080000) /* USART1 Partial2 Alternate Function mapping */ +#define GPIO_PartialRemap3_USART1 ((uint32_t)0xD0080004) /* USART1 Partial3 Alternate Function mapping */ +#define GPIO_PartialRemap4_USART1 ((uint32_t)0xD0100000) /* USART1 Partial4 Alternate Function mapping */ +#define GPIO_FullRemap_USART1 ((uint32_t)0xD0100004) /* USART1 Full Alternate Function mapping */ +/* bit[29:27] = 011b */ +#define GPIO_PartialRemap1_USART2 ((uint32_t)0xD8000008) /* USART2 Partial1 Alternate Function mapping */ +#define GPIO_PartialRemap2_USART2 ((uint32_t)0xD8040000) /* USART2 Partial2 Alternate Function mapping */ +#define GPIO_FullRemap_USART2 ((uint32_t)0xD8040008) /* USART2 Full Alternate Function mapping */ +/* bit[29:27] = 100b */ +#define GPIO_PartialRemap1_TIM1 ((uint32_t)0xE0000040) /* TIM1 Partial1 Alternate Function mapping */ +#define GPIO_PartialRemap2_TIM1 ((uint32_t)0xE0000080) /* TIM1 Partial2 Alternate Function mapping */ +#define GPIO_PartialRemap3_TIM1 ((uint32_t)0xE00000C0) /* TIM1 Partial3 Alternate Function mapping */ +#define GPIO_PartialRemap4_TIM1 ((uint32_t)0xE0400000) /* TIM1 Partial4 Alternate Function mapping */ +#define GPIO_PartialRemap5_TIM1 ((uint32_t)0xE0400040) /* TIM1 Partial5 Alternate Function mapping */ +#define GPIO_FullRemap_TIM1 ((uint32_t)0xE04000C0) /* TIM1 Full Alternate Function mapping */ +/* bit[29:27] = 101b */ +#define GPIO_PartialRemap1_TIM2 ((uint32_t)0xE8000100) /* TIM2 Partial1 Alternate Function mapping */ +#define GPIO_PartialRemap2_TIM2 ((uint32_t)0xE8000200) /* TIM2 Partial2 Alternate Function mapping */ +#define GPIO_PartialRemap3_TIM2 ((uint32_t)0xE8000300) /* TIM2 Partial3 Alternate Function mapping */ +#define GPIO_PartialRemap4_TIM2 ((uint32_t)0xE8200000) /* TIM2 Partial4 Alternate Function mapping */ +#define GPIO_PartialRemap5_TIM2 ((uint32_t)0xE8200100) /* TIM2 Partial5 Alternate Function mapping */ +#define GPIO_FullRemap_TIM2 ((uint32_t)0xE8200300) /* TIM2 Full Alternate Function mapping */ + +//bit[31:30] = 00b - PCFR1 +#define GPIO_PartialRemap_USART3 ((uint32_t)0x00140020) /* USART3 Partial Alternate Function mapping */ +#define GPIO_FullRemap_USART3 ((uint32_t)0x00140030) /* USART3 Full Alternate Function mapping */ +#define GPIO_Remap_TIM3 ((uint32_t)0x00000400) /* TIM3 Alternate Function mapping */ +#define GPIO_Remap_TIM4 ((uint32_t)0x00001000) /* TIM4 Alternate Function mapping */ +#define GPIO_Remap1_CAN1 ((uint32_t)0x001D4000) /* CAN1 Alternate Function mapping */ +#define GPIO_Remap2_CAN1 ((uint32_t)0x001D6000) /* CAN1 Alternate Function mapping */ +#define GPIO_Remap_PD01 ((uint32_t)0x00008000) /* PD01 Alternate Function mapping */ +#define GPIO_Remap_SWJ_Disable ((uint32_t)0x00300400) /* GPIO_Remap_SWJ_Disable - Full SDI Disabled (SDI) */ + +//bit[31:30] = 01b - PCFR2 +#define GPIO_Remap_USART4 ((uint32_t)0x40000001) /* USART4 Alternate Function mapping */ +#define GPIO_Remap_LPTIM ((uint32_t)0x40000200) /* LPTIM Alternate Function mapping */ + +/* GPIO_Port_Sources */ +#define GPIO_PortSourceGPIOA ((uint8_t)0x00) +#define GPIO_PortSourceGPIOB ((uint8_t)0x01) +#define GPIO_PortSourceGPIOC ((uint8_t)0x02) +#define GPIO_PortSourceGPIOD ((uint8_t)0x03) + +/* GPIO_Pin_sources */ +#define GPIO_PinSource0 ((uint8_t)0x00) +#define GPIO_PinSource1 ((uint8_t)0x01) +#define GPIO_PinSource2 ((uint8_t)0x02) +#define GPIO_PinSource3 ((uint8_t)0x03) +#define GPIO_PinSource4 ((uint8_t)0x04) +#define GPIO_PinSource5 ((uint8_t)0x05) +#define GPIO_PinSource6 ((uint8_t)0x06) +#define GPIO_PinSource7 ((uint8_t)0x07) +#define GPIO_PinSource8 ((uint8_t)0x08) +#define GPIO_PinSource9 ((uint8_t)0x09) +#define GPIO_PinSource10 ((uint8_t)0x0A) +#define GPIO_PinSource11 ((uint8_t)0x0B) +#define GPIO_PinSource12 ((uint8_t)0x0C) +#define GPIO_PinSource13 ((uint8_t)0x0D) +#define GPIO_PinSource14 ((uint8_t)0x0E) +#define GPIO_PinSource15 ((uint8_t)0x0F) + + +void GPIO_DeInit(GPIO_TypeDef *GPIOx); +void GPIO_AFIODeInit(void); +void GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_InitStruct); +void GPIO_StructInit(GPIO_InitTypeDef *GPIO_InitStruct); +uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin); +uint16_t GPIO_ReadInputData(GPIO_TypeDef *GPIOx); +uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin); +uint16_t GPIO_ReadOutputData(GPIO_TypeDef *GPIOx); +void GPIO_SetBits(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin); +void GPIO_ResetBits(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin); +void GPIO_WriteBit(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, BitAction BitVal); +void GPIO_Write(GPIO_TypeDef *GPIOx, uint16_t PortVal); +void GPIO_PinLockConfig(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin); +void GPIO_EventOutputConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource); +void GPIO_EventOutputCmd(FunctionalState NewState); +void GPIO_PinRemapConfig(uint32_t GPIO_Remap, FunctionalState NewState); +void GPIO_EXTILineConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource); +void GPIO_IPD_Unused(void); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/ZDBMS/BMS_CC/Peripheral/inc/ch32l103_i2c.h b/ZDBMS/BMS_CC/Peripheral/inc/ch32l103_i2c.h new file mode 100644 index 0000000..6489e8e --- /dev/null +++ b/ZDBMS/BMS_CC/Peripheral/inc/ch32l103_i2c.h @@ -0,0 +1,424 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32l103_i2c.h + * Author : WCH + * Version : V1.0.0 + * Date : 2023/07/08 + * Description : This file contains all the functions prototypes for the + * I2C firmware library. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#ifndef __CH32L103_I2C_H +#define __CH32L103_I2C_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "ch32l103.h" + +/* I2C Init structure definition */ +typedef struct +{ + uint32_t I2C_ClockSpeed; /* Specifies the clock frequency. + This parameter must be set to a value lower than 400kHz */ + + uint16_t I2C_Mode; /* Specifies the I2C mode. + This parameter can be a value of @ref I2C_mode */ + + uint16_t I2C_DutyCycle; /* Specifies the I2C fast mode duty cycle. + This parameter can be a value of @ref I2C_duty_cycle_in_fast_mode */ + + uint16_t I2C_OwnAddress1; /* Specifies the first device own address. + This parameter can be a 7-bit or 10-bit address. */ + + uint16_t I2C_Ack; /* Enables or disables the acknowledgement. + This parameter can be a value of @ref I2C_acknowledgement */ + + uint16_t I2C_AcknowledgedAddress; /* Specifies if 7-bit or 10-bit address is acknowledged. + This parameter can be a value of @ref I2C_acknowledged_address */ +} I2C_InitTypeDef; + +/* I2C_mode */ +#define I2C_Mode_I2C ((uint16_t)0x0000) +#define I2C_Mode_SMBusDevice ((uint16_t)0x0002) +#define I2C_Mode_SMBusHost ((uint16_t)0x000A) + +/* I2C_duty_cycle_in_fast_mode */ +#define I2C_DutyCycle_16_9 ((uint16_t)0x4000) /* I2C fast mode Tlow/Thigh = 16/9 */ +#define I2C_DutyCycle_2 ((uint16_t)0xBFFF) /* I2C fast mode Tlow/Thigh = 2 */ + +/* I2C_acknowledgement */ +#define I2C_Ack_Enable ((uint16_t)0x0400) +#define I2C_Ack_Disable ((uint16_t)0x0000) + +/* I2C_transfer_direction */ +#define I2C_Direction_Transmitter ((uint8_t)0x00) +#define I2C_Direction_Receiver ((uint8_t)0x01) + +/* I2C_acknowledged_address */ +#define I2C_AcknowledgedAddress_7bit ((uint16_t)0x4000) +#define I2C_AcknowledgedAddress_10bit ((uint16_t)0xC000) + +/* I2C_registers */ +#define I2C_Register_CTLR1 ((uint8_t)0x00) +#define I2C_Register_CTLR2 ((uint8_t)0x04) +#define I2C_Register_OADDR1 ((uint8_t)0x08) +#define I2C_Register_OADDR2 ((uint8_t)0x0C) +#define I2C_Register_DATAR ((uint8_t)0x10) +#define I2C_Register_STAR1 ((uint8_t)0x14) +#define I2C_Register_STAR2 ((uint8_t)0x18) +#define I2C_Register_CKCFGR ((uint8_t)0x1C) +#define I2C_Register_RTR ((uint8_t)0x20) + +/* I2C_SMBus_alert_pin_level */ +#define I2C_SMBusAlert_Low ((uint16_t)0x2000) +#define I2C_SMBusAlert_High ((uint16_t)0xDFFF) + +/* I2C_PEC_position */ +#define I2C_PECPosition_Next ((uint16_t)0x0800) +#define I2C_PECPosition_Current ((uint16_t)0xF7FF) + +/* I2C_NACK_position */ +#define I2C_NACKPosition_Next ((uint16_t)0x0800) +#define I2C_NACKPosition_Current ((uint16_t)0xF7FF) + +/* I2C_interrupts_definition */ +#define I2C_IT_BUF ((uint16_t)0x0400) +#define I2C_IT_EVT ((uint16_t)0x0200) +#define I2C_IT_ERR ((uint16_t)0x0100) + +/* I2C_interrupts_definition */ +#define I2C_IT_SMBALERT ((uint32_t)0x01008000) +#define I2C_IT_TIMEOUT ((uint32_t)0x01004000) +#define I2C_IT_PECERR ((uint32_t)0x01001000) +#define I2C_IT_OVR ((uint32_t)0x01000800) +#define I2C_IT_AF ((uint32_t)0x01000400) +#define I2C_IT_ARLO ((uint32_t)0x01000200) +#define I2C_IT_BERR ((uint32_t)0x01000100) +#define I2C_IT_TXE ((uint32_t)0x06000080) +#define I2C_IT_RXNE ((uint32_t)0x06000040) +#define I2C_IT_STOPF ((uint32_t)0x02000010) +#define I2C_IT_ADD10 ((uint32_t)0x02000008) +#define I2C_IT_BTF ((uint32_t)0x02000004) +#define I2C_IT_ADDR ((uint32_t)0x02000002) +#define I2C_IT_SB ((uint32_t)0x02000001) + +/* STAR2 register flags */ +#define I2C_FLAG_DUALF ((uint32_t)0x00800000) +#define I2C_FLAG_SMBHOST ((uint32_t)0x00400000) +#define I2C_FLAG_SMBDEFAULT ((uint32_t)0x00200000) +#define I2C_FLAG_GENCALL ((uint32_t)0x00100000) +#define I2C_FLAG_TRA ((uint32_t)0x00040000) +#define I2C_FLAG_BUSY ((uint32_t)0x00020000) +#define I2C_FLAG_MSL ((uint32_t)0x00010000) + +/* STAR1 register flags */ +#define I2C_FLAG_SMBALERT ((uint32_t)0x10008000) +#define I2C_FLAG_TIMEOUT ((uint32_t)0x10004000) +#define I2C_FLAG_PECERR ((uint32_t)0x10001000) +#define I2C_FLAG_OVR ((uint32_t)0x10000800) +#define I2C_FLAG_AF ((uint32_t)0x10000400) +#define I2C_FLAG_ARLO ((uint32_t)0x10000200) +#define I2C_FLAG_BERR ((uint32_t)0x10000100) +#define I2C_FLAG_TXE ((uint32_t)0x10000080) +#define I2C_FLAG_RXNE ((uint32_t)0x10000040) +#define I2C_FLAG_STOPF ((uint32_t)0x10000010) +#define I2C_FLAG_ADD10 ((uint32_t)0x10000008) +#define I2C_FLAG_BTF ((uint32_t)0x10000004) +#define I2C_FLAG_ADDR ((uint32_t)0x10000002) +#define I2C_FLAG_SB ((uint32_t)0x10000001) + +/****************I2C Master Events (Events grouped in order of communication)********************/ + +/******************************************************************************************************************** + * @brief Start communicate + * + * After master use I2C_GenerateSTART() function sending the START condition,the master + * has to wait for event 5(the Start condition has been correctly + * released on the I2C bus ). + * + */ +/* EVT5 */ +#define I2C_EVENT_MASTER_MODE_SELECT ((uint32_t)0x00030001) /* BUSY, MSL and SB flag */ + +/******************************************************************************************************************** + * @brief Address Acknowledge + * + * When start condition correctly released on the bus(check EVT5), the + * master use I2C_Send7bitAddress() function sends the address of the slave(s) with which it will communicate + * it also determines master as transmitter or Receiver. Then the master has to wait that a slave acknowledges + * his address. If an acknowledge is sent on the bus, one of the following events will be set: + * + * 1) In case of Master Receiver (7-bit addressing): the I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED + * event is set. + * + * 2) In case of Master Transmitter (7-bit addressing): the I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED + * is set + * + * 3) In case of 10-Bit addressing mode, the master (after generating the START + * and checking on EVT5) use I2C_SendData() function send the header of 10-bit addressing mode. + * Then master wait EVT9. EVT9 means that the 10-bit addressing header has been correctly sent + * on the bus. Then master should use the function I2C_Send7bitAddress() to send the second part + * of the 10-bit address (LSB) . Then master should wait for event 6. + * + * + */ + +/* EVT6 */ +#define I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED ((uint32_t)0x00070082) /* BUSY, MSL, ADDR, TXE and TRA flags */ +#define I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED ((uint32_t)0x00030002) /* BUSY, MSL and ADDR flags */ +/* EVT9 */ +#define I2C_EVENT_MASTER_MODE_ADDRESS10 ((uint32_t)0x00030008) /* BUSY, MSL and ADD10 flags */ + +/******************************************************************************************************************** + * @brief Communication events + * + * If START condition has generated and slave address + * been acknowledged. then the master has to check one of the following events for + * communication procedures: + * + * 1) Master Receiver mode: The master has to wait on the event EVT7 then use + * I2C_ReceiveData() function to read the data received from the slave. + * + * 2) Master Transmitter mode: The master use I2C_SendData() function to send data + * then to wait on event EVT8 or EVT8_2. + * These two events are similar: + * - EVT8 means that the data has been written in the data register and is + * being shifted out. + * - EVT8_2 means that the data has been physically shifted out and output + * on the bus. + * In most cases, using EVT8 is sufficient for the application. + * Using EVT8_2 will leads to a slower communication speed but will more reliable . + * EVT8_2 is also more suitable than EVT8 for testing on the last data transmission + * + * Note: + * In case the user software does not guarantee that this event EVT7 is managed before + * the current byte end of transfer, then user may check on I2C_EVENT_MASTER_BYTE_RECEIVED + * and I2C_FLAG_BTF flag at the same time .But in this case the communication may be slower. + * + * + */ + +/* Master Receive mode */ +/* EVT7 */ +#define I2C_EVENT_MASTER_BYTE_RECEIVED ((uint32_t)0x00030040) /* BUSY, MSL and RXNE flags */ + +/* Master Transmitter mode*/ +/* EVT8 */ +#define I2C_EVENT_MASTER_BYTE_TRANSMITTING ((uint32_t)0x00070080) /* TRA, BUSY, MSL, TXE flags */ +/* EVT8_2 */ +#define I2C_EVENT_MASTER_BYTE_TRANSMITTED ((uint32_t)0x00070084) /* TRA, BUSY, MSL, TXE and BTF flags */ + +/******************I2C Slave Events (Events grouped in order of communication)******************/ + +/******************************************************************************************************************** + * @brief Start Communicate events + * + * Wait on one of these events at the start of the communication. It means that + * the I2C peripheral detected a start condition of master device generate on the bus. + * If the acknowledge feature is enabled through function I2C_AcknowledgeConfig()),The peripheral generates an ACK condition on the bus. + * + * a) In normal case (only one address managed by the slave), when the address + * sent by the master matches the own address of the peripheral (configured by + * I2C_OwnAddress1 field) the I2C_EVENT_SLAVE_XXX_ADDRESS_MATCHED event is set + * (where XXX could be TRANSMITTER or RECEIVER). + * + * b) In case the address sent by the master matches the second address of the + * peripheral (configured by the function I2C_OwnAddress2Config() and enabled + * by the function I2C_DualAddressCmd()) the events I2C_EVENT_SLAVE_XXX_SECONDADDRESS_MATCHED + * (where XXX could be TRANSMITTER or RECEIVER) are set. + * + * c) In case the address sent by the master is General Call (address 0x00) and + * if the General Call is enabled for the peripheral (using function I2C_GeneralCallCmd()) + * the following event is set I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED. + * + */ + +/* EVT1 */ +/* a) Case of One Single Address managed by the slave */ +#define I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED ((uint32_t)0x00020002) /* BUSY and ADDR flags */ +#define I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED ((uint32_t)0x00060082) /* TRA, BUSY, TXE and ADDR flags */ + +/* b) Case of Dual address managed by the slave */ +#define I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED ((uint32_t)0x00820000) /* DUALF and BUSY flags */ +#define I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED ((uint32_t)0x00860080) /* DUALF, TRA, BUSY and TXE flags */ + +/* c) Case of General Call enabled for the slave */ +#define I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED ((uint32_t)0x00120000) /* GENCALL and BUSY flags */ + +/******************************************************************************************************************** + * @brief Communication events + * + * Wait on one of these events when EVT1 has already been checked : + * + * - Slave Receiver mode: + * - EVT2--The device is expecting to receive a data byte . + * - EVT4--The device is expecting the end of the communication: master + * sends a stop condition and data transmission is stopped. + * + * - Slave Transmitter mode: + * - EVT3--When a byte has been transmitted by the slave and the Master is expecting + * the end of the byte transmission. The two events I2C_EVENT_SLAVE_BYTE_TRANSMITTED and + * I2C_EVENT_SLAVE_BYTE_TRANSMITTING are similar. If the user software doesn't guarantee + * the EVT3 is managed before the current byte end of transfer The second one can optionally + * be used. + * - EVT3_2--When the master sends a NACK to tell slave device that data transmission + * shall end . The slave device has to stop sending + * data bytes and wait a Stop condition from bus. + * + * Note: + * If the user software does not guarantee that the event 2 is + * managed before the current byte end of transfer, User may check on I2C_EVENT_SLAVE_BYTE_RECEIVED + * and I2C_FLAG_BTF flag at the same time . + * In this case the communication will be slower. + * + */ + +/* Slave Receiver mode*/ +/* EVT2 */ +#define I2C_EVENT_SLAVE_BYTE_RECEIVED ((uint32_t)0x00020040) /* BUSY and RXNE flags */ +/* EVT4 */ +#define I2C_EVENT_SLAVE_STOP_DETECTED ((uint32_t)0x00000010) /* STOPF flag */ + +/* Slave Transmitter mode*/ +/* EVT3 */ +#define I2C_EVENT_SLAVE_BYTE_TRANSMITTED ((uint32_t)0x00060084) /* TRA, BUSY, TXE and BTF flags */ +#define I2C_EVENT_SLAVE_BYTE_TRANSMITTING ((uint32_t)0x00060080) /* TRA, BUSY and TXE flags */ +/* EVT3_2 */ +#define I2C_EVENT_SLAVE_ACK_FAILURE ((uint32_t)0x00000400) /* AF flag */ + + +void I2C_DeInit(I2C_TypeDef *I2Cx); +void I2C_Init(I2C_TypeDef *I2Cx, I2C_InitTypeDef *I2C_InitStruct); +void I2C_StructInit(I2C_InitTypeDef *I2C_InitStruct); +void I2C_Cmd(I2C_TypeDef *I2Cx, FunctionalState NewState); +void I2C_DMACmd(I2C_TypeDef *I2Cx, FunctionalState NewState); +void I2C_DMALastTransferCmd(I2C_TypeDef *I2Cx, FunctionalState NewState); +void I2C_GenerateSTART(I2C_TypeDef *I2Cx, FunctionalState NewState); +void I2C_GenerateSTOP(I2C_TypeDef *I2Cx, FunctionalState NewState); +void I2C_AcknowledgeConfig(I2C_TypeDef *I2Cx, FunctionalState NewState); +void I2C_OwnAddress2Config(I2C_TypeDef *I2Cx, uint8_t Address); +void I2C_DualAddressCmd(I2C_TypeDef *I2Cx, FunctionalState NewState); +void I2C_GeneralCallCmd(I2C_TypeDef *I2Cx, FunctionalState NewState); +void I2C_ITConfig(I2C_TypeDef *I2Cx, uint16_t I2C_IT, FunctionalState NewState); +void I2C_SendData(I2C_TypeDef *I2Cx, uint8_t Data); +uint8_t I2C_ReceiveData(I2C_TypeDef *I2Cx); +void I2C_Send7bitAddress(I2C_TypeDef *I2Cx, uint8_t Address, uint8_t I2C_Direction); +uint16_t I2C_ReadRegister(I2C_TypeDef *I2Cx, uint8_t I2C_Register); +void I2C_SoftwareResetCmd(I2C_TypeDef *I2Cx, FunctionalState NewState); +void I2C_NACKPositionConfig(I2C_TypeDef *I2Cx, uint16_t I2C_NACKPosition); +void I2C_SMBusAlertConfig(I2C_TypeDef *I2Cx, uint16_t I2C_SMBusAlert); +void I2C_TransmitPEC(I2C_TypeDef *I2Cx, FunctionalState NewState); +void I2C_PECPositionConfig(I2C_TypeDef *I2Cx, uint16_t I2C_PECPosition); +void I2C_CalculatePEC(I2C_TypeDef *I2Cx, FunctionalState NewState); +uint8_t I2C_GetPEC(I2C_TypeDef *I2Cx); +void I2C_ARPCmd(I2C_TypeDef *I2Cx, FunctionalState NewState); +void I2C_StretchClockCmd(I2C_TypeDef *I2Cx, FunctionalState NewState); +void I2C_FastModeDutyCycleConfig(I2C_TypeDef *I2Cx, uint16_t I2C_DutyCycle); + + +/***************************************************************************************** + * + * I2C State Monitoring Functions + * + **************************************************************************************** + * This I2C driver provides three different ways for I2C state monitoring + * profit the application requirements and constraints: + * + * + * a) First way: + * Using I2C_CheckEvent() function: + * It compares the status registers (STARR1 and STAR2) content to a given event + * (can be the combination of more flags). + * If the current status registers includes the given flags will return SUCCESS. + * and if the current status registers miss flags will returns ERROR. + * - When to use: + * - This function is suitable for most applications as well as for startup + * activity since the events are fully described in the product reference manual + * (CH32FV2x-V3xRM). + * - It is also suitable for users who need to define their own events. + * - Limitations: + * - If an error occurs besides to the monitored error, + * the I2C_CheckEvent() function may return SUCCESS despite the communication + * in corrupted state. it is suggeted to use error interrupts to monitor the error + * events and handle them in IRQ handler. + * + * + * Note: + * The following functions are recommended for error management: : + * - I2C_ITConfig() main function of configure and enable the error interrupts. + * - I2Cx_ER_IRQHandler() will be called when the error interrupt happen. + * Where x is the peripheral instance (I2C1, I2C2 ...) + * - I2Cx_ER_IRQHandler() will call I2C_GetFlagStatus() or I2C_GetITStatus() functions + * to determine which error occurred. + * - I2C_ClearFlag() \ I2C_ClearITPendingBit() \ I2C_SoftwareResetCmd() + * \ I2C_GenerateStop() will be use to clear the error flag and source, + * and return to correct communication status. + * + * + * b) Second way: + * Using the function to get a single word(uint32_t) composed of status register 1 and register 2. + * (Status Register 2 value is shifted left by 16 bits and concatenated to Status Register 1). + * - When to use: + * + * - This function is suitable for the same applications above but it + * don't have the limitations of I2C_GetFlagStatus() function . + * The returned value could be compared to events already defined in the + * library (CH32L103_i2c.h) or to custom values defined by user. + * - This function can be used to monitor the status of multiple flags simultaneously. + * - Contrary to the I2C_CheckEvent () function, this function can choose the time to + * accept the event according to the user's needs (when all event flags are set and + * no other flags are set, or only when the required flags are set) + * + * - Limitations: + * - User may need to define his own events. + * - Same remark concerning the error management is applicable for this + * function if user decides to check only regular communication flags (and + * ignores error flags). + * + * + * c) Third way: + * Using the function I2C_GetFlagStatus() get the status of + * one single flag . + * - When to use: + * - This function could be used for specific applications or in debug phase. + * - It is suitable when only one flag checking is needed . + * + * - Limitations: + * - Call this function to access the status register. Some flag bits may be cleared. + * - Function may need to be called twice or more in order to monitor one single event. + */ + + + +/********************************************************* + * + * a) Basic state monitoring(First way) + ******************************************************** + */ +ErrorStatus I2C_CheckEvent(I2C_TypeDef* I2Cx, uint32_t I2C_EVENT); +/********************************************************* + * + * b) Advanced state monitoring(Second way) + ******************************************************** + */ +uint32_t I2C_GetLastEvent(I2C_TypeDef* I2Cx); +/********************************************************* + * + * c) Flag-based state monitoring(Third way) + ********************************************************* + */ +FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG); + +void I2C_ClearFlag(I2C_TypeDef *I2Cx, uint32_t I2C_FLAG); +ITStatus I2C_GetITStatus(I2C_TypeDef *I2Cx, uint32_t I2C_IT); +void I2C_ClearITPendingBit(I2C_TypeDef *I2Cx, uint32_t I2C_IT); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/ZDBMS/BMS_CC/Peripheral/inc/ch32l103_iwdg.h b/ZDBMS/BMS_CC/Peripheral/inc/ch32l103_iwdg.h new file mode 100644 index 0000000..b72715d --- /dev/null +++ b/ZDBMS/BMS_CC/Peripheral/inc/ch32l103_iwdg.h @@ -0,0 +1,50 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32l103_iwdg.h + * Author : WCH + * Version : V1.0.0 + * Date : 2023/07/08 + * Description : This file contains all the functions prototypes for the + * IWDG firmware library. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#ifndef __CH32L103_IWDG_H +#define __CH32L103_IWDG_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "ch32l103.h" + +/* IWDG_WriteAccess */ +#define IWDG_WriteAccess_Enable ((uint16_t)0x5555) +#define IWDG_WriteAccess_Disable ((uint16_t)0x0000) + +/* IWDG_prescaler */ +#define IWDG_Prescaler_4 ((uint8_t)0x00) +#define IWDG_Prescaler_8 ((uint8_t)0x01) +#define IWDG_Prescaler_16 ((uint8_t)0x02) +#define IWDG_Prescaler_32 ((uint8_t)0x03) +#define IWDG_Prescaler_64 ((uint8_t)0x04) +#define IWDG_Prescaler_128 ((uint8_t)0x05) +#define IWDG_Prescaler_256 ((uint8_t)0x06) + +/* IWDG_Flag */ +#define IWDG_FLAG_PVU ((uint16_t)0x0001) +#define IWDG_FLAG_RVU ((uint16_t)0x0002) + +void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess); +void IWDG_SetPrescaler(uint8_t IWDG_Prescaler); +void IWDG_SetReload(uint16_t Reload); +void IWDG_ReloadCounter(void); +void IWDG_Enable(void); +FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/ZDBMS/BMS_CC/Peripheral/inc/ch32l103_lptim.h b/ZDBMS/BMS_CC/Peripheral/inc/ch32l103_lptim.h new file mode 100644 index 0000000..5f4a1ad --- /dev/null +++ b/ZDBMS/BMS_CC/Peripheral/inc/ch32l103_lptim.h @@ -0,0 +1,200 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32l103_lptim.h + * Author : WCH + * Version : V1.0.0 + * Date : 2024/07/15 + * Description : This file contains all the functions prototypes for the + * TIM firmware library. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#ifndef __CH32L103_LPTIM_H +#define __CH32L103_LPTIM_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "ch32l103.h" + +typedef struct +{ + uint32_t LPTIM_ClockSource; /* Selects the clock source. + This parameter can be a value of @ref LPTIM_Clock_Source */ + + union{ + uint32_t LPTIM_ClockPolarity; /* Configures Clock Polarity(No Encoder mode). + This parameter can be a value of @ref LPTIM_ClockPolarity */ + + uint32_t LPTIM_EncoderMode; /* Configures Encoder mode. + This parameter can be a value of @ref LPTIM_EncoderMode */ + }; + + uint32_t LPTIM_ClockSampleTime; /* Configures Clock Sample Time. + This parameter can be a value of @ref LPTIM_ClockSampleTime */ + + uint32_t LPTIM_TriggerSampleTime; /* Configures Trigger Sample Time. + This parameter can be a value of @ref LPTIM_TriggerSampleTime */ + + uint32_t LPTIM_ClockPrescaler; /* Configures the clock Prescaler. + This parameter can be a value of @ref LPTIM_ClockPrescaler */ + + uint32_t LPTIM_TriggerSource; /* Configures trigger source. + This parameter can be a value of @ref LPTIM_TriggerSource */ + + uint32_t LPTIM_ExTriggerPolarity; /* Configures external trigger polarity. + This parameter can be a value of @ref LPTIM_ExTriggerPolarity */ + + FunctionalState LPTIM_TimeOut; /* Specifies whether the time out function. + This parameter can be set to ENABLE or DISABLE */ + + FunctionalState LPTIM_OnePulseMode; /* Specifies whether the PWM out one pulse. + This parameter can be set to ENABLE or DISABLE */ + + uint32_t LPTIM_OutputPolarity; /* Configures output polarity. + This parameter can be a value of @ref LPTIM_OutputPolarity */ + + uint32_t LPTIM_UpdateMode; /* Configures update mode. + This parameter can be a value of @ref LPTIM_UpdateMode */ + + uint32_t LPTIM_CountSource; /* Configures Counter Source. + This parameter can be a value of @ref LPTIM_CountSource */ + + FunctionalState LPTIM_Encoder; /* Specifies whether open Encoder function. + This parameter can be set to ENABLE or DISABLE */ + + uint32_t LPTIM_InClockSource; /* Specifies Internal clock source. + This parameter can be a value of @ref LPTIM_InClockSource */ + + FunctionalState LPTIM_ForceOutHigh; /* Specifies whether the PWM out high level. + This parameter can be set to ENABLE or DISABLE */ + + FunctionalState LPTIM_SingleMode; /* Specifies whether single mode. + This parameter can be set to ENABLE or DISABLE */ + + FunctionalState LPTIM_ContinuousMode; /* Specifies whether continuous mode. + This parameter can be set to ENABLE or DISABLE */ + + FunctionalState LPTIM_PWMOut; /* Specifies whether PWM out function. + This parameter can be set to ENABLE or DISABLE */ + + FunctionalState LPTIM_CounterDirIndicat; /* Specifies whether counter direction indicate function. + This parameter can be set to ENABLE or DISABLE */ + + uint16_t LPTIM_Pulse; /* Specifies the pulse value to be loaded into the Capture Compare Register. + This parameter can be a number between 0x0000 and 0xFFFF */ + + uint16_t LPTIM_Period; /* Specifies the period value to be loaded into the active + This parameter must be a number between 0x0000 and 0xFFFF. */ +} LPTIM_TimeBaseInitTypeDef; + + +/* LPTIM_Clock_Source */ +#define LPTIM_ClockSource_In ((uint32_t)0x00000000) +#define LPTIM_ClockSource_Ex ((uint32_t)0x00000001) + +/* LPTIM_ClockPolarity */ +#define LPTIM_ClockPolarity_Rising ((uint32_t)0x00000000) +#define LPTIM_ClockPolarity_Falling ((uint32_t)0x00000002) +#define LPTIM_ClockPolarity_Rising_Falling ((uint32_t)0x00000004) + +/* LPTIM_ClockPrescalerTime */ +#define LPTIM_ClockSampleTime_0T ((uint32_t)0x00000000) +#define LPTIM_ClockSampleTime_2T ((uint32_t)0x00000008) +#define LPTIM_ClockSampleTime_4T ((uint32_t)0x00000010) +#define LPTIM_ClockSampleTime_8T ((uint32_t)0x00000018) + +/* LPTIM_TriggerSampleTime */ +#define LPTIM_TriggerSampleTime_0T ((uint32_t)0x00000000) +#define LPTIM_TriggerSampleTime_2T ((uint32_t)0x00000040) +#define LPTIM_TriggerSampleTime_4T ((uint32_t)0x00000080) +#define LPTIM_TriggerSampleTime_8T ((uint32_t)0x000000C0) + +/* LPTIM_ClockPrescaler */ +#define LPTIM_TClockPrescaler_DIV1 ((uint32_t)0x00000000) +#define LPTIM_TClockPrescaler_DIV2 ((uint32_t)0x00000200) +#define LPTIM_TClockPrescaler_DIV4 ((uint32_t)0x00000400) +#define LPTIM_TClockPrescaler_DIV8 ((uint32_t)0x00000600) +#define LPTIM_TClockPrescaler_DIV16 ((uint32_t)0x00000800) +#define LPTIM_TClockPrescaler_DIV32 ((uint32_t)0x00000A00) +#define LPTIM_TClockPrescaler_DIV64 ((uint32_t)0x00000C00) +#define LPTIM_TClockPrescaler_DIV128 ((uint32_t)0x00000E00) + +/* LPTIM_TriggerSource */ +#define LPTIM_TriggerSource_ETR ((uint32_t)0x00000000) +#define LPTIM_TriggerSource_RTC_ALARM ((uint32_t)0x00002000) +#define LPTIM_TriggerSource_TAMP ((uint32_t)0x00004000) + +/* LPTIM_ExTriggerPolarity */ +#define LPTIM_ExTriggerPolarity_Disable ((uint32_t)0x00000000) +#define LPTIM_ExTriggerPolarity_Rising ((uint32_t)0x00020000) +#define LPTIM_ExTriggerPolarity_Falling ((uint32_t)0x00040000) +#define LPTIM_ExTriggerPolarity_Rising_Falling ((uint32_t)0x00060000) + +/* LPTIM_OutputPolarity */ +#define LPTIM_OutputPolarity_High ((uint32_t)0x00000000) +#define LPTIM_OutputPolarity_Low ((uint32_t)0x00200000) + +/* LPTIM_UpdateMode */ +#define LPTIM_UpdateMode0 ((uint32_t)0x00000000) +#define LPTIM_UpdateMode1 ((uint32_t)0x00400000) + +/* LPTIM_CountSource */ +#define LPTIM_CountSource_Internal ((uint32_t)0x00000000) +#define LPTIM_CountSource_External ((uint32_t)0x00800000) + +/* LPTIM_InClockSource */ +#define LPTIM_InClockSource_PCLK1 ((uint32_t)0x00000000) +#define LPTIM_InClockSource_HSI ((uint32_t)0x02000000) +#define LPTIM_InClockSource_LSE ((uint32_t)0x04000000) +#define LPTIM_InClockSource_LSI ((uint32_t)0x06000000) + +/* LPTIM_Flag_Definition */ +#define LPTIM_FLAG_DIR_SYNC ((uint32_t)0x00000080) +#define LPTIM_FLAG_DOWN ((uint32_t)0x00000040) +#define LPTIM_FLAG_UP ((uint32_t)0x00000020) +#define LPTIM_FLAG_ARROK ((uint32_t)0x00000010) +#define LPTIM_FLAG_CMPOK ((uint32_t)0x00000008) +#define LPTIM_FLAG_EXTTRIG ((uint32_t)0x00000004) +#define LPTIM_FLAG_ARRM ((uint32_t)0x00000002) +#define LPTIM_FLAG_CMPM ((uint32_t)0x00000001) + +/* LPTIM_Interrupts_Definition */ +#define LPTIM_IT_DOWN ((uint32_t)0x00000040) +#define LPTIM_IT_UP ((uint32_t)0x00000020) +#define LPTIM_IT_ARROK ((uint32_t)0x00000010) +#define LPTIM_IT_CMPOK ((uint32_t)0x00000008) +#define LPTIM_IT_EXTTRIG ((uint32_t)0x00000004) +#define LPTIM_IT_ARRM ((uint32_t)0x00000002) +#define LPTIM_IT_CMPM ((uint32_t)0x00000001) + + +#define LPYIM_OutputPolarity_High LPTIM_OutputPolarity_High +#define LPYIM_OutputPolarity_Low LPTIM_OutputPolarity_Low +#define LPYIM_UpdateMode0 LPTIM_UpdateMode0 +#define LPYIM_UpdateMode1 LPTIM_UpdateMode1 + + +void LPTIM_DeInit(void); +void LPTIM_TimeBaseInit(LPTIM_TimeBaseInitTypeDef* LPTIM_TimeBaseInitStruct); +void LPTIM_TimeBaseStructInit(LPTIM_TimeBaseInitTypeDef* LPTIM_TimeBaseInitStruct); +void LPTIM_CounterDirIndicat_Cmd(FunctionalState NewState); +void LPTIM_OutCmd(FunctionalState NewState); +void LPTIM_Cmd(FunctionalState NewState); +uint16_t LPTIM_GetCounter(void); +void LPTIM_SetAutoreload(uint16_t Autoreload); +void LPTIM_SetCompare(uint16_t Compare); +void LPTIM_ITConfig(uint32_t LPTIM_IT, FunctionalState NewState); +FlagStatus LPTIM_GetFlagStatus(uint32_t LPTIM_FLAG); +void LPTIM_ClearFlag(uint32_t LPTIM_FLAG); +ITStatus LPTIM_GetITStatus(uint32_t LPTIM_IT); +void LPTIM_ClearITPendingBit(uint32_t LPTIM_IT); + + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/ZDBMS/BMS_CC/Peripheral/inc/ch32l103_misc.h b/ZDBMS/BMS_CC/Peripheral/inc/ch32l103_misc.h new file mode 100644 index 0000000..15cd9f9 --- /dev/null +++ b/ZDBMS/BMS_CC/Peripheral/inc/ch32l103_misc.h @@ -0,0 +1,72 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32l103_misc.h + * Author : WCH + * Version : V1.0.0 + * Date : 2023/12/26 + * Description : This file contains all the functions prototypes for the + * miscellaneous firmware library functions. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#ifndef __CH32L103_MISC_H +#define __CH32L103_MISC_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "ch32l103.h" + +/* CSR_INTSYSCR_INEST_definition */ +#define INTSYSCR_INEST_NoEN 0x00 /* interrupt nesting disable(CSR-0x804 bit1 = 0) */ +#define INTSYSCR_INEST_EN 0x01 /* interrupt nesting enable(CSR-0x804 bit1 = 1) */ + +/* Check the configuration of CSR(0x804) in the startup file(.S) + * interrupt nesting enable(CSR-0x804 bit1 = 1) + * priority - bit[7] - Preemption Priority + * bit[6:5] - Sub priority + * bit[4:0] - Reserve + * interrupt nesting disable(CSR-0x804 bit1 = 0) + * priority - bit[7:5] - Sub priority + * bit[4:0] - Reserve + */ + +#ifndef INTSYSCR_INEST +#define INTSYSCR_INEST INTSYSCR_INEST_EN +#endif + +/* NVIC Init Structure definition + * interrupt nesting enable(CSR-0x804 bit1 = 1) + * NVIC_IRQChannelPreemptionPriority - range from 0 to 1. + * NVIC_IRQChannelSubPriority - range from 0 to 3. + * + * interrupt nesting disable(CSR-0x804 bit1 = 0) + * NVIC_IRQChannelPreemptionPriority - range is 0. + * NVIC_IRQChannelSubPriority - range from 0 to 7. + * + */ +typedef struct +{ + uint8_t NVIC_IRQChannel; + uint8_t NVIC_IRQChannelPreemptionPriority; + uint8_t NVIC_IRQChannelSubPriority; + FunctionalState NVIC_IRQChannelCmd; +} NVIC_InitTypeDef; + +/* Preemption_Priority_Group */ +#if (INTSYSCR_INEST == INTSYSCR_INEST_NoEN) +#define NVIC_PriorityGroup_0 ((uint32_t)0x00) /* interrupt nesting disable(CSR-0x804 bit1 = 0) */ +#else +#define NVIC_PriorityGroup_1 ((uint32_t)0x01) /* interrupt nesting enable(CSR-0x804 bit1 = 1) */ +#endif + +void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup); +void NVIC_Init(NVIC_InitTypeDef *NVIC_InitStruct); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/ZDBMS/BMS_CC/Peripheral/inc/ch32l103_opa.h b/ZDBMS/BMS_CC/Peripheral/inc/ch32l103_opa.h new file mode 100644 index 0000000..93a5901 --- /dev/null +++ b/ZDBMS/BMS_CC/Peripheral/inc/ch32l103_opa.h @@ -0,0 +1,243 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32l103_opa.h + * Author : WCH + * Version : V1.0.0 + * Date : 2024/11/05 + * Description : This file contains all the functions prototypes for the + * OPA firmware library. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#ifndef __CH32L103_OPA_H +#define __CH32L103_OPA_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "ch32l103.h" + +/* OPA_member_enumeration */ +typedef enum +{ + OPA1 = 0, +} OPA_Num_TypeDef; + +/* OPA_out_channel_enumeration */ +typedef enum +{ + OUT_IO_OUT0 = 0, /* PA3 */ + OUT_IO_OUT1, /* PB1 */ + OUT_IO_OUT2, /* PA2 */ + OUT_IO_OUT3, /* PA4 */ + OUT_IO_OUT4, /* PB0 */ + OUT_IO_OFF +} OPA_Mode_TypeDef; + +/* OPA_PSEL_enumeration */ +typedef enum +{ + CHP0 = 0, /* PB15 */ + CHP1, /* PB0 */ + CHP2, /* PB14 */ + CHP3, /* PA7 */ + CHP4, /* PA0 */ + CHP5, /* PA6 */ + CHP_OFF +} OPA_PSEL_TypeDef; + +/* OPA_FB_enumeration */ +typedef enum +{ + FB_OFF = 0, + FB_ON +} OPA_FB_TypeDef; + +/* OPA_NSEL_enumeration */ +typedef enum +{ + CHN0 = 0, /* PB11 */ + CHN1, /* PA6 */ + CHN2, /* PB10 */ + CHN3, /* PA5 */ + CHN4, /* PA1 */ + CHN5, /* PA7 */ + CHN2_PGA_32xIN, /* PB10 */ + CHN_PGA_8xIN, + CHN_PGA_16xIN, + CHN_PGA_32xIN, + CHN_PGA_64xIN, + CHN_OFF = 0xF +} OPA_NSEL_TypeDef; + +/* OPA_PSEL_POLL_enumeration */ +typedef enum +{ + CHP_OPA1_OFF = 0, + CHP_OPA1_ON, +} OPA_PSEL_POLL_TypeDef; + +/* OPA_BKIN_EN_enumeration */ +typedef enum +{ + BKIN_OPA1_OFF = 0, /* TIM1 braking signal source form IO input */ + BKIN_OPA1_ON, /* TIM1 braking signal source form OPA output */ +} OPA_BKIN_EN_TypeDef; + +/* OPA_RST_EN_enumeration */ +typedef enum +{ + RST_OPA1_OFF = 0, + RST_OPA1_ON, +} OPA_RST_EN_TypeDef; + +/* OPA_OUT_IE_enumeration */ +typedef enum +{ + OUT_IE_OPA1_OFF = 0, + OUT_IE_OPA1_ON, +} OPA_OUT_IE_TypeDef; + +/* OPA_CNT_IE_enumeration */ +typedef enum +{ + CNT_IE_OFF = 0, + CNT_IE_ON, +} OPA_CNT_IE_TypeDef; + +/* OPA_NMI_IE_enumeration */ +typedef enum +{ + NMI_IE_OFF = 0, + NMI_IE_ON, +} OPA_NMI_IE_TypeDef; + +/* OPA_PSEL_POLL_NUM_enumeration */ +typedef enum +{ + CHP_POLL_NUM_1 = 0, + CHP_POLL_NUM_2, + CHP_POLL_NUM_3, + CHP_POLL_NUM_4, + CHP_POLL_NUM_5, + CHP_POLL_NUM_6 +} OPA_PSEL_POLL_NUM_TypeDef; + +/* Offset_voltage_adjustment_value_polarity */ +typedef enum +{ + OPA_Vos_Ads_N = 0, + OPA_Vos_Ads_P +} OPA_Vos_ADS_POLARITY_TypeDef; + +/* OPA Init Structure definition */ +typedef struct +{ + uint16_t OPA_POLL_Interval; /* OPA polling interval = (OPA_POLL_Interval+1)*1us + This parameter must range from 0 to 0x1FF.*/ + OPA_Num_TypeDef OPA_NUM; /* Specifies the members of OPA */ + OPA_Mode_TypeDef Mode; /* Specifies the mode of OPA */ + OPA_PSEL_TypeDef PSEL; /* Specifies the positive channel of OPA */ + OPA_FB_TypeDef FB; /* Specifies the internal feedback resistor of OPA */ + OPA_NSEL_TypeDef NSEL; /* Specifies the negative channel of OPA */ + OPA_PSEL_POLL_TypeDef PSEL_POLL; /* Specifies the positive channel poll of OPA */ + OPA_BKIN_EN_TypeDef BKIN_EN; /* Specifies the brake input source of OPA */ + OPA_RST_EN_TypeDef RST_EN; /* Specifies the reset source of OPA */ + OPA_OUT_IE_TypeDef OUT_IE; /* Specifies the out interrupt of OPA */ + OPA_CNT_IE_TypeDef CNT_IE; /* Specifies the out interrupt rising edge of sampling data */ + OPA_NMI_IE_TypeDef NMI_IE; /* Specifies the out NIM interrupt of OPA */ + OPA_PSEL_POLL_NUM_TypeDef POLL_NUM; /* Specifies the number of forward inputs*/ +} OPA_InitTypeDef; + +/* CMP_member_enumeration */ +typedef enum +{ + CMP1 = 0, + CMP2, + CMP3 +} CMP_Num_TypeDef; + +/* CMP_out_channel_enumeration */ +typedef enum +{ + OUT_IO0 = 0, + OUT_IO1, + OUT_IO_TIM2 +} CMP_Mode_TypeDef; + +/* CMP_NSEL_enumeration */ +typedef enum +{ + CMP_CHN0 = 0, + CMP_CHN1, +} CMP_NSEL_TypeDef; + +/* CMP_PSEL_enumeration */ +typedef enum +{ + CMP_CHP_0 = 0, + CMP_CHP_1, +} CMP_PSEL_TypeDef; + +#define CMP_CHP1 CMP_CHP_0 +#define CMP_CHP2 CMP_CHP_1 + +/* CMP_HYEN_enumeration */ +typedef enum +{ + CMP_HYEN0 = 0, + CMP_HYEN1, +} CMP_HYEN_TypeDef; + +/* CMP Init Structure definition */ +typedef struct +{ + CMP_Num_TypeDef CMP_NUM; /* Specifies the members of CMP */ + CMP_Mode_TypeDef Mode; /* Specifies the mode of CMP */ + CMP_NSEL_TypeDef NSEL; /* Specifies the negative channel of CMP */ + CMP_PSEL_TypeDef PSEL; /* Specifies the positive channel of CMP */ + CMP_HYEN_TypeDef HYEN; /* Specifies the hysteresis comparator of CMP */ +} CMP_InitTypeDef; + +/* Current channel for OPA polling enumeration */ +typedef enum +{ + O1P0 = 0, + O1P1, + O1P2, + O1P3, + O1P4, + O1P5, +} OPA_POLL_NUM_TypeDef; + +/* OPA_flags_definition */ +#define OPA_FLAG_OUT_OPA1 ((uint16_t)0x1000) +#define OPA_FLAG_OUT_CNT ((uint16_t)0x4000) + +/* CMP_WakeUp_IO_mode_definition */ +#define CMP_WakeUp_Rising_Falling ((uint32_t)0x01000000) +#define CMP_WakeUp_Rising ((uint32_t)0x02000000) +#define CMP_WakeUp_Falling ((uint32_t)0x03000000) + +void OPCM_Unlock(void); +void OPCM_Lock(void); +void OPA_Init(OPA_InitTypeDef *OPA_InitStruct); +void OPA_StructInit(OPA_InitTypeDef *OPA_InitStruct); +void OPA_Cmd(OPA_Num_TypeDef OPA_NUM, FunctionalState NewState); +void OPA_LP_Cmd(FunctionalState NewState); +void OPA_CMP_Init(CMP_InitTypeDef *CMP_InitStruct); +void OPA_CMP_StructInit(CMP_InitTypeDef *CMP_InitStruct); +void OPA_CMP_Cmd(CMP_Num_TypeDef CMP_NUM, FunctionalState NewState); +void OPA_CMP_LP_Cmd(CMP_Num_TypeDef CMP_NUM, FunctionalState NewState); +void OPA_CMP_WakeUp_ModeConfig(uint32_t CMP_WakeUP_Mode); +FlagStatus OPA_GetFlagStatus( uint16_t OPA_FLAG); +void OPA_ClearFlag(uint16_t OPA_FLAG); +OPA_POLL_NUM_TypeDef OPA_POLL_CNT(void); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/ZDBMS/BMS_CC/Peripheral/inc/ch32l103_pwr.h b/ZDBMS/BMS_CC/Peripheral/inc/ch32l103_pwr.h new file mode 100644 index 0000000..2607430 --- /dev/null +++ b/ZDBMS/BMS_CC/Peripheral/inc/ch32l103_pwr.h @@ -0,0 +1,68 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32l103_pwr.h + * Author : WCH + * Version : V1.0.0 + * Date : 2023/07/08 + * Description : This file contains all the functions prototypes for the PWR + * firmware library. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#ifndef __CH32L103_PWR_H +#define __CH32L103_PWR_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "ch32l103.h" + +/* PVD_detection_level */ +#define PWR_PVDLevel_0 ((uint32_t)0x00000000) +#define PWR_PVDLevel_1 ((uint32_t)0x00000020) +#define PWR_PVDLevel_2 ((uint32_t)0x00000040) +#define PWR_PVDLevel_3 ((uint32_t)0x00000060) +#define PWR_PVDLevel_4 ((uint32_t)0x00000080) +#define PWR_PVDLevel_5 ((uint32_t)0x000000A0) +#define PWR_PVDLevel_6 ((uint32_t)0x000000C0) +#define PWR_PVDLevel_7 ((uint32_t)0x000000E0) + +/* Regulator_state_is_STOP_mode */ +#define PWR_Regulator_ON ((uint32_t)0x00000000) +#define PWR_Regulator_LowPower ((uint32_t)0x00000001) + +/* STOP_mode_entry */ +#define PWR_STOPEntry_WFI ((uint8_t)0x01) +#define PWR_STOPEntry_WFE ((uint8_t)0x02) + +/* PWR_Flag */ +#define PWR_FLAG_WU ((uint32_t)0x00000001) +#define PWR_FLAG_SB ((uint32_t)0x00000002) +#define PWR_FLAG_PVDO ((uint32_t)0x00000004) + +void PWR_DeInit(void); +void PWR_BackupAccessCmd(FunctionalState NewState); +void PWR_PVDCmd(FunctionalState NewState); +void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel); +void PWR_WakeUpPinCmd(FunctionalState NewState); +void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry); +void PWR_EnterSTANDBYMode(void); +FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG); +void PWR_ClearFlag(uint32_t PWR_FLAG); +void PWR_EnterSTANDBYMode_RAM(void); +void PWR_EnterSTANDBYMode_RAM_LV(void); +void PWR_EnterSTANDBYMode_RAM_VBAT_EN(void); +void PWR_EnterSTANDBYMode_RAM_LV_VBAT_EN(void); +void PWR_EnterSTOPMode_RAM_LV(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry); +void PWR_LDO_LP_Cmd(FunctionalState NewState); +void PWR_STOPMode_Auto_LDO_LP_Cmd(FunctionalState NewState); +void PWR_FLASH_LP_Cmd(FunctionalState NewState); + + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/ZDBMS/BMS_CC/Peripheral/inc/ch32l103_rcc.h b/ZDBMS/BMS_CC/Peripheral/inc/ch32l103_rcc.h new file mode 100644 index 0000000..150e4f5 --- /dev/null +++ b/ZDBMS/BMS_CC/Peripheral/inc/ch32l103_rcc.h @@ -0,0 +1,220 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32l103_rcc.h + * Author : WCH + * Version : V1.0.0 + * Date : 2023/07/08 + * Description : This file provides all the RCC firmware functions. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#ifndef __CH32L103_RCC_H +#define __CH32L103_RCC_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "ch32l103.h" + +/* RCC_Exported_Types */ +typedef struct +{ + uint32_t SYSCLK_Frequency; /* returns SYSCLK clock frequency expressed in Hz */ + uint32_t HCLK_Frequency; /* returns HCLK clock frequency expressed in Hz */ + uint32_t PCLK1_Frequency; /* returns PCLK1 clock frequency expressed in Hz */ + uint32_t PCLK2_Frequency; /* returns PCLK2 clock frequency expressed in Hz */ + uint32_t ADCCLK_Frequency; /* returns ADCCLK clock frequency expressed in Hz */ +} RCC_ClocksTypeDef; + +/* HSE_configuration */ +#define RCC_HSE_OFF ((uint32_t)0x00000000) +#define RCC_HSE_ON ((uint32_t)0x00010000) +#define RCC_HSE_Bypass ((uint32_t)0x00040000) + +/* PLL_entry_clock_source */ +#define RCC_PLLSource_HSI_Div2 ((uint32_t)0x00000000) +#define RCC_PLLSource_HSE_Div1 ((uint32_t)0x00010000) +#define RCC_PLLSource_HSE_Div2 ((uint32_t)0x00030000) + +/* PLL_multiplication_factor for other CH32L103 */ +#define RCC_PLLMul_2 ((uint32_t)0x00000000) +#define RCC_PLLMul_3 ((uint32_t)0x00040000) +#define RCC_PLLMul_4 ((uint32_t)0x00080000) +#define RCC_PLLMul_5 ((uint32_t)0x000C0000) +#define RCC_PLLMul_6 ((uint32_t)0x00100000) +#define RCC_PLLMul_7 ((uint32_t)0x00140000) +#define RCC_PLLMul_8 ((uint32_t)0x00180000) +#define RCC_PLLMul_9 ((uint32_t)0x001C0000) +#define RCC_PLLMul_10 ((uint32_t)0x00200000) +#define RCC_PLLMul_11 ((uint32_t)0x00240000) +#define RCC_PLLMul_12 ((uint32_t)0x00280000) +#define RCC_PLLMul_13 ((uint32_t)0x002C0000) +#define RCC_PLLMul_14 ((uint32_t)0x00300000) +#define RCC_PLLMul_15 ((uint32_t)0x00340000) +#define RCC_PLLMul_16 ((uint32_t)0x00380000) +#define RCC_PLLMul_18 ((uint32_t)0x003C0000) + +/* System_clock_source */ +#define RCC_SYSCLKSource_HSI ((uint32_t)0x00000000) +#define RCC_SYSCLKSource_HSE ((uint32_t)0x00000001) +#define RCC_SYSCLKSource_PLLCLK ((uint32_t)0x00000002) + +/* HB_clock_source */ +#define RCC_SYSCLK_Div1 ((uint32_t)0x00000000) +#define RCC_SYSCLK_Div2 ((uint32_t)0x00000080) +#define RCC_SYSCLK_Div4 ((uint32_t)0x00000090) +#define RCC_SYSCLK_Div8 ((uint32_t)0x000000A0) +#define RCC_SYSCLK_Div16 ((uint32_t)0x000000B0) +#define RCC_SYSCLK_Div64 ((uint32_t)0x000000C0) +#define RCC_SYSCLK_Div128 ((uint32_t)0x000000D0) +#define RCC_SYSCLK_Div256 ((uint32_t)0x000000E0) +#define RCC_SYSCLK_Div512 ((uint32_t)0x000000F0) + +/* PB1_PB2_clock_source */ +#define RCC_HCLK_Div1 ((uint32_t)0x00000000) +#define RCC_HCLK_Div2 ((uint32_t)0x00000400) +#define RCC_HCLK_Div4 ((uint32_t)0x00000500) +#define RCC_HCLK_Div8 ((uint32_t)0x00000600) +#define RCC_HCLK_Div16 ((uint32_t)0x00000700) + +/* RCC_Interrupt_source */ +#define RCC_IT_LSIRDY ((uint8_t)0x01) +#define RCC_IT_LSERDY ((uint8_t)0x02) +#define RCC_IT_HSIRDY ((uint8_t)0x04) +#define RCC_IT_HSERDY ((uint8_t)0x08) +#define RCC_IT_PLLRDY ((uint8_t)0x10) +#define RCC_IT_CSS ((uint8_t)0x80) + +/* USB_Device_clock_source */ +#define RCC_USBCLKSource_PLLCLK_Div1 ((uint32_t)0x00000000) +#define RCC_USBCLKSource_PLLCLK_Div2 ((uint32_t)0x00400000) +#define RCC_USBCLKSource_PLLCLK_Div1_5 ((uint32_t)0x00800000) + +/* ADC_clock_source */ +#define RCC_PCLK2_Div2 ((uint32_t)0x00000000) +#define RCC_PCLK2_Div4 ((uint32_t)0x00004000) +#define RCC_PCLK2_Div6 ((uint32_t)0x00008000) +#define RCC_PCLK2_Div8 ((uint32_t)0x0000C000) +#define RCC_HCLK_ADC ((uint32_t)0x80000000) + +/* LSE_configuration */ +#define RCC_LSE_OFF ((uint8_t)0x00) +#define RCC_LSE_ON ((uint8_t)0x01) +#define RCC_LSE_Bypass ((uint8_t)0x04) + +/* RTC_clock_source */ +#define RCC_RTCCLKSource_LSE ((uint32_t)0x00000100) +#define RCC_RTCCLKSource_LSI ((uint32_t)0x00000200) +#define RCC_RTCCLKSource_HSE_Div128 ((uint32_t)0x00000300) + +/* HB_peripheral */ +#define RCC_HBPeriph_DMA1 ((uint32_t)0x00000001) +#define RCC_HBPeriph_SRAM ((uint32_t)0x00000004) +#define RCC_HBPeriph_CRC ((uint32_t)0x00000040) +#define RCC_HBPeriph_USBFS ((uint32_t)0x00001000) +#define RCC_HBPeriph_USBPD ((uint32_t)0x00020000) + +/* PB2_peripheral */ +#define RCC_PB2Periph_AFIO ((uint32_t)0x00000001) +#define RCC_PB2Periph_GPIOA ((uint32_t)0x00000004) +#define RCC_PB2Periph_GPIOB ((uint32_t)0x00000008) +#define RCC_PB2Periph_GPIOC ((uint32_t)0x00000010) +#define RCC_PB2Periph_GPIOD ((uint32_t)0x00000020) +#define RCC_PB2Periph_ADC1 ((uint32_t)0x00000200) +#define RCC_PB2Periph_TIM1 ((uint32_t)0x00000800) +#define RCC_PB2Periph_SPI1 ((uint32_t)0x00001000) +#define RCC_PB2Periph_USART1 ((uint32_t)0x00004000) + +/* PB1_peripheral */ +#define RCC_PB1Periph_TIM2 ((uint32_t)0x00000001) +#define RCC_PB1Periph_TIM3 ((uint32_t)0x00000002) +#define RCC_PB1Periph_TIM4 ((uint32_t)0x00000004) +#define RCC_PB1Periph_WWDG ((uint32_t)0x00000800) +#define RCC_PB1Periph_SPI2 ((uint32_t)0x00004000) +#define RCC_PB1Periph_USART2 ((uint32_t)0x00020000) +#define RCC_PB1Periph_USART3 ((uint32_t)0x00040000) +#define RCC_PB1Periph_USART4 ((uint32_t)0x00080000) +#define RCC_PB1Periph_I2C1 ((uint32_t)0x00200000) +#define RCC_PB1Periph_I2C2 ((uint32_t)0x00400000) +#define RCC_PB1Periph_CAN1 ((uint32_t)0x02000000) +#define RCC_PB1Periph_BKP ((uint32_t)0x08000000) +#define RCC_PB1Periph_PWR ((uint32_t)0x10000000) +#define RCC_PB1Periph_LPTIM ((uint32_t)0x80000000) + +/* Clock_source_to_output_on_MCO_pin */ +#define RCC_MCO_NoClock ((uint8_t)0x00) +#define RCC_MCO_SYSCLK ((uint8_t)0x04) +#define RCC_MCO_HSI ((uint8_t)0x05) +#define RCC_MCO_HSE ((uint8_t)0x06) +#define RCC_MCO_PLLCLK_Div2 ((uint8_t)0x07) + +/* RCC_Flag */ +#define RCC_FLAG_HSIRDY ((uint8_t)0x21) +#define RCC_FLAG_HSERDY ((uint8_t)0x31) +#define RCC_FLAG_PLLRDY ((uint8_t)0x39) +#define RCC_FLAG_LSERDY ((uint8_t)0x41) +#define RCC_FLAG_LSIRDY ((uint8_t)0x61) +#define RCC_FLAG_PINRST ((uint8_t)0x7A) +#define RCC_FLAG_PORRST ((uint8_t)0x7B) +#define RCC_FLAG_SFTRST ((uint8_t)0x7C) +#define RCC_FLAG_IWDGRST ((uint8_t)0x7D) +#define RCC_FLAG_WWDGRST ((uint8_t)0x7E) +#define RCC_FLAG_LPWRRST ((uint8_t)0x7F) + +/* SysTick_clock_source */ +#define SysTick_CLKSource_HCLK_Div8 ((uint32_t)0xFFFFFFFB) +#define SysTick_CLKSource_HCLK ((uint32_t)0x00000004) + +/* ADC_clock_H_Level_Duty_Cycle */ +#define RCC_ADC_H_Level_Mode0 ((uint32_t)0x00000000) +#define RCC_ADC_H_Level_Mode1 ((uint32_t)0x10000000) +#define RCC_ADC_H_Level_Mode2 ((uint32_t)0x20000000) +#define RCC_ADC_H_Level_Mode3 ((uint32_t)0x30000000) +#define RCC_ADC_H_Level_Mode4 ((uint32_t)0x40000000) +#define RCC_ADC_H_Level_Mode5 ((uint32_t)0x50000000) +#define RCC_ADC_H_Level_Mode6 ((uint32_t)0x60000000) +#define RCC_ADC_H_Level_Mode7 ((uint32_t)0x70000000) + +void RCC_DeInit(void); +void RCC_HSEConfig(uint32_t RCC_HSE); +ErrorStatus RCC_WaitForHSEStartUp(void); +void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue); +void RCC_HSICmd(FunctionalState NewState); +void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t RCC_PLLMul); +void RCC_PLLCmd(FunctionalState NewState); +void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource); +uint8_t RCC_GetSYSCLKSource(void); +void RCC_HCLKConfig(uint32_t RCC_SYSCLK); +void RCC_PCLK1Config(uint32_t RCC_HCLK); +void RCC_PCLK2Config(uint32_t RCC_HCLK); +void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState); +void RCC_USBCLKConfig(uint32_t RCC_USBCLKSource); +void RCC_ADCCLKConfig(uint32_t RCC_PCLK2); +void RCC_LSEConfig(uint8_t RCC_LSE); +void RCC_LSICmd(FunctionalState NewState); +void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource); +void RCC_RTCCLKCmd(FunctionalState NewState); +void RCC_GetClocksFreq(RCC_ClocksTypeDef *RCC_Clocks); +void RCC_HBPeriphClockCmd(uint32_t RCC_HBPeriph, FunctionalState NewState); +void RCC_PB2PeriphClockCmd(uint32_t RCC_PB2Periph, FunctionalState NewState); +void RCC_PB1PeriphClockCmd(uint32_t RCC_PB1Periph, FunctionalState NewState); +void RCC_PB2PeriphResetCmd(uint32_t RCC_PB2Periph, FunctionalState NewState); +void RCC_PB1PeriphResetCmd(uint32_t RCC_PB1Periph, FunctionalState NewState); +void RCC_BackupResetCmd(FunctionalState NewState); +void RCC_ClockSecuritySystemCmd(FunctionalState NewState); +void RCC_MCOConfig(uint8_t RCC_MCO); +FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG); +void RCC_ClearFlag(void); +ITStatus RCC_GetITStatus(uint8_t RCC_IT); +void RCC_ClearITPendingBit(uint8_t RCC_IT); +void RCC_ADCCLKDutyCycleConfig(uint32_t RCC_DutyCycle); +void RCC_HSE_LP_Cmd(FunctionalState NewState); +void RCC_HSI_LP_Cmd(FunctionalState NewState); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/ZDBMS/BMS_CC/Peripheral/inc/ch32l103_rtc.h b/ZDBMS/BMS_CC/Peripheral/inc/ch32l103_rtc.h new file mode 100644 index 0000000..77ae7a0 --- /dev/null +++ b/ZDBMS/BMS_CC/Peripheral/inc/ch32l103_rtc.h @@ -0,0 +1,55 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32l103_rtc.h + * Author : WCH + * Version : V1.0.0 + * Date : 2023/07/08 + * Description : This file contains all the functions prototypes for the RTC + * firmware library. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#ifndef __CH32L103_RTC_H +#define __CH32L103_RTC_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "ch32l103.h" + + +/* RTC_interrupts_define */ +#define RTC_IT_OW ((uint16_t)0x0004) /* Overflow interrupt */ +#define RTC_IT_ALR ((uint16_t)0x0002) /* Alarm interrupt */ +#define RTC_IT_SEC ((uint16_t)0x0001) /* Second interrupt */ + +/* RTC_interrupts_flags */ +#define RTC_FLAG_RTOFF ((uint16_t)0x0020) /* RTC Operation OFF flag */ +#define RTC_FLAG_RSF ((uint16_t)0x0008) /* Registers Synchronized flag */ +#define RTC_FLAG_OW ((uint16_t)0x0004) /* Overflow flag */ +#define RTC_FLAG_ALR ((uint16_t)0x0002) /* Alarm flag */ +#define RTC_FLAG_SEC ((uint16_t)0x0001) /* Second flag */ + + +void RTC_ITConfig(uint16_t RTC_IT, FunctionalState NewState); +void RTC_EnterConfigMode(void); +void RTC_ExitConfigMode(void); +uint32_t RTC_GetCounter(void); +void RTC_SetCounter(uint32_t CounterValue); +void RTC_SetPrescaler(uint32_t PrescalerValue); +void RTC_SetAlarm(uint32_t AlarmValue); +uint32_t RTC_GetDivider(void); +void RTC_WaitForLastTask(void); +void RTC_WaitForSynchro(void); +FlagStatus RTC_GetFlagStatus(uint16_t RTC_FLAG); +void RTC_ClearFlag(uint16_t RTC_FLAG); +ITStatus RTC_GetITStatus(uint16_t RTC_IT); +void RTC_ClearITPendingBit(uint16_t RTC_IT); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/ZDBMS/BMS_CC/Peripheral/inc/ch32l103_spi.h b/ZDBMS/BMS_CC/Peripheral/inc/ch32l103_spi.h new file mode 100644 index 0000000..d1189a9 --- /dev/null +++ b/ZDBMS/BMS_CC/Peripheral/inc/ch32l103_spi.h @@ -0,0 +1,158 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32l103_spi.h + * Author : WCH + * Version : V1.0.0 + * Date : 2024/06/05 + * Description : This file contains all the functions prototypes for the + * SPI firmware library. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#ifndef __CH32L103_SPI_H +#define __CH32L103_SPI_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "ch32l103.h" + +/* SPI Init structure definition */ +typedef struct +{ + uint16_t SPI_Direction; /* Specifies the SPI unidirectional or bidirectional data mode. + This parameter can be a value of @ref SPI_data_direction */ + + uint16_t SPI_Mode; /* Specifies the SPI operating mode. + This parameter can be a value of @ref SPI_mode */ + + uint16_t SPI_DataSize; /* Specifies the SPI data size. + This parameter can be a value of @ref SPI_data_size */ + + uint16_t SPI_CPOL; /* Specifies the serial clock steady state. + This parameter can be a value of @ref SPI_Clock_Polarity + When using SPI slave mode to send data, the CPOL bit should be set to 1 */ + + uint16_t SPI_CPHA; /* Specifies the clock active edge for the bit capture. + This parameter can be a value of @ref SPI_Clock_Phase */ + + uint16_t SPI_NSS; /* Specifies whether the NSS signal is managed by + hardware (NSS pin) or by software using the SSI bit. + This parameter can be a value of @ref SPI_Slave_Select_management */ + + uint16_t SPI_BaudRatePrescaler; /* Specifies the Baud Rate prescaler value which will be + used to configure the transmit and receive SCK clock. + This parameter can be a value of @ref SPI_BaudRate_Prescaler. + @note The communication clock is derived from the master + clock. The slave clock does not need to be set. */ + + uint16_t SPI_FirstBit; /* Specifies whether data transfers start from MSB or LSB bit. + This parameter can be a value of @ref SPI_MSB_LSB_transmission */ + + uint16_t SPI_CRCPolynomial; /* Specifies the polynomial used for the CRC calculation. */ +} SPI_InitTypeDef; + +/* SPI_data_direction */ +#define SPI_Direction_2Lines_FullDuplex ((uint16_t)0x0000) +#define SPI_Direction_2Lines_RxOnly ((uint16_t)0x0400) +#define SPI_Direction_1Line_Rx ((uint16_t)0x8000) +#define SPI_Direction_1Line_Tx ((uint16_t)0xC000) + +/* SPI_mode */ +#define SPI_Mode_Master ((uint16_t)0x0104) +#define SPI_Mode_Slave ((uint16_t)0x0000) + +/* SPI_data_size */ +#define SPI_DataSize_16b ((uint16_t)0x0800) +#define SPI_DataSize_8b ((uint16_t)0x0000) + +/* SPI_Clock_Polarity */ +#define SPI_CPOL_Low ((uint16_t)0x0000) +#define SPI_CPOL_High ((uint16_t)0x0002)//When using SPI slave mode to send data, the CPOL bit should be set to 1. + +/* SPI_Clock_Phase */ +#define SPI_CPHA_1Edge ((uint16_t)0x0000) +#define SPI_CPHA_2Edge ((uint16_t)0x0001) + +/* SPI_Slave_Select_management */ +#define SPI_NSS_Soft ((uint16_t)0x0200) +#define SPI_NSS_Hard ((uint16_t)0x0000) + +/* SPI_BaudRate_Prescaler */ +#define SPI_BaudRatePrescaler_2 ((uint16_t)0x0000) +#define SPI_BaudRatePrescaler_4 ((uint16_t)0x0008) +#define SPI_BaudRatePrescaler_8 ((uint16_t)0x0010) +#define SPI_BaudRatePrescaler_16 ((uint16_t)0x0018) +#define SPI_BaudRatePrescaler_32 ((uint16_t)0x0020) +#define SPI_BaudRatePrescaler_64 ((uint16_t)0x0028) +#define SPI_BaudRatePrescaler_128 ((uint16_t)0x0030) +#define SPI_BaudRatePrescaler_256 ((uint16_t)0x0038) + +/* SPI_MSB_LSB_transmission */ +#define SPI_FirstBit_MSB ((uint16_t)0x0000) +#define SPI_FirstBit_LSB ((uint16_t)0x0080) + +/* SPI_DMA_transfer_requests */ +#define SPI_I2S_DMAReq_Tx ((uint16_t)0x0002) +#define SPI_I2S_DMAReq_Rx ((uint16_t)0x0001) + +/* SPI_NSS_internal_software_management */ +#define SPI_NSSInternalSoft_Set ((uint16_t)0x0100) +#define SPI_NSSInternalSoft_Reset ((uint16_t)0xFEFF) + +/* SPI_CRC_Transmit_Receive */ +#define SPI_CRC_Tx ((uint8_t)0x00) +#define SPI_CRC_Rx ((uint8_t)0x01) + +/* SPI_direction_transmit_receive */ +#define SPI_Direction_Rx ((uint16_t)0xBFFF) +#define SPI_Direction_Tx ((uint16_t)0x4000) + +/* SPI_interrupts_definition */ +#define SPI_I2S_IT_TXE ((uint8_t)0x71) +#define SPI_I2S_IT_RXNE ((uint8_t)0x60) +#define SPI_I2S_IT_ERR ((uint8_t)0x50) +#define SPI_I2S_IT_OVR ((uint8_t)0x56) +#define SPI_IT_MODF ((uint8_t)0x55) +#define SPI_IT_CRCERR ((uint8_t)0x54) + +/* SPI_flags_definition */ +#define SPI_I2S_FLAG_RXNE ((uint16_t)0x0001) +#define SPI_I2S_FLAG_TXE ((uint16_t)0x0002) +#define SPI_FLAG_CRCERR ((uint16_t)0x0010) +#define SPI_FLAG_MODF ((uint16_t)0x0020) +#define SPI_I2S_FLAG_OVR ((uint16_t)0x0040) +#define SPI_I2S_FLAG_BSY ((uint16_t)0x0080) + + + +void SPI_I2S_DeInit(SPI_TypeDef *SPIx); +void SPI_Init(SPI_TypeDef *SPIx, SPI_InitTypeDef *SPI_InitStruct); +void SPI_StructInit(SPI_InitTypeDef *SPI_InitStruct); +void SPI_Cmd(SPI_TypeDef *SPIx, FunctionalState NewState); +void I2S_Cmd(SPI_TypeDef *SPIx, FunctionalState NewState); +void SPI_I2S_ITConfig(SPI_TypeDef *SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState); +void SPI_I2S_DMACmd(SPI_TypeDef *SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState); +void SPI_I2S_SendData(SPI_TypeDef *SPIx, uint16_t Data); +uint16_t SPI_I2S_ReceiveData(SPI_TypeDef *SPIx); +void SPI_NSSInternalSoftwareConfig(SPI_TypeDef *SPIx, uint16_t SPI_NSSInternalSoft); +void SPI_SSOutputCmd(SPI_TypeDef *SPIx, FunctionalState NewState); +void SPI_DataSizeConfig(SPI_TypeDef *SPIx, uint16_t SPI_DataSize); +void SPI_TransmitCRC(SPI_TypeDef *SPIx); +void SPI_CalculateCRC(SPI_TypeDef *SPIx, FunctionalState NewState); +uint16_t SPI_GetCRC(SPI_TypeDef *SPIx, uint8_t SPI_CRC); +uint16_t SPI_GetCRCPolynomial(SPI_TypeDef *SPIx); +void SPI_BiDirectionalLineConfig(SPI_TypeDef *SPIx, uint16_t SPI_Direction); +FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef *SPIx, uint16_t SPI_I2S_FLAG); +void SPI_I2S_ClearFlag(SPI_TypeDef *SPIx, uint16_t SPI_I2S_FLAG); +ITStatus SPI_I2S_GetITStatus(SPI_TypeDef *SPIx, uint8_t SPI_I2S_IT); +void SPI_I2S_ClearITPendingBit(SPI_TypeDef *SPIx, uint8_t SPI_I2S_IT); +void SPI_HighSpeedRead_Cmd(SPI_TypeDef *SPIx, FunctionalState NewState); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/ZDBMS/BMS_CC/Peripheral/inc/ch32l103_tim.h b/ZDBMS/BMS_CC/Peripheral/inc/ch32l103_tim.h new file mode 100644 index 0000000..9043720 --- /dev/null +++ b/ZDBMS/BMS_CC/Peripheral/inc/ch32l103_tim.h @@ -0,0 +1,517 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32l103_tim.h + * Author : WCH + * Version : V1.0.0 + * Date : 2023/07/08 + * Description : This file contains all the functions prototypes for the + * TIM firmware library. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#ifndef __CH32L103_TIM_H +#define __CH32L103_TIM_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "ch32l103.h" + +/* TIM Time Base Init structure definition */ +typedef struct +{ + uint32_t TIM_Period; /* Specifies the period value to be loaded into the active + Auto-Reload Register at the next update event. + This parameter must be a number between 0x0000 and 0xFFFF for TIM1-TIM2-TIM3. + This parameter must be a number between 0x00000000 and 0xFFFFFFFF for TIM4. */ + + uint16_t TIM_Prescaler; /* Specifies the prescaler value used to divide the TIM clock. + This parameter can be a number between 0x0000 and 0xFFFF */ + + uint16_t TIM_CounterMode; /* Specifies the counter mode. + This parameter can be a value of @ref TIM_Counter_Mode */ + + uint16_t TIM_ClockDivision; /* Specifies the clock division. + This parameter can be a value of @ref TIM_Clock_Division_CKD */ + + uint8_t TIM_RepetitionCounter; /* Specifies the repetition counter value. Each time the RCR downcounter + reaches zero, an update event is generated and counting restarts + from the RCR value (N). + This means in PWM mode that (N+1) corresponds to: + - the number of PWM periods in edge-aligned mode + - the number of half PWM period in center-aligned mode + This parameter must be a number between 0x00 and 0xFF. + @note This parameter is valid only for TIM1 and TIM8. */ +} TIM_TimeBaseInitTypeDef; + +/* TIM Output Compare Init structure definition */ +typedef struct +{ + uint32_t TIM_Pulse; /* Specifies the pulse value to be loaded into the Capture Compare Register. + This parameter can be a number between 0x0000 and 0xFFFF for TIM1-TIM2-TIM3. + This parameter must be a number between 0x00000000 and 0xFFFFFFFF for TIM4. */ + + uint16_t TIM_OCMode; /* Specifies the TIM mode. + This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */ + + uint16_t TIM_OutputState; /* Specifies the TIM Output Compare state. + This parameter can be a value of @ref TIM_Output_Compare_state */ + + uint16_t TIM_OutputNState; /* Specifies the TIM complementary Output Compare state. + This parameter can be a value of @ref TIM_Output_Compare_N_state + @note This parameter is valid only for TIM1 and TIM8. */ + + uint16_t TIM_OCPolarity; /* Specifies the output polarity. + This parameter can be a value of @ref TIM_Output_Compare_Polarity */ + + uint16_t TIM_OCNPolarity; /* Specifies the complementary output polarity. + This parameter can be a value of @ref TIM_Output_Compare_N_Polarity + @note This parameter is valid only for TIM1 and TIM8. */ + + uint16_t TIM_OCIdleState; /* Specifies the TIM Output Compare pin state during Idle state. + This parameter can be a value of @ref TIM_Output_Compare_Idle_State + @note This parameter is valid only for TIM1 and TIM8. */ + + uint16_t TIM_OCNIdleState; /* Specifies the TIM Output Compare pin state during Idle state. + This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State + @note This parameter is valid only for TIM1 and TIM8. */ +} TIM_OCInitTypeDef; + +/* TIM Input Capture Init structure definition */ +typedef struct +{ + uint16_t TIM_Channel; /* Specifies the TIM channel. + This parameter can be a value of @ref TIM_Channel */ + + uint16_t TIM_ICPolarity; /* Specifies the active edge of the input signal. + This parameter can be a value of @ref TIM_Input_Capture_Polarity */ + + uint16_t TIM_ICSelection; /* Specifies the input. + This parameter can be a value of @ref TIM_Input_Capture_Selection */ + + uint16_t TIM_ICPrescaler; /* Specifies the Input Capture Prescaler. + This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ + + uint16_t TIM_ICFilter; /* Specifies the input capture filter. + This parameter can be a number between 0x0 and 0xF */ +} TIM_ICInitTypeDef; + +/* BDTR structure definition */ +typedef struct +{ + uint16_t TIM_OSSRState; /* Specifies the Off-State selection used in Run mode. + This parameter can be a value of @ref OSSR_Off_State_Selection_for_Run_mode_state */ + + uint16_t TIM_OSSIState; /* Specifies the Off-State used in Idle state. + This parameter can be a value of @ref OSSI_Off_State_Selection_for_Idle_mode_state */ + + uint16_t TIM_LOCKLevel; /* Specifies the LOCK level parameters. + This parameter can be a value of @ref Lock_level */ + + uint16_t TIM_DeadTime; /* Specifies the delay time between the switching-off and the + switching-on of the outputs. + This parameter can be a number between 0x00 and 0xFF */ + + uint16_t TIM_Break; /* Specifies whether the TIM Break input is enabled or not. + This parameter can be a value of @ref Break_Input_enable_disable */ + + uint16_t TIM_BreakPolarity; /* Specifies the TIM Break Input pin polarity. + This parameter can be a value of @ref Break_Polarity */ + + uint16_t TIM_AutomaticOutput; /* Specifies whether the TIM Automatic Output feature is enabled or not. + This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */ +} TIM_BDTRInitTypeDef; + +/* TIM_Output_Compare_and_PWM_modes */ +#define TIM_OCMode_Timing ((uint16_t)0x0000) +#define TIM_OCMode_Active ((uint16_t)0x0010) +#define TIM_OCMode_Inactive ((uint16_t)0x0020) +#define TIM_OCMode_Toggle ((uint16_t)0x0030) +#define TIM_OCMode_PWM1 ((uint16_t)0x0060) +#define TIM_OCMode_PWM2 ((uint16_t)0x0070) + +/* TIM_One_Pulse_Mode */ +#define TIM_OPMode_Single ((uint16_t)0x0008) +#define TIM_OPMode_Repetitive ((uint16_t)0x0000) + +/* TIM_Channel */ +#define TIM_Channel_1 ((uint16_t)0x0000) +#define TIM_Channel_2 ((uint16_t)0x0004) +#define TIM_Channel_3 ((uint16_t)0x0008) +#define TIM_Channel_4 ((uint16_t)0x000C) + +/* TIM_Clock_Division_CKD */ +#define TIM_CKD_DIV1 ((uint16_t)0x0000) +#define TIM_CKD_DIV2 ((uint16_t)0x0100) +#define TIM_CKD_DIV4 ((uint16_t)0x0200) + +/* TIM_Counter_Mode */ +#define TIM_CounterMode_Up ((uint16_t)0x0000) +#define TIM_CounterMode_Down ((uint16_t)0x0010) +#define TIM_CounterMode_CenterAligned1 ((uint16_t)0x0020) +#define TIM_CounterMode_CenterAligned2 ((uint16_t)0x0040) +#define TIM_CounterMode_CenterAligned3 ((uint16_t)0x0060) + +/* TIM_Output_Compare_Polarity */ +#define TIM_OCPolarity_High ((uint16_t)0x0000) +#define TIM_OCPolarity_Low ((uint16_t)0x0002) + +/* TIM_Output_Compare_N_Polarity */ +#define TIM_OCNPolarity_High ((uint16_t)0x0000) +#define TIM_OCNPolarity_Low ((uint16_t)0x0008) + +/* TIM_Output_Compare_state */ +#define TIM_OutputState_Disable ((uint16_t)0x0000) +#define TIM_OutputState_Enable ((uint16_t)0x0001) + +/* TIM_Output_Compare_N_state */ +#define TIM_OutputNState_Disable ((uint16_t)0x0000) +#define TIM_OutputNState_Enable ((uint16_t)0x0004) + +/* TIM_Capture_Compare_state */ +#define TIM_CCx_Enable ((uint16_t)0x0001) +#define TIM_CCx_Disable ((uint16_t)0x0000) + +/* TIM_Capture_Compare_N_state */ +#define TIM_CCxN_Enable ((uint16_t)0x0004) +#define TIM_CCxN_Disable ((uint16_t)0x0000) + +/* Break_Input_enable_disable */ +#define TIM_Break_Enable ((uint16_t)0x1000) +#define TIM_Break_Disable ((uint16_t)0x0000) + +/* Break_Polarity */ +#define TIM_BreakPolarity_Low ((uint16_t)0x0000) +#define TIM_BreakPolarity_High ((uint16_t)0x2000) + +/* TIM_AOE_Bit_Set_Reset */ +#define TIM_AutomaticOutput_Enable ((uint16_t)0x4000) +#define TIM_AutomaticOutput_Disable ((uint16_t)0x0000) + +/* Lock_level */ +#define TIM_LOCKLevel_OFF ((uint16_t)0x0000) +#define TIM_LOCKLevel_1 ((uint16_t)0x0100) +#define TIM_LOCKLevel_2 ((uint16_t)0x0200) +#define TIM_LOCKLevel_3 ((uint16_t)0x0300) + +/* OSSI_Off_State_Selection_for_Idle_mode_state */ +#define TIM_OSSIState_Enable ((uint16_t)0x0400) +#define TIM_OSSIState_Disable ((uint16_t)0x0000) + +/* OSSR_Off_State_Selection_for_Run_mode_state */ +#define TIM_OSSRState_Enable ((uint16_t)0x0800) +#define TIM_OSSRState_Disable ((uint16_t)0x0000) + +/* TIM_Output_Compare_Idle_State */ +#define TIM_OCIdleState_Set ((uint16_t)0x0100) +#define TIM_OCIdleState_Reset ((uint16_t)0x0000) + +/* TIM_Output_Compare_N_Idle_State */ +#define TIM_OCNIdleState_Set ((uint16_t)0x0200) +#define TIM_OCNIdleState_Reset ((uint16_t)0x0000) + +/* TIM_Input_Capture_Polarity */ +#define TIM_ICPolarity_Rising ((uint16_t)0x0000) +#define TIM_ICPolarity_Falling ((uint16_t)0x0002) +#define TIM_ICPolarity_BothEdge ((uint16_t)0x000A) + +/* TIM_Input_Capture_Selection */ +#define TIM_ICSelection_DirectTI ((uint16_t)0x0001) /* TIM Input 1, 2, 3 or 4 is selected to be \ + connected to IC1, IC2, IC3 or IC4, respectively */ +#define TIM_ICSelection_IndirectTI ((uint16_t)0x0002) /* TIM Input 1, 2, 3 or 4 is selected to be \ + connected to IC2, IC1, IC4 or IC3, respectively. */ +#define TIM_ICSelection_TRC ((uint16_t)0x0003) /* TIM Input 1, 2, 3 or 4 is selected to be connected to TRC. */ + +/* TIM_Input_Capture_Prescaler */ +#define TIM_ICPSC_DIV1 ((uint16_t)0x0000) /* Capture performed each time an edge is detected on the capture input. */ +#define TIM_ICPSC_DIV2 ((uint16_t)0x0004) /* Capture performed once every 2 events. */ +#define TIM_ICPSC_DIV4 ((uint16_t)0x0008) /* Capture performed once every 4 events. */ +#define TIM_ICPSC_DIV8 ((uint16_t)0x000C) /* Capture performed once every 8 events. */ + +/* TIM_interrupt_sources */ +#define TIM_IT_Update ((uint16_t)0x0001) +#define TIM_IT_CC1 ((uint16_t)0x0002) +#define TIM_IT_CC2 ((uint16_t)0x0004) +#define TIM_IT_CC3 ((uint16_t)0x0008) +#define TIM_IT_CC4 ((uint16_t)0x0010) +#define TIM_IT_COM ((uint16_t)0x0020) +#define TIM_IT_Trigger ((uint16_t)0x0040) +#define TIM_IT_Break ((uint16_t)0x0080) + +/* TIM_DMA_Base_address */ +#define TIM_DMABase_CR1 ((uint16_t)0x0000) +#define TIM_DMABase_CR2 ((uint16_t)0x0001) +#define TIM_DMABase_SMCR ((uint16_t)0x0002) +#define TIM_DMABase_DIER ((uint16_t)0x0003) +#define TIM_DMABase_SR ((uint16_t)0x0004) +#define TIM_DMABase_EGR ((uint16_t)0x0005) +#define TIM_DMABase_CCMR1 ((uint16_t)0x0006) +#define TIM_DMABase_CCMR2 ((uint16_t)0x0007) +#define TIM_DMABase_CCER ((uint16_t)0x0008) +#define TIM_DMABase_CNT ((uint16_t)0x0009) +#define TIM_DMABase_PSC ((uint16_t)0x000A) +#define TIM_DMABase_ARR ((uint16_t)0x000B) +#define TIM_DMABase_RCR ((uint16_t)0x000C) +#define TIM_DMABase_CCR1 ((uint16_t)0x000D) +#define TIM_DMABase_CCR2 ((uint16_t)0x000E) +#define TIM_DMABase_CCR3 ((uint16_t)0x000F) +#define TIM_DMABase_CCR4 ((uint16_t)0x0010) +#define TIM_DMABase_BDTR ((uint16_t)0x0011) +#define TIM_DMABase_DCR ((uint16_t)0x0012) + +/* TIM_DMA_Burst_Length */ +#define TIM_DMABurstLength_1Transfer ((uint16_t)0x0000) +#define TIM_DMABurstLength_2Transfers ((uint16_t)0x0100) +#define TIM_DMABurstLength_3Transfers ((uint16_t)0x0200) +#define TIM_DMABurstLength_4Transfers ((uint16_t)0x0300) +#define TIM_DMABurstLength_5Transfers ((uint16_t)0x0400) +#define TIM_DMABurstLength_6Transfers ((uint16_t)0x0500) +#define TIM_DMABurstLength_7Transfers ((uint16_t)0x0600) +#define TIM_DMABurstLength_8Transfers ((uint16_t)0x0700) +#define TIM_DMABurstLength_9Transfers ((uint16_t)0x0800) +#define TIM_DMABurstLength_10Transfers ((uint16_t)0x0900) +#define TIM_DMABurstLength_11Transfers ((uint16_t)0x0A00) +#define TIM_DMABurstLength_12Transfers ((uint16_t)0x0B00) +#define TIM_DMABurstLength_13Transfers ((uint16_t)0x0C00) +#define TIM_DMABurstLength_14Transfers ((uint16_t)0x0D00) +#define TIM_DMABurstLength_15Transfers ((uint16_t)0x0E00) +#define TIM_DMABurstLength_16Transfers ((uint16_t)0x0F00) +#define TIM_DMABurstLength_17Transfers ((uint16_t)0x1000) +#define TIM_DMABurstLength_18Transfers ((uint16_t)0x1100) + +/* TIM_DMA_sources */ +#define TIM_DMA_Update ((uint16_t)0x0100) +#define TIM_DMA_CC1 ((uint16_t)0x0200) +#define TIM_DMA_CC2 ((uint16_t)0x0400) +#define TIM_DMA_CC3 ((uint16_t)0x0800) +#define TIM_DMA_CC4 ((uint16_t)0x1000) +#define TIM_DMA_COM ((uint16_t)0x2000) +#define TIM_DMA_Trigger ((uint16_t)0x4000) + +/* TIM_External_Trigger_Prescaler */ +#define TIM_ExtTRGPSC_OFF ((uint16_t)0x0000) +#define TIM_ExtTRGPSC_DIV2 ((uint16_t)0x1000) +#define TIM_ExtTRGPSC_DIV4 ((uint16_t)0x2000) +#define TIM_ExtTRGPSC_DIV8 ((uint16_t)0x3000) + +/* TIM_Internal_Trigger_Selection */ +#define TIM_TS_ITR0 ((uint16_t)0x0000) +#define TIM_TS_ITR1 ((uint16_t)0x0010) +#define TIM_TS_ITR2 ((uint16_t)0x0020) +#define TIM_TS_ITR3 ((uint16_t)0x0030) +#define TIM_TS_TI1F_ED ((uint16_t)0x0040) +#define TIM_TS_TI1FP1 ((uint16_t)0x0050) +#define TIM_TS_TI2FP2 ((uint16_t)0x0060) +#define TIM_TS_ETRF ((uint16_t)0x0070) + +/* TIM_TIx_External_Clock_Source */ +#define TIM_TIxExternalCLK1Source_TI1 ((uint16_t)0x0050) +#define TIM_TIxExternalCLK1Source_TI2 ((uint16_t)0x0060) +#define TIM_TIxExternalCLK1Source_TI1ED ((uint16_t)0x0040) + +/* TIM_External_Trigger_Polarity */ +#define TIM_ExtTRGPolarity_Inverted ((uint16_t)0x8000) +#define TIM_ExtTRGPolarity_NonInverted ((uint16_t)0x0000) + +/* TIM_Prescaler_Reload_Mode */ +#define TIM_PSCReloadMode_Update ((uint16_t)0x0000) +#define TIM_PSCReloadMode_Immediate ((uint16_t)0x0001) + +/* TIM_Forced_Action */ +#define TIM_ForcedAction_Active ((uint16_t)0x0050) +#define TIM_ForcedAction_InActive ((uint16_t)0x0040) + +/* TIM_Encoder_Mode */ +#define TIM_EncoderMode_TI1 ((uint16_t)0x0001) +#define TIM_EncoderMode_TI2 ((uint16_t)0x0002) +#define TIM_EncoderMode_TI12 ((uint16_t)0x0003) + +/* TIM_Event_Source */ +#define TIM_EventSource_Update ((uint16_t)0x0001) +#define TIM_EventSource_CC1 ((uint16_t)0x0002) +#define TIM_EventSource_CC2 ((uint16_t)0x0004) +#define TIM_EventSource_CC3 ((uint16_t)0x0008) +#define TIM_EventSource_CC4 ((uint16_t)0x0010) +#define TIM_EventSource_COM ((uint16_t)0x0020) +#define TIM_EventSource_Trigger ((uint16_t)0x0040) +#define TIM_EventSource_Break ((uint16_t)0x0080) + +/* TIM_Update_Source */ +#define TIM_UpdateSource_Global ((uint16_t)0x0000) /* Source of update is the counter overflow/underflow \ + or the setting of UG bit, or an update generation \ + through the slave mode controller. */ +#define TIM_UpdateSource_Regular ((uint16_t)0x0001) /* Source of update is counter overflow/underflow. */ + +/* TIM_Output_Compare_Preload_State */ +#define TIM_OCPreload_Enable ((uint16_t)0x0008) +#define TIM_OCPreload_Disable ((uint16_t)0x0000) + +/* TIM_Output_Compare_Fast_State */ +#define TIM_OCFast_Enable ((uint16_t)0x0004) +#define TIM_OCFast_Disable ((uint16_t)0x0000) + +/* TIM_Output_Compare_Clear_State */ +#define TIM_OCClear_Enable ((uint16_t)0x0080) +#define TIM_OCClear_Disable ((uint16_t)0x0000) + +/* TIM_Trigger_Output_Source */ +#define TIM_TRGOSource_Reset ((uint16_t)0x0000) +#define TIM_TRGOSource_Enable ((uint16_t)0x0010) +#define TIM_TRGOSource_Update ((uint16_t)0x0020) +#define TIM_TRGOSource_OC1 ((uint16_t)0x0030) +#define TIM_TRGOSource_OC1Ref ((uint16_t)0x0040) +#define TIM_TRGOSource_OC2Ref ((uint16_t)0x0050) +#define TIM_TRGOSource_OC3Ref ((uint16_t)0x0060) +#define TIM_TRGOSource_OC4Ref ((uint16_t)0x0070) + +/* TIM_Slave_Mode */ +#define TIM_SlaveMode_Reset ((uint16_t)0x0004) +#define TIM_SlaveMode_Gated ((uint16_t)0x0005) +#define TIM_SlaveMode_Trigger ((uint16_t)0x0006) +#define TIM_SlaveMode_External1 ((uint16_t)0x0007) + +/* TIM_Master_Slave_Mode */ +#define TIM_MasterSlaveMode_Enable ((uint16_t)0x0080) +#define TIM_MasterSlaveMode_Disable ((uint16_t)0x0000) + +/* TIM_Flags */ +#define TIM_FLAG_Update ((uint16_t)0x0001) +#define TIM_FLAG_CC1 ((uint16_t)0x0002) +#define TIM_FLAG_CC2 ((uint16_t)0x0004) +#define TIM_FLAG_CC3 ((uint16_t)0x0008) +#define TIM_FLAG_CC4 ((uint16_t)0x0010) +#define TIM_FLAG_COM ((uint16_t)0x0020) +#define TIM_FLAG_Trigger ((uint16_t)0x0040) +#define TIM_FLAG_Break ((uint16_t)0x0080) +#define TIM_FLAG_CC1OF ((uint16_t)0x0200) +#define TIM_FLAG_CC2OF ((uint16_t)0x0400) +#define TIM_FLAG_CC3OF ((uint16_t)0x0800) +#define TIM_FLAG_CC4OF ((uint16_t)0x1000) + +/* TIM_Legacy */ +#define TIM_DMABurstLength_1Byte TIM_DMABurstLength_1Transfer +#define TIM_DMABurstLength_2Bytes TIM_DMABurstLength_2Transfers +#define TIM_DMABurstLength_3Bytes TIM_DMABurstLength_3Transfers +#define TIM_DMABurstLength_4Bytes TIM_DMABurstLength_4Transfers +#define TIM_DMABurstLength_5Bytes TIM_DMABurstLength_5Transfers +#define TIM_DMABurstLength_6Bytes TIM_DMABurstLength_6Transfers +#define TIM_DMABurstLength_7Bytes TIM_DMABurstLength_7Transfers +#define TIM_DMABurstLength_8Bytes TIM_DMABurstLength_8Transfers +#define TIM_DMABurstLength_9Bytes TIM_DMABurstLength_9Transfers +#define TIM_DMABurstLength_10Bytes TIM_DMABurstLength_10Transfers +#define TIM_DMABurstLength_11Bytes TIM_DMABurstLength_11Transfers +#define TIM_DMABurstLength_12Bytes TIM_DMABurstLength_12Transfers +#define TIM_DMABurstLength_13Bytes TIM_DMABurstLength_13Transfers +#define TIM_DMABurstLength_14Bytes TIM_DMABurstLength_14Transfers +#define TIM_DMABurstLength_15Bytes TIM_DMABurstLength_15Transfers +#define TIM_DMABurstLength_16Bytes TIM_DMABurstLength_16Transfers +#define TIM_DMABurstLength_17Bytes TIM_DMABurstLength_17Transfers +#define TIM_DMABurstLength_18Bytes TIM_DMABurstLength_18Transfers + +/* TIM_Capture_Mode */ +#define TIM_Capture_Mode0 ((uint16_t)0x0000) +#define TIM_Capture_Mode1 ((uint16_t)0x4000) + +void TIM_DeInit(TIM_TypeDef *TIMx); +void TIM_TimeBaseInit(TIM_TypeDef *TIMx, TIM_TimeBaseInitTypeDef *TIM_TimeBaseInitStruct); +void TIM_OC1Init(TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct); +void TIM_OC2Init(TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct); +void TIM_OC3Init(TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct); +void TIM_OC4Init(TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct); +void TIM_ICInit(TIM_TypeDef *TIMx, TIM_ICInitTypeDef *TIM_ICInitStruct); +void TIM_PWMIConfig(TIM_TypeDef *TIMx, TIM_ICInitTypeDef *TIM_ICInitStruct); +void TIM_BDTRConfig(TIM_TypeDef *TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct); +void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef *TIM_TimeBaseInitStruct); +void TIM_OCStructInit(TIM_OCInitTypeDef *TIM_OCInitStruct); +void TIM_ICStructInit(TIM_ICInitTypeDef *TIM_ICInitStruct); +void TIM_BDTRStructInit(TIM_BDTRInitTypeDef *TIM_BDTRInitStruct); +void TIM_Cmd(TIM_TypeDef *TIMx, FunctionalState NewState); +void TIM_CtrlPWMOutputs(TIM_TypeDef *TIMx, FunctionalState NewState); +void TIM_ITConfig(TIM_TypeDef *TIMx, uint16_t TIM_IT, FunctionalState NewState); +void TIM_GenerateEvent(TIM_TypeDef *TIMx, uint16_t TIM_EventSource); +void TIM_DMAConfig(TIM_TypeDef *TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength); +void TIM_DMACmd(TIM_TypeDef *TIMx, uint16_t TIM_DMASource, FunctionalState NewState); +void TIM_InternalClockConfig(TIM_TypeDef *TIMx); +void TIM_ITRxExternalClockConfig(TIM_TypeDef *TIMx, uint16_t TIM_InputTriggerSource); +void TIM_TIxExternalClockConfig(TIM_TypeDef *TIMx, uint16_t TIM_TIxExternalCLKSource, + uint16_t TIM_ICPolarity, uint16_t ICFilter); +void TIM_ETRClockMode1Config(TIM_TypeDef *TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, + uint16_t ExtTRGFilter); +void TIM_ETRClockMode2Config(TIM_TypeDef *TIMx, uint16_t TIM_ExtTRGPrescaler, + uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter); +void TIM_ETRConfig(TIM_TypeDef *TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, + uint16_t ExtTRGFilter); +void TIM_PrescalerConfig(TIM_TypeDef *TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode); +void TIM_CounterModeConfig(TIM_TypeDef *TIMx, uint16_t TIM_CounterMode); +void TIM_SelectInputTrigger(TIM_TypeDef *TIMx, uint16_t TIM_InputTriggerSource); +void TIM_EncoderInterfaceConfig(TIM_TypeDef *TIMx, uint16_t TIM_EncoderMode, + uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity); +void TIM_ForcedOC1Config(TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction); +void TIM_ForcedOC2Config(TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction); +void TIM_ForcedOC3Config(TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction); +void TIM_ForcedOC4Config(TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction); +void TIM_ARRPreloadConfig(TIM_TypeDef *TIMx, FunctionalState NewState); +void TIM_SelectCOM(TIM_TypeDef *TIMx, FunctionalState NewState); +void TIM_SelectCCDMA(TIM_TypeDef *TIMx, FunctionalState NewState); +void TIM_CCPreloadControl(TIM_TypeDef *TIMx, FunctionalState NewState); +void TIM_OC1PreloadConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPreload); +void TIM_OC2PreloadConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPreload); +void TIM_OC3PreloadConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPreload); +void TIM_OC4PreloadConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPreload); +void TIM_OC1FastConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCFast); +void TIM_OC2FastConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCFast); +void TIM_OC3FastConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCFast); +void TIM_OC4FastConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCFast); +void TIM_ClearOC1Ref(TIM_TypeDef *TIMx, uint16_t TIM_OCClear); +void TIM_ClearOC2Ref(TIM_TypeDef *TIMx, uint16_t TIM_OCClear); +void TIM_ClearOC3Ref(TIM_TypeDef *TIMx, uint16_t TIM_OCClear); +void TIM_ClearOC4Ref(TIM_TypeDef *TIMx, uint16_t TIM_OCClear); +void TIM_OC1PolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity); +void TIM_OC1NPolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCNPolarity); +void TIM_OC2PolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity); +void TIM_OC2NPolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCNPolarity); +void TIM_OC3PolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity); +void TIM_OC3NPolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCNPolarity); +void TIM_OC4PolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity); +void TIM_CCxCmd(TIM_TypeDef *TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx); +void TIM_CCxNCmd(TIM_TypeDef *TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN); +void TIM_SelectOCxM(TIM_TypeDef *TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode); +void TIM_UpdateDisableConfig(TIM_TypeDef *TIMx, FunctionalState NewState); +void TIM_UpdateRequestConfig(TIM_TypeDef *TIMx, uint16_t TIM_UpdateSource); +void TIM_SelectHallSensor(TIM_TypeDef *TIMx, FunctionalState NewState); +void TIM_SelectOnePulseMode(TIM_TypeDef *TIMx, uint16_t TIM_OPMode); +void TIM_SelectOutputTrigger(TIM_TypeDef *TIMx, uint16_t TIM_TRGOSource); +void TIM_SelectSlaveMode(TIM_TypeDef *TIMx, uint16_t TIM_SlaveMode); +void TIM_SelectMasterSlaveMode(TIM_TypeDef *TIMx, uint16_t TIM_MasterSlaveMode); +void TIM_SetCounter(TIM_TypeDef *TIMx, uint32_t Counter); +void TIM_SetAutoreload(TIM_TypeDef *TIMx, uint32_t Autoreload); +void TIM_SetCompare1(TIM_TypeDef *TIMx, uint32_t Compare1); +void TIM_SetCompare2(TIM_TypeDef *TIMx, uint32_t Compare2); +void TIM_SetCompare3(TIM_TypeDef *TIMx, uint32_t Compare3); +void TIM_SetCompare4(TIM_TypeDef *TIMx, uint32_t Compare4); +void TIM_SetIC1Prescaler(TIM_TypeDef *TIMx, uint16_t TIM_ICPSC); +void TIM_SetIC2Prescaler(TIM_TypeDef *TIMx, uint16_t TIM_ICPSC); +void TIM_SetIC3Prescaler(TIM_TypeDef *TIMx, uint16_t TIM_ICPSC); +void TIM_SetIC4Prescaler(TIM_TypeDef *TIMx, uint16_t TIM_ICPSC); +void TIM_SetClockDivision(TIM_TypeDef *TIMx, uint16_t TIM_CKD); +uint32_t TIM_GetCapture1(TIM_TypeDef *TIMx); +uint32_t TIM_GetCapture2(TIM_TypeDef *TIMx); +uint32_t TIM_GetCapture3(TIM_TypeDef *TIMx); +uint32_t TIM_GetCapture4(TIM_TypeDef *TIMx); +uint32_t TIM_GetCounter(TIM_TypeDef *TIMx); +uint16_t TIM_GetPrescaler(TIM_TypeDef *TIMx); +FlagStatus TIM_GetFlagStatus(TIM_TypeDef *TIMx, uint16_t TIM_FLAG); +void TIM_ClearFlag(TIM_TypeDef *TIMx, uint16_t TIM_FLAG); +ITStatus TIM_GetITStatus(TIM_TypeDef *TIMx, uint16_t TIM_IT); +void TIM_ClearITPendingBit(TIM_TypeDef *TIMx, uint16_t TIM_IT); +void TIM_CaptureLevelIndicate_Cmd(TIM_TypeDef *TIMx, FunctionalState NewState); +void TIM_CaptureModeConfig(TIM_TypeDef *TIMx, uint16_t TIM_CaptureMode); + + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/ZDBMS/BMS_CC/Peripheral/inc/ch32l103_usart.h b/ZDBMS/BMS_CC/Peripheral/inc/ch32l103_usart.h new file mode 100644 index 0000000..c981f49 --- /dev/null +++ b/ZDBMS/BMS_CC/Peripheral/inc/ch32l103_usart.h @@ -0,0 +1,188 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32l103_usart.h + * Author : WCH + * Version : V1.0.0 + * Date : 2023/07/08 + * Description : This file contains all the functions prototypes for the + * USART firmware library. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#ifndef __CH32L103_USART_H +#define __CH32L103_USART_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "ch32l103.h" + +/* USART Init Structure definition */ +typedef struct +{ + uint32_t USART_BaudRate; /* This member configures the USART communication baud rate. + The baud rate is computed using the following formula: + - IntegerDivider = ((PCLKx) / (16 * (USART_InitStruct->USART_BaudRate))) + - FractionalDivider = ((IntegerDivider - ((u32) IntegerDivider)) * 16) + 0.5 */ + + uint16_t USART_WordLength; /* Specifies the number of data bits transmitted or received in a frame. + This parameter can be a value of @ref USART_Word_Length */ + + uint16_t USART_StopBits; /* Specifies the number of stop bits transmitted. + This parameter can be a value of @ref USART_Stop_Bits */ + + uint16_t USART_Parity; /* Specifies the parity mode. + This parameter can be a value of @ref USART_Parity + @note When parity is enabled, the computed parity is inserted + at the MSB position of the transmitted data (9th bit when + the word length is set to 9 data bits; 8th bit when the + word length is set to 8 data bits). */ + + uint16_t USART_Mode; /* Specifies wether the Receive or Transmit mode is enabled or disabled. + This parameter can be a value of @ref USART_Mode */ + + uint16_t USART_HardwareFlowControl; /* Specifies wether the hardware flow control mode is enabled + or disabled. + This parameter can be a value of @ref USART_Hardware_Flow_Control */ +} USART_InitTypeDef; + +/* USART Clock Init Structure definition */ +typedef struct +{ + uint16_t USART_Clock; /* Specifies whether the USART clock is enabled or disabled. + This parameter can be a value of @ref USART_Clock */ + + uint16_t USART_CPOL; /* Specifies the steady state value of the serial clock. + This parameter can be a value of @ref USART_Clock_Polarity */ + + uint16_t USART_CPHA; /* Specifies the clock transition on which the bit capture is made. + This parameter can be a value of @ref USART_Clock_Phase */ + + uint16_t USART_LastBit; /* Specifies whether the clock pulse corresponding to the last transmitted + data bit (MSB) has to be output on the SCLK pin in synchronous mode. + This parameter can be a value of @ref USART_Last_Bit */ +} USART_ClockInitTypeDef; + +/* USART_Word_Length */ +#define USART_WordLength_8b ((uint16_t)0x0000) +#define USART_WordLength_9b ((uint16_t)0x1000) + +/* USART_Stop_Bits */ +#define USART_StopBits_1 ((uint16_t)0x0000) +#define USART_StopBits_0_5 ((uint16_t)0x1000) +#define USART_StopBits_2 ((uint16_t)0x2000) +#define USART_StopBits_1_5 ((uint16_t)0x3000) + +/* USART_Parity */ +#define USART_Parity_No ((uint16_t)0x0000) +#define USART_Parity_Even ((uint16_t)0x0400) +#define USART_Parity_Odd ((uint16_t)0x0600) + +/* USART_Mode */ +#define USART_Mode_Rx ((uint16_t)0x0004) +#define USART_Mode_Tx ((uint16_t)0x0008) + +/* USART_Hardware_Flow_Control */ +#define USART_HardwareFlowControl_None ((uint16_t)0x0000) +#define USART_HardwareFlowControl_RTS ((uint16_t)0x0100) +#define USART_HardwareFlowControl_CTS ((uint16_t)0x0200) +#define USART_HardwareFlowControl_RTS_CTS ((uint16_t)0x0300) + +/* USART_Clock */ +#define USART_Clock_Disable ((uint16_t)0x0000) +#define USART_Clock_Enable ((uint16_t)0x0800) + +/* USART_Clock_Polarity */ +#define USART_CPOL_Low ((uint16_t)0x0000) +#define USART_CPOL_High ((uint16_t)0x0400) + +/* USART_Clock_Phase */ +#define USART_CPHA_1Edge ((uint16_t)0x0000) +#define USART_CPHA_2Edge ((uint16_t)0x0200) + +/* USART_Last_Bit */ +#define USART_LastBit_Disable ((uint16_t)0x0000) +#define USART_LastBit_Enable ((uint16_t)0x0100) + +/* USART_Interrupt_definition */ +#define USART_IT_PE ((uint16_t)0x0028) +#define USART_IT_TXE ((uint16_t)0x0727) +#define USART_IT_TC ((uint16_t)0x0626) +#define USART_IT_RXNE ((uint16_t)0x0525) +#define USART_IT_ORE_RX ((uint16_t)0x0325) +#define USART_IT_IDLE ((uint16_t)0x0424) +#define USART_IT_LBD ((uint16_t)0x0846) +#define USART_IT_CTS ((uint16_t)0x096A) +#define USART_IT_ERR ((uint16_t)0x0060) +#define USART_IT_ORE_ER ((uint16_t)0x0360) +#define USART_IT_NE ((uint16_t)0x0260) +#define USART_IT_FE ((uint16_t)0x0160) + +#define USART_IT_ORE USART_IT_ORE_ER + +/* USART_DMA_Requests */ +#define USART_DMAReq_Tx ((uint16_t)0x0080) +#define USART_DMAReq_Rx ((uint16_t)0x0040) + +/* USART_WakeUp_methods */ +#define USART_WakeUp_IdleLine ((uint16_t)0x0000) +#define USART_WakeUp_AddressMark ((uint16_t)0x0800) + +/* USART_LIN_Break_Detection_Length */ +#define USART_LINBreakDetectLength_10b ((uint16_t)0x0000) +#define USART_LINBreakDetectLength_11b ((uint16_t)0x0020) + +/* USART_IrDA_Low_Power */ +#define USART_IrDAMode_LowPower ((uint16_t)0x0004) +#define USART_IrDAMode_Normal ((uint16_t)0x0000) + +/* USART_Flags */ +#define USART_FLAG_RX_BUSY ((uint16_t)0x0400) +#define USART_FLAG_CTS ((uint16_t)0x0200) +#define USART_FLAG_LBD ((uint16_t)0x0100) +#define USART_FLAG_TXE ((uint16_t)0x0080) +#define USART_FLAG_TC ((uint16_t)0x0040) +#define USART_FLAG_RXNE ((uint16_t)0x0020) +#define USART_FLAG_IDLE ((uint16_t)0x0010) +#define USART_FLAG_ORE ((uint16_t)0x0008) +#define USART_FLAG_NE ((uint16_t)0x0004) +#define USART_FLAG_FE ((uint16_t)0x0002) +#define USART_FLAG_PE ((uint16_t)0x0001) + +void USART_DeInit(USART_TypeDef *USARTx); +void USART_Init(USART_TypeDef *USARTx, USART_InitTypeDef *USART_InitStruct); +void USART_StructInit(USART_InitTypeDef *USART_InitStruct); +void USART_ClockInit(USART_TypeDef *USARTx, USART_ClockInitTypeDef *USART_ClockInitStruct); +void USART_ClockStructInit(USART_ClockInitTypeDef *USART_ClockInitStruct); +void USART_Cmd(USART_TypeDef *USARTx, FunctionalState NewState); +void USART_ITConfig(USART_TypeDef *USARTx, uint16_t USART_IT, FunctionalState NewState); +void USART_DMACmd(USART_TypeDef *USARTx, uint16_t USART_DMAReq, FunctionalState NewState); +void USART_SetAddress(USART_TypeDef *USARTx, uint8_t USART_Address); +void USART_WakeUpConfig(USART_TypeDef *USARTx, uint16_t USART_WakeUp); +void USART_ReceiverWakeUpCmd(USART_TypeDef *USARTx, FunctionalState NewState); +void USART_LINBreakDetectLengthConfig(USART_TypeDef *USARTx, uint16_t USART_LINBreakDetectLength); +void USART_LINCmd(USART_TypeDef *USARTx, FunctionalState NewState); +void USART_SendData(USART_TypeDef *USARTx, uint16_t Data); +uint16_t USART_ReceiveData(USART_TypeDef *USARTx); +void USART_SendBreak(USART_TypeDef *USARTx); +void USART_SetGuardTime(USART_TypeDef *USARTx, uint8_t USART_GuardTime); +void USART_SetPrescaler(USART_TypeDef *USARTx, uint8_t USART_Prescaler); +void USART_SmartCardCmd(USART_TypeDef *USARTx, FunctionalState NewState); +void USART_SmartCardNACKCmd(USART_TypeDef *USARTx, FunctionalState NewState); +void USART_HalfDuplexCmd(USART_TypeDef *USARTx, FunctionalState NewState); +void USART_OverSampling8Cmd(USART_TypeDef *USARTx, FunctionalState NewState); +void USART_OneBitMethodCmd(USART_TypeDef *USARTx, FunctionalState NewState); +void USART_IrDAConfig(USART_TypeDef *USARTx, uint16_t USART_IrDAMode); +void USART_IrDACmd(USART_TypeDef *USARTx, FunctionalState NewState); +FlagStatus USART_GetFlagStatus(USART_TypeDef *USARTx, uint16_t USART_FLAG); +void USART_ClearFlag(USART_TypeDef *USARTx, uint16_t USART_FLAG); +ITStatus USART_GetITStatus(USART_TypeDef *USARTx, uint16_t USART_IT); +void USART_ClearITPendingBit(USART_TypeDef *USARTx, uint16_t USART_IT); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/ZDBMS/BMS_CC/Peripheral/inc/ch32l103_usb.h b/ZDBMS/BMS_CC/Peripheral/inc/ch32l103_usb.h new file mode 100644 index 0000000..a3689f0 --- /dev/null +++ b/ZDBMS/BMS_CC/Peripheral/inc/ch32l103_usb.h @@ -0,0 +1,513 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32l103_usb.h + * Author : WCH + * Version : V1.0.0 + * Date : 2024/01/19 + * Description : This file contains all the functions prototypes for the USB + * firmware library. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#ifndef __CH32L103_USB_H +#define __CH32L103_USB_H + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef __cplusplus + extern "C" { +#endif + +/*******************************************************************************/ +/* Header File */ +#include "stdint.h" + +/*******************************************************************************/ +/* USB Communication Related Macro Definition */ + +/* USB Endpoint0 Size */ +#ifndef DEFAULT_ENDP0_SIZE +#define DEFAULT_ENDP0_SIZE 8 +#endif + +/* USB Buffer Size */ +#ifndef USBFS_MAX_PACKET_SIZE +#define USBFS_MAX_PACKET_SIZE 64 +#endif + +/* USB PID */ +#ifndef USB_PID_SETUP +#define USB_PID_NULL 0x00 +#define USB_PID_SOF 0x05 +#define USB_PID_SETUP 0x0D +#define USB_PID_IN 0x09 +#define USB_PID_OUT 0x01 +#define USB_PID_NYET 0x06 +#define USB_PID_ACK 0x02 +#define USB_PID_NAK 0x0A +#define USB_PID_STALL 0x0E +#define USB_PID_DATA0 0x03 +#define USB_PID_DATA1 0x0B +#define USB_PID_PRE 0x0C +#endif + +/* USB standard device request code */ +#ifndef USB_GET_DESCRIPTOR +#define USB_GET_STATUS 0x00 +#define USB_CLEAR_FEATURE 0x01 +#define USB_SET_FEATURE 0x03 +#define USB_SET_ADDRESS 0x05 +#define USB_GET_DESCRIPTOR 0x06 +#define USB_SET_DESCRIPTOR 0x07 +#define USB_GET_CONFIGURATION 0x08 +#define USB_SET_CONFIGURATION 0x09 +#define USB_GET_INTERFACE 0x0A +#define USB_SET_INTERFACE 0x0B +#define USB_SYNCH_FRAME 0x0C +#endif + +#define DEF_STRING_DESC_LANG 0x00 +#define DEF_STRING_DESC_MANU 0x01 +#define DEF_STRING_DESC_PROD 0x02 +#define DEF_STRING_DESC_SERN 0x03 + +/* USB hub class request code */ +#ifndef HUB_GET_DESCRIPTOR +#define HUB_GET_STATUS 0x00 +#define HUB_CLEAR_FEATURE 0x01 +#define HUB_GET_STATE 0x02 +#define HUB_SET_FEATURE 0x03 +#define HUB_GET_DESCRIPTOR 0x06 +#define HUB_SET_DESCRIPTOR 0x07 +#endif + +/* USB HID class request code */ +#ifndef HID_GET_REPORT +#define HID_GET_REPORT 0x01 +#define HID_GET_IDLE 0x02 +#define HID_GET_PROTOCOL 0x03 +#define HID_SET_REPORT 0x09 +#define HID_SET_IDLE 0x0A +#define HID_SET_PROTOCOL 0x0B +#endif + +/* Bit Define for USB Request Type */ +#ifndef USB_REQ_TYP_MASK +#define USB_REQ_TYP_IN 0x80 +#define USB_REQ_TYP_OUT 0x00 +#define USB_REQ_TYP_READ 0x80 +#define USB_REQ_TYP_WRITE 0x00 +#define USB_REQ_TYP_MASK 0x60 +#define USB_REQ_TYP_STANDARD 0x00 +#define USB_REQ_TYP_CLASS 0x20 +#define USB_REQ_TYP_VENDOR 0x40 +#define USB_REQ_TYP_RESERVED 0x60 +#define USB_REQ_RECIP_MASK 0x1F +#define USB_REQ_RECIP_DEVICE 0x00 +#define USB_REQ_RECIP_INTERF 0x01 +#define USB_REQ_RECIP_ENDP 0x02 +#define USB_REQ_RECIP_OTHER 0x03 +#define USB_REQ_FEAT_REMOTE_WAKEUP 0x01 +#define USB_REQ_FEAT_ENDP_HALT 0x00 +#endif + +/* USB Descriptor Type */ +#ifndef USB_DESCR_TYP_DEVICE +#define USB_DESCR_TYP_DEVICE 0x01 +#define USB_DESCR_TYP_CONFIG 0x02 +#define USB_DESCR_TYP_STRING 0x03 +#define USB_DESCR_TYP_INTERF 0x04 +#define USB_DESCR_TYP_ENDP 0x05 +#define USB_DESCR_TYP_QUALIF 0x06 +#define USB_DESCR_TYP_SPEED 0x07 +#define USB_DESCR_TYP_OTG 0x09 +#define USB_DESCR_TYP_BOS 0X0F +#define USB_DESCR_TYP_HID 0x21 +#define USB_DESCR_TYP_REPORT 0x22 +#define USB_DESCR_TYP_PHYSIC 0x23 +#define USB_DESCR_TYP_CS_INTF 0x24 +#define USB_DESCR_TYP_CS_ENDP 0x25 +#define USB_DESCR_TYP_HUB 0x29 +#endif + +/* USB Device Class */ +#ifndef USB_DEV_CLASS_HUB +#define USB_DEV_CLASS_RESERVED 0x00 +#define USB_DEV_CLASS_AUDIO 0x01 +#define USB_DEV_CLASS_COMMUNIC 0x02 +#define USB_DEV_CLASS_HID 0x03 +#define USB_DEV_CLASS_MONITOR 0x04 +#define USB_DEV_CLASS_PHYSIC_IF 0x05 +#define USB_DEV_CLASS_POWER 0x06 +#define USB_DEV_CLASS_IMAGE 0x06 +#define USB_DEV_CLASS_PRINTER 0x07 +#define USB_DEV_CLASS_STORAGE 0x08 +#define USB_DEV_CLASS_HUB 0x09 +#define USB_DEV_CLASS_VEN_SPEC 0xFF +#endif + +/* USB Hub Class Request */ +#ifndef HUB_GET_HUB_DESCRIPTOR +#define HUB_CLEAR_HUB_FEATURE 0x20 +#define HUB_CLEAR_PORT_FEATURE 0x23 +#define HUB_GET_BUS_STATE 0xA3 +#define HUB_GET_HUB_DESCRIPTOR 0xA0 +#define HUB_GET_HUB_STATUS 0xA0 +#define HUB_GET_PORT_STATUS 0xA3 +#define HUB_SET_HUB_DESCRIPTOR 0x20 +#define HUB_SET_HUB_FEATURE 0x20 +#define HUB_SET_PORT_FEATURE 0x23 +#endif + +/* Hub Class Feature Selectors */ +#ifndef HUB_PORT_RESET +#define HUB_C_HUB_LOCAL_POWER 0 +#define HUB_C_HUB_OVER_CURRENT 1 +#define HUB_PORT_CONNECTION 0 +#define HUB_PORT_ENABLE 1 +#define HUB_PORT_SUSPEND 2 +#define HUB_PORT_OVER_CURRENT 3 +#define HUB_PORT_RESET 4 +#define HUB_PORT_POWER 8 +#define HUB_PORT_LOW_SPEED 9 +#define HUB_C_PORT_CONNECTION 16 +#define HUB_C_PORT_ENABLE 17 +#define HUB_C_PORT_SUSPEND 18 +#define HUB_C_PORT_OVER_CURRENT 19 +#define HUB_C_PORT_RESET 20 +#endif + +/* USB HID Class Request Code */ +#ifndef HID_GET_REPORT +#define HID_GET_REPORT 0x01 +#define HID_GET_IDLE 0x02 +#define HID_GET_PROTOCOL 0x03 +#define HID_SET_REPORT 0x09 +#define HID_SET_IDLE 0x0A +#define HID_SET_PROTOCOL 0x0B +#endif + +/* USB CDC Class request code */ +#ifndef CDC_GET_LINE_CODING +#define CDC_GET_LINE_CODING 0x21 /* This request allows the host to find out the currently configured line coding */ +#define CDC_SET_LINE_CODING 0x20 /* Configures DTE rate, stop-bits, parity, and number-of-character */ +#define CDC_SET_LINE_CTLSTE 0x22 /* This request generates RS-232/V.24 style control signals */ +#define CDC_SEND_BREAK 0x23 /* Sends special carrier modulation used to specify RS-232 style break */ +#endif + +/* USB UDisk */ +#ifndef USB_BO_CBW_SIZE +#define USB_BO_CBW_SIZE 0x1F +#define USB_BO_CSW_SIZE 0x0D +#endif +#ifndef USB_BO_CBW_SIG0 +#define USB_BO_CBW_SIG0 0x55 +#define USB_BO_CBW_SIG1 0x53 +#define USB_BO_CBW_SIG2 0x42 +#define USB_BO_CBW_SIG3 0x43 +#define USB_BO_CSW_SIG0 0x55 +#define USB_BO_CSW_SIG1 0x53 +#define USB_BO_CSW_SIG2 0x42 +#define USB_BO_CSW_SIG3 0x53 +#endif + +/*******************************************************************************/ +/* USBFS Related Register Macro Definition */ + +/* R8_USB_CTRL */ +#define USBFS_UC_HOST_MODE 0x80 +#define USBFS_UC_LOW_SPEED 0x40 +#define USBFS_UC_SYS_CTRL_MASK 0x30 +#define USBFS_UC_SYS_CTRL0 0x00 +#define USBFS_UC_SYS_CTRL1 0x10 +#define USBFS_UC_SYS_CTRL2 0x20 +#define USBFS_UC_SYS_CTRL3 0x30 +#define USBFS_UC_DEV_PU_EN 0x20 +#define USBFS_UC_INT_BUSY 0x08 +#define USBFS_UC_RESET_SIE 0x04 +#define USBFS_UC_CLR_ALL 0x02 +#define USBFS_UC_DMA_EN 0x01 + +/* R8_USB_INT_EN */ +#define USBFS_UIE_DEV_NAK 0x40 +#define USBFS_UID_1_WIRE 0x20 +#define USBFS_UIE_FIFO_OV 0x10 +#define USBFS_UIE_HST_SOF 0x08 +#define USBFS_UIE_SUSPEND 0x04 +#define USBFS_UIE_TRANSFER 0x02 +#define USBFS_UIE_DETECT 0x01 +#define USBFS_UIE_BUS_RST 0x01 + +/* R8_USB_DEV_AD */ +#define USBFS_UDA_GP_BIT 0x80 +#define USBFS_USB_ADDR_MASK 0x7F + +/* R8_USB_MIS_ST */ +#define USBFS_UMS_SOF_PRES 0x80 +#define USBFS_UMS_SOF_ACT 0x40 +#define USBFS_UMS_SIE_FREE 0x20 +#define USBFS_UMS_R_FIFO_RDY 0x10 +#define USBFS_UMS_BUS_RESET 0x08 +#define USBFS_UMS_SUSPEND 0x04 +#define USBFS_UMS_DM_LEVEL 0x02 +#define USBFS_UMS_DEV_ATTACH 0x01 + +/* R8_USB_INT_FG */ +#define USBFS_U_IS_NAK 0x80 // RO, indicate current USB transfer is NAK received +#define USBFS_U_TOG_OK 0x40 // RO, indicate current USB transfer toggle is OK +#define USBFS_U_SIE_FREE 0x20 // RO, indicate USB SIE free status +#define USBFS_UIF_FIFO_OV 0x10 // FIFO overflow interrupt flag for USB, direct bit address clear or write 1 to clear +#define USBFS_UIF_HST_SOF 0x08 // host SOF timer interrupt flag for USB host, direct bit address clear or write 1 to clear +#define USBFS_UIF_SUSPEND 0x04 // USB suspend or resume event interrupt flag, direct bit address clear or write 1 to clear +#define USBFS_UIF_TRANSFER 0x02 // USB transfer completion interrupt flag, direct bit address clear or write 1 to clear +#define USBFS_UIF_DETECT 0x01 // device detected event interrupt flag for USB host mode, direct bit address clear or write 1 to clear +#define USBFS_UIF_BUS_RST 0x01 // bus reset event interrupt flag for USB device mode, direct bit address clear or write 1 to clear + +/* R8_USB_INT_ST */ +#define USBFS_SETUP_ACT 0x80 // RO, indicate current SETUP transaction completed +#define USBFS_UIS_TOG_OK 0x40 // RO, indicate current USB transfer toggle is OK +#define USBFS_UIS_TOKEN_MASK 0x30 // RO, bit mask of current token PID code received for USB device mode +#define USBFS_UIS_TOKEN_OUT 0x00 +#define USBFS_UIS_TOKEN_IN 0x20 +#define USBFS_UIS_TOKEN_SETUP 0x30 +// bUIS_TOKEN1 & bUIS_TOKEN0: current token PID code received for USB device mode +// 00: OUT token PID received +// 10: IN token PID received +// 11: SETUP token PID received +#define USBFS_UIS_ENDP_MASK 0x0F // RO, bit mask of current transfer endpoint number for USB device mode +#define USBFS_UIS_H_RES_MASK 0x0F // RO, bit mask of current transfer handshake response for USB host mode: 0000=no response, time out from device, others=handshake response PID received + +/* R8_UDEV_CTRL */ +#define USBFS_UD_PD_DIS 0x80 // disable USB UDP/UDM pulldown resistance: 0=enable pulldown, 1=disable +#define USBFS_UD_DP_PIN 0x20 // ReadOnly: indicate current UDP pin level +#define USBFS_UD_DM_PIN 0x10 // ReadOnly: indicate current UDM pin level +#define USBFS_UD_LOW_SPEED 0x04 // enable USB physical port low speed: 0=full speed, 1=low speed +#define USBFS_UD_GP_BIT 0x02 // general purpose bit +#define USBFS_UD_PORT_EN 0x01 // enable USB physical port I/O: 0=disable, 1=enable + +/* R8_UEP4_1_MOD */ +#define USBFS_UEP1_RX_EN 0x80 // enable USB endpoint 1 receiving (OUT) +#define USBFS_UEP1_TX_EN 0x40 // enable USB endpoint 1 transmittal (IN) +#define USBFS_UEP1_BUF_MOD 0x10 // buffer mode of USB endpoint 1 +#define USBFS_UEP4_RX_EN 0x08 // enable USB endpoint 4 receiving (OUT) +#define USBFS_UEP4_TX_EN 0x04 // enable USB endpoint 4 transmittal (IN) +#define USBFS_UEP4_BUF_MOD 0x01 + +/* R8_UEP2_3_MOD */ +#define USBFS_UEP3_RX_EN 0x80 // enable USB endpoint 3 receiving (OUT) +#define USBFS_UEP3_TX_EN 0x40 // enable USB endpoint 3 transmittal (IN) +#define USBFS_UEP3_BUF_MOD 0x10 // buffer mode of USB endpoint 3 +#define USBFS_UEP2_RX_EN 0x08 // enable USB endpoint 2 receiving (OUT) +#define USBFS_UEP2_TX_EN 0x04 // enable USB endpoint 2 transmittal (IN) +#define USBFS_UEP2_BUF_MOD 0x01 // buffer mode of USB endpoint 2 + +/* R8_UEP5_6_MOD */ +#define USBFS_UEP6_RX_EN 0x80 // enable USB endpoint 6 receiving (OUT) +#define USBFS_UEP6_TX_EN 0x40 // enable USB endpoint 6 transmittal (IN) +#define USBFS_UEP6_BUF_MOD 0x10 // buffer mode of USB endpoint 6 +#define USBFS_UEP5_RX_EN 0x08 // enable USB endpoint 5 receiving (OUT) +#define USBFS_UEP5_TX_EN 0x04 // enable USB endpoint 5 transmittal (IN) +#define USBFS_UEP5_BUF_MOD 0x01 // buffer mode of USB endpoint 5 + +/* R8_UEP7_MOD */ +#define USBFS_UEP7_RX_EN 0x08 // enable USB endpoint 7 receiving (OUT) +#define USBFS_UEP7_TX_EN 0x04 // enable USB endpoint 7 transmittal (IN) +#define USBFS_UEP7_BUF_MOD 0x01 // buffer mode of USB endpoint 7 + +/* R8_UEPn_TX_CTRL */ +#define USBFS_UEP_T_AUTO_TOG 0x08 // enable automatic toggle after successful transfer completion on endpoint 1/2/3: 0=manual toggle, 1=automatic toggle +#define USBFS_UEP_T_TOG 0x04 // prepared data toggle flag of USB endpoint X transmittal (IN): 0=DATA0, 1=DATA1 +#define USBFS_UEP_T_RES_MASK 0x03 // bit mask of handshake response type for USB endpoint X transmittal (IN) +#define USBFS_UEP_T_RES_ACK 0x00 +#define USBFS_UEP_T_RES_NONE 0x01 +#define USBFS_UEP_T_RES_NAK 0x02 +#define USBFS_UEP_T_RES_STALL 0x03 +// bUEP_T_RES1 & bUEP_T_RES0: handshake response type for USB endpoint X transmittal (IN) +// 00: DATA0 or DATA1 then expecting ACK (ready) +// 01: DATA0 or DATA1 then expecting no response, time out from host, for non-zero endpoint isochronous transactions +// 10: NAK (busy) +// 11: STALL (error) +// host aux setup + +/* R8_UEPn_RX_CTRL, n=0-7 */ +#define USBFS_UEP_R_AUTO_TOG 0x08 // enable automatic toggle after successful transfer completion on endpoint 1/2/3: 0=manual toggle, 1=automatic toggle +#define USBFS_UEP_R_TOG 0x04 // expected data toggle flag of USB endpoint X receiving (OUT): 0=DATA0, 1=DATA1 +#define USBFS_UEP_R_RES_MASK 0x03 // bit mask of handshake response type for USB endpoint X receiving (OUT) +#define USBFS_UEP_R_RES_ACK 0x00 +#define USBFS_UEP_R_RES_NONE 0x01 +#define USBFS_UEP_R_RES_NAK 0x02 +#define USBFS_UEP_R_RES_STALL 0x03 +// RB_UEP_R_RES1 & RB_UEP_R_RES0: handshake response type for USB endpoint X receiving (OUT) +// 00: ACK (ready) +// 01: no response, time out to host, for non-zero endpoint isochronous transactions +// 10: NAK (busy) +// 11: STALL (error) + +/* R8_UHOST_CTRL */ +#define USBFS_UH_PD_DIS 0x80 // disable USB UDP/UDM pulldown resistance: 0=enable pulldown, 1=disable +#define USBFS_UH_DP_PIN 0x20 // ReadOnly: indicate current UDP pin level +#define USBFS_UH_DM_PIN 0x10 // ReadOnly: indicate current UDM pin level +#define USBFS_UH_LOW_SPEED 0x04 // enable USB port low speed: 0=full speed, 1=low speed +#define USBFS_UH_BUS_RESET 0x02 // control USB bus reset: 0=normal, 1=force bus reset +#define USBFS_UH_PORT_EN 0x01 // enable USB port: 0=disable, 1=enable port, automatic disabled if USB device detached + +/* R32_UH_EP_MOD */ +#define USBFS_UH_EP_TX_EN 0x40 // enable USB host OUT endpoint transmittal +#define USBFS_UH_EP_TBUF_MOD 0x10 // buffer mode of USB host OUT endpoint +#define USBFS_UH_EP_RX_EN 0x08 // enable USB host IN endpoint receiving +#define USBFS_UH_EP_RBUF_MOD 0x01 // buffer mode of USB host IN endpoint + +/* R16_UH_SETUP */ +#define USBFS_UH_PRE_PID_EN 0x0400 // USB host PRE PID enable for low speed device via hub +#define USBFS_UH_SOF_EN 0x0004 // USB host automatic SOF enable + +/* R8_UH_EP_PID */ +#define USBFS_UH_TOKEN_MASK 0xF0 // bit mask of token PID for USB host transfer +#define USBFS_UH_ENDP_MASK 0x0F // bit mask of endpoint number for USB host transfer + +/* R8_UH_RX_CTRL */ +#define USBFS_UH_R_AUTO_TOG 0x08 // enable automatic toggle after successful transfer completion: 0=manual toggle, 1=automatic toggle +#define USBFS_UH_R_TOG 0x04 // expected data toggle flag of host receiving (IN): 0=DATA0, 1=DATA1 +#define USBFS_UH_R_RES 0x01 // prepared handshake response type for host receiving (IN): 0=ACK (ready), 1=no response, time out to device, for isochronous transactions + +/* R8_UH_TX_CTRL */ +#define USBFS_UH_T_AUTO_TOG 0x08 // enable automatic toggle after successful transfer completion: 0=manual toggle, 1=automatic toggle +#define USBFS_UH_T_TOG 0x04 // prepared data toggle flag of host transmittal (SETUP/OUT): 0=DATA0, 1=DATA1 +#define USBFS_UH_T_RES 0x01 // expected handshake response type for host transmittal (SETUP/OUT): 0=ACK (ready), 1=no response, time out from device, for isochronous transactions + +/*******************************************************************************/ +/* Struct Definition */ + +/* USB Setup Request */ +typedef struct __attribute__((packed)) _USB_SETUP_REQ +{ + uint8_t bRequestType; + uint8_t bRequest; + uint16_t wValue; + uint16_t wIndex; + uint16_t wLength; +} USB_SETUP_REQ, *PUSB_SETUP_REQ; + +/* USB Device Descriptor */ +typedef struct __attribute__((packed)) _USB_DEVICE_DESCR +{ + uint8_t bLength; + uint8_t bDescriptorType; + uint16_t bcdUSB; + uint8_t bDeviceClass; + uint8_t bDeviceSubClass; + uint8_t bDeviceProtocol; + uint8_t bMaxPacketSize0; + uint16_t idVendor; + uint16_t idProduct; + uint16_t bcdDevice; + uint8_t iManufacturer; + uint8_t iProduct; + uint8_t iSerialNumber; + uint8_t bNumConfigurations; +} USB_DEV_DESCR, *PUSB_DEV_DESCR; + +/* USB Configuration Descriptor */ +typedef struct __attribute__((packed)) _USB_CONFIG_DESCR +{ + uint8_t bLength; + uint8_t bDescriptorType; + uint16_t wTotalLength; + uint8_t bNumInterfaces; + uint8_t bConfigurationValue; + uint8_t iConfiguration; + uint8_t bmAttributes; + uint8_t MaxPower; +} USB_CFG_DESCR, *PUSB_CFG_DESCR; + +/* USB Interface Descriptor */ +typedef struct __attribute__((packed)) _USB_INTERF_DESCR +{ + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bInterfaceNumber; + uint8_t bAlternateSetting; + uint8_t bNumEndpoints; + uint8_t bInterfaceClass; + uint8_t bInterfaceSubClass; + uint8_t bInterfaceProtocol; + uint8_t iInterface; +} USB_ITF_DESCR, *PUSB_ITF_DESCR; + +/* USB Endpoint Descriptor */ +typedef struct __attribute__((packed)) _USB_ENDPOINT_DESCR +{ + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bEndpointAddress; + uint8_t bmAttributes; + uint8_t wMaxPacketSizeL; + uint8_t wMaxPacketSizeH; + uint8_t bInterval; +} USB_ENDP_DESCR, *PUSB_ENDP_DESCR; + +/* USB Configuration Descriptor Set */ +typedef struct __attribute__((packed)) _USB_CONFIG_DESCR_LONG +{ + USB_CFG_DESCR cfg_descr; + USB_ITF_DESCR itf_descr; + USB_ENDP_DESCR endp_descr[ 1 ]; +} USB_CFG_DESCR_LONG, *PUSB_CFG_DESCR_LONG; + +/* USB HUB Descriptor */ +typedef struct __attribute__((packed)) _USB_HUB_DESCR +{ + uint8_t bDescLength; + uint8_t bDescriptorType; + uint8_t bNbrPorts; + uint8_t wHubCharacteristicsL; + uint8_t wHubCharacteristicsH; + uint8_t bPwrOn2PwrGood; + uint8_t bHubContrCurrent; + uint8_t DeviceRemovable; + uint8_t PortPwrCtrlMask; +} USB_HUB_DESCR, *PUSB_HUB_DESCR; + +/* USB HID Descriptor */ +typedef struct __attribute__((packed)) _USB_HID_DESCR +{ + uint8_t bLength; + uint8_t bDescriptorType; + uint16_t bcdHID; + uint8_t bCountryCode; + uint8_t bNumDescriptors; + uint8_t bDescriptorTypeX; + uint8_t wDescriptorLengthL; + uint8_t wDescriptorLengthH; +} USB_HID_DESCR, *PUSB_HID_DESCR; + +/* USB UDisk */ +typedef struct __attribute__((packed)) _UDISK_BOC_CBW +{ + uint32_t mCBW_Sig; + uint32_t mCBW_Tag; + uint32_t mCBW_DataLen; + uint8_t mCBW_Flag; + uint8_t mCBW_LUN; + uint8_t mCBW_CB_Len; + uint8_t mCBW_CB_Buf[ 16 ]; +} UDISK_BOC_CBW, *PXUDISK_BOC_CBW; + +/* USB UDisk */ +typedef struct __attribute__((packed)) _UDISK_BOC_CSW +{ + uint32_t mCBW_Sig; + uint32_t mCBW_Tag; + uint32_t mCSW_Residue; + uint8_t mCSW_Status; +} UDISK_BOC_CSW, *PXUDISK_BOC_CSW; + + +#ifdef __cplusplus +} +#endif + +#endif /*_CH32L103_USB_H */ diff --git a/ZDBMS/BMS_CC/Peripheral/inc/ch32l103_usbpd.h b/ZDBMS/BMS_CC/Peripheral/inc/ch32l103_usbpd.h new file mode 100644 index 0000000..f95caba --- /dev/null +++ b/ZDBMS/BMS_CC/Peripheral/inc/ch32l103_usbpd.h @@ -0,0 +1,408 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32l103_can.h + * Author : WCH + * Version : V1.0.0 + * Date : 2023/07/08 + * Description : This file contains all the functions prototypes for the + * CAN firmware library. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#ifndef __CH32L103_USBPD_H +#define __CH32L103_USBPD_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "ch32l103.h" + +#ifndef VOID +#define VOID void +#endif +#ifndef CONST +#define CONST const +#endif +#ifndef BOOL +typedef unsigned char BOOL; +#endif +#ifndef BOOLEAN +typedef unsigned char BOOLEAN; +#endif +#ifndef CHAR +typedef char CHAR; +#endif +#ifndef INT8 +typedef char INT8; +#endif +#ifndef INT16 +typedef short INT16; +#endif +#ifndef INT32 +typedef long INT32; +#endif +#ifndef UINT8 +typedef unsigned char UINT8; +#endif +#ifndef UINT16 +typedef unsigned short UINT16; +#endif +#ifndef UINT32 +typedef unsigned long UINT32; +#endif +#ifndef UINT8V +typedef unsigned char volatile UINT8V; +#endif +#ifndef UINT16V +typedef unsigned short volatile UINT16V; +#endif +#ifndef UINT32V +typedef unsigned long volatile UINT32V; +#endif + +#ifndef PVOID +typedef void *PVOID; +#endif +#ifndef PCHAR +typedef char *PCHAR; +#endif +#ifndef PCHAR +typedef const char *PCCHAR; +#endif +#ifndef PINT8 +typedef char *PINT8; +#endif +#ifndef PINT16 +typedef short *PINT16; +#endif +#ifndef PINT32 +typedef long *PINT32; +#endif +#ifndef PUINT8 +typedef unsigned char *PUINT8; +#endif +#ifndef PUINT16 +typedef unsigned short *PUINT16; +#endif +#ifndef PUINT32 +typedef unsigned long *PUINT32; +#endif +#ifndef PUINT8V +typedef volatile unsigned char *PUINT8V; +#endif +#ifndef PUINT16V +typedef volatile unsigned short *PUINT16V; +#endif +#ifndef PUINT32V +typedef volatile unsigned long *PUINT32V; +#endif + + /******************************************************************************/ +/* Related macro definitions */ + +/* Define the return value of the function */ +#ifndef SUCCESS +#define SUCCESS 0 +#endif +#ifndef FAIL +#define FAIL 0xFF +#endif + +/* Register Bit Definition */ +/* USBPD->CONFIG */ +#define PD_FILT_ED (1<<0) /* PD pin input filter enable */ +#define PD_ALL_CLR (1<<1) /* Clear all interrupt flags */ +#define CC_SEL (1<<2) /* Select PD communication port */ +#define PD_DMA_EN (1<<3) /* Enable DMA for USBPD */ +#define PD_RST_EN (1<<4) /* PD mode reset command enable */ +#define WAKE_POLAR (1<<5) /* PD port wake-up level */ +#define IE_PD_IO (1<<10) /* PD IO interrupt enable */ +#define IE_RX_BIT (1<<11) /* Receive bit interrupt enable */ +#define IE_RX_BYTE (1<<12) /* Receive byte interrupt enable */ +#define IE_RX_ACT (1<<13) /* Receive completion interrupt enable */ +#define IE_RX_RESET (1<<14) /* Reset interrupt enable */ +#define IE_TX_END (1<<15) /* Transfer completion interrupt enable */ + +/* USBPD->CONTROL */ +#define PD_TX_EN (1<<0) /* USBPD transceiver mode and transmit enable */ +#define BMC_START (1<<1) /* BMC send start signal */ +#define RX_STATE_0 (1<<2) /* PD received state bit 0 */ +#define RX_STATE_1 (1<<3) /* PD received state bit 1 */ +#define RX_STATE_2 (1<<4) /* PD received state bit 2 */ +#define DATA_FLAG (1<<5) /* Cache data valid flag bit */ +#define TX_BIT_BACK (1<<6) /* Indicates the current bit status of the BMC when sending the code */ +#define BMC_BYTE_HI (1<<7) /* Indicates the current half-byte status of the PD data being sent and received */ + +/* USBPD->TX_SEL */ +#define TX_SEL1 (0<<0) +#define TX_SEL1_SYNC1 (0<<0) /* 0-SYNC1 */ +#define TX_SEL1_RST1 (1<<0) /* 1-RST1 */ +#define TX_SEL2_Mask (3<<2) +#define TX_SEL2_SYNC1 (0<<2) /* 00-SYNC1 */ +#define TX_SEL2_SYNC3 (1<<2) /* 01-SYNC3 */ +#define TX_SEL2_RST1 (2<<2) /* 1x-RST1 */ +#define TX_SEL3_Mask (3<<4) +#define TX_SEL3_SYNC1 (0<<4) /* 00-SYNC1 */ +#define TX_SEL3_SYNC3 (1<<4) /* 01-SYNC3 */ +#define TX_SEL3_RST1 (2<<4) /* 1x-RST1 */ +#define TX_SEL4_Mask (3<<6) +#define TX_SEL4_SYNC2 (0<<6) /* 00-SYNC2 */ +#define TX_SEL4_SYNC3 (1<<6) /* 01-SYNC3 */ +#define TX_SEL4_RST2 (2<<6) /* 1x-RST2 */ + +/* USBPD->STATUS */ +#define BMC_AUX (3<<0) /* BMC auxiliary information */ +#define BMC_AUX_INVALID (0<<0) /* 00-Invalid */ +#define BMC_AUX_SOP0 (1<<0) /* 01-SOP0 */ +#define BMC_AUX_SOP1_HRST (2<<0) /* 10-SOP1 hard reset */ +#define BMC_AUX_SOP2_CRST (3<<0) /* 11-SOP2 cable reset */ +#define BUF_ERR (1<<2) /* BUFFER or DMA error interrupt flag */ +#define IF_RX_BIT (1<<3) /* Receive bit or 5bit interrupt flag */ +#define IF_RX_BYTE (1<<4) /* Receive byte or SOP interrupt flag */ +#define IF_RX_ACT (1<<5) /* Receive completion interrupt flag */ +#define IF_RX_RESET (1<<6) /* Receive reset interrupt flag */ +#define IF_TX_END (1<<7) /* Transfer completion interrupt flag */ + +/* USBPD->PORT_CC1 */ +/* USBPD->PORT_CC2 */ +#define PA_CC_AI (1<<0) /* CC port comparator analogue input */ +#define CC_PD (1<<1) /* CC port pull-down resistor enable */ +#define CC_PU_Mask (3<<2) /* Clear CC port pull-up current */ +#define CC_NO_PU (0<<2) /* 00-Prohibit pull-up current */ +#define CC_PU_330 (1<<2) /* 01-330uA */ +#define CC_PU_180 (2<<2) /* 10-180uA */ +#define CC_PU_80 (3<<2) /* 11-80uA */ +#define CC_LVE (1<<4) /* CC port output low voltage enable */ +#define CC_CE (7<<5) /* Enable the voltage comparator on port CC */ +#define CC_NO_CMP (0<<5) /* 000-closed */ +#define CC_CMP_22 (2<<5) /* 010-0.22V */ +#define CC_CMP_45 (3<<5) /* 011-0.45V */ +#define CC_CMP_55 (4<<5) /* 100-0.55V */ +#define CC_CMP_66 (5<<5) /* 101-0.66V */ +#define CC_CMP_95 (6<<5) /* 110-0.95V */ +#define CC_CMP_123 (7<<5) /* 111-1.23V */ + +#define USBPD_IN_HVT (1<<9) +/********************************************************* +* PD pin PB6/PB7 high threshold input mode: +* 1: High threshold input (2.2V typical), to reduce the I/O power consumption during PD communication +* 0: Normal GPIO threshold input +* *******************************************************/ + +/* Control Message Types */ +#define DEF_TYPE_RESERVED 0x00 +#define DEF_TYPE_GOODCRC 0x01 /* Send By: Source,Sink,Cable Plug */ +#define DEF_TYPE_GOTOMIN 0x02 /* Send By: Source */ +#define DEF_TYPE_ACCEPT 0x03 /* Send By: Source,Sink,Cable Plug */ +#define DEF_TYPE_REJECT 0x04 /* Send By: Source,Sink,Cable Plug */ +#define DEF_TYPE_PING 0x05 /* Send By: Source */ +#define DEF_TYPE_PS_RDY 0x06 /* Send By: Source,Sink */ +#define DEF_TYPE_GET_SRC_CAP 0x07 /* Send By: Sink,DRP */ +#define DEF_TYPE_GET_SNK_CAP 0x08 /* Send By: Source,DRP */ +#define DEF_TYPE_DR_SWAP 0x09 /* Send By: Source,Sink */ +#define DEF_TYPE_PR_SWAP 0x0A /* Send By: Source,Sink */ +#define DEF_TYPE_VCONN_SWAP 0x0B /* Send By: Source,Sink */ +#define DEF_TYPE_WAIT 0x0C /* Send By: Source,Sink */ +#define DEF_TYPE_SOFT_RESET 0x0D /* Send By: Source,Sink */ +#define DEF_TYPE_DATA_RESET 0x0E /* Send By: Source,Sink */ +#define DEF_TYPE_DATA_RESET_CMP 0x0F /* Send By: Source,Sink */ +#define DEF_TYPE_NOT_SUPPORT 0x10 /* Send By: Source,Sink,Cable Plug */ +#define DEF_TYPE_GET_SRC_CAP_EX 0x11 /* Send By: Sink,DRP */ +#define DEF_TYPE_GET_STATUS 0x12 /* Send By: Source,Sink */ +#define DEF_TYPE_GET_STATUS_R 0X02 /* ext=1 */ +#define DEF_TYPE_FR_SWAP 0x13 /* Send By: Sink */ +#define DEF_TYPE_GET_PPS_STATUS 0x14 /* Send By: Sink */ +#define DEF_TYPE_GET_CTY_CODES 0x15 /* Send By: Source,Sink */ +#define DEF_TYPE_GET_SNK_CAP_EX 0x16 /* Send By: Source,DRP */ +#define DEF_TYPE_GET_SRC_INFO 0x17 /* Send By: Sink,DRP */ +#define DEF_TYPE_GET_REVISION 0x18 /* Send By: Source,Sink */ + +/* Data Message Types */ +#define DEF_TYPE_SRC_CAP 0x01 /* Send By: Source,Dual-Role Power */ +#define DEF_TYPE_REQUEST 0x02 /* Send By: Sink */ +#define DEF_TYPE_BIST 0x03 /* Send By: Tester,Source,Sink */ +#define DEF_TYPE_SNK_CAP 0x04 /* Send By: Sink,Dual-Role Power */ +#define DEF_TYPE_BAT_STATUS 0x05 /* Send By: Source,Sink */ +#define DEF_TYPE_ALERT 0x06 /* Send By: Source,Sink */ +#define DEF_TYPE_GET_CTY_INFO 0x07 /* Send By: Source,Sink */ +#define DEF_TYPE_ENTER_USB 0x08 /* Send By: DFP */ +#define DEF_TYPE_EPR_REQUEST 0x09 /* Send By: Sink */ +#define DEF_TYPE_EPR_MODE 0x0A /* Send By: Source,Sink */ +#define DEF_TYPE_SRC_INFO 0x0B /* Send By: Source */ +#define DEF_TYPE_REVISION 0x0C /* Send By: Source,Sink,Cable Plug */ +#define DEF_TYPE_VENDOR_DEFINED 0x0F /* Send By: Source,Sink,Cable Plug */ + +/* Vendor Define Message Command */ +#define DEF_VDM_DISC_IDENT 0x01 +#define DEF_VDM_DISC_SVID 0x02 +#define DEF_VDM_DISC_MODE 0x03 +#define DEF_VDM_ENTER_MODE 0x04 +#define DEF_VDM_EXIT_MODE 0x05 +#define DEF_VDM_ATTENTION 0x06 +#define DEF_VDM_DP_S_UPDATE 0x10 +#define DEF_VDM_DP_CONFIG 0x11 + +/* PD Revision */ +#define DEF_PD_REVISION_10 0x00 +#define DEF_PD_REVISION_20 0x01 +#define DEF_PD_REVISION_30 0x02 + + +/* PD PHY Channel */ +#define DEF_PD_CC1 0x00 +#define DEF_PD_CC2 0x01 + +#define PIN_CC1 GPIO_Pin_6 +#define PIN_CC2 GPIO_Pin_7 + +/* PD Tx Status */ +#define DEF_PD_TX_OK 0x00 +#define DEF_PD_TX_FAIL 0x01 + +/* PDO INDEX */ +#define PDO_INDEX_1 1 +#define PDO_INDEX_2 2 +#define PDO_INDEX_3 3 +#define PDO_INDEX_4 4 +#define PDO_INDEX_5 5 + +/******************************************************************************/ +#define UPD_TMR_TX_96M (160-1) /* timer value for USB PD BMC transmittal @Fsys=96MHz */ +#define UPD_TMR_RX_96M (240-1) /* timer value for USB PD BMC receiving @Fsys=96MHz */ +#define UPD_TMR_TX_48M (80-1) /* timer value for USB PD BMC transmittal @Fsys=48MHz */ +#define UPD_TMR_RX_48M (120-1) /* timer value for USB PD BMC receiving @Fsys=48MHz */ +#define UPD_TMR_TX_24M (40-1) /* timer value for USB PD BMC transmittal @Fsys=24MHz */ +#define UPD_TMR_RX_24M (60-1) /* timer value for USB PD BMC receiving @Fsys=24MHz */ +#define UPD_TMR_TX_12M (20-1) /* timer value for USB PD BMC transmittal @Fsys=12MHz */ +#define UPD_TMR_RX_12M (30-1) /* timer value for USB PD BMC receiving @Fsys=12MHz */ + +#define MASK_PD_STAT 0x03 /* Bit mask for current PD status */ +#define PD_RX_SOP0 0x01 /* SOP0 received */ +#define PD_RX_SOP1_HRST 0x02 /* SOP1 or Hard Reset received */ +#define PD_RX_SOP2_CRST 0x03 /* SOP2 or Cable Reset received */ + +#define UPD_SOP0 ( TX_SEL1_SYNC1 | TX_SEL2_SYNC1 | TX_SEL3_SYNC1 | TX_SEL4_SYNC2 ) /* SOP1 */ +#define UPD_SOP1 ( TX_SEL1_SYNC1 | TX_SEL2_SYNC1 | TX_SEL3_SYNC3 | TX_SEL4_SYNC3 ) /* SOP2 */ +#define UPD_SOP2 ( TX_SEL1_SYNC1 | TX_SEL2_SYNC3 | TX_SEL3_SYNC1 | TX_SEL4_SYNC3 ) /* SOP3 */ +#define UPD_HARD_RESET ( TX_SEL1_RST1 | TX_SEL2_RST1 | TX_SEL3_RST1 | TX_SEL4_RST2 ) /* Hard Reset*/ +#define UPD_CABLE_RESET ( TX_SEL1_RST1 | TX_SEL2_SYNC1 | TX_SEL3_RST1 | TX_SEL4_SYNC3 ) /* Cable Reset*/ + + +#define bCC_CMP_22 0X01 +#define bCC_CMP_45 0X02 +#define bCC_CMP_55 0X04 +#define bCC_CMP_66 0X08 +#define bCC_CMP_95 0X10 +#define bCC_CMP_123 0X20 +#define bCC_CMP_220 0X40 + +/******************************************************************************/ +/* PD State Machine */ +typedef enum +{ + STA_IDLE = 0, /* 0: No task status */ + STA_DISCONNECT, /* 1: Disconnection */ + STA_SRC_CONNECT, /* 2: SRC connect */ + STA_RX_SRC_CAP_WAIT, /* 3: Waiting to receive SRC_CAP */ + STA_RX_SRC_CAP, /* 4: SRC_CAP received */ + STA_TX_REQ, /* 5: Send REQUEST */ + STA_RX_ACCEPT_WAIT, /* 6: Waiting to receive ACCEPT */ + STA_RX_ACCEPT, /* 7: ACCEPT received */ + STA_RX_REJECT, /* 8: REJECT received */ + STA_RX_PS_RDY_WAIT, /* 9: Waiting to receive PS_RDY */ + STA_RX_PS_RDY, /* 10: PS_RDY received */ + STA_SINK_CONNECT, /* 11: SNK access */ + STA_TX_SRC_CAP, /* 12: Send SRC_CAP */ + STA_RX_REQ_WAIT, /* 13: Waiting to receive REQUEST */ + STA_RX_REQ, /* 14: REQUEST received */ + STA_TX_ACCEPT, /* 15: Send ACCEPT */ + STA_TX_REJECT, /* 16: Send REJECT */ + STA_ADJ_VOL, /* 17: Adjustment of output voltage and current */ + STA_TX_PS_RDY, /* 18: Send PS_RDY */ + STA_TX_DR_SWAP, /* 19: Send DR_SWAP */ + STA_RX_DR_SWAP_ACCEPT, /* 20: Waiting to receive the answer ACCEPT from DR_SWAP */ + STA_TX_PR_SWAP, /* 21: Send PR_SWAP */ + STA_RX_PR_SWAP_ACCEPT, /* 22: Waiting to receive the answer ACCEPT from PR_SWAP */ + STA_RX_PR_SWAP_PS_RDY, /* 23: Waiting to receive the answer PS_RDY from PR_SWAP */ + STA_TX_PR_SWAP_PS_RDY, /* 24: Send answer PS_RDY for PR_SWAP */ + STA_PR_SWAP_RECON_WAIT, /* 25: Wait for PR_SWAP before reconnecting */ + STA_SRC_RECON_WAIT, /* 26: Waiting for SRC to reconnect */ + STA_SINK_RECON_WAIT, /* 27: Waiting for SNK to reconnect */ + STA_RX_APD_PS_RDY_WAIT, /* 28: Waiting for PS_RDY from the receiving adapter */ + STA_RX_APD_PS_RDY, /* 29: PS_RDY received from the adapter */ + STA_MODE_SWITCH, /* 30: Mode switching */ + STA_TX_SOFTRST, /* 31: Sending a software reset */ + STA_TX_HRST, /* 32: Send hardware reset */ + STA_PHY_RST, /* 33: PHY reset */ + STA_APD_IDLE_WAIT, /* 34: Waiting for the adapter to become idle */ +} CC_STATUS; + +/******************************************************************************/ +/* PD Message Header Struct */ +typedef union +{ + struct _Message_Header + { + UINT8 MsgType: 5; /* Message Type */ + UINT8 PDRole: 1; /* 0-UFP; 1-DFP */ + UINT8 SpecRev: 2; /* 00-Rev1.0; 01-Rev2.0; 10-Rev3.0; */ + UINT8 PRRole: 1; /* 0-Sink; 1-Source */ + UINT8 MsgID: 3; + UINT8 NumDO: 3; + UINT8 Ext: 1; + }Message_Header; + UINT16 Data; +}_Message_Header; + +/******************************************************************************/ +/* Bit definition */ +typedef union +{ + struct _BITS_ + { + UINT8 Msg_Recvd: 1; /* Notify the main program of the receipt of a PD packet */ + UINT8 Connected: 1; /* PD Physical Layer Connected Flag */ + UINT8 Stop_Det_Chk: 1; /* 0-Enable detection; 1-Disable disconnection detection */ + UINT8 PD_Role: 1; /* 0-UFP; 1-DFP */ + UINT8 PR_Role: 1; /* 0-Sink; 1-Source */ + UINT8 Auto_Ack_PRRole: 1; /* Role used by auto-responder 0:SINK; 1:SOURCE */ + UINT8 PD_Version: 1; /* PD version 0-PD2.0; 1-PD3.0 */ + UINT8 VDM_Version: 1; /* VDM Version 0-1.0 1-2.0 */ + UINT8 HPD_Connected: 1; /* HPD Physical Layer Connected Flag */ + UINT8 HPD_Det_Chk: 1; /* 0-turn off HPD connection detection; 1-turn on HPD connection detection */ + UINT8 CC_Sel_En: 1; /* 0-CC channel selection toggle enable; 1-CC channel selection toggle disable */ + UINT8 CC_Sel_State: 1; /* 0-CC channel selection switches to 0; 1-CC channel selection switches to 1 */ + UINT8 PD_Comm_Succ: 1; /* 0-PD communication unsuccessful; 1-PD communication successful; */ + UINT8 Recv: 3; + }Bit; + UINT16 Bit_Flag; +}_BIT_FLAG; + +/* PD control-related structures */ +typedef struct _PD_CONTROL +{ + CC_STATUS PD_State; /* PD communication status machine */ + CC_STATUS PD_State_Last; /* PD communication status machine (last value) */ + UINT8 Msg_ID; /* ID of the message sent */ + UINT8 Det_Timer; /* PD connection status detection timing */ + UINT8 Det_Cnt; /* Number of PD connection status detections */ + UINT8 Det_Sel_Cnt; /* Number of SEL toggles for PD connection status detection */ + UINT8 HPD_Det_Timer; /* HPD connection detection timing */ + UINT8 HPD_Det_Cnt; /* HPD pin connection status detection count */ + UINT16 PD_Comm_Timer; /* PD shared timing variables */ + UINT8 ReqPDO_Idx; /* Index of the requested PDO, valid values 1-7 */ + UINT16 PD_BusIdle_Timer; /* Bus Idle Time Timer */ + UINT8 Mode_Try_Cnt; /* Number of retries for current mode, highest bit marks mode */ + UINT8 Err_Op_Cnt; /* Exception operation count */ + UINT8 Adapter_Idle_Cnt; /* Adapter communication idle timing */ + _BIT_FLAG Flag; /* Flag byte bit definition */ +}PD_CONTROL, *pPD_CONTROL; + + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/ZDBMS/BMS_CC/Peripheral/inc/ch32l103_wwdg.h b/ZDBMS/BMS_CC/Peripheral/inc/ch32l103_wwdg.h new file mode 100644 index 0000000..a97fe3f --- /dev/null +++ b/ZDBMS/BMS_CC/Peripheral/inc/ch32l103_wwdg.h @@ -0,0 +1,41 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32l103_wwdg.h + * Author : WCH + * Version : V1.0.0 + * Date : 2023/07/08 + * Description : This file contains all the functions prototypes for the WWDG + * firmware library. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#ifndef __CH32L103_WWDG_H +#define __CH32L103_WWDG_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "ch32l103.h" + +/* WWDG_Prescaler */ +#define WWDG_Prescaler_1 ((uint32_t)0x00000000) +#define WWDG_Prescaler_2 ((uint32_t)0x00000080) +#define WWDG_Prescaler_4 ((uint32_t)0x00000100) +#define WWDG_Prescaler_8 ((uint32_t)0x00000180) + +void WWDG_DeInit(void); +void WWDG_SetPrescaler(uint32_t WWDG_Prescaler); +void WWDG_SetWindowValue(uint8_t WindowValue); +void WWDG_EnableIT(void); +void WWDG_SetCounter(uint8_t Counter); +void WWDG_Enable(uint8_t Counter); +FlagStatus WWDG_GetFlagStatus(void); +void WWDG_ClearFlag(void); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/ZDBMS/BMS_CC/Peripheral/src/ch32l103_adc.c b/ZDBMS/BMS_CC/Peripheral/src/ch32l103_adc.c new file mode 100644 index 0000000..cda926b --- /dev/null +++ b/ZDBMS/BMS_CC/Peripheral/src/ch32l103_adc.c @@ -0,0 +1,1344 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32l103_adc.c + * Author : WCH + * Version : V1.0.1 + * Date : 2025/01/07 + * Description : This file provides all the ADC firmware functions. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#include "ch32l103_adc.h" +#include "ch32l103_rcc.h" + +/* CFG Keys */ +#define CFG_KEY1 ((uint32_t)0x45670123) +#define CFG_KEY2 ((uint32_t)0xCDEF89AB) + +/* ADC DISCNUM mask */ +#define CTLR1_DISCNUM_Reset ((uint32_t)0xFFFF1FFF) + +/* ADC DISCEN mask */ +#define CTLR1_DISCEN_Set ((uint32_t)0x00000800) +#define CTLR1_DISCEN_Reset ((uint32_t)0xFFFFF7FF) + +/* ADC JAUTO mask */ +#define CTLR1_JAUTO_Set ((uint32_t)0x00000400) +#define CTLR1_JAUTO_Reset ((uint32_t)0xFFFFFBFF) + +/* ADC JDISCEN mask */ +#define CTLR1_JDISCEN_Set ((uint32_t)0x00001000) +#define CTLR1_JDISCEN_Reset ((uint32_t)0xFFFFEFFF) + +/* ADC AWDCH mask */ +#define CTLR1_AWDCH_Reset ((uint32_t)0xFFFFFFE0) + +/* ADC Analog watchdog enable mode mask */ +#define CTLR1_AWDMode_Reset ((uint32_t)0xFF3FFDFF) + +/* CTLR1 register Mask */ +#define CTLR1_CLEAR_Mask ((uint32_t)0xE0F0FEFF) + +/* ADC ADON mask */ +#define CTLR2_ADON_Set ((uint32_t)0x00000001) +#define CTLR2_ADON_Reset ((uint32_t)0xFFFFFFFE) + +/* ADC DMA mask */ +#define CTLR2_DMA_Set ((uint32_t)0x00000100) +#define CTLR2_DMA_Reset ((uint32_t)0xFFFFFEFF) + +/* ADC RSTCAL mask */ +#define CTLR2_RSTCAL_Set ((uint32_t)0x00000008) + +/* ADC CAL mask */ +#define CTLR2_CAL_Set ((uint32_t)0x00000004) + +/* ADC SWSTART mask */ +#define CTLR2_SWSTART_Set ((uint32_t)0x00400000) + +/* ADC EXTTRIG mask */ +#define CTLR2_EXTTRIG_Set ((uint32_t)0x00100000) +#define CTLR2_EXTTRIG_Reset ((uint32_t)0xFFEFFFFF) + +/* ADC Software start mask */ +#define CTLR2_EXTTRIG_SWSTART_Set ((uint32_t)0x00500000) +#define CTLR2_EXTTRIG_SWSTART_Reset ((uint32_t)0xFFAFFFFF) + +/* ADC JEXTSEL mask */ +#define CTLR2_JEXTSEL_Reset ((uint32_t)0xFFFF8FFF) + +/* ADC JEXTTRIG mask */ +#define CTLR2_JEXTTRIG_Set ((uint32_t)0x00008000) +#define CTLR2_JEXTTRIG_Reset ((uint32_t)0xFFFF7FFF) + +/* ADC JSWSTART mask */ +#define CTLR2_JSWSTART_Set ((uint32_t)0x00200000) + +/* ADC injected software start mask */ +#define CTLR2_JEXTTRIG_JSWSTART_Set ((uint32_t)0x00208000) +#define CTLR2_JEXTTRIG_JSWSTART_Reset ((uint32_t)0xFFDF7FFF) + +/* ADC TSPD mask */ +#define CTLR2_TSVREFE_Set ((uint32_t)0x00800000) +#define CTLR2_TSVREFE_Reset ((uint32_t)0xFF7FFFFF) + +/* CTLR2 register Mask */ +#define CTLR2_CLEAR_Mask ((uint32_t)0xFFF1F7FD) + +/* ADC SQx mask */ +#define RSQR3_SQ_Set ((uint32_t)0x0000001F) +#define RSQR2_SQ_Set ((uint32_t)0x0000001F) +#define RSQR1_SQ_Set ((uint32_t)0x0000001F) + +/* RSQR1 register Mask */ +#define RSQR1_CLEAR_Mask ((uint32_t)0xFF0FFFFF) + +/* ADC JSQx mask */ +#define ISQR_JSQ_Set ((uint32_t)0x0000001F) + +/* ADC JL mask */ +#define ISQR_JL_Set ((uint32_t)0x00300000) +#define ISQR_JL_Reset ((uint32_t)0xFFCFFFFF) + +/* ADC SMPx mask */ +#define SAMPTR1_SMP_Set ((uint32_t)0x00000007) +#define SAMPTR2_SMP_Set ((uint32_t)0x00000007) + +/* ADC IDATARx registers offset */ +#define IDATAR_Offset ((uint8_t)0x28) + +/* ADC1 RDATAR register base address */ +#define RDATAR_ADDRESS ((uint32_t)0x4001244C) + + +/********************************************************************* + * @fn ADC_DeInit + * + * @brief Deinitializes the ADCx peripheral registers to their default + * reset values. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * + * @return none + */ +void ADC_DeInit(ADC_TypeDef *ADCx) +{ + if(ADCx == ADC1) + { + RCC_PB2PeriphResetCmd(RCC_PB2Periph_ADC1, ENABLE); + RCC_PB2PeriphResetCmd(RCC_PB2Periph_ADC1, DISABLE); + } +} + +/********************************************************************* + * @fn ADC_Init + * + * @brief Initializes the ADCx peripheral according to the specified + * parameters in the ADC_InitStruct. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * ADC_InitStruct - pointer to an ADC_InitTypeDef structure that + * contains the configuration information for the specified ADC + * peripheral. + * + * @return none + */ +void ADC_Init(ADC_TypeDef *ADCx, ADC_InitTypeDef *ADC_InitStruct) +{ + uint32_t tmpreg1 = 0; + uint8_t tmpreg2 = 0; + + tmpreg1 = ADCx->CTLR1; + tmpreg1 &= CTLR1_CLEAR_Mask; + tmpreg1 |= (uint32_t)(ADC_InitStruct->ADC_Mode | (uint32_t)ADC_InitStruct->ADC_OutputBuffer | + (uint32_t)ADC_InitStruct->ADC_Pga | ((uint32_t)ADC_InitStruct->ADC_ScanConvMode << 8)); + ADCx->CTLR1 = tmpreg1; + + tmpreg1 = ADCx->CTLR2; + tmpreg1 &= CTLR2_CLEAR_Mask; + tmpreg1 |= (uint32_t)(ADC_InitStruct->ADC_DataAlign | ADC_InitStruct->ADC_ExternalTrigConv | + ((uint32_t)ADC_InitStruct->ADC_ContinuousConvMode << 1)); + ADCx->CTLR2 = tmpreg1; + + tmpreg1 = ADCx->RSQR1; + tmpreg1 &= RSQR1_CLEAR_Mask; + tmpreg2 |= (uint8_t)(ADC_InitStruct->ADC_NbrOfChannel - (uint8_t)1); + tmpreg1 |= (uint32_t)tmpreg2 << 20; + ADCx->RSQR1 = tmpreg1; +} + +/********************************************************************* + * @fn ADC_StructInit + * + * @brief Fills each ADC_InitStruct member with its default value. + * + * @param ADC_InitStruct - pointer to an ADC_InitTypeDef structure that + * contains the configuration information for the specified ADC + * peripheral. + * + * @return none + */ +void ADC_StructInit(ADC_InitTypeDef *ADC_InitStruct) +{ + ADC_InitStruct->ADC_Mode = ADC_Mode_Independent; + ADC_InitStruct->ADC_ScanConvMode = DISABLE; + ADC_InitStruct->ADC_ContinuousConvMode = DISABLE; + ADC_InitStruct->ADC_ExternalTrigConv = ADC_ExternalTrigConv_T1_CC1; + ADC_InitStruct->ADC_DataAlign = ADC_DataAlign_Right; + ADC_InitStruct->ADC_NbrOfChannel = 1; +} + +/********************************************************************* + * @fn ADC_Cmd + * + * @brief Enables or disables the specified ADC peripheral. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void ADC_Cmd(ADC_TypeDef *ADCx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + ADCx->CTLR2 |= CTLR2_ADON_Set; + } + else + { + ADCx->CTLR2 &= CTLR2_ADON_Reset; + } +} + +/********************************************************************* + * @fn ADC_DMACmd + * + * @brief Enables or disables the specified ADC DMA request. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void ADC_DMACmd(ADC_TypeDef *ADCx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + ADCx->CTLR2 |= CTLR2_DMA_Set; + } + else + { + ADCx->CTLR2 &= CTLR2_DMA_Reset; + } +} + +/********************************************************************* + * @fn ADC_ITConfig + * + * @brief Enables or disables the specified ADC interrupts. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * ADC_IT - specifies the ADC interrupt sources to be enabled or disabled. + * ADC_IT_EOC - End of conversion interrupt mask. + * ADC_IT_AWD - Analog watchdog interrupt mask. + * ADC_IT_JEOC - End of injected conversion interrupt mask. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void ADC_ITConfig(ADC_TypeDef *ADCx, uint16_t ADC_IT, FunctionalState NewState) +{ + uint8_t itmask = 0; + + itmask = (uint8_t)ADC_IT; + + if(NewState != DISABLE) + { + ADCx->CTLR1 |= itmask; + } + else + { + ADCx->CTLR1 &= (~(uint32_t)itmask); + } +} + +/********************************************************************* + * @fn ADC_ResetCalibration + * + * @brief Resets the selected ADC calibration registers. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * + * @return none + */ +void ADC_ResetCalibration(ADC_TypeDef *ADCx) +{ + ADCx->CTLR2 |= CTLR2_RSTCAL_Set; +} + +/********************************************************************* + * @fn ADC_GetResetCalibrationStatus + * + * @brief Gets the selected ADC reset calibration registers status. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * + * @return FlagStatus: SET or RESET. + */ +FlagStatus ADC_GetResetCalibrationStatus(ADC_TypeDef *ADCx) +{ + FlagStatus bitstatus = RESET; + + if((ADCx->CTLR2 & CTLR2_RSTCAL_Set) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn ADC_StartCalibration + * + * @brief Starts the selected ADC calibration process. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * + * @return None + */ +void ADC_StartCalibration(ADC_TypeDef *ADCx) +{ + ADCx->CTLR2 |= CTLR2_CAL_Set; +} + +/********************************************************************* + * @fn ADC_GetCalibrationStatus + * + * @brief Gets the selected ADC calibration status. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * + * @return FlagStatus: SET or RESET. + */ +FlagStatus ADC_GetCalibrationStatus(ADC_TypeDef *ADCx) +{ + FlagStatus bitstatus = RESET; + + if((ADCx->CTLR2 & CTLR2_CAL_Set) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn ADC_SoftwareStartConvCmd + * + * @brief Enables or disables the selected ADC software start conversion. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * NewState - ENABLE or DISABLE. + * + * @return None + */ +void ADC_SoftwareStartConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + ADCx->CTLR2 |= CTLR2_EXTTRIG_SWSTART_Set; + } + else + { + ADCx->CTLR2 &= CTLR2_EXTTRIG_SWSTART_Reset; + } +} + +/********************************************************************* + * @fn ADC_GetSoftwareStartConvStatus + * + * @brief Gets the selected ADC Software start conversion Status. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * + * @return FlagStatus - SET or RESET. + */ + +FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef *ADCx) +{ + FlagStatus bitstatus = RESET; + + if((ADCx->CTLR2 & CTLR2_SWSTART_Set) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn ADC_DiscModeChannelCountConfig + * + * @brief Configures the discontinuous mode for the selected ADC regular + * group channel. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * Number - specifies the discontinuous mode regular channel + * count value(1-8). + * + * @return None + */ +void ADC_DiscModeChannelCountConfig(ADC_TypeDef *ADCx, uint8_t Number) +{ + uint32_t tmpreg1 = 0; + uint32_t tmpreg2 = 0; + + tmpreg1 = ADCx->CTLR1; + tmpreg1 &= CTLR1_DISCNUM_Reset; + tmpreg2 = Number - 1; + tmpreg1 |= tmpreg2 << 13; + ADCx->CTLR1 = tmpreg1; +} + +/********************************************************************* + * @fn ADC_DiscModeCmd + * + * @brief Enables or disables the discontinuous mode on regular group + * channel for the specified ADC. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * NewState - ENABLE or DISABLE. + * + * @return None + */ +void ADC_DiscModeCmd(ADC_TypeDef *ADCx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + ADCx->CTLR1 |= CTLR1_DISCEN_Set; + } + else + { + ADCx->CTLR1 &= CTLR1_DISCEN_Reset; + } +} + +/********************************************************************* + * @fn ADC_RegularChannelConfig + * + * @brief Configures for the selected ADC regular channel its corresponding + * rank in the sequencer and its sample time. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * ADC_Channel - the ADC channel to configure. + * ADC_Channel_0 - ADC Channel0 selected. + * ADC_Channel_1 - ADC Channel1 selected. + * ADC_Channel_2 - ADC Channel2 selected. + * ADC_Channel_3 - ADC Channel3 selected. + * ADC_Channel_4 - ADC Channel4 selected. + * ADC_Channel_5 - ADC Channel5 selected. + * ADC_Channel_6 - ADC Channel6 selected. + * ADC_Channel_7 - ADC Channel7 selected. + * ADC_Channel_8 - ADC Channel8 selected. + * ADC_Channel_9 - ADC Channel9 selected. + * ADC_Channel_16 - ADC Channel16 selected. + * ADC_Channel_17 - ADC Channel17 selected. + * Rank - The rank in the regular group sequencer. + * This parameter must be between 1 to 16. + * ADC_SampleTime - The sample time value to be set for the selected channel. + * ADC_SampleTime_CyclesMode0 - Sample time equal to 1.5 cycles(CFG bit[5]-ADC_LP=0). + * - Sample time equal to 7.5 cycles(CFG bit[5]-ADC_LP=1). + * ADC_SampleTime_CyclesMode1 - Sample time equal to 7.5 cycles(CFG bit[5]-ADC_LP=0). + * - Sample time equal to 11.5 cycles(CFG bit[5]-ADC_LP=1). + * ADC_SampleTime_CyclesMode2 - Sample time equal to 13.5 cycles(CFG bit[5]-ADC_LP=0). + * - Sample time equal to 17.5 cycles(CFG bit[5]-ADC_LP=1). + * ADC_SampleTime_CyclesMode3 - Sample time equal to 28.5 cycles(CFG bit[5]-ADC_LP=0). + * - Sample time equal to 27.5 cycles(CFG bit[5]-ADC_LP=1). + * ADC_SampleTime_CyclesMode4 - Sample time equal to 41.5 cycles(CFG bit[5]-ADC_LP=0). + * - Sample time equal to 47.5 cycles(CFG bit[5]-ADC_LP=1). + * ADC_SampleTime_CyclesMode5 - Sample time equal to 55.5 cycles(CFG bit[5]-ADC_LP=0). + * - Sample time equal to 55.5 cycles(CFG bit[5]-ADC_LP=1). + * ADC_SampleTime_CyclesMode6 - Sample time equal to 71.5 cycles(CFG bit[5]-ADC_LP=0). + * - Sample time equal to 71.5 cycles(CFG bit[5]-ADC_LP=1). + * ADC_SampleTime_CyclesMode7 - Sample time equal to 239.5 cycles(CFG bit[5]-ADC_LP=0). + * - Sample time equal to 239.5 cycles(CFG bit[5]-ADC_LP=1). + * + * @return None + */ +void ADC_RegularChannelConfig(ADC_TypeDef *ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime) +{ + uint32_t tmpreg1 = 0, tmpreg2 = 0; + + if(ADC_Channel > ADC_Channel_9) + { + tmpreg1 = ADCx->SAMPTR1; + tmpreg2 = SAMPTR1_SMP_Set << (3 * (ADC_Channel - 10)); + tmpreg1 &= ~tmpreg2; + tmpreg2 = (uint32_t)ADC_SampleTime << (3 * (ADC_Channel - 10)); + tmpreg1 |= tmpreg2; + ADCx->SAMPTR1 = tmpreg1; + } + else + { + tmpreg1 = ADCx->SAMPTR2; + tmpreg2 = SAMPTR2_SMP_Set << (3 * ADC_Channel); + tmpreg1 &= ~tmpreg2; + tmpreg2 = (uint32_t)ADC_SampleTime << (3 * ADC_Channel); + tmpreg1 |= tmpreg2; + ADCx->SAMPTR2 = tmpreg1; + } + + if(Rank < 7) + { + tmpreg1 = ADCx->RSQR3; + tmpreg2 = RSQR3_SQ_Set << (5 * (Rank - 1)); + tmpreg1 &= ~tmpreg2; + tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 1)); + tmpreg1 |= tmpreg2; + ADCx->RSQR3 = tmpreg1; + } + else if(Rank < 13) + { + tmpreg1 = ADCx->RSQR2; + tmpreg2 = RSQR2_SQ_Set << (5 * (Rank - 7)); + tmpreg1 &= ~tmpreg2; + tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 7)); + tmpreg1 |= tmpreg2; + ADCx->RSQR2 = tmpreg1; + } + else + { + tmpreg1 = ADCx->RSQR1; + tmpreg2 = RSQR1_SQ_Set << (5 * (Rank - 13)); + tmpreg1 &= ~tmpreg2; + tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 13)); + tmpreg1 |= tmpreg2; + ADCx->RSQR1 = tmpreg1; + } +} + +/********************************************************************* + * @fn ADC_ExternalTrigConvCmd + * + * @brief Enables or disables the ADCx conversion through external trigger. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * NewState - ENABLE or DISABLE. + * + * @return None + */ +void ADC_ExternalTrigConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + ADCx->CTLR2 |= CTLR2_EXTTRIG_Set; + } + else + { + ADCx->CTLR2 &= CTLR2_EXTTRIG_Reset; + } +} + +/********************************************************************* + * @fn ADC_GetConversionValue + * + * @brief Returns the last ADCx conversion result data for regular channel. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * + * @return ADCx->RDATAR - The Data conversion value. + */ +uint16_t ADC_GetConversionValue(ADC_TypeDef *ADCx) +{ + return (uint16_t)ADCx->RDATAR; +} + +/********************************************************************* + * @fn ADC_GetDualModeConversionValue + * + * @brief Returns the last ADC1 and conversion result data in dual mode. + * + * @return RDATAR_ADDRESS - The Data conversion value. + */ +uint32_t ADC_GetDualModeConversionValue(void) +{ + return (*(__IO uint32_t *)RDATAR_ADDRESS); +} + +/********************************************************************* + * @fn ADC_AutoInjectedConvCmd + * + * @brief Enables or disables the selected ADC automatic injected group + * conversion after regular one. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * NewState - ENABLE or DISABLE. + * + * @return None + */ +void ADC_AutoInjectedConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + ADCx->CTLR1 |= CTLR1_JAUTO_Set; + } + else + { + ADCx->CTLR1 &= CTLR1_JAUTO_Reset; + } +} + +/********************************************************************* + * @fn ADC_InjectedDiscModeCmd + * + * @brief Enables or disables the discontinuous mode for injected group + * channel for the specified ADC. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * NewState - ENABLE or DISABLE. + * + * @return None + */ +void ADC_InjectedDiscModeCmd(ADC_TypeDef *ADCx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + ADCx->CTLR1 |= CTLR1_JDISCEN_Set; + } + else + { + ADCx->CTLR1 &= CTLR1_JDISCEN_Reset; + } +} + +/********************************************************************* + * @fn ADC_ExternalTrigInjectedConvConfig + * + * @brief Configures the ADCx external trigger for injected channels conversion. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * ADC_ExternalTrigInjecConv - specifies the ADC trigger to start + * injected conversion. + * ADC_ExternalTrigInjecConv_T1_TRGO - Timer1 TRGO event selected. + * ADC_ExternalTrigInjecConv_T1_CC4 - Timer1 capture compare4 selected. + * ADC_ExternalTrigInjecConv_T2_TRGO - Timer2 TRGO event selected. + * ADC_ExternalTrigInjecConv_T2_CC1 - Timer2 capture compare1 selected. + * ADC_ExternalTrigInjecConv_T3_CC4 - Timer3 capture compare4 selected. + * ADC_ExternalTrigInjecConv_T4_TRGO - Timer4 TRGO event selected. + * ADC_ExternalTrigInjecConv_Ext_IT15 - External interrupt + * line 15 event selected. + * ADC_ExternalTrigInjecConv_None - Injected conversion started + * by software and not by external trigger. + * + * @return None + */ +void ADC_ExternalTrigInjectedConvConfig(ADC_TypeDef *ADCx, uint32_t ADC_ExternalTrigInjecConv) +{ + uint32_t tmpreg = 0; + + tmpreg = ADCx->CTLR2; + tmpreg &= CTLR2_JEXTSEL_Reset; + tmpreg |= ADC_ExternalTrigInjecConv; + ADCx->CTLR2 = tmpreg; +} + +/********************************************************************* + * @fn ADC_ExternalTrigInjectedConvCmd + * + * @brief Enables or disables the ADCx injected channels conversion through + * external trigger. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * NewState - ENABLE or DISABLE. + * + * @return None + */ +void ADC_ExternalTrigInjectedConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + ADCx->CTLR2 |= CTLR2_JEXTTRIG_Set; + } + else + { + ADCx->CTLR2 &= CTLR2_JEXTTRIG_Reset; + } +} + +/********************************************************************* + * @fn ADC_SoftwareStartInjectedConvCmd + * + * @brief Enables or disables the selected ADC start of the injected + * channels conversion. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * NewState - ENABLE or DISABLE. + * + * @return None + */ +void ADC_SoftwareStartInjectedConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + ADCx->CTLR2 |= CTLR2_JEXTTRIG_JSWSTART_Set; + } + else + { + ADCx->CTLR2 &= CTLR2_JEXTTRIG_JSWSTART_Reset; + } +} + +/********************************************************************* + * @fn ADC_GetSoftwareStartInjectedConvCmdStatus + * + * @brief Gets the selected ADC Software start injected conversion Status. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * + * @return FlagStatus: SET or RESET. + */ +FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_TypeDef *ADCx) +{ + FlagStatus bitstatus = RESET; + + if((ADCx->CTLR2 & CTLR2_JSWSTART_Set) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn ADC_InjectedChannelConfig + * + * @brief Configures for the selected ADC injected channel its corresponding + * rank in the sequencer and its sample time. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * ADC_Channel - the ADC channel to configure. + * ADC_Channel_0 - ADC Channel0 selected. + * ADC_Channel_1 - ADC Channel1 selected. + * ADC_Channel_2 - ADC Channel2 selected. + * ADC_Channel_3 - ADC Channel3 selected. + * ADC_Channel_4 - ADC Channel4 selected. + * ADC_Channel_5 - ADC Channel5 selected. + * ADC_Channel_6 - ADC Channel6 selected. + * ADC_Channel_7 - ADC Channel7 selected. + * ADC_Channel_8 - ADC Channel8 selected. + * ADC_Channel_9 - ADC Channel9 selected. + * ADC_Channel_16 - ADC Channel16 selected. + * ADC_Channel_17 - ADC Channel17 selected. + * Rank - The rank in the regular group sequencer. + * This parameter must be between 1 to 4. + * ADC_SampleTime - The sample time value to be set for the selected channel. + * ADC_SampleTime_1Cycles5 - Sample time equal to 1.5 cycles. + * ADC_SampleTime_7Cycles5 - Sample time equal to 7.5 cycles. + * ADC_SampleTime_13Cycles5 - Sample time equal to 13.5 cycles. + * ADC_SampleTime_28Cycles5 - Sample time equal to 28.5 cycles. + * ADC_SampleTime_41Cycles5 - Sample time equal to 41.5 cycles. + * ADC_SampleTime_55Cycles5 - Sample time equal to 55.5 cycles. + * ADC_SampleTime_71Cycles5 - Sample time equal to 71.5 cycles. + * ADC_SampleTime_239Cycles5 - Sample time equal to 239.5 cycles. + * + * @return None + */ +void ADC_InjectedChannelConfig(ADC_TypeDef *ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime) +{ + uint32_t tmpreg1 = 0, tmpreg2 = 0, tmpreg3 = 0; + + if(ADC_Channel > ADC_Channel_9) + { + tmpreg1 = ADCx->SAMPTR1; + tmpreg2 = SAMPTR1_SMP_Set << (3 * (ADC_Channel - 10)); + tmpreg1 &= ~tmpreg2; + tmpreg2 = (uint32_t)ADC_SampleTime << (3 * (ADC_Channel - 10)); + tmpreg1 |= tmpreg2; + ADCx->SAMPTR1 = tmpreg1; + } + else + { + tmpreg1 = ADCx->SAMPTR2; + tmpreg2 = SAMPTR2_SMP_Set << (3 * ADC_Channel); + tmpreg1 &= ~tmpreg2; + tmpreg2 = (uint32_t)ADC_SampleTime << (3 * ADC_Channel); + tmpreg1 |= tmpreg2; + ADCx->SAMPTR2 = tmpreg1; + } + + tmpreg1 = ADCx->ISQR; + tmpreg3 = (tmpreg1 & ISQR_JL_Set) >> 20; + tmpreg2 = ISQR_JSQ_Set << (5 * (uint8_t)((Rank + 3) - (tmpreg3 + 1))); + tmpreg1 &= ~tmpreg2; + tmpreg2 = (uint32_t)ADC_Channel << (5 * (uint8_t)((Rank + 3) - (tmpreg3 + 1))); + tmpreg1 |= tmpreg2; + ADCx->ISQR = tmpreg1; +} + +/********************************************************************* + * @fn ADC_InjectedSequencerLengthConfig + * + * @brief Configures the sequencer length for injected channels. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * Length - The sequencer length. + * This parameter must be a number between 1 to 4. + * + * @return None + */ +void ADC_InjectedSequencerLengthConfig(ADC_TypeDef *ADCx, uint8_t Length) +{ + uint32_t tmpreg1 = 0; + uint32_t tmpreg2 = 0; + + tmpreg1 = ADCx->ISQR; + tmpreg1 &= ISQR_JL_Reset; + tmpreg2 = Length - 1; + tmpreg1 |= tmpreg2 << 20; + ADCx->ISQR = tmpreg1; +} + +/********************************************************************* + * @fn ADC_SetInjectedOffset + * + * @brief Set the injected channels conversion value offset. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * ADC_InjectedChannel: the ADC injected channel to set its offset. + * ADC_InjectedChannel_1 - Injected Channel1 selected. + * ADC_InjectedChannel_2 - Injected Channel2 selected. + * ADC_InjectedChannel_3 - Injected Channel3 selected. + * ADC_InjectedChannel_4 - Injected Channel4 selected. + * Offset - the offset value for the selected ADC injected channel. + * This parameter must be a 12bit value. + * + * @return None + */ +void ADC_SetInjectedOffset(ADC_TypeDef *ADCx, uint8_t ADC_InjectedChannel, uint16_t Offset) +{ + __IO uint32_t tmp = 0; + + tmp = (uint32_t)ADCx; + tmp += ADC_InjectedChannel; + + *(__IO uint32_t *)tmp = (uint32_t)Offset; +} + +/********************************************************************* + * @fn ADC_GetInjectedConversionValue + * + * @brief Returns the ADC injected channel conversion result. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * ADC_InjectedChannel - the ADC injected channel to set its offset. + * ADC_InjectedChannel_1 - Injected Channel1 selected. + * ADC_InjectedChannel_2 - Injected Channel2 selected. + * ADC_InjectedChannel_3 - Injected Channel3 selected. + * ADC_InjectedChannel_4 - Injected Channel4 selected. + * + * @return tmp - The Data conversion value. + */ +uint16_t ADC_GetInjectedConversionValue(ADC_TypeDef *ADCx, uint8_t ADC_InjectedChannel) +{ + __IO uint32_t tmp = 0; + + tmp = (uint32_t)ADCx; + tmp += ADC_InjectedChannel + IDATAR_Offset; + + return (uint16_t)(*(__IO uint32_t *)tmp); +} + +/********************************************************************* + * @fn ADC_AnalogWatchdogCmd + * + * @brief Enables or disables the analog watchdog on single/all regular + * or injected channels. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * ADC_AnalogWatchdog - the ADC analog watchdog configuration. + * ADC_AnalogWatchdog_SingleRegEnable - Analog watchdog on a + * single regular channel. + * ADC_AnalogWatchdog_SingleInjecEnable - Analog watchdog on a + * single injected channel. + * ADC_AnalogWatchdog_SingleRegOrInjecEnable - Analog watchdog + * on a single regular or injected channel. + * ADC_AnalogWatchdog_AllRegEnable - Analog watchdog on all + * regular channel. + * ADC_AnalogWatchdog_AllInjecEnable - Analog watchdog on all + * injected channel. + * ADC_AnalogWatchdog_AllRegAllInjecEnable - Analog watchdog on + * all regular and injected channels. + * ADC_AnalogWatchdog_None - No channel guarded by the analog + * watchdog. + * + * @return none + */ +void ADC_AnalogWatchdogCmd(ADC_TypeDef *ADCx, uint32_t ADC_AnalogWatchdog) +{ + uint32_t tmpreg = 0; + + tmpreg = ADCx->CTLR1; + tmpreg &= CTLR1_AWDMode_Reset; + tmpreg |= ADC_AnalogWatchdog; + ADCx->CTLR1 = tmpreg; +} + +/********************************************************************* + * @fn ADC_AnalogWatchdogThresholdsConfig + * + * @brief Configures the high and low thresholds of the analog watchdog. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * HighThreshold - the ADC analog watchdog High threshold value. + * This parameter must be a 12bit value. + * LowThreshold - the ADC analog watchdog Low threshold value. + * This parameter must be a 12bit value. + * + * @return none + */ +void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef *ADCx, uint16_t HighThreshold, + uint16_t LowThreshold) +{ + ADCx->WDHTR = HighThreshold; + ADCx->WDLTR = LowThreshold; +} + +/********************************************************************* + * @fn ADC_AnalogWatchdogSingleChannelConfig + * + * @brief Configures the analog watchdog guarded single channel. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * ADC_Channel - the ADC channel to configure. + * ADC_Channel_0 - ADC Channel0 selected. + * ADC_Channel_1 - ADC Channel1 selected. + * ADC_Channel_2 - ADC Channel2 selected. + * ADC_Channel_3 - ADC Channel3 selected. + * ADC_Channel_4 - ADC Channel4 selected. + * ADC_Channel_5 - ADC Channel5 selected. + * ADC_Channel_6 - ADC Channel6 selected. + * ADC_Channel_7 - ADC Channel7 selected. + * ADC_Channel_8 - ADC Channel8 selected. + * ADC_Channel_9 - ADC Channel9 selected. + * ADC_Channel_16 - ADC Channel16 selected. + * ADC_Channel_17 - ADC Channel17 selected. + * + * @return None + */ +void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef *ADCx, uint8_t ADC_Channel) +{ + uint32_t tmpreg = 0; + + tmpreg = ADCx->CTLR1; + tmpreg &= CTLR1_AWDCH_Reset; + tmpreg |= ADC_Channel; + ADCx->CTLR1 = tmpreg; +} + +/********************************************************************* + * @fn ADC_TempSensorVrefintCmd + * + * @brief Enables or disables the temperature sensor and Vrefint channel. + * + * @param NewState - ENABLE or DISABLE. + * + * @return none + */ +void ADC_TempSensorVrefintCmd(FunctionalState NewState) +{ + if(NewState != DISABLE) + { + ADC1->CTLR2 |= CTLR2_TSVREFE_Set; + } + else + { + ADC1->CTLR2 &= CTLR2_TSVREFE_Reset; + } +} + +/********************************************************************* + * @fn ADC_GetFlagStatus + * + * @brief Checks whether the specified ADC flag is set or not. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * ADC_FLAG - specifies the flag to check. + * ADC_FLAG_AWD - Analog watchdog flag. + * ADC_FLAG_EOC - End of conversion flag. + * ADC_FLAG_JEOC - End of injected group conversion flag. + * ADC_FLAG_JSTRT - Start of injected group conversion flag. + * ADC_FLAG_STRT - Start of regular group conversion flag. + * + * @return FlagStatus: SET or RESET. + */ +FlagStatus ADC_GetFlagStatus(ADC_TypeDef *ADCx, uint8_t ADC_FLAG) +{ + FlagStatus bitstatus = RESET; + + if((ADCx->STATR & ADC_FLAG) != (uint8_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn ADC_ClearFlag + * + * @brief Clears the ADCx's pending flags. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * ADC_FLAG - specifies the flag to clear. + * ADC_FLAG_AWD - Analog watchdog flag. + * ADC_FLAG_EOC - End of conversion flag. + * ADC_FLAG_JEOC - End of injected group conversion flag. + * ADC_FLAG_JSTRT - Start of injected group conversion flag. + * ADC_FLAG_STRT - Start of regular group conversion flag. + * + * @return none + */ +void ADC_ClearFlag(ADC_TypeDef *ADCx, uint8_t ADC_FLAG) +{ + ADCx->STATR = ~(uint32_t)ADC_FLAG; +} + +/********************************************************************* + * @fn ADC_GetITStatus + * + * @brief Checks whether the specified ADC interrupt has occurred or not. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * ADC_IT - specifies the ADC interrupt source to check. + * ADC_IT_EOC - End of conversion interrupt mask. + * ADC_IT_AWD - Analog watchdog interrupt mask. + * ADC_IT_JEOC - End of injected conversion interrupt mask. + * + * @return FlagStatus: SET or RESET. + */ +ITStatus ADC_GetITStatus(ADC_TypeDef *ADCx, uint16_t ADC_IT) +{ + ITStatus bitstatus = RESET; + uint32_t itmask = 0, enablestatus = 0; + + itmask = ADC_IT >> 8; + enablestatus = (ADCx->CTLR1 & (uint8_t)ADC_IT); + + if(((ADCx->STATR & itmask) != (uint32_t)RESET) && enablestatus) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn ADC_ClearITPendingBit + * + * @brief Clears the ADCx's interrupt pending bits. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * ADC_IT - specifies the ADC interrupt pending bit to clear. + * ADC_IT_EOC - End of conversion interrupt mask. + * ADC_IT_AWD - Analog watchdog interrupt mask. + * ADC_IT_JEOC - End of injected conversion interrupt mask. + * + * @return none + */ +void ADC_ClearITPendingBit(ADC_TypeDef *ADCx, uint16_t ADC_IT) +{ + uint8_t itmask = 0; + + itmask = (uint8_t)(ADC_IT >> 8); + ADCx->STATR = ~(uint32_t)itmask; +} + +/********************************************************************* + * @fn TempSensor_Volt_To_Temper + * + * @brief Internal Temperature Sensor Voltage to temperature. + * + * @param Value - Voltage Value(mv). + * + * @return Temper - Temperature Value. + */ +s32 TempSensor_Volt_To_Temper(s32 Value) +{ + s32 Temper, Refer_Volt, Refer_Temper; + s32 k = 42; + + Refer_Volt = (s32)((TS_Val) & 0x0000FFFF); + Refer_Temper = (s32)(((TS_Val) >> 16) & 0x0000FFFF); + + Temper = Refer_Temper - ((Value - Refer_Volt) * 10 + (k >> 1)) / k; + + return Temper; +} + +/********************************************************************* + * @fn ADC_BufferCmd + * + * @brief Enables or disables the ADCx buffer. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void ADC_BufferCmd(ADC_TypeDef *ADCx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + ADCx->CTLR1 |= (1 << 26); + } + else + { + ADCx->CTLR1 &= ~(1 << 26); + } +} + +/********************************************************************* + * @fn ADC_TKey_ChannelxMulShieldCmd + * + * @brief Enables or disables TKey Multiplex shielding of the selected ADC channel. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * ADC_Channel - the ADC channel to configure. + * ADC_Channel_0 - ADC Channel0 selected. + * ADC_Channel_1 - ADC Channel1 selected. + * ADC_Channel_2 - ADC Channel2 selected. + * ADC_Channel_3 - ADC Channel3 selected. + * ADC_Channel_4 - ADC Channel4 selected. + * ADC_Channel_5 - ADC Channel5 selected. + * ADC_Channel_6 - ADC Channel6 selected. + * ADC_Channel_7 - ADC Channel7 selected. + * ADC_Channel_8 - ADC Channel8 selected. + * ADC_Channel_9 - ADC Channel9 selected. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void ADC_TKey_ChannelxMulShieldCmd(ADC_TypeDef *ADCx, uint8_t ADC_Channel, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + ADCx->CFG |= ((1<<9)<< ADC_Channel); + } + else + { + ADCx->CFG &= ~((1<<9)<< ADC_Channel); + } +} + +/********************************************************************* + * @fn ADC_TKey_MulShieldCmd + * + * @brief Enables or disables the TKey Multiplex shielding. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void ADC_TKey_MulShieldCmd(ADC_TypeDef *ADCx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + ADCx->CFG |= (1 << 8); + } + else + { + ADCx->CFG &= ~(1 << 8); + } +} + +/********************************************************************* + * @fn ADC_DutyDelayCmd + * + * @brief Enables or disables the Duty delay. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void ADC_DutyDelayCmd(ADC_TypeDef *ADCx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + ADCx->CFG |= (1 << 7); + } + else + { + ADCx->CFG &= ~(1 << 7); + } +} + +/********************************************************************* + * @fn ADC_FIFO_Cmd + * + * @brief Enables or disables the FIFO. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void ADC_FIFO_Cmd(ADC_TypeDef *ADCx, FunctionalState NewState) +{ + FLASH->KEYR = CFG_KEY1; + FLASH->KEYR = CFG_KEY2; + FLASH->MODEKEYR = CFG_KEY1; + FLASH->OBKEYR = CFG_KEY2; + while((*(vu32*)0x40022034) & (1<<29)); // wait unlock + + *(vu32*)0x4002202C |= (1<<9); //offset calibration + (*(vu32*)0x40022034) |= (1<<29); //lock + while(((*(vu32*)0x40022034) & (1<<29)) == 0); //wait lock + + if(NewState != DISABLE) + { + ADCx->CFG |= (1 << 6); + } + else + { + ADCx->CFG &= ~(1 << 6); + } +} + +/********************************************************************* + * @fn ADC_Sample_ModeConfig + * + * @brief Configures the ADC Sample Mode. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * ADC_Sample_Mode - Sample Mode. + * ADC_Sample_NoOver_1M_Mode - sampling rate no over 1M(<=1M) mode. + * ADC_Sample_Over_1M_Mode - sampling rate over 1M(>1M) mode. + * + * @return none + */ +void ADC_Sample_ModeConfig(ADC_TypeDef *ADCx, uint32_t ADC_Sample_Mode) +{ + ADCx->CFG &= ~ADC_Sample_Over_1M_Mode; + ADCx->CFG |= ADC_Sample_Mode; +} + +/********************************************************************* + * @fn ADC_OffsetCalibrationConfig + * + * @brief Configures the Offset Calibration. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * + * @return None + */ +void ADC_OffsetCalibrationConfig(ADC_TypeDef *ADCx) +{ + uint16_t tmp; + + tmp = ADC_Trim; + ADCx->CFG &= ~0x0000000F; + ADCx->CFG |= (uint32_t)((tmp & 0x07) | (((tmp & 0x8000)^0x8000) >> 12)); +} + +/********************************************************************* + * @fn ADC_AnalogWatchdogResetCmd + * + * @brief Enables or disables the analog watch dog reset function. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void ADC_AnalogWatchdogResetCmd(ADC_TypeDef *ADCx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + ADCx->CFG |= (1 << 4); + } + else + { + ADCx->CFG &= ~(1 << 4); + } +} + +/********************************************************************* + * @fn Get_CalibrationValue + * + * @brief Get ADCx Calibration Value. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * + * @return CalibrationValue + */ +int16_t Get_CalibrationValue(ADC_TypeDef *ADCx) +{ + __IO uint8_t i, j; + uint16_t buf[10]; + __IO uint16_t t; + + ADCx->CTLR2|=(7<<17); + ADC_Cmd(ADCx, ENABLE); + ADC_FIFO_Cmd(ADCx, ENABLE); + ADC_ResetCalibration(ADCx); + while(ADC_GetResetCalibrationStatus(ADCx)); + ADC_StartCalibration(ADCx); + while(ADC_GetCalibrationStatus(ADCx)); + ADC_RegularChannelConfig(ADCx, ADC_Channel_CalInternal, 1, ADC_SampleTime_CyclesMode0); + for(i = 0; i < 10; i++) + { + ADC_SoftwareStartConvCmd(ADCx, ENABLE); + while(!ADC_GetFlagStatus(ADCx, ADC_FLAG_EOC)); + buf[i] = ADC_GetConversionValue(ADCx); + } + for(i = 0; i < 10; i++) + { + for(j = 0; j < 9; j++) + { + if(buf[j] > buf[j + 1]) + { + t = buf[j]; + buf[j] = buf[j + 1]; + buf[j + 1] = t; + } + } + } + + t = 0; + for(i = 0; i < 6; i++) + { + t += buf[i + 2]; + } + t = (t / 6) + ((t % 6) / 3); + ADC_Cmd(ADC1, DISABLE); + return (int16_t)(2048 - (int16_t)t); +} + + diff --git a/ZDBMS/BMS_CC/Peripheral/src/ch32l103_bkp.c b/ZDBMS/BMS_CC/Peripheral/src/ch32l103_bkp.c new file mode 100644 index 0000000..ae9869b --- /dev/null +++ b/ZDBMS/BMS_CC/Peripheral/src/ch32l103_bkp.c @@ -0,0 +1,244 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32l103_bkp.c + * Author : WCH + * Version : V1.0.0 + * Date : 2023/07/08 + * Description : This file provides all the BKP firmware functions. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#include "ch32l103_bkp.h" +#include "ch32l103_rcc.h" + +/* BKP registers bit mask */ + +/* OCTLR register bit mask */ +#define OCTLR_CAL_MASK ((uint16_t)0xFF80) +#define OCTLR_MASK ((uint16_t)0xFC7F) + +/********************************************************************* + * @fn BKP_DeInit + * + * @brief Deinitializes the BKP peripheral registers to their default reset values. + * + * @return none + */ +void BKP_DeInit(void) +{ + RCC_BackupResetCmd(ENABLE); + RCC_BackupResetCmd(DISABLE); +} + +/********************************************************************* + * @fn BKP_TamperPinLevelConfig + * + * @brief Configures the Tamper Pin active level. + * + * @param BKP_TamperPinLevel - specifies the Tamper Pin active level. + * BKP_TamperPinLevel_High - Tamper pin active on high level. + * BKP_TamperPinLevel_Low - Tamper pin active on low level. + * + * @return none + */ +void BKP_TamperPinLevelConfig(uint16_t BKP_TamperPinLevel) +{ + if(BKP_TamperPinLevel) + { + BKP->TPCTLR |= (1 << 1); + } + else + { + BKP->TPCTLR &= ~(1 << 1); + } +} + +/********************************************************************* + * @fn BKP_TamperPinCmd + * + * @brief Enables or disables the Tamper Pin activation. + * + * @param NewState - ENABLE or DISABLE. + * + * @return none + */ +void BKP_TamperPinCmd(FunctionalState NewState) +{ + if(NewState) + { + BKP->TPCTLR |= (1 << 0); + } + else + { + BKP->TPCTLR &= ~(1 << 0); + } +} + +/********************************************************************* + * @fn BKP_ITConfig + * + * @brief Enables or disables the Tamper Pin Interrupt. + * + * @param NewState - ENABLE or DISABLE. + * + * @return none + */ +void BKP_ITConfig(FunctionalState NewState) +{ + if(NewState) + { + BKP->TPCSR |= (1 << 2); + } + else + { + BKP->TPCSR &= ~(1 << 2); + } +} + +/********************************************************************* + * @fn BKP_RTCOutputConfig + * + * @brief Select the RTC output source to output on the Tamper pin. + * + * @param BKP_RTCOutputSource - specifies the RTC output source. + * BKP_RTCOutputSource_None - no RTC output on the Tamper pin. + * BKP_RTCOutputSource_CalibClock - output the RTC clock with + * frequency divided by 64 on the Tamper pin. + * BKP_RTCOutputSource_Alarm - output the RTC Alarm pulse signal + * on the Tamper pin. + * BKP_RTCOutputSource_Second - output the RTC Second pulse + * signal on the Tamper pin. + * + * @return none + */ +void BKP_RTCOutputConfig(uint16_t BKP_RTCOutputSource) +{ + uint16_t tmpreg = 0; + + tmpreg = BKP->OCTLR; + tmpreg &= OCTLR_MASK; + tmpreg |= BKP_RTCOutputSource; + BKP->OCTLR = tmpreg; +} + +/********************************************************************* + * @fn BKP_SetRTCCalibrationValue + * + * @brief Sets RTC Clock Calibration value. + * + * @param CalibrationValue - specifies the RTC Clock Calibration value. + * This parameter must be a number between 0 and 0x1F. + * + * @return none + */ +void BKP_SetRTCCalibrationValue(uint8_t CalibrationValue) +{ + uint16_t tmpreg = 0; + + tmpreg = BKP->OCTLR; + tmpreg &= OCTLR_CAL_MASK; + tmpreg |= CalibrationValue; + BKP->OCTLR = tmpreg; +} + +/********************************************************************* + * @fn BKP_WriteBackupRegister + * + * @brief Writes user data to the specified Data Backup Register. + * + * @param BKP_DR - specifies the Data Backup Register. + * Data - data to write. + * + * @return none + */ +void BKP_WriteBackupRegister(uint16_t BKP_DR, uint16_t Data) +{ + __IO uint32_t tmp = 0; + + tmp = (uint32_t)BKP_BASE; + tmp += BKP_DR; + *(__IO uint32_t *)tmp = Data; +} + +/********************************************************************* + * @fn BKP_ReadBackupRegister + * + * @brief Reads data from the specified Data Backup Register. + * + * @param BKP_DR - specifies the Data Backup Register. + * This parameter can be BKP_DRx where x=[1, 42]. + * + * @return none + */ +uint16_t BKP_ReadBackupRegister(uint16_t BKP_DR) +{ + __IO uint32_t tmp = 0; + + tmp = (uint32_t)BKP_BASE; + tmp += BKP_DR; + + return (*(__IO uint16_t *)tmp); +} + +/********************************************************************* + * @fn BKP_GetFlagStatus + * + * @brief Checks whether the Tamper Pin Event flag is set or not. + * + * @return FlagStatus - SET or RESET. + */ +FlagStatus BKP_GetFlagStatus(void) +{ + if(BKP->TPCSR & (1 << 8)) + { + return SET; + } + else + { + return RESET; + } +} + +/********************************************************************* + * @fn BKP_ClearFlag + * + * @brief Clears Tamper Pin Event pending flag. + * + * @return none + */ +void BKP_ClearFlag(void) +{ + BKP->TPCSR |= BKP_CTE; +} + +/********************************************************************* + * @fn BKP_GetITStatus + * + * @brief Checks whether the Tamper Pin Interrupt has occurred or not. + * + * @return ITStatus - SET or RESET. + */ +ITStatus BKP_GetITStatus(void) +{ + if(BKP->TPCSR & (1 << 9)) + { + return SET; + } + else + { + return RESET; + } +} + +/********************************************************************* + * @fn BKP_ClearITPendingBit + * + * @brief Clears Tamper Pin Interrupt pending bit. + * + * @return none + */ +void BKP_ClearITPendingBit(void) +{ + BKP->TPCSR |= BKP_CTI; +} diff --git a/ZDBMS/BMS_CC/Peripheral/src/ch32l103_can.c b/ZDBMS/BMS_CC/Peripheral/src/ch32l103_can.c new file mode 100644 index 0000000..0e5e240 --- /dev/null +++ b/ZDBMS/BMS_CC/Peripheral/src/ch32l103_can.c @@ -0,0 +1,1697 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32l103_can.c + * Author : WCH + * Version : V1.0.0 + * Date : 2023/07/08 + * Description : This file provides all the CAN firmware functions. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#include "ch32l103_can.h" +#include "ch32l103_rcc.h" + +/* CAN CTLR Register bits */ +#define CTLR_DBF ((uint32_t)0x00010000) + +/* CAN Mailbox Transmit Request */ +#define TMIDxR_TXRQ ((uint32_t)0x00000001) + +/* CAN FCTLR Register bits */ +#define FCTLR_FINIT ((uint32_t)0x00000001) + +/* Time out for INAK bit */ +#define INAK_TIMEOUT ((uint32_t)0x0000FFFF) +/* Time out for SLAK bit */ +#define SLAK_TIMEOUT ((uint32_t)0x0000FFFF) + + +/* Flags in TSTATR register */ +#define CAN_FLAGS_TSTATR ((uint32_t)0x08000000) +/* Flags in RFIFO1 register */ +#define CAN_FLAGS_RFIFO1 ((uint32_t)0x04000000) +/* Flags in RFIFO0 register */ +#define CAN_FLAGS_RFIFO0 ((uint32_t)0x02000000) +/* Flags in STATR register */ +#define CAN_FLAGS_STATR ((uint32_t)0x01000000) +/* Flags in ERRSR register */ +#define CAN_FLAGS_ERRSR ((uint32_t)0x00F00000) + +/* Mailboxes definition */ +#define CAN_TXMAILBOX_0 ((uint8_t)0x00) +#define CAN_TXMAILBOX_1 ((uint8_t)0x01) +#define CAN_TXMAILBOX_2 ((uint8_t)0x02) + + +#define CAN_MODE_MASK ((uint32_t) 0x00000003) + +static ITStatus CheckITStatus(uint32_t CAN_Reg, uint32_t It_Bit); + + +/********************************************************************* + * @fn CAN_DeInit + * + * @brief Deinitializes the CAN peripheral registers to their default reset + * values. + * + * @param CANx - where x can be 1 to select the CAN peripheral. + * + * @return none + */ +void CAN_DeInit(CAN_TypeDef* CANx) +{ + if (CANx == CAN1) + { + RCC_PB1PeriphResetCmd(RCC_PB1Periph_CAN1, ENABLE); + RCC_PB1PeriphResetCmd(RCC_PB1Periph_CAN1, DISABLE); + } +} + +/********************************************************************* + * @fn CAN_Init + * + * @brief Initializes the CAN peripheral according to the specified + * parameters in the CAN_InitStruct. + * + * @param CANx - where x can be 1 to select the CAN peripheral. + * CAN_InitStruct - pointer to a CAN_InitTypeDef structure that + * contains the configuration information for the CAN peripheral. + * + * @return InitStatus - CAN InitStatus state. +* CAN_InitStatus_Failed. +* CAN_InitStatus_Success. + */ +uint8_t CAN_Init(CAN_TypeDef* CANx, CAN_InitTypeDef* CAN_InitStruct) +{ + uint8_t InitStatus = CAN_InitStatus_Failed; + uint32_t wait_ack = 0x00000000; + + CANx->CANFD_CR &= ~(1); + + CANx->CTLR &= (~(uint32_t)CAN_CTLR_SLEEP); + CANx->CTLR |= CAN_CTLR_INRQ ; + + while (((CANx->STATR & CAN_STATR_INAK) != CAN_STATR_INAK) && (wait_ack != INAK_TIMEOUT)) + { + wait_ack++; + } + + if ((CANx->STATR & CAN_STATR_INAK) != CAN_STATR_INAK) + { + InitStatus = CAN_InitStatus_Failed; + } + else + { + if (CAN_InitStruct->CAN_TTCM == ENABLE) + { + CANx->CTLR |= CAN_CTLR_TTCM; + } + else + { + CANx->CTLR &= ~(uint32_t)CAN_CTLR_TTCM; + } + + if (CAN_InitStruct->CAN_ABOM == ENABLE) + { + CANx->CTLR |= CAN_CTLR_ABOM; + } + else + { + CANx->CTLR &= ~(uint32_t)CAN_CTLR_ABOM; + } + + if (CAN_InitStruct->CAN_AWUM == ENABLE) + { + CANx->CTLR |= CAN_CTLR_AWUM; + } + else + { + CANx->CTLR &= ~(uint32_t)CAN_CTLR_AWUM; + } + + if (CAN_InitStruct->CAN_NART == ENABLE) + { + CANx->CTLR |= CAN_CTLR_NART; + } + else + { + CANx->CTLR &= ~(uint32_t)CAN_CTLR_NART; + } + + if (CAN_InitStruct->CAN_RFLM == ENABLE) + { + CANx->CTLR |= CAN_CTLR_RFLM; + } + else + { + CANx->CTLR &= ~(uint32_t)CAN_CTLR_RFLM; + } + + if (CAN_InitStruct->CAN_TXFP == ENABLE) + { + CANx->CTLR |= CAN_CTLR_TXFP; + } + else + { + CANx->CTLR &= ~(uint32_t)CAN_CTLR_TXFP; + } + + CANx->BTIMR = (uint32_t)((uint32_t)CAN_InitStruct->CAN_Mode << 30) | \ + ((uint32_t)CAN_InitStruct->CAN_SJW << 24) | \ + ((uint32_t)CAN_InitStruct->CAN_BS1 << 16) | \ + ((uint32_t)CAN_InitStruct->CAN_BS2 << 20) | \ + ((uint32_t)CAN_InitStruct->CAN_Prescaler - 1); + CANx->CTLR &= ~(uint32_t)CAN_CTLR_INRQ; + wait_ack = 0; + + while (((CANx->STATR & CAN_STATR_INAK) == CAN_STATR_INAK) && (wait_ack != INAK_TIMEOUT)) + { + wait_ack++; + } + + if ((CANx->STATR & CAN_STATR_INAK) == CAN_STATR_INAK) + { + InitStatus = CAN_InitStatus_Failed; + } + else + { + InitStatus = CAN_InitStatus_Success ; + } + } + + return InitStatus; +} + +/********************************************************************* + * @fn CAN_FilterInit + * + * @brief Initializes the CAN peripheral according to the specified + * parameters in the CAN_FilterInitStruct. + * + * @param CAN_FilterInitStruct - pointer to a CAN_FilterInitTypeDef + * structure that contains the configuration information. + * + * @return none + */ +void CAN_FilterInit(CAN_FilterInitTypeDef* CAN_FilterInitStruct) +{ + uint32_t filter_number_bit_pos = 0; + + filter_number_bit_pos = ((uint32_t)1) << CAN_FilterInitStruct->CAN_FilterNumber; + CAN1->FCTLR |= FCTLR_FINIT; + CAN1->FWR &= ~(uint32_t)filter_number_bit_pos; + + if (CAN_FilterInitStruct->CAN_FilterScale == CAN_FilterScale_16bit) + { + CAN1->FSCFGR &= ~(uint32_t)filter_number_bit_pos; + + CAN1->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR1 = + ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdLow) << 16) | + (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdLow); + + CAN1->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR2 = + ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdHigh) << 16) | + (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdHigh); + } + + if (CAN_FilterInitStruct->CAN_FilterScale == CAN_FilterScale_32bit) + { + CAN1->FSCFGR |= filter_number_bit_pos; + + CAN1->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR1 = + ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdHigh) << 16) | + (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdLow); + + CAN1->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR2 = + ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdHigh) << 16) | + (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdLow); + } + + if (CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdMask) + { + CAN1->FMCFGR &= ~(uint32_t)filter_number_bit_pos; + } + else + { + CAN1->FMCFGR |= (uint32_t)filter_number_bit_pos; + } + + if (CAN_FilterInitStruct->CAN_FilterFIFOAssignment == CAN_Filter_FIFO0) + { + CAN1->FAFIFOR &= ~(uint32_t)filter_number_bit_pos; + } + + if (CAN_FilterInitStruct->CAN_FilterFIFOAssignment == CAN_Filter_FIFO1) + { + CAN1->FAFIFOR |= (uint32_t)filter_number_bit_pos; + } + + if (CAN_FilterInitStruct->CAN_FilterActivation == ENABLE) + { + CAN1->FWR |= filter_number_bit_pos; + } + + CAN1->FCTLR &= ~FCTLR_FINIT; +} + +/********************************************************************* + * @fn CAN_StructInit + * + * @brief Fills each CAN_InitStruct member with its default value. + * + * @param CAN_InitStruct - pointer to a CAN_InitTypeDef structure which + * will be initialized. + * + * @return none + */ +void CAN_StructInit(CAN_InitTypeDef* CAN_InitStruct) +{ + CAN_InitStruct->CAN_TTCM = DISABLE; + CAN_InitStruct->CAN_ABOM = DISABLE; + CAN_InitStruct->CAN_AWUM = DISABLE; + CAN_InitStruct->CAN_NART = DISABLE; + CAN_InitStruct->CAN_RFLM = DISABLE; + CAN_InitStruct->CAN_TXFP = DISABLE; + CAN_InitStruct->CAN_Mode = CAN_Mode_Normal; + CAN_InitStruct->CAN_SJW = CAN_SJW_1tq; + CAN_InitStruct->CAN_BS1 = CAN_BS1_4tq; + CAN_InitStruct->CAN_BS2 = CAN_BS2_3tq; + CAN_InitStruct->CAN_Prescaler = 1; +} + +/********************************************************************* + * @fn CAN_SlaveStartBank + * + * @brief This function applies only to CH32 Connectivity line devices. + * + * @param CAN_BankNumber - Select the start slave bank filter from 1..27. + * + * @return none + */ +void CAN_SlaveStartBank(uint8_t CAN_BankNumber) +{ + CAN1->FCTLR |= FCTLR_FINIT; + CAN1->FCTLR &= (uint32_t)0xFFFFC0F1 ; + CAN1->FCTLR |= (uint32_t)(CAN_BankNumber)<<8; + CAN1->FCTLR &= ~FCTLR_FINIT; +} + +/********************************************************************* + * @fn CAN_DBGFreeze + * + * @brief Enables or disables the DBG Freeze for CAN. + * + * @param CANx - where x can be 1 to select the CAN peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void CAN_DBGFreeze(CAN_TypeDef* CANx, FunctionalState NewState) +{ + if (NewState != DISABLE) + { + CANx->CTLR |= CTLR_DBF; + } + else + { + CANx->CTLR &= ~CTLR_DBF; + } +} + +/********************************************************************* + * @fn CAN_TTComModeCmd + * + * @brief Enables or disables the CAN Time TriggerOperation communication mode. + * + * @param CANx - where x can be 1 to select the CAN peripheral. + * NewState - ENABLE or DISABLE. + * Note- + * DLC must be programmed as 8 in order Time Stamp (2 bytes) to be + * sent over the CAN bus. + * + * @return none + */ +void CAN_TTComModeCmd(CAN_TypeDef* CANx, FunctionalState NewState) +{ + if (NewState != DISABLE) + { + CANx->CTLR |= CAN_CTLR_TTCM; + + CANx->sTxMailBox[0].TXMDTR |= ((uint32_t)CAN_TXMDT0R_TGT); + CANx->sTxMailBox[1].TXMDTR |= ((uint32_t)CAN_TXMDT1R_TGT); + CANx->sTxMailBox[2].TXMDTR |= ((uint32_t)CAN_TXMDT2R_TGT); + } + else + { + CANx->CTLR &= (uint32_t)(~(uint32_t)CAN_CTLR_TTCM); + + CANx->sTxMailBox[0].TXMDTR &= ((uint32_t)~CAN_TXMDT0R_TGT); + CANx->sTxMailBox[1].TXMDTR &= ((uint32_t)~CAN_TXMDT1R_TGT); + CANx->sTxMailBox[2].TXMDTR &= ((uint32_t)~CAN_TXMDT2R_TGT); + } +} + +/********************************************************************* + * @fn CAN_Transmit + * + * @brief Initiates the transmission of a message. + * + * @param CANx - where x can be 1 to select the CAN peripheral. + * TxMessage - pointer to a structure which contains CAN Id, CAN + * DLC and CAN data. + * + * @return transmit_mailbox - The number of the mailbox that is used for + * transmission or CAN_TxStatus_NoMailBox if there is no empty mailbox. + */ +uint8_t CAN_Transmit(CAN_TypeDef* CANx, CanTxMsg* TxMessage) +{ + uint8_t transmit_mailbox = 0; + + CANx->CANFD_CR &= ~(1); + + if ((CANx->TSTATR&CAN_TSTATR_TME0) == CAN_TSTATR_TME0) + { + transmit_mailbox = 0; + } + else if ((CANx->TSTATR&CAN_TSTATR_TME1) == CAN_TSTATR_TME1) + { + transmit_mailbox = 1; + } + else if ((CANx->TSTATR&CAN_TSTATR_TME2) == CAN_TSTATR_TME2) + { + transmit_mailbox = 2; + } + else + { + transmit_mailbox = CAN_TxStatus_NoMailBox; + } + + if (transmit_mailbox != CAN_TxStatus_NoMailBox) + { + CANx->sTxMailBox[transmit_mailbox].TXMIR &= TMIDxR_TXRQ; + if (TxMessage->IDE == CAN_Id_Standard) + { + CANx->sTxMailBox[transmit_mailbox].TXMIR |= ((TxMessage->StdId << 21) | \ + TxMessage->RTR); + } + else + { + CANx->sTxMailBox[transmit_mailbox].TXMIR |= ((TxMessage->ExtId << 3) | \ + TxMessage->IDE | \ + TxMessage->RTR); + } + + TxMessage->DLC &= (uint8_t)0x0000000F; + CANx->sTxMailBox[transmit_mailbox].TXMDTR &= (uint32_t)0xFFFFFFF0; + CANx->sTxMailBox[transmit_mailbox].TXMDTR |= TxMessage->DLC; + + CANx->sTxMailBox[transmit_mailbox].TXMDLR = (((uint32_t)TxMessage->Data[3] << 24) | + ((uint32_t)TxMessage->Data[2] << 16) | + ((uint32_t)TxMessage->Data[1] << 8) | + ((uint32_t)TxMessage->Data[0])); + CANx->sTxMailBox[transmit_mailbox].TXMDHR = (((uint32_t)TxMessage->Data[7] << 24) | + ((uint32_t)TxMessage->Data[6] << 16) | + ((uint32_t)TxMessage->Data[5] << 8) | + ((uint32_t)TxMessage->Data[4])); + CANx->sTxMailBox[transmit_mailbox].TXMIR |= TMIDxR_TXRQ; + } + + return transmit_mailbox; +} + +/********************************************************************* + * @fn CAN_TransmitStatus + * + * @brief Checks the transmission of a message. + * + * @param CANx - where x can be 1 to select the CAN peripheral. + * TransmitMailbox - the number of the mailbox that is used for + * transmission. + * + * @return state - + * CAN_TxStatus_Ok. + * CAN_TxStatus_Failed. + */ +uint8_t CAN_TransmitStatus(CAN_TypeDef* CANx, uint8_t TransmitMailbox) +{ + uint32_t state = 0; + + switch (TransmitMailbox) + { + case (CAN_TXMAILBOX_0): + state = CANx->TSTATR & (CAN_TSTATR_RQCP0 | CAN_TSTATR_TXOK0 | CAN_TSTATR_TME0); + break; + + case (CAN_TXMAILBOX_1): + state = CANx->TSTATR & (CAN_TSTATR_RQCP1 | CAN_TSTATR_TXOK1 | CAN_TSTATR_TME1); + break; + + case (CAN_TXMAILBOX_2): + state = CANx->TSTATR & (CAN_TSTATR_RQCP2 | CAN_TSTATR_TXOK2 | CAN_TSTATR_TME2); + break; + + default: + state = CAN_TxStatus_Failed; + break; + } + + switch (state) + { + case (0x0): + state = CAN_TxStatus_Pending; + break; + + case (CAN_TSTATR_RQCP0 | CAN_TSTATR_TME0): + state = CAN_TxStatus_Failed; + break; + + case (CAN_TSTATR_RQCP1 | CAN_TSTATR_TME1): + state = CAN_TxStatus_Failed; + break; + + case (CAN_TSTATR_RQCP2 | CAN_TSTATR_TME2): + state = CAN_TxStatus_Failed; + break; + + case (CAN_TSTATR_RQCP0 | CAN_TSTATR_TXOK0 | CAN_TSTATR_TME0): + state = CAN_TxStatus_Ok; + break; + + case (CAN_TSTATR_RQCP1 | CAN_TSTATR_TXOK1 | CAN_TSTATR_TME1): + state = CAN_TxStatus_Ok; + break; + + case (CAN_TSTATR_RQCP2 | CAN_TSTATR_TXOK2 | CAN_TSTATR_TME2): + state = CAN_TxStatus_Ok; + break; + + default: + state = CAN_TxStatus_Failed; + break; + } + + return (uint8_t) state; +} + +/********************************************************************* + * @fn CAN_CancelTransmit + * + * @brief Cancels a transmit request. + * + * @param CANx - where x can be 1 to select the CAN peripheral. + * Mailbox - Mailbox number. + * CAN_TXMAILBOX_0. + * CAN_TXMAILBOX_1. + * CAN_TXMAILBOX_2. + * + * @return none + */ +void CAN_CancelTransmit(CAN_TypeDef* CANx, uint8_t Mailbox) +{ + switch (Mailbox) + { + case (CAN_TXMAILBOX_0): + CANx->TSTATR |= CAN_TSTATR_ABRQ0; + break; + + case (CAN_TXMAILBOX_1): + CANx->TSTATR |= CAN_TSTATR_ABRQ1; + break; + + case (CAN_TXMAILBOX_2): + CANx->TSTATR |= CAN_TSTATR_ABRQ2; + break; + + default: + break; + } +} + +/********************************************************************* + * @fn CAN_Receive + * + * @brief Receives a message. + * + * @param CANx - where x can be 1 to select the CAN peripheral. + * FIFONumber - Receive FIFO number. + * CAN_FIFO0. + * CAN_FIFO1. + * RxMessage - pointer to a structure receive message which contains + * CAN Id, CAN DLC, CAN datas and FMI number. + * + * @return none + */ +void CAN_Receive(CAN_TypeDef* CANx, uint8_t FIFONumber, CanRxMsg* RxMessage) +{ + RxMessage->IDE = (uint8_t)0x04 & CANx->sFIFOMailBox[FIFONumber].RXMIR; + + if (RxMessage->IDE == CAN_Id_Standard) + { + RxMessage->StdId = (uint32_t)0x000007FF & (CANx->sFIFOMailBox[FIFONumber].RXMIR >> 21); + } + else + { + RxMessage->ExtId = (uint32_t)0x1FFFFFFF & (CANx->sFIFOMailBox[FIFONumber].RXMIR >> 3); + } + + RxMessage->RTR = (uint8_t)0x02 & CANx->sFIFOMailBox[FIFONumber].RXMIR; + RxMessage->DLC = (uint8_t)0x0F & CANx->sFIFOMailBox[FIFONumber].RXMDTR; + RxMessage->FMI = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RXMDTR >> 8); + RxMessage->Data[0] = (uint8_t)0xFF & CANx->sFIFOMailBox[FIFONumber].RXMDLR; + RxMessage->Data[1] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RXMDLR >> 8); + RxMessage->Data[2] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RXMDLR >> 16); + RxMessage->Data[3] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RXMDLR >> 24); + RxMessage->Data[4] = (uint8_t)0xFF & CANx->sFIFOMailBox[FIFONumber].RXMDHR; + RxMessage->Data[5] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RXMDHR >> 8); + RxMessage->Data[6] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RXMDHR >> 16); + RxMessage->Data[7] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RXMDHR >> 24); + + if (FIFONumber == CAN_FIFO0) + { + CANx->RFIFO0 |= CAN_RFIFO0_RFOM0; + } + else + { + CANx->RFIFO1 |= CAN_RFIFO1_RFOM1; + } +} + +/********************************************************************* + * @fn CAN_FIFORelease + * + * @brief Releases the specified FIFO. + * + * @param CANx - where x can be 1 to select the CAN peripheral. + * FIFONumber - Receive FIFO number. + * CAN_FIFO0. + * CAN_FIFO1. + * + * @return none + */ +void CAN_FIFORelease(CAN_TypeDef* CANx, uint8_t FIFONumber) +{ + if (FIFONumber == CAN_FIFO0) + { + CANx->RFIFO0 |= CAN_RFIFO0_RFOM0; + } + else + { + CANx->RFIFO1 |= CAN_RFIFO1_RFOM1; + } +} + +/********************************************************************* + * @fn CAN_MessagePending + * + * @brief Returns the number of pending messages. + * + * @param CANx - where x can be 1 to select the CAN peripheral. + * FIFONumber - Receive FIFO number. + * CAN_FIFO0. + * CAN_FIFO1. + * + * @return message_pending: which is the number of pending message. + */ +uint8_t CAN_MessagePending(CAN_TypeDef* CANx, uint8_t FIFONumber) +{ + uint8_t message_pending=0; + + if (FIFONumber == CAN_FIFO0) + { + message_pending = (uint8_t)(CANx->RFIFO0&(uint32_t)0x03); + } + else if (FIFONumber == CAN_FIFO1) + { + message_pending = (uint8_t)(CANx->RFIFO1&(uint32_t)0x03); + } + else + { + message_pending = 0; + } + + return message_pending; +} + +/********************************************************************* + * @fn CAN_OperatingModeRequest + * + * @brief Select the CAN Operation mode. + * + * @param CANx - where x can be 1 to select the CAN peripheral. + * CAN_OperatingMode - CAN Operating Mode. + * CAN_OperatingMode_Initialization. + * CAN_OperatingMode_Normal. + * CAN_OperatingMode_Sleep. + * + * @return status - + * CAN_ModeStatus_Failed - CAN failed entering the specific mode. + * CAN_ModeStatus_Success - CAN Succeed entering the specific mode. + */ +uint8_t CAN_OperatingModeRequest(CAN_TypeDef* CANx, uint8_t CAN_OperatingMode) +{ + uint8_t status = CAN_ModeStatus_Failed; + uint32_t timeout = INAK_TIMEOUT; + + if (CAN_OperatingMode == CAN_OperatingMode_Initialization) + { + CANx->CTLR = (uint32_t)((CANx->CTLR & (uint32_t)(~(uint32_t)CAN_CTLR_SLEEP)) | CAN_CTLR_INRQ); + + while (((CANx->STATR & CAN_MODE_MASK) != CAN_STATR_INAK) && (timeout != 0)) + { + timeout--; + } + if ((CANx->STATR & CAN_MODE_MASK) != CAN_STATR_INAK) + { + status = CAN_ModeStatus_Failed; + } + else + { + status = CAN_ModeStatus_Success; + } + } + else if (CAN_OperatingMode == CAN_OperatingMode_Normal) + { + CANx->CTLR &= (uint32_t)(~(CAN_CTLR_SLEEP|CAN_CTLR_INRQ)); + + while (((CANx->STATR & CAN_MODE_MASK) != 0) && (timeout!=0)) + { + timeout--; + } + if ((CANx->STATR & CAN_MODE_MASK) != 0) + { + status = CAN_ModeStatus_Failed; + } + else + { + status = CAN_ModeStatus_Success; + } + } + else if (CAN_OperatingMode == CAN_OperatingMode_Sleep) + { + CANx->CTLR = (uint32_t)((CANx->CTLR & (uint32_t)(~(uint32_t)CAN_CTLR_INRQ)) | CAN_CTLR_SLEEP); + + while (((CANx->STATR & CAN_MODE_MASK) != CAN_STATR_SLAK) && (timeout!=0)) + { + timeout--; + } + if ((CANx->STATR & CAN_MODE_MASK) != CAN_STATR_SLAK) + { + status = CAN_ModeStatus_Failed; + } + else + { + status = CAN_ModeStatus_Success; + } + } + else + { + status = CAN_ModeStatus_Failed; + } + + return (uint8_t) status; +} + +/********************************************************************* + * @fn CAN_Sleep + * + * @brief Enters the low power mode. + * + * @param CANx - where x can be 1 to select the CAN peripheral. + * + * @return sleepstatus - + * CAN_Sleep_Ok. + * CAN_Sleep_Failed. + */ +uint8_t CAN_Sleep(CAN_TypeDef* CANx) +{ + uint8_t sleepstatus = CAN_Sleep_Failed; + + CANx->CTLR = (((CANx->CTLR) & (uint32_t)(~(uint32_t)CAN_CTLR_INRQ)) | CAN_CTLR_SLEEP); + + if ((CANx->STATR & (CAN_STATR_SLAK|CAN_STATR_INAK)) == CAN_STATR_SLAK) + { + sleepstatus = CAN_Sleep_Ok; + } + + return (uint8_t)sleepstatus; +} + +/********************************************************************* + * @fn CAN_WakeUp + * + * @brief Wakes the CAN up. + * + * @param CANx - where x can be 1 to select the CAN peripheral. + * + * @return wakeupstatus - + * CAN_WakeUp_Ok. + * CAN_WakeUp_Failed. + */ +uint8_t CAN_WakeUp(CAN_TypeDef* CANx) +{ + uint32_t wait_slak = SLAK_TIMEOUT; + uint8_t wakeupstatus = CAN_WakeUp_Failed; + + CANx->CTLR &= ~(uint32_t)CAN_CTLR_SLEEP; + + while(((CANx->STATR & CAN_STATR_SLAK) == CAN_STATR_SLAK)&&(wait_slak!=0x00)) + { + wait_slak--; + } + if((CANx->STATR & CAN_STATR_SLAK) != CAN_STATR_SLAK) + { + wakeupstatus = CAN_WakeUp_Ok; + } + + return (uint8_t)wakeupstatus; +} + +/********************************************************************* + * @fn CAN_GetLastErrorCode + * + * @brief Returns the CANx's last error code (LEC). + * + * @param CANx - where x can be 1 to select the CAN peripheral. + * + * @return errorcode - specifies the Error code. + * CAN_ErrorCode_NoErr - No Error. + * CAN_ErrorCode_StuffErr - Stuff Error. + * CAN_ErrorCode_FormErr - Form Error. + * CAN_ErrorCode_ACKErr - Acknowledgment Error. + * CAN_ErrorCode_BitRecessiveErr - Bit Recessive Error. + * CAN_ErrorCode_BitDominantErr - Bit Dominant Error. + * CAN_ErrorCode_CRCErr - CRC Error. + * CAN_ErrorCode_SoftwareSetErr - Software Set Error. + */ +uint8_t CAN_GetLastErrorCode(CAN_TypeDef* CANx) +{ + uint8_t errorcode=0; + + errorcode = (((uint8_t)CANx->ERRSR) & (uint8_t)CAN_ERRSR_LEC); + + return errorcode; +} + +/********************************************************************* + * @fn CAN_GetReceiveErrorCounter + * + * @brief Returns the CANx Receive Error Counter (REC). + * + * @param CANx - where x can be 1 to select the CAN peripheral. + * Note- + * In case of an error during reception, this counter is incremented + * by 1 or by 8 depending on the error condition as defined by the CAN + * standard. After every successful reception, the counter is + * decremented by 1 or reset to 120 if its value was higher than 128. + * When the counter value exceeds 127, the CAN controller enters the + * error passive state. + * @return counter - CAN Receive Error Counter. + */ +uint8_t CAN_GetReceiveErrorCounter(CAN_TypeDef* CANx) +{ + uint8_t counter=0; + + counter = (uint8_t)((CANx->ERRSR & CAN_ERRSR_REC)>> 24); + + return counter; +} + +/********************************************************************* + * @fn CAN_GetLSBTransmitErrorCounter + * + * @brief Returns the LSB of the 9-bit CANx Transmit Error Counter(TEC). + * + * @param CANx - where x can be 1 to select the CAN peripheral. + * + * @return counter - LSB of the 9-bit CAN Transmit Error Counter. + */ +uint8_t CAN_GetLSBTransmitErrorCounter(CAN_TypeDef* CANx) +{ + uint8_t counter=0; + + counter = (uint8_t)((CANx->ERRSR & CAN_ERRSR_TEC)>> 16); + + return counter; +} + +/********************************************************************* + * @fn CAN_ITConfig + * + * @brief Enables or disables the specified CANx interrupts. + * + * @param CANx - where x can be 1 to select the CAN peripheral. + * CAN_IT - specifies the CAN interrupt sources to be enabled or disabled. + * CAN_IT_TME. + * CAN_IT_FMP0. + * CAN_IT_FF0. + * CAN_IT_FOV0. + * CAN_IT_FMP1. + * CAN_IT_FF1. + * CAN_IT_FOV1. + * CAN_IT_EWG. + * CAN_IT_EPV. + * CAN_IT_LEC. + * CAN_IT_ERR. + * CAN_IT_WKU. + * CAN_IT_SLK. + * NewState - ENABLE or DISABLE. + * + * @return counter - LSB of the 9-bit CAN Transmit Error Counter. + */ +void CAN_ITConfig(CAN_TypeDef* CANx, uint32_t CAN_IT, FunctionalState NewState) +{ + if (NewState != DISABLE) + { + CANx->INTENR |= CAN_IT; + } + else + { + CANx->INTENR &= ~CAN_IT; + } +} + +/********************************************************************* + * @fn CAN_GetFlagStatus + * + * @brief Checks whether the specified CAN flag is set or not. + * + * @param CANx - where x can be 1 to select the CAN peripheral. + * CAN_FLAG - specifies the flag to check. + * CAN_FLAG_EWG. + * CAN_FLAG_EPV. + * CAN_FLAG_BOF. + * CAN_FLAG_RQCP0. + * CAN_FLAG_RQCP1. + * CAN_FLAG_RQCP2. + * CAN_FLAG_FMP1. + * CAN_FLAG_FF1. + * CAN_FLAG_FOV1. + * CAN_FLAG_FMP0. + * CAN_FLAG_FF0. + * CAN_FLAG_FOV0. + * CAN_FLAG_WKU. + * CAN_FLAG_SLAK. + * CAN_FLAG_LEC. + * NewState - ENABLE or DISABLE. + * + * @return FlagStatus - SET or RESET. + */ +FlagStatus CAN_GetFlagStatus(CAN_TypeDef* CANx, uint32_t CAN_FLAG) +{ + FlagStatus bitstatus = RESET; + + if((CAN_FLAG & CAN_FLAGS_ERRSR) != (uint32_t)RESET) + { + if ((CANx->ERRSR & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + } + else if((CAN_FLAG & CAN_FLAGS_STATR) != (uint32_t)RESET) + { + if ((CANx->STATR & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + } + else if((CAN_FLAG & CAN_FLAGS_TSTATR) != (uint32_t)RESET) + { + if ((CANx->TSTATR & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + } + else if((CAN_FLAG & CAN_FLAGS_RFIFO0) != (uint32_t)RESET) + { + if ((CANx->RFIFO0 & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + } + else + { + if ((uint32_t)(CANx->RFIFO1 & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + } + + return bitstatus; +} + +/********************************************************************* + * @fn CAN_ClearFlag + * + * @brief Clears the CAN's pending flags. + * + * @param CANx - where x can be 1 to select the CAN peripheral. + * CAN_FLAG - specifies the flag to clear. + * CAN_FLAG_RQCP0. + * CAN_FLAG_RQCP1. + * CAN_FLAG_RQCP2. + * CAN_FLAG_FF1. + * CAN_FLAG_FOV1. + * CAN_FLAG_FF0. + * CAN_FLAG_FOV0. + * CAN_FLAG_WKU. + * CAN_FLAG_SLAK. + * CAN_FLAG_LEC. + * + * @return none + */ +void CAN_ClearFlag(CAN_TypeDef* CANx, uint32_t CAN_FLAG) +{ + uint32_t flagtmp=0; + + if (CAN_FLAG == CAN_FLAG_LEC) + { + CANx->ERRSR = (uint32_t)RESET; + } + else + { + flagtmp = CAN_FLAG & 0x000FFFFF; + + if ((CAN_FLAG & CAN_FLAGS_RFIFO0)!=(uint32_t)RESET) + { + CANx->RFIFO0 = (uint32_t)(flagtmp); + } + else if ((CAN_FLAG & CAN_FLAGS_RFIFO1)!=(uint32_t)RESET) + { + CANx->RFIFO1 = (uint32_t)(flagtmp); + } + else if ((CAN_FLAG & CAN_FLAGS_TSTATR)!=(uint32_t)RESET) + { + CANx->TSTATR = (uint32_t)(flagtmp); + } + else + { + CANx->STATR = (uint32_t)(flagtmp); + } + } +} + +/********************************************************************* + * @fn CAN_GetITStatus + * + * @brief Checks whether the specified CANx interrupt has occurred or not. + * + * @param CANx - where x can be 1 to select the CAN peripheral. + * CAN_IT - specifies the CAN interrupt source to check. + * CAN_IT_TME. + * CAN_IT_FMP0. + * CAN_IT_FF0. + * CAN_IT_FOV0. + * CAN_IT_FMP1. + * CAN_IT_FF1. + * CAN_IT_FOV1. + * CAN_IT_WKU. + * CAN_IT_SLK. + * CAN_IT_EWG. + * CAN_IT_EPV. + * CAN_IT_BOF. + * CAN_IT_LEC. + * CAN_IT_ERR. + * + * @return ITStatus - SET or RESET. + */ +ITStatus CAN_GetITStatus(CAN_TypeDef* CANx, uint32_t CAN_IT) +{ + ITStatus itstatus = RESET; + + if((CANx->INTENR & CAN_IT) != RESET) + { + switch (CAN_IT) + { + case CAN_IT_TME: + itstatus = CheckITStatus(CANx->TSTATR, CAN_TSTATR_RQCP0|CAN_TSTATR_RQCP1|CAN_TSTATR_RQCP2); + break; + + case CAN_IT_FMP0: + itstatus = CheckITStatus(CANx->RFIFO0, CAN_RFIFO0_FMP0); + break; + + case CAN_IT_FF0: + itstatus = CheckITStatus(CANx->RFIFO0, CAN_RFIFO0_FULL0); + break; + + case CAN_IT_FOV0: + itstatus = CheckITStatus(CANx->RFIFO0, CAN_RFIFO0_FOVR0); + break; + + case CAN_IT_FMP1: + itstatus = CheckITStatus(CANx->RFIFO1, CAN_RFIFO1_FMP1); + break; + + case CAN_IT_FF1: + itstatus = CheckITStatus(CANx->RFIFO1, CAN_RFIFO1_FULL1); + break; + + case CAN_IT_FOV1: + itstatus = CheckITStatus(CANx->RFIFO1, CAN_RFIFO1_FOVR1); + break; + + case CAN_IT_WKU: + itstatus = CheckITStatus(CANx->STATR, CAN_STATR_WKUI); + break; + + case CAN_IT_SLK: + itstatus = CheckITStatus(CANx->STATR, CAN_STATR_SLAKI); + break; + + case CAN_IT_EWG: + itstatus = CheckITStatus(CANx->ERRSR, CAN_ERRSR_EWGF); + break; + + case CAN_IT_EPV: + itstatus = CheckITStatus(CANx->ERRSR, CAN_ERRSR_EPVF); + break; + + case CAN_IT_BOF: + itstatus = CheckITStatus(CANx->ERRSR, CAN_ERRSR_BOFF); + break; + + case CAN_IT_LEC: + itstatus = CheckITStatus(CANx->ERRSR, CAN_ERRSR_LEC); + break; + + case CAN_IT_ERR: + itstatus = CheckITStatus(CANx->STATR, CAN_STATR_ERRI); + break; + + default : + itstatus = RESET; + break; + } + } + else + { + itstatus = RESET; + } + + return itstatus; +} + +/********************************************************************* + * @fn CAN_ClearITPendingBit + * + * @brief Clears the CANx's interrupt pending bits. + * + * @param CANx - where x can be 1 to select the CAN peripheral. + * CAN_IT - specifies the interrupt pending bit to clear. + * CAN_IT_TME. + * CAN_IT_FF0. + * CAN_IT_FOV0. + * CAN_IT_FF1. + * CAN_IT_FOV1. + * CAN_IT_WKU. + * CAN_IT_SLK. + * CAN_IT_EWG. + * CAN_IT_EPV. + * CAN_IT_BOF. + * CAN_IT_LEC. + * CAN_IT_ERR. + * + * @return none + */ +void CAN_ClearITPendingBit(CAN_TypeDef* CANx, uint32_t CAN_IT) +{ + switch (CAN_IT) + { + case CAN_IT_TME: + CANx->TSTATR = CAN_TSTATR_RQCP0|CAN_TSTATR_RQCP1|CAN_TSTATR_RQCP2; + break; + + case CAN_IT_FF0: + CANx->RFIFO0 = CAN_RFIFO0_FULL0; + break; + + case CAN_IT_FOV0: + CANx->RFIFO0 = CAN_RFIFO0_FOVR0; + break; + + case CAN_IT_FF1: + CANx->RFIFO1 = CAN_RFIFO1_FULL1; + break; + + case CAN_IT_FOV1: + CANx->RFIFO1 = CAN_RFIFO1_FOVR1; + break; + + case CAN_IT_WKU: + CANx->STATR = CAN_STATR_WKUI; + break; + + case CAN_IT_SLK: + CANx->STATR = CAN_STATR_SLAKI; + break; + + case CAN_IT_EWG: + CANx->STATR = CAN_STATR_ERRI; + break; + + case CAN_IT_EPV: + CANx->STATR = CAN_STATR_ERRI; + break; + + case CAN_IT_BOF: + CANx->STATR = CAN_STATR_ERRI; + break; + + case CAN_IT_LEC: + CANx->ERRSR = RESET; + CANx->STATR = CAN_STATR_ERRI; + break; + + case CAN_IT_ERR: + CANx->ERRSR = RESET; + CANx->STATR = CAN_STATR_ERRI; + break; + + default : + break; + } +} + +/********************************************************************* + * @fn CheckITStatus + * + * @brief Checks whether the CAN interrupt has occurred or not. + * + * @param CAN_Reg - specifies the CAN interrupt register to check + * It_Bit - specifies the interrupt source bit to check. + * + * @return ITStatus - SET or RESET. + */ +static ITStatus CheckITStatus(uint32_t CAN_Reg, uint32_t It_Bit) +{ + ITStatus pendingbitstatus = RESET; + + if ((CAN_Reg & It_Bit) != (uint32_t)RESET) + { + pendingbitstatus = SET; + } + else + { + pendingbitstatus = RESET; + } + + return pendingbitstatus; +} + +/********************************************************************* + * @fn CAN_BS1_ModeConfig + * + * @brief Configures the CAN the number of time quanta in Bit and mode. + * + * @param CANx - where x can be 1 to select the CAN peripheral. + * CAN_BS1_Mode - CAN BS1 Mode + * CAN_BS1_4bit - 4bit mode + * CAN_BS1_tq = TS1[3:0];(CANx->BTIMR) + * This parameter must range from 0x00 to 0x0F. + * CAN_BS1_6bit - 6bit mode + * CAN_BS1_tq = (TS1[1:0] << 4) + BTR_TS1_T[3:0];(CANx->BTIMR) + * This parameter must range from 0x00 to 0x3F. + * + * @return none + */ +void CAN_BS1_ModeConfig(CAN_TypeDef* CANx, uint32_t CAN_BS1_Mode, uint8_t CAN_BS1_tq) +{ + CANx->CANFD_CR &= ~(CAN_BS1_6bit); + CANx->BTIMR &= ~(0x000FF000); + + if(CAN_BS1_Mode == CAN_BS1_6bit) + { + CANx->CANFD_CR |= CAN_BS1_6bit; + CANx->BTIMR |= (CAN_BS1_tq << 16); + } + else if(CAN_BS1_Mode == CAN_BS1_4bit) + { + CANx->BTIMR |= (CAN_BS1_tq << 12); + } +} + +/********************************************************************* + * @fn CAN_BusOff_ErrCntConfig + * + * @brief Configures the CAN the number of err count bus off. + * + * @param CANx - where x can be 1 to select the CAN peripheral. + * BusOff_ErrCnt - Err count bus off. + * This parameter must range from 0x00 to 0xFF. + * + * @return none + */ +void CAN_BusOff_ErrCntConfig(CAN_TypeDef *CANx, uint8_t BusOff_ErrCnt) +{ + CANx->TERR_CNT &= ~(0x000000FF); + CANx->TERR_CNT |= (uint32_t)BusOff_ErrCnt; +} + +/********************************************************************* + * @fn CANFD_Restrict_ModeCmd + * + * @brief Enables or disables the CANFD restrict mode. + * + * @param CANx - where x can be 1 to select the CANFD peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void CANFD_Restrict_ModeCmd(CAN_TypeDef *CANx, FunctionalState NewState) +{ + + if(NewState) + { + CANx->CANFD_CR |= (1<<9); + } + else + { + CANx->CANFD_CR &= ~(1<<9); + } +} + +/********************************************************************* + * @fn CANFD_Init + * + * @brief Initializes the CAN peripheral according to the specified + * parameters in the CANFD_InitStruct. + * + * @param CANx - where x can be 1 to select the CAN peripheral. + * CANFD_InitStruct - pointer to a CANFD_InitTypeDef structure that + * contains the configuration information for the CAN peripheral. + * + * @return InitStatus - CAN InitStatus state. +* CAN_InitStatus_Failed. +* CAN_InitStatus_Success. + */ +uint8_t CANFD_Init(CAN_TypeDef* CANx, CANFD_InitTypeDef* CANFD_InitStruct) +{ + uint8_t InitStatus = CAN_InitStatus_Failed; + uint32_t wait_ack = 0x00000000; + + CANx->CANFD_CR |= 1; + + CANx->CTLR &= (~(uint32_t)CAN_CTLR_SLEEP); + CANx->CTLR |= CAN_CTLR_INRQ ; + + while (((CANx->STATR & CAN_STATR_INAK) != CAN_STATR_INAK) && (wait_ack != INAK_TIMEOUT)) + { + wait_ack++; + } + + if ((CANx->STATR & CAN_STATR_INAK) != CAN_STATR_INAK) + { + InitStatus = CAN_InitStatus_Failed; + } + else + { + if (CANFD_InitStruct->CANFD_TTCM == ENABLE) + { + CANx->CTLR |= CAN_CTLR_TTCM; + } + else + { + CANx->CTLR &= ~(uint32_t)CAN_CTLR_TTCM; + } + + if (CANFD_InitStruct->CANFD_ABOM == ENABLE) + { + CANx->CTLR |= CAN_CTLR_ABOM; + } + else + { + CANx->CTLR &= ~(uint32_t)CAN_CTLR_ABOM; + } + + if (CANFD_InitStruct->CANFD_AWUM == ENABLE) + { + CANx->CTLR |= CAN_CTLR_AWUM; + } + else + { + CANx->CTLR &= ~(uint32_t)CAN_CTLR_AWUM; + } + + if (CANFD_InitStruct->CANFD_NART == ENABLE) + { + CANx->CTLR |= CAN_CTLR_NART; + } + else + { + CANx->CTLR &= ~(uint32_t)CAN_CTLR_NART; + } + + if (CANFD_InitStruct->CANFD_TXFP == ENABLE) + { + CANx->CTLR |= CAN_CTLR_TXFP; + } + else + { + CANx->CTLR &= ~(uint32_t)CAN_CTLR_TXFP; + } + + if (CANFD_InitStruct->CANFD_RES_Error == ENABLE) + { + CANx->CANFD_CR |= (1<<7); + } + else + { + CANx->CANFD_CR &= ~(1<<7); + } + + if (CANFD_InitStruct->CANFD_BRS_TXM0 == ENABLE) + { + CANx->CANFD_CR |= (1<<1); + } + else + { + CANx->CANFD_CR &= ~(1<<1); + } + + if (CANFD_InitStruct->CANFD_BRS_TXM1 == ENABLE) + { + CANx->CANFD_CR |= (1<<2); + } + else + { + CANx->CANFD_CR &= ~(1<<2); + } + + if (CANFD_InitStruct->CANFD_BRS_TXM2 == ENABLE) + { + CANx->CANFD_CR |= (1<<3); + } + else + { + CANx->CANFD_CR &= ~(1<<3); + } + + if (CANFD_InitStruct->CANFD_ESI_Auto_TXM0 == ENABLE) + { + CANx->CANFD_CR |= (1<<4); + } + else + { + CANx->CANFD_CR &= ~(1<<4); + } + + if (CANFD_InitStruct->CANFD_ESI_Auto_TXM1 == ENABLE) + { + CANx->CANFD_CR |= (1<<5); + } + else + { + CANx->CANFD_CR &= ~(1<<5); + } + + if (CANFD_InitStruct->CANFD_ESI_Auto_TXM2 == ENABLE) + { + CANx->CANFD_CR |= (1<<6); + } + else + { + CANx->CANFD_CR &= ~(1<<6); + } + + CANx->CANFD_BTR &= ~(0x009F1FFF); + CANx->CANFD_TDCT &= ~(0x00003F3F); + + CANx->CANFD_TDCT = (uint32_t)((uint32_t)CANFD_InitStruct->CANFD_TDC_FILTER << 8) | \ + ((uint32_t)CANFD_InitStruct->CANFD_TDC0); + + CANx->CANFD_BTR = (uint32_t)((uint32_t)CANFD_InitStruct->CANFD_TDCE << 23) | \ + (((uint32_t)CANFD_InitStruct->CANFD_Prescaler-1) << 16) | \ + ((uint32_t)CANFD_InitStruct->CANFD_BS1 << 8) | \ + ((uint32_t)CANFD_InitStruct->CANFD_BS2 << 4) | \ + ((uint32_t)CANFD_InitStruct->CANFD_SJW); + + CANx->CTLR &= ~(uint32_t)CAN_CTLR_INRQ; + wait_ack = 0; + + while (((CANx->STATR & CAN_STATR_INAK) == CAN_STATR_INAK) && (wait_ack != INAK_TIMEOUT)) + { + wait_ack++; + } + + if ((CANx->STATR & CAN_STATR_INAK) == CAN_STATR_INAK) + { + InitStatus = CAN_InitStatus_Failed; + } + else + { + InitStatus = CAN_InitStatus_Success ; + } + } + + return InitStatus; +} + +/********************************************************************* + * @fn CANFD_StructInit + * + * @brief Fills each CANFD_InitStruct member with its default value. + * + * @param CANFD_InitStruct - pointer to a CANFD_InitTypeDef structure which + * will be initialized. + * + * @return none + */ +void CANFD_StructInit(CANFD_InitTypeDef* CANFD_InitStruct) +{ + CANFD_InitStruct->CANFD_TTCM = DISABLE; + CANFD_InitStruct->CANFD_ABOM = DISABLE; + CANFD_InitStruct->CANFD_AWUM = DISABLE; + CANFD_InitStruct->CANFD_NART = DISABLE; + CANFD_InitStruct->CANFD_TXFP = DISABLE; + + CANFD_InitStruct->CANFD_RES_Error = DISABLE; + CANFD_InitStruct->CANFD_ESI_Auto_TXM0 = DISABLE; + CANFD_InitStruct->CANFD_ESI_Auto_TXM1 = DISABLE; + CANFD_InitStruct->CANFD_ESI_Auto_TXM2 = DISABLE; + CANFD_InitStruct->CANFD_BRS_TXM0 = DISABLE; + CANFD_InitStruct->CANFD_BRS_TXM1 = DISABLE; + CANFD_InitStruct->CANFD_BRS_TXM2 = DISABLE; + + CANFD_InitStruct->CANFD_TDC_FILTER = 0; + CANFD_InitStruct->CANFD_TDC0 = 2; + CANFD_InitStruct->CANFD_TDCE = ENABLE; + + CANFD_InitStruct->CANFD_Mode = CAN_Mode_Normal; + CANFD_InitStruct->CANFD_SJW = CANFD_SJW_8tq; + CANFD_InitStruct->CANFD_BS1 = CANFD_BS1_7tq; + CANFD_InitStruct->CANFD_BS2 = CANFD_BS2_4tq; + CANFD_InitStruct->CANFD_Prescaler = 1; +} + +/********************************************************************* + * @fn CANFD_Transmit + * + * @brief Initiates the transmission of a message for CANFD. + * + * @param CANx - where x can be 1 to select the CAN peripheral. + * TxMessage - pointer to a structure which contains CAN Id, CAN + * DLC and CAN data. + * + * @return transmit_mailbox - The number of the mailbox that is used for + * transmission or CAN_TxStatus_NoMailBox if there is no empty mailbox. + */ +uint8_t CANFD_Transmit(CAN_TypeDef* CANx, CanFDTxMsg* TxMessage) +{ + uint8_t transmit_mailbox = 0; + + CANx->CANFD_CR |= (1); + + if ((CANx->TSTATR&CAN_TSTATR_TME0) == CAN_TSTATR_TME0) + { + transmit_mailbox = 0; + } + else if ((CANx->TSTATR&CAN_TSTATR_TME1) == CAN_TSTATR_TME1) + { + transmit_mailbox = 1; + } + else if ((CANx->TSTATR&CAN_TSTATR_TME2) == CAN_TSTATR_TME2) + { + transmit_mailbox = 2; + } + else + { + transmit_mailbox = CAN_TxStatus_NoMailBox; + } + + if (transmit_mailbox != CAN_TxStatus_NoMailBox) + { + CANx->sTxMailBox[transmit_mailbox].TXMIR &= TMIDxR_TXRQ; + if (TxMessage->IDE == CAN_Id_Standard) + { + CANx->sTxMailBox[transmit_mailbox].TXMIR |= ((TxMessage->StdId << 21) | \ + TxMessage->RTR); + } + else + { + CANx->sTxMailBox[transmit_mailbox].TXMIR |= ((TxMessage->ExtId << 3) | \ + TxMessage->IDE | \ + TxMessage->RTR); + } + + TxMessage->DLC &= (uint8_t)0x0000000F; + CANx->sTxMailBox[transmit_mailbox].TXMDTR &= (uint32_t)0xFFFFFFF0; + CANx->sTxMailBox[transmit_mailbox].TXMDTR |= TxMessage->DLC; + CANx->CANFD_DMA_T[transmit_mailbox] = (uint32_t)TxMessage->Data; + CANx->sTxMailBox[transmit_mailbox].TXMIR |= TMIDxR_TXRQ; + } + + return transmit_mailbox; +} + +/********************************************************************* + * @fn CANFD_Receive + * + * @brief Receives a message. + * + * @param CANx - where x can be 1 to select the CAN peripheral. + * FIFONumber - Receive FIFO number. + * CAN_FIFO0. + * CAN_FIFO1. + * RxMessage - pointer to a structure receive message which contains + * CAN Id, CAN DLC, CAN datas and FMI number. + * + * @return ErrorStatus - NoREADY or READY. + */ +ErrorStatus CANFD_Receive(CAN_TypeDef* CANx, uint8_t FIFONumber, CanFDRxMsg* RxMessage) +{ + ErrorStatus sta = NoREADY; + uint8_t len, i; + uint32_t adr; + + if((CANx->sFIFOMailBox[FIFONumber].RXMIR & 1) == 0) return sta; + + RxMessage->IDE = (uint8_t)0x04 & CANx->sFIFOMailBox[FIFONumber].RXMIR; + + if (RxMessage->IDE == CAN_Id_Standard) + { + RxMessage->StdId = (uint32_t)0x000007FF & (CANx->sFIFOMailBox[FIFONumber].RXMIR >> 21); + } + else + { + RxMessage->ExtId = (uint32_t)0x1FFFFFFF & (CANx->sFIFOMailBox[FIFONumber].RXMIR >> 3); + } + + RxMessage->RTR = (uint8_t)0x02 & CANx->sFIFOMailBox[FIFONumber].RXMIR; + + len = (uint8_t)0x0F & CANx->sFIFOMailBox[FIFONumber].RXMDTR; + + if(len <= 8) + { + RxMessage->DLC = len; + } + else if(len <= 12) + { + RxMessage->DLC = (len - 6) * 4; + } + else if(len <= 15) + { + RxMessage->DLC = (len - 11) * 16; + } + + RxMessage->FMI = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RXMDTR >> 8); + RxMessage->BRS = (uint8_t)0x01 & (CANx->sFIFOMailBox[FIFONumber].RXMDTR >> 4); + RxMessage->ESI = (uint8_t)0x01 & (CANx->sFIFOMailBox[FIFONumber].RXMDTR >> 5); + RxMessage->RES = (uint8_t)0x01 & (CANx->sFIFOMailBox[FIFONumber].RXMDTR >> 6); + + adr = CANx->CANFD_DMA_R[FIFONumber] + 0x20000000; + + for(i=0; iDLC; i++) + { + RxMessage->Data[i] = *((uint8_t*)adr++); + } + + if (FIFONumber == CAN_FIFO0) + { + CANx->RFIFO0 |= CAN_RFIFO0_RFOM0; + } + else + { + CANx->RFIFO1 |= CAN_RFIFO1_RFOM1; + } + + sta = READY; + + return sta; +} + + +/********************************************************************* + * @fn CANFD_GetTransmitDelayOffsetVal + * + * @brief Returns the CANx Transmit Delay Offset Value. + * + * @param CANx - where x can be 1 to select the CAN peripheral. + * + * @return val - CAN Transmit Delay Offset Value. + */ +uint8_t CANFD_GetTransmitDelayOffsetVal(CAN_TypeDef *CANx) +{ + uint8_t val=0; + + val = (uint8_t)((CANx->CANFD_PSR & 0x00FF0000)>> 16); + + return val; +} + +/********************************************************************* + * @fn CANFD_TransmitMailbox_DMAAdr + * + * @brief Set Transmit Mailbox DMA address. + * + * @param CANx - where x can be 1 to select the CAN peripheral. + * MailboxNumber - Transmit Mailbox. + * CAN_Transmit_Mailbox0. + * CAN_Transmit_Mailbox1. + * CAN_Transmit_Mailbox2. + * address - DMA address. + * + * @return none. + */ +void CANFD_TransmitMailbox_DMAAdr(CAN_TypeDef *CANx, uint8_t MailboxNumber, uint32_t Address) +{ + CANx->CANFD_DMA_T[MailboxNumber] = Address; +} + +/********************************************************************* + * @fn CANFD_ReceiveFIFO_DMAAdr + * + * @brief Set receives FIFO DMA address. + * + * @param CANx - where x can be 1 to select the CAN peripheral. + * FIFONumber - Receive FIFO number. + * CAN_FIFO0. + * CAN_FIFO1. + * address - DMA address. + * + * @return none. + */ +void CANFD_ReceiveFIFO_DMAAdr(CAN_TypeDef *CANx, uint8_t FIFONumber, uint32_t Address) +{ + CANx->CANFD_DMA_R[FIFONumber] = Address; +} diff --git a/ZDBMS/BMS_CC/Peripheral/src/ch32l103_crc.c b/ZDBMS/BMS_CC/Peripheral/src/ch32l103_crc.c new file mode 100644 index 0000000..d2eebe6 --- /dev/null +++ b/ZDBMS/BMS_CC/Peripheral/src/ch32l103_crc.c @@ -0,0 +1,99 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32l103_crc.c + * Author : WCH + * Version : V1.0.0 + * Date : 2023/07/08 + * Description : This file provides all the CRC firmware functions. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#include "ch32l103_crc.h" + +/********************************************************************* + * @fn CRC_ResetDR + * + * @brief Resets the CRC Data register (DR). + * + * @return none + */ +void CRC_ResetDR(void) +{ + CRC->CTLR = CRC_CTLR_RESET; +} + +/********************************************************************* + * @fn CRC_CalcCRC + * + * @brief Computes the 32-bit CRC of a given data word(32-bit). + * + * @param Data - data word(32-bit) to compute its CRC. + * + * @return 32-bit CRC. + */ +uint32_t CRC_CalcCRC(uint32_t Data) +{ + CRC->DATAR = Data; + + return (CRC->DATAR); +} + +/********************************************************************* + * @fn CRC_CalcBlockCRC + * + * @brief Computes the 32-bit CRC of a given buffer of data word(32-bit). + * + * @param pBuffer - pointer to the buffer containing the data to be computed. + * BufferLength - length of the buffer to be computed. + * + * @return 32-bit CRC. + */ +uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength) +{ + uint32_t index = 0; + + for(index = 0; index < BufferLength; index++){ + CRC->DATAR = pBuffer[index]; + } + + return (CRC->DATAR); +} + +/********************************************************************* + * @fn CRC_GetCRC + * + * @brief Returns the current CRC value. + * + * @return 32-bit CRC. + */ +uint32_t CRC_GetCRC(void) +{ + return (CRC->DATAR); +} + +/********************************************************************* + * @fn CRC_SetIDRegister + * + * @brief Stores a 8-bit data in the Independent Data(ID) register. + * + * @param IDValue - 8-bit value to be stored in the ID register. + * + * @return none + */ +void CRC_SetIDRegister(uint8_t IDValue) +{ + CRC->IDATAR = IDValue; +} + +/********************************************************************* + * @fn CRC_GetIDRegister + * + * @brief Returns the 8-bit data stored in the Independent Data(ID) register. + * + * @return 8-bit value of the ID register. + */ +uint8_t CRC_GetIDRegister(void) +{ + return (CRC->IDATAR); +} diff --git a/ZDBMS/BMS_CC/Peripheral/src/ch32l103_dbgmcu.c b/ZDBMS/BMS_CC/Peripheral/src/ch32l103_dbgmcu.c new file mode 100644 index 0000000..44ec56c --- /dev/null +++ b/ZDBMS/BMS_CC/Peripheral/src/ch32l103_dbgmcu.c @@ -0,0 +1,126 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32l103_dbgmcu.c + * Author : WCH + * Version : V1.0.0 + * Date : 2024/05/06 + * Description : This file provides all the DBGMCU firmware functions. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#include "ch32l103_dbgmcu.h" + +#define IDCODE_DEVID_MASK ((uint32_t)0x0000FFFF) + + +/********************************************************************* + * @fn DBGMCU_GetREVID + * + * @brief Returns the device revision identifier. + * + * @return Revision identifier. + */ +uint32_t DBGMCU_GetREVID(void) +{ + return (CHIPID >> 16); +} + +/********************************************************************* + * @fn DBGMCU_GetDEVID + * + * @brief Returns the device identifier. + * + * @return Device identifier. + */ +uint32_t DBGMCU_GetDEVID(void) +{ + return (CHIPID & IDCODE_DEVID_MASK); +} + +/********************************************************************* + * @fn __get_DEBUG_CR + * + * @brief Return the DEBUGE Control Register + * + * @return DEBUGE Control value + */ +uint32_t __get_DEBUG_CR(void) +{ + uint32_t result; + + __asm volatile("csrr %0,""0x7C0" : "=r"(result)); + return (result); +} + +/********************************************************************* + * @fn __set_DEBUG_CR + * + * @brief Set the DEBUGE Control Register + * + * @param value - set DEBUGE Control value + * + * @return none + */ +void __set_DEBUG_CR(uint32_t value) +{ + __asm volatile("csrw 0x7C0, %0" : : "r"(value)); +} + + +/********************************************************************* + * @fn DBGMCU_Config + * + * @brief Configures the specified peripheral and low power mode behavior + * when the MCU under Debug mode. + * + * @param DBGMCU_Periph - specifies the peripheral and low power mode. + * DBGMCU_SLEEP - Debug sleep stopped when Core is halted + * DBGMCU_STOP - Debug stop stopped when Core is halted + * DBGMCU_STANDBY - Debug standby stopped when Core is halted + * DBGMCU_IWDG_STOP - Debug IWDG stopped when Core is halted + * DBGMCU_WWDG_STOP - Debug WWDG stopped when Core is halted + * DBGMCU_I2C1_SMBUS_TIMEOUT - Debug I2C1 SMBUS time out when Core is halted + * DBGMCU_I2C2_SMBUS_TIMEOUT - Debug I2C2 SMBUS time out when Core is halted + * DBGMCU_TIM1_STOP - TIM1 counter stopped when Core is halted + * DBGMCU_TIM2_STOP - TIM2 counter stopped when Core is halted + * DBGMCU_TIM3_STOP - TIM3 counter stopped when Core is halted + * DBGMCU_TIM4_STOP - TIM4 counter stopped when Core is halted + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState) +{ + uint32_t val; + + if(NewState != DISABLE) + { + __set_DEBUG_CR(DBGMCU_Periph); + } + else + { + val = __get_DEBUG_CR(); + val &= ~(uint32_t)DBGMCU_Periph; + __set_DEBUG_CR(val); + } +} + +/********************************************************************* + * @fn DBGMCU_GetCHIPID + * + * @brief Returns the CHIP identifier. + * + * @return Device identifier. + * ChipID List- + * CH32L103C8T6-0x103107x0 + * CH32L103F8P6-0x103A07x0 + * CH32L103G8R6-0x103B07x0 + * CH32L103K8U6-0x103207x0 + * CH32L103F8U6-0x103D07x0 + * + */ +uint32_t DBGMCU_GetCHIPID( void ) +{ + return( CHIPID ); +} diff --git a/ZDBMS/BMS_CC/Peripheral/src/ch32l103_dma.c b/ZDBMS/BMS_CC/Peripheral/src/ch32l103_dma.c new file mode 100644 index 0000000..53feb25 --- /dev/null +++ b/ZDBMS/BMS_CC/Peripheral/src/ch32l103_dma.c @@ -0,0 +1,432 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32l103_dma.c + * Author : WCH + * Version : V1.0.0 + * Date : 2023/07/08 + * Description : This file provides all the DMA firmware functions. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#include "ch32l103_dma.h" +#include "ch32l103_rcc.h" + +/* DMA1 Channelx interrupt pending bit masks */ +#define DMA1_Channel1_IT_Mask ((uint32_t)(DMA_GIF1 | DMA_TCIF1 | DMA_HTIF1 | DMA_TEIF1)) +#define DMA1_Channel2_IT_Mask ((uint32_t)(DMA_GIF2 | DMA_TCIF2 | DMA_HTIF2 | DMA_TEIF2)) +#define DMA1_Channel3_IT_Mask ((uint32_t)(DMA_GIF3 | DMA_TCIF3 | DMA_HTIF3 | DMA_TEIF3)) +#define DMA1_Channel4_IT_Mask ((uint32_t)(DMA_GIF4 | DMA_TCIF4 | DMA_HTIF4 | DMA_TEIF4)) +#define DMA1_Channel5_IT_Mask ((uint32_t)(DMA_GIF5 | DMA_TCIF5 | DMA_HTIF5 | DMA_TEIF5)) +#define DMA1_Channel6_IT_Mask ((uint32_t)(DMA_GIF6 | DMA_TCIF6 | DMA_HTIF6 | DMA_TEIF6)) +#define DMA1_Channel7_IT_Mask ((uint32_t)(DMA_GIF7 | DMA_TCIF7 | DMA_HTIF7 | DMA_TEIF7)) +#define DMA1_Channel8_IT_Mask ((uint32_t)(DMA_GIF8 | DMA_TCIF8 | DMA_HTIF8 | DMA_TEIF8)) + +/* DMA registers Masks */ +#define CFGR_CLEAR_Mask ((uint32_t)0xFFFF800F) + +/********************************************************************* + * @fn DMA_DeInit + * + * @brief Deinitializes the DMAy Channelx registers to their default + * reset values. + * + * @param DMAy_Channelx - here y can be 1 to select the DMA and x can be + * 1 to 8 for DMA1 to select the DMA Channel. + * + * @return none + */ +void DMA_DeInit(DMA_Channel_TypeDef *DMAy_Channelx) +{ + DMAy_Channelx->CFGR &= (uint16_t)(~DMA_CFGR1_EN); + DMAy_Channelx->CFGR = 0; + DMAy_Channelx->CNTR = 0; + DMAy_Channelx->PADDR = 0; + DMAy_Channelx->MADDR = 0; + if(DMAy_Channelx == DMA1_Channel1) + { + DMA1->INTFCR |= DMA1_Channel1_IT_Mask; + } + else if(DMAy_Channelx == DMA1_Channel2) + { + DMA1->INTFCR |= DMA1_Channel2_IT_Mask; + } + else if(DMAy_Channelx == DMA1_Channel3) + { + DMA1->INTFCR |= DMA1_Channel3_IT_Mask; + } + else if(DMAy_Channelx == DMA1_Channel4) + { + DMA1->INTFCR |= DMA1_Channel4_IT_Mask; + } + else if(DMAy_Channelx == DMA1_Channel5) + { + DMA1->INTFCR |= DMA1_Channel5_IT_Mask; + } + else if(DMAy_Channelx == DMA1_Channel6) + { + DMA1->INTFCR |= DMA1_Channel6_IT_Mask; + } + else if(DMAy_Channelx == DMA1_Channel7) + { + DMA1->INTFCR |= DMA1_Channel7_IT_Mask; + } + else if(DMAy_Channelx == DMA1_Channel8) + { + DMA1->INTFCR |= DMA1_Channel8_IT_Mask; + } +} + +/********************************************************************* + * @fn DMA_Init + * + * @brief Initializes the DMAy Channelx according to the specified + * parameters in the DMA_InitStruct. + * + * @param DMAy_Channelx - here y can be 1 to select the DMA and x can be + * 1 to 8 for DMA1 to select the DMA Channel. + * DMA_InitStruct - pointer to a DMA_InitTypeDef structure that contains + * contains the configuration information for the specified DMA Channel. + * + * @return none + */ +void DMA_Init(DMA_Channel_TypeDef *DMAy_Channelx, DMA_InitTypeDef *DMA_InitStruct) +{ + uint32_t tmpreg = 0; + + tmpreg = DMAy_Channelx->CFGR; + tmpreg &= CFGR_CLEAR_Mask; + tmpreg |= DMA_InitStruct->DMA_DIR | DMA_InitStruct->DMA_Mode | + DMA_InitStruct->DMA_PeripheralInc | DMA_InitStruct->DMA_MemoryInc | + DMA_InitStruct->DMA_PeripheralDataSize | DMA_InitStruct->DMA_MemoryDataSize | + DMA_InitStruct->DMA_Priority | DMA_InitStruct->DMA_M2M; + + DMAy_Channelx->CFGR = tmpreg; + DMAy_Channelx->CNTR = DMA_InitStruct->DMA_BufferSize; + DMAy_Channelx->PADDR = DMA_InitStruct->DMA_PeripheralBaseAddr; + DMAy_Channelx->MADDR = DMA_InitStruct->DMA_MemoryBaseAddr; +} + +/********************************************************************* + * @fn DMA_StructInit + * + * @brief Fills each DMA_InitStruct member with its default value. + * + * @param DMAy_Channelx - here y can be 1 to select the DMA and x can be + * 1 to 8 for DMA1 to select the DMA Channel. + * DMA_InitStruct - pointer to a DMA_InitTypeDef structure that contains + * contains the configuration information for the specified DMA Channel. + * + * @return none + */ +void DMA_StructInit(DMA_InitTypeDef *DMA_InitStruct) +{ + DMA_InitStruct->DMA_PeripheralBaseAddr = 0; + DMA_InitStruct->DMA_MemoryBaseAddr = 0; + DMA_InitStruct->DMA_DIR = DMA_DIR_PeripheralSRC; + DMA_InitStruct->DMA_BufferSize = 0; + DMA_InitStruct->DMA_PeripheralInc = DMA_PeripheralInc_Disable; + DMA_InitStruct->DMA_MemoryInc = DMA_MemoryInc_Disable; + DMA_InitStruct->DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte; + DMA_InitStruct->DMA_MemoryDataSize = DMA_MemoryDataSize_Byte; + DMA_InitStruct->DMA_Mode = DMA_Mode_Normal; + DMA_InitStruct->DMA_Priority = DMA_Priority_Low; + DMA_InitStruct->DMA_M2M = DMA_M2M_Disable; +} + +/********************************************************************* + * @fn DMA_Cmd + * + * @brief Enables or disables the specified DMAy Channelx. + * + * @param DMAy_Channelx - here y can be 1 to select the DMA and x can be + * 1 to 8 for DMA1 to select the DMA Channel. + * NewState - new state of the DMAy Channelx(ENABLE or DISABLE). + * + * @return none + */ +void DMA_Cmd(DMA_Channel_TypeDef *DMAy_Channelx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + DMAy_Channelx->CFGR |= DMA_CFGR1_EN; + } + else + { + DMAy_Channelx->CFGR &= (uint16_t)(~DMA_CFGR1_EN); + } +} + +/********************************************************************* + * @fn DMA_ITConfig + * + * @brief Enables or disables the specified DMAy Channelx interrupts. + * + * @param DMAy_Channelx - here y can be 1 to select the DMA and x can be + * 1 to 8 for DMA1 to select the DMA Channel. + * DMA_IT - specifies the DMA interrupts sources to be enabled + * or disabled. + * DMA_IT_TC - Transfer complete interrupt mask + * DMA_IT_HT - Half transfer interrupt mask + * DMA_IT_TE - Transfer error interrupt mask + * NewState - new state of the DMAy Channelx(ENABLE or DISABLE). + * + * @return none + */ +void DMA_ITConfig(DMA_Channel_TypeDef *DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + DMAy_Channelx->CFGR |= DMA_IT; + } + else + { + DMAy_Channelx->CFGR &= ~DMA_IT; + } +} + +/********************************************************************* + * @fn DMA_SetCurrDataCounter + * + * @brief Sets the number of data units in the current DMAy Channelx transfer. + * + * @param DMAy_Channelx - here y can be 1 to select the DMA and x can be + * 1 to 8 for DMA1 to select the DMA Channel. + * DataNumber - The number of data units in the current DMAy Channelx + * transfer. + * + * @return none + */ +void DMA_SetCurrDataCounter(DMA_Channel_TypeDef *DMAy_Channelx, uint16_t DataNumber) +{ + DMAy_Channelx->CNTR = DataNumber; +} + +/********************************************************************* + * @fn DMA_GetCurrDataCounter + * + * @brief Returns the number of remaining data units in the current + * DMAy Channelx transfer. + * + * @param DMAy_Channelx - here y can be 1 to select the DMA and x can be + * 1 to 8 for DMA1 to select the DMA Channel. + * + * @return DataNumber - The number of remaining data units in the current + * DMAy Channelx transfer. + */ +uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef *DMAy_Channelx) +{ + return ((uint16_t)(DMAy_Channelx->CNTR)); +} + +/********************************************************************* + * @fn DMA_GetFlagStatus + * + * @brief Checks whether the specified DMAy Channelx flag is set or not. + * + * @param DMAy_FLAG - specifies the flag to check. + * DMA1_FLAG_GL1 - DMA1 Channel1 global flag. + * DMA1_FLAG_TC1 - DMA1 Channel1 transfer complete flag. + * DMA1_FLAG_HT1 - DMA1 Channel1 half transfer flag. + * DMA1_FLAG_TE1 - DMA1 Channel1 transfer error flag. + * DMA1_FLAG_GL2 - DMA1 Channel2 global flag. + * DMA1_FLAG_TC2 - DMA1 Channel2 transfer complete flag. + * DMA1_FLAG_HT2 - DMA1 Channel2 half transfer flag. + * DMA1_FLAG_TE2 - DMA1 Channel2 transfer error flag. + * DMA1_FLAG_GL3 - DMA1 Channel3 global flag. + * DMA1_FLAG_TC3 - DMA1 Channel3 transfer complete flag. + * DMA1_FLAG_HT3 - DMA1 Channel3 half transfer flag. + * DMA1_FLAG_TE3 - DMA1 Channel3 transfer error flag. + * DMA1_FLAG_GL4 - DMA1 Channel4 global flag. + * DMA1_FLAG_TC4 - DMA1 Channel4 transfer complete flag. + * DMA1_FLAG_HT4 - DMA1 Channel4 half transfer flag. + * DMA1_FLAG_TE4 - DMA1 Channel4 transfer error flag. + * DMA1_FLAG_GL5 - DMA1 Channel5 global flag. + * DMA1_FLAG_TC5 - DMA1 Channel5 transfer complete flag. + * DMA1_FLAG_HT5 - DMA1 Channel5 half transfer flag. + * DMA1_FLAG_TE5 - DMA1 Channel5 transfer error flag. + * DMA1_FLAG_GL6 - DMA1 Channel6 global flag. + * DMA1_FLAG_TC6 - DMA1 Channel6 transfer complete flag. + * DMA1_FLAG_HT6 - DMA1 Channel6 half transfer flag. + * DMA1_FLAG_TE6 - DMA1 Channel6 transfer error flag. + * DMA1_FLAG_GL7 - DMA1 Channel7 global flag. + * DMA1_FLAG_TC7 - DMA1 Channel7 transfer complete flag. + * DMA1_FLAG_HT7 - DMA1 Channel7 half transfer flag. + * DMA1_FLAG_TE7 - DMA1 Channel7 transfer error flag. + * DMA1_FLAG_GL8 - DMA1 Channel8 global flag. + * DMA1_FLAG_TC8 - DMA1 Channel8 transfer complete flag. + * DMA1_FLAG_HT8 - DMA1 Channel8 half transfer flag. + * DMA1_FLAG_TE8 - DMA1 Channel8 transfer error flag. + * + * @return The new state of DMAy_FLAG (SET or RESET). + */ +FlagStatus DMA_GetFlagStatus(uint32_t DMAy_FLAG) +{ + FlagStatus bitstatus = RESET; + uint32_t tmpreg = 0; + + tmpreg = DMA1->INTFR; + + if((tmpreg & DMAy_FLAG) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn DMA_ClearFlag + * + * @brief Clears the DMAy Channelx's pending flags. + * + * @param DMAy_FLAG - specifies the flag to check. + * DMA1_FLAG_GL1 - DMA1 Channel1 global flag. + * DMA1_FLAG_TC1 - DMA1 Channel1 transfer complete flag. + * DMA1_FLAG_HT1 - DMA1 Channel1 half transfer flag. + * DMA1_FLAG_TE1 - DMA1 Channel1 transfer error flag. + * DMA1_FLAG_GL2 - DMA1 Channel2 global flag. + * DMA1_FLAG_TC2 - DMA1 Channel2 transfer complete flag. + * DMA1_FLAG_HT2 - DMA1 Channel2 half transfer flag. + * DMA1_FLAG_TE2 - DMA1 Channel2 transfer error flag. + * DMA1_FLAG_GL3 - DMA1 Channel3 global flag. + * DMA1_FLAG_TC3 - DMA1 Channel3 transfer complete flag. + * DMA1_FLAG_HT3 - DMA1 Channel3 half transfer flag. + * DMA1_FLAG_TE3 - DMA1 Channel3 transfer error flag. + * DMA1_FLAG_GL4 - DMA1 Channel4 global flag. + * DMA1_FLAG_TC4 - DMA1 Channel4 transfer complete flag. + * DMA1_FLAG_HT4 - DMA1 Channel4 half transfer flag. + * DMA1_FLAG_TE4 - DMA1 Channel4 transfer error flag. + * DMA1_FLAG_GL5 - DMA1 Channel5 global flag. + * DMA1_FLAG_TC5 - DMA1 Channel5 transfer complete flag. + * DMA1_FLAG_HT5 - DMA1 Channel5 half transfer flag. + * DMA1_FLAG_TE5 - DMA1 Channel5 transfer error flag. + * DMA1_FLAG_GL6 - DMA1 Channel6 global flag. + * DMA1_FLAG_TC6 - DMA1 Channel6 transfer complete flag. + * DMA1_FLAG_HT6 - DMA1 Channel6 half transfer flag. + * DMA1_FLAG_TE6 - DMA1 Channel6 transfer error flag. + * DMA1_FLAG_GL7 - DMA1 Channel7 global flag. + * DMA1_FLAG_TC7 - DMA1 Channel7 transfer complete flag. + * DMA1_FLAG_HT7 - DMA1 Channel7 half transfer flag. + * DMA1_FLAG_TE7 - DMA1 Channel7 transfer error flag. + * DMA1_FLAG_GL8 - DMA1 Channel8 global flag. + * DMA1_FLAG_TC8 - DMA1 Channel8 transfer complete flag. + * DMA1_FLAG_HT8 - DMA1 Channel8 half transfer flag. + * DMA1_FLAG_TE8 - DMA1 Channel8 transfer error flag. + * + * @return none + */ +void DMA_ClearFlag(uint32_t DMAy_FLAG) +{ + DMA1->INTFCR = DMAy_FLAG; +} + +/********************************************************************* + * @fn DMA_GetITStatus + * + * @brief Checks whether the specified DMAy Channelx interrupt has + * occurred or not. + * + * @param DMAy_IT - specifies the DMAy interrupt source to check. + * DMA1_IT_GL1 - DMA1 Channel1 global flag. + * DMA1_IT_TC1 - DMA1 Channel1 transfer complete flag. + * DMA1_IT_HT1 - DMA1 Channel1 half transfer flag. + * DMA1_IT_TE1 - DMA1 Channel1 transfer error flag. + * DMA1_IT_GL2 - DMA1 Channel2 global flag. + * DMA1_IT_TC2 - DMA1 Channel2 transfer complete flag. + * DMA1_IT_HT2 - DMA1 Channel2 half transfer flag. + * DMA1_IT_TE2 - DMA1 Channel2 transfer error flag. + * DMA1_IT_GL3 - DMA1 Channel3 global flag. + * DMA1_IT_TC3 - DMA1 Channel3 transfer complete flag. + * DMA1_IT_HT3 - DMA1 Channel3 half transfer flag. + * DMA1_IT_TE3 - DMA1 Channel3 transfer error flag. + * DMA1_IT_GL4 - DMA1 Channel4 global flag. + * DMA1_IT_TC4 - DMA1 Channel4 transfer complete flag. + * DMA1_IT_HT4 - DMA1 Channel4 half transfer flag. + * DMA1_IT_TE4 - DMA1 Channel4 transfer error flag. + * DMA1_IT_GL5 - DMA1 Channel5 global flag. + * DMA1_IT_TC5 - DMA1 Channel5 transfer complete flag. + * DMA1_IT_HT5 - DMA1 Channel5 half transfer flag. + * DMA1_IT_TE5 - DMA1 Channel5 transfer error flag. + * DMA1_IT_GL6 - DMA1 Channel6 global flag. + * DMA1_IT_TC6 - DMA1 Channel6 transfer complete flag. + * DMA1_IT_HT6 - DMA1 Channel6 half transfer flag. + * DMA1_IT_TE6 - DMA1 Channel6 transfer error flag. + * DMA1_IT_GL7 - DMA1 Channel7 global flag. + * DMA1_IT_TC7 - DMA1 Channel7 transfer complete flag. + * DMA1_IT_HT7 - DMA1 Channel7 half transfer flag. + * DMA1_IT_TE7 - DMA1 Channel7 transfer error flag. + * DMA1_IT_GL8 - DMA1 Channel8 global flag. + * DMA1_IT_TC8 - DMA1 Channel8 transfer complete flag. + * DMA1_IT_HT8 - DMA1 Channel8 half transfer flag. + * DMA1_IT_TE8 - DMA1 Channel8 transfer error flag. + * + * @return The new state of DMAy_IT (SET or RESET). + */ +ITStatus DMA_GetITStatus(uint32_t DMAy_IT) +{ + ITStatus bitstatus = RESET; + uint32_t tmpreg = 0; + + tmpreg = DMA1->INTFR; + + if((tmpreg & DMAy_IT) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/********************************************************************* + * @fn DMA_ClearITPendingBit + * + * @brief Clears the DMAy Channelx's interrupt pending bits. + * + * @param DMAy_IT - specifies the DMAy interrupt source to check. + * DMA1_IT_GL1 - DMA1 Channel1 global flag. + * DMA1_IT_TC1 - DMA1 Channel1 transfer complete flag. + * DMA1_IT_HT1 - DMA1 Channel1 half transfer flag. + * DMA1_IT_TE1 - DMA1 Channel1 transfer error flag. + * DMA1_IT_GL2 - DMA1 Channel2 global flag. + * DMA1_IT_TC2 - DMA1 Channel2 transfer complete flag. + * DMA1_IT_HT2 - DMA1 Channel2 half transfer flag. + * DMA1_IT_TE2 - DMA1 Channel2 transfer error flag. + * DMA1_IT_GL3 - DMA1 Channel3 global flag. + * DMA1_IT_TC3 - DMA1 Channel3 transfer complete flag. + * DMA1_IT_HT3 - DMA1 Channel3 half transfer flag. + * DMA1_IT_TE3 - DMA1 Channel3 transfer error flag. + * DMA1_IT_GL4 - DMA1 Channel4 global flag. + * DMA1_IT_TC4 - DMA1 Channel4 transfer complete flag. + * DMA1_IT_HT4 - DMA1 Channel4 half transfer flag. + * DMA1_IT_TE4 - DMA1 Channel4 transfer error flag. + * DMA1_IT_GL5 - DMA1 Channel5 global flag. + * DMA1_IT_TC5 - DMA1 Channel5 transfer complete flag. + * DMA1_IT_HT5 - DMA1 Channel5 half transfer flag. + * DMA1_IT_TE5 - DMA1 Channel5 transfer error flag. + * DMA1_IT_GL6 - DMA1 Channel6 global flag. + * DMA1_IT_TC6 - DMA1 Channel6 transfer complete flag. + * DMA1_IT_HT6 - DMA1 Channel6 half transfer flag. + * DMA1_IT_TE6 - DMA1 Channel6 transfer error flag. + * DMA1_IT_GL7 - DMA1 Channel7 global flag. + * DMA1_IT_TC7 - DMA1 Channel7 transfer complete flag. + * DMA1_IT_HT7 - DMA1 Channel7 half transfer flag. + * DMA1_IT_TE7 - DMA1 Channel7 transfer error flag. + * DMA1_IT_GL8 - DMA1 Channel8 global flag. + * DMA1_IT_TC8 - DMA1 Channel8 transfer complete flag. + * DMA1_IT_HT8 - DMA1 Channel8 half transfer flag. + * DMA1_IT_TE8 - DMA1 Channel8 transfer error flag. + * + * @return none + */ +void DMA_ClearITPendingBit(uint32_t DMAy_IT) +{ + DMA1->INTFCR = DMAy_IT; +} diff --git a/ZDBMS/BMS_CC/Peripheral/src/ch32l103_exti.c b/ZDBMS/BMS_CC/Peripheral/src/ch32l103_exti.c new file mode 100644 index 0000000..5cdc822 --- /dev/null +++ b/ZDBMS/BMS_CC/Peripheral/src/ch32l103_exti.c @@ -0,0 +1,182 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32l103_exti.c + * Author : WCH + * Version : V1.0.0 + * Date : 2023/07/08 + * Description : This file provides all the EXTI firmware functions. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#include "ch32l103_exti.h" + +/* No interrupt selected */ +#define EXTI_LINENONE ((uint32_t)0x000000) + +/********************************************************************* + * @fn EXTI_DeInit + * + * @brief Deinitializes the EXTI peripheral registers to their default + * reset values. + * + * @return none. + */ +void EXTI_DeInit(void) +{ + EXTI->INTENR = 0x00000000; + EXTI->EVENR = 0x00000000; + EXTI->RTENR = 0x00000000; + EXTI->FTENR = 0x00000000; + EXTI->INTFR = 0x007FFFFF; +} + +/********************************************************************* + * @fn EXTI_Init + * + * @brief Initializes the EXTI peripheral according to the specified + * parameters in the EXTI_InitStruct. + * + * @param EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure + * + * @return none. + */ +void EXTI_Init(EXTI_InitTypeDef *EXTI_InitStruct) +{ + uint32_t tmp = 0; + + tmp = (uint32_t)EXTI_BASE; + if(EXTI_InitStruct->EXTI_LineCmd != DISABLE) + { + EXTI->INTENR &= ~EXTI_InitStruct->EXTI_Line; + EXTI->EVENR &= ~EXTI_InitStruct->EXTI_Line; + tmp += EXTI_InitStruct->EXTI_Mode; + *(__IO uint32_t *)tmp |= EXTI_InitStruct->EXTI_Line; + EXTI->RTENR &= ~EXTI_InitStruct->EXTI_Line; + EXTI->FTENR &= ~EXTI_InitStruct->EXTI_Line; + if(EXTI_InitStruct->EXTI_Trigger == EXTI_Trigger_Rising_Falling) + { + EXTI->RTENR |= EXTI_InitStruct->EXTI_Line; + EXTI->FTENR |= EXTI_InitStruct->EXTI_Line; + } + else + { + tmp = (uint32_t)EXTI_BASE; + tmp += EXTI_InitStruct->EXTI_Trigger; + *(__IO uint32_t *)tmp |= EXTI_InitStruct->EXTI_Line; + } + } + else + { + tmp += EXTI_InitStruct->EXTI_Mode; + *(__IO uint32_t *)tmp &= ~EXTI_InitStruct->EXTI_Line; + } +} + +/********************************************************************* + * @fn EXTI_StructInit + * + * @brief Fills each EXTI_InitStruct member with its reset value. + * + * @param EXTI_InitStruct - pointer to a EXTI_InitTypeDef structure + * + * @return none. + */ +void EXTI_StructInit(EXTI_InitTypeDef *EXTI_InitStruct) +{ + EXTI_InitStruct->EXTI_Line = EXTI_LINENONE; + EXTI_InitStruct->EXTI_Mode = EXTI_Mode_Interrupt; + EXTI_InitStruct->EXTI_Trigger = EXTI_Trigger_Falling; + EXTI_InitStruct->EXTI_LineCmd = DISABLE; +} + +/********************************************************************* + * @fn EXTI_GenerateSWInterrupt + * + * @brief Generates a Software interrupt. + * + * @param EXTI_Line - specifies the EXTI lines to be enabled or disabled. + * + * @return none. + */ +void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line) +{ + EXTI->SWIEVR |= EXTI_Line; +} + +/********************************************************************* + * @fn EXTI_GetFlagStatus + * + * @brief Checks whether the specified EXTI line flag is set or not. + * + * @param EXTI_Line - specifies the EXTI lines to be enabled or disabled. + * + * @return The new state of EXTI_Line (SET or RESET). + */ +FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line) +{ + FlagStatus bitstatus = RESET; + if((EXTI->INTFR & EXTI_Line) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/********************************************************************* + * @fn EXTI_ClearFlag + * + * @brief Clears the EXTI's line pending flags. + * + * @param EXTI_Line - specifies the EXTI lines to be enabled or disabled. + * + * @return None + */ +void EXTI_ClearFlag(uint32_t EXTI_Line) +{ + EXTI->INTFR = EXTI_Line; +} + +/********************************************************************* + * @fn EXTI_GetITStatus + * + * @brief Checks whether the specified EXTI line is asserted or not. + * + * @param EXTI_Line - specifies the EXTI lines to be enabled or disabled. + * + * @return The new state of EXTI_Line (SET or RESET). + */ +ITStatus EXTI_GetITStatus(uint32_t EXTI_Line) +{ + ITStatus bitstatus = RESET; + uint32_t enablestatus = 0; + + enablestatus = EXTI->INTENR & EXTI_Line; + if(((EXTI->INTFR & EXTI_Line) != (uint32_t)RESET) && (enablestatus != (uint32_t)RESET)) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/********************************************************************* + * @fn EXTI_ClearITPendingBit + * + * @brief Clears the EXTI's line pending bits. + * + * @param EXTI_Line - specifies the EXTI lines to be enabled or disabled. + * + * @return none + */ +void EXTI_ClearITPendingBit(uint32_t EXTI_Line) +{ + EXTI->INTFR = EXTI_Line; +} diff --git a/ZDBMS/BMS_CC/Peripheral/src/ch32l103_flash.c b/ZDBMS/BMS_CC/Peripheral/src/ch32l103_flash.c new file mode 100644 index 0000000..7da1107 --- /dev/null +++ b/ZDBMS/BMS_CC/Peripheral/src/ch32l103_flash.c @@ -0,0 +1,1009 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32l103_flash.c + * Author : WCH + * Version : V1.0.1 + * Date : 2024/12/11 + * Description : This file provides all the FLASH firmware functions. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#include "ch32l103_flash.h" + +/* Flash Access Control Register bits */ +#define ACR_LATENCY_Mask ((uint32_t)0xFFFFFFFC) + +/* Flash Control Register bits */ +#define CR_PER_Set ((uint32_t)0x00000002) +#define CR_PER_Reset ((uint32_t)0xFFFFFFFD) +#define CR_MER_Set ((uint32_t)0x00000004) +#define CR_MER_Reset ((uint32_t)0xFFFFFFFB) +#define CR_OPTER_Set ((uint32_t)0x00000020) +#define CR_OPTER_Reset ((uint32_t)0xFFFFFFDF) +#define CR_STRT_Set ((uint32_t)0x00000040) +#define CR_LOCK_Set ((uint32_t)0x00000080) +#define CR_FLOCK_Set ((uint32_t)0x00008000) +#define CR_PAGE_PG ((uint32_t)0x00010000) +#define CR_PAGE_ER ((uint32_t)0x00020000) +#define CR_PAGE_ER_Reset ((uint32_t)0xFFFDFFFF) +#define CR_BUF_LOAD ((uint32_t)0x00040000) +#define CR_BUF_RST ((uint32_t)0x00080000) +#define CR_BER32 ((uint32_t)0x00800000) + +/* FLASH Status Register bits */ +#define SR_BSY ((uint32_t)0x00000001) +#define SR_WRPRTERR ((uint32_t)0x00000010) +#define SR_EOP ((uint32_t)0x00000020) + +/* FLASH Mask */ +#define RDPRT_Mask ((uint32_t)0x00000002) +#define WRP0_Mask ((uint32_t)0x000000FF) +#define WRP1_Mask ((uint32_t)0x0000FF00) +#define WRP2_Mask ((uint32_t)0x00FF0000) +#define WRP3_Mask ((uint32_t)0xFF000000) + +/* FLASH Keys */ +#define RDP_Key ((uint16_t)0x00A5) +#define FLASH_KEY1 ((uint32_t)0x45670123) +#define FLASH_KEY2 ((uint32_t)0xCDEF89AB) + +/* Delay definition */ +#define EraseTimeout ((uint32_t)0x000B0000) +#define ProgramTimeout ((uint32_t)0x00005000) + +/* Flash Program Valid Address */ +#define ValidAddrStart (FLASH_BASE) +#define ValidAddrEnd (FLASH_BASE + 0x10000) + +/* FLASH Size */ +#define Size_256B 0x100 +#define Size_1KB 0x400 +#define Size_32KB 0x8000 + +/******************************************************************************** + * @fn FLASH_SetLatency + * + * @brief Sets the code latency value. + * + * @param FLASH_Latency - specifies the FLASH Latency mode. + * FLASH_Latency_0 - FLASH Latency mode 0 + * FLASH_Latency_1 - FLASH Latency mode 1 + * FLASH_Latency_2 - FLASH Latency mode 2 + * + * @return None + */ +void FLASH_SetLatency(uint32_t FLASH_Latency) +{ + uint32_t tmpreg = 0; + + tmpreg = FLASH->ACTLR; + tmpreg &= ACR_LATENCY_Mask; + tmpreg |= FLASH_Latency; + FLASH->ACTLR = tmpreg; +} + +/******************************************************************************** + * @fn FLASH_Unlock + * + * @brief Unlocks the FLASH Program Erase Controller. + * + * @return None + */ +void FLASH_Unlock(void) +{ + /* Authorize the FPEC of Bank1 Access */ + FLASH->KEYR = FLASH_KEY1; + FLASH->KEYR = FLASH_KEY2; +} + +/******************************************************************************** + * @fn FLASH_Lock + * + * @brief Locks the FLASH Program Erase Controller. + * + * @return None + */ +void FLASH_Lock(void) +{ + FLASH->CTLR |= CR_LOCK_Set; +} + +/******************************************************************************** + * @fn FLASH_ErasePage + * + * @brief Erases a specified FLASH page(1KB). + * + * @param Page_Address - The page address to be erased. + * + * @return FLASH Status - FLASH_BUSY, FLASH_ERROR_PG, + * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. + */ +FLASH_Status FLASH_ErasePage(uint32_t Page_Address) +{ + FLASH_Status status = FLASH_COMPLETE; + + status = FLASH_WaitForLastOperation(EraseTimeout); + + if(status == FLASH_COMPLETE) + { + FLASH->CTLR &= (CR_OPTER_Reset & CR_PAGE_ER_Reset); + FLASH->CTLR |= CR_PER_Set; + FLASH->ADDR = Page_Address; + FLASH->CTLR |= CR_STRT_Set; + + status = FLASH_WaitForLastOperation(EraseTimeout); + + FLASH->CTLR &= CR_PER_Reset; + } + + return status; +} + +/******************************************************************************** + * @fn FLASH_EraseAllPages + * + * @brief Erases all FLASH pages. + * + * @return FLASH Status - FLASH_BUSY, FLASH_ERROR_PG, + * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. + */ +FLASH_Status FLASH_EraseAllPages(void) +{ + FLASH_Status status = FLASH_COMPLETE; + + status = FLASH_WaitForLastOperation(EraseTimeout); + if(status == FLASH_COMPLETE) + { + FLASH->CTLR &= (CR_OPTER_Reset & CR_PAGE_ER_Reset); + FLASH->CTLR |= CR_MER_Set; + FLASH->CTLR |= CR_STRT_Set; + + status = FLASH_WaitForLastOperation(EraseTimeout); + + FLASH->CTLR &= CR_MER_Reset; + } + + return status; +} + +/******************************************************************************** + * @fn FLASH_EraseOptionBytes + * + * @brief Erases the FLASH option bytes. + * + * @return FLASH Status - FLASH_BUSY, FLASH_ERROR_PG, + * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. + */ +FLASH_Status FLASH_EraseOptionBytes(void) +{ + FLASH_Status status = FLASH_COMPLETE; + + status = FLASH_WaitForLastOperation(EraseTimeout); + if(status == FLASH_COMPLETE) + { + FLASH_Unlock(); + + FLASH->OBKEYR = FLASH_KEY1; + FLASH->OBKEYR = FLASH_KEY2; + + FLASH->CTLR &= (CR_OPTER_Reset & CR_PAGE_ER_Reset); + FLASH->CTLR |= CR_OPTER_Set; + FLASH->CTLR |= CR_STRT_Set; + status = FLASH_WaitForLastOperation(EraseTimeout); + + FLASH->CTLR &= CR_OPTER_Reset; + + FLASH_Lock(); + } + return status; +} + +/********************************************************************* + * @fn FLASH_OptionBytePR + * + * @brief Programs option bytes. + * + * @param pbuf - data. + * + * @return none + */ +void FLASH_OptionBytePR(u32* pbuf) +{ + uint8_t i; + + FLASH_EraseOptionBytes(); + FLASH_Unlock_Fast(); + FLASH_BufReset(); + + for(i=0; i<4; i++) + { + FLASH_BufLoad((OB_BASE + 4*i), *pbuf++); + } + + FLASH_ProgramPage_Fast(OB_BASE); + FLASH_Lock_Fast(); +} + +/********************************************************************* + * @fn FLASH_EnableWriteProtection + * + * @brief Write protects the desired sectors + * + * @param FLASH_Sectors - specifies the address of the pages to be write protected. + * + * @return FLASH Status - FLASH_BUSY, FLASH_ERROR_PG, + * FLASH_ERROR_WRP, FLASH_COMPLETE , FLASH_TIMEOUT or FLASH_RDP. + */ +FLASH_Status FLASH_EnableWriteProtection(uint32_t FLASH_Pages) +{ + uint8_t WRP0_Data = 0xFF, WRP1_Data = 0xFF, WRP2_Data = 0xFF, WRP3_Data = 0xFF; + uint32_t buf[4]; + uint8_t i; + FLASH_Status status = FLASH_COMPLETE; + + if((FLASH->OBR & RDPRT_Mask) != (uint32_t)RESET) + { + status = FLASH_RDP; + } + else{ + FLASH_Pages = (uint32_t)(~FLASH_Pages); + WRP0_Data = (uint8_t)(FLASH_Pages & WRP0_Mask); + WRP1_Data = (uint8_t)((FLASH_Pages & WRP1_Mask) >> 8); + WRP2_Data = (uint8_t)((FLASH_Pages & WRP2_Mask) >> 16); + WRP3_Data = (uint8_t)((FLASH_Pages & WRP3_Mask) >> 24); + + status = FLASH_WaitForLastOperation(ProgramTimeout); + + if(status == FLASH_COMPLETE) + { + for(i=0; i<4; i++){ + buf[i] = *(uint32_t*)(OB_BASE + 4*i); + } + + buf[2] = ((uint32_t)(((uint32_t)(WRP0_Data) & 0x00FF) + (((uint32_t)(~WRP0_Data) & 0x00FF) << 8) \ + + (((uint32_t)(WRP1_Data) & 0x00FF) << 16) + (((uint32_t)(~WRP1_Data) & 0x00FF) << 24))); + buf[3] = ((uint32_t)(((uint32_t)(WRP2_Data) & 0x00FF) + (((uint32_t)(~WRP2_Data) & 0x00FF) << 8) \ + + (((uint32_t)(WRP3_Data) & 0x00FF) << 16) + (((uint32_t)(~WRP3_Data) & 0x00FF) << 24))); + + FLASH_OptionBytePR(buf); + } + } + + return status; +} + +/********************************************************************* + * @fn FLASH_EnableReadOutProtection + * + * @brief Enables the read out protection. + * + * @param Newstate - new state of the ReadOut Protection(ENABLE or DISABLE). + * + * @return FLASH Status - FLASH_BUSY, FLASH_ERROR_PG, + * FLASH_ERROR_WRP, FLASH_COMPLETE, FLASH_TIMEOUT or FLASH_RDP. + */ +FLASH_Status FLASH_EnableReadOutProtection(void) +{ + FLASH_Status status = FLASH_COMPLETE; + uint32_t buf[4]; + uint8_t i; + + if((FLASH->OBR & RDPRT_Mask) != (uint32_t)RESET) + { + status = FLASH_RDP; + } + else{ + status = FLASH_WaitForLastOperation(EraseTimeout); + if(status == FLASH_COMPLETE) + { + for(i=0; i<4; i++){ + buf[i] = *(uint32_t*)(OB_BASE + 4*i); + } + + buf[0] = 0x000000FF + (buf[0] & 0xFFFF0000); + FLASH_OptionBytePR(buf); + } + } + + return status; +} + +/********************************************************************* + * @fn FLASH_UserOptionByteConfig + * + * @brief Programs the FLASH User Option Byte - IWDG_SW / RST_STOP / RST_STDBY/CAN_BusOff_MODE. + * + * @param OB_IWDG - Selects the IWDG mode. + * OB_IWDG_SW - Software IWDG selected + * OB_IWDG_HW - Hardware IWDG selected + * OB_STOP - Reset event when entering STOP mode. + * OB_STOP_NoRST - No reset generated when entering in STOP + * OB_STOP_RST - Reset generated when entering in STOP + * OB_STDBY - Reset event when entering Standby mode. + * OB_STDBY_NoRST - No reset generated when entering in STANDBY + * OB_STDBY_RST - Reset generated when entering in STANDBY + * OB_CAN - Set CAN bus off recovery time. + * OB_CAN_BusOff_MODE1 - Faster recovery time from Bus off. + * OB_CAN_BusOff_MODE2 - Normal recovery time from bus off. + * + * @return FLASH Status - FLASH_BUSY, FLASH_ERROR_PG, + * FLASH_ERROR_WRP, FLASH_COMPLETE , FLASH_TIMEOUT or FLASH_RDP. + */ +FLASH_Status FLASH_UserOptionByteConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY, uint8_t OB_CAN) +{ + FLASH_Status status = FLASH_COMPLETE; + uint8_t UserByte; + uint32_t buf[4]; + uint8_t i; + + if((FLASH->OBR & RDPRT_Mask) != (uint32_t)RESET) + { + status = FLASH_RDP; + } + else{ + UserByte = OB_IWDG | (uint8_t)(OB_STOP | (uint8_t)(OB_STDBY | (uint8_t)(OB_CAN | (uint8_t)0xD8))); + + for(i=0; i<4; i++){ + buf[i] = *(uint32_t*)(OB_BASE + 4*i); + } + buf[0] = ((uint32_t)((((uint32_t)(UserByte) & 0x00FF) << 16) + (((uint32_t)(~UserByte) & 0x00FF) << 24))) + 0x00005AA5; + + FLASH_OptionBytePR(buf); + } + + return status; +} + +/********************************************************************* + * @fn FLASH_GetUserOptionByte + * + * @brief Returns the FLASH User Option Bytes values. + * + * @return The FLASH User Option Bytes values:IWDG_SW(Bit0), RST_STOP(Bit1), + * RST_STDBY(Bit2) ,CAN_BusOff_MODE(bit7) ,DATA0(bit[15:8]) and + * DATA1(bit[23:16]). + */ +uint32_t FLASH_GetUserOptionByte(void) +{ + return (uint32_t)(FLASH->OBR >> 2); +} + +/********************************************************************* + * @fn FLASH_GetWriteProtectionOptionByte + * + * @brief Returns the FLASH Write Protection Option Bytes Register value. + * + * @return The FLASH Write Protection Option Bytes Register value. + */ +uint32_t FLASH_GetWriteProtectionOptionByte(void) +{ + return (uint32_t)(FLASH->WPR); +} + +/********************************************************************* + * @fn FLASH_GetReadOutProtectionStatus + * + * @brief Checks whether the FLASH Read Out Protection Status is set or not. + * + * @return FLASH ReadOut Protection Status(SET or RESET) + */ +FlagStatus FLASH_GetReadOutProtectionStatus(void) +{ + FlagStatus readoutstatus = RESET; + if((FLASH->OBR & RDPRT_Mask) != (uint32_t)RESET) + { + readoutstatus = SET; + } + else + { + readoutstatus = RESET; + } + return readoutstatus; +} + +/********************************************************************* + * @fn FLASH_ITConfig + * + * @brief Enables or disables the specified FLASH interrupts. + * + * @param FLASH_IT - specifies the FLASH interrupt sources to be enabled or disabled. + * FLASH_IT_ERROR - FLASH Error Interrupt + * FLASH_IT_EOP - FLASH end of operation Interrupt + * NewState - new state of the specified Flash interrupts(ENABLE or DISABLE). + * + * @return FLASH Prefetch Buffer Status (SET or RESET). + */ +void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + FLASH->CTLR |= FLASH_IT; + } + else + { + FLASH->CTLR &= ~(uint32_t)FLASH_IT; + } +} + +/********************************************************************* + * @fn FLASH_GetFlagStatus + * + * @brief Checks whether the specified FLASH flag is set or not. + * + * @param FLASH_FLAG - specifies the FLASH flag to check. + * FLASH_FLAG_BSY - FLASH Busy flag + * FLASH_FLAG_WRPRTERR - FLASH Write protected error flag + * FLASH_FLAG_EOP - FLASH End of Operation flag + * FLASH_FLAG_WAKE_UP - FLASH Wake up of Operation flag + * FLASH_FLAG_OPTERR - FLASH Option Byte error flag + * + * @return The new state of FLASH_FLAG (SET or RESET). + */ +FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG) +{ + FlagStatus bitstatus = RESET; + + if(FLASH_FLAG == FLASH_FLAG_OPTERR) + { + if((FLASH->OBR & FLASH_FLAG_OPTERR) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + } + else + { + if((FLASH->STATR & FLASH_FLAG) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + } + return bitstatus; +} + +/********************************************************************* + * @fn FLASH_ClearFlag + * + * @brief Clears the FLASH's pending flags. + * + * @param FLASH_FLAG - specifies the FLASH flags to clear. + * FLASH_FLAG_WRPRTERR - FLASH Write protected error flag + * FLASH_FLAG_EOP - FLASH End of Operation flag + * + * @return none + */ +void FLASH_ClearFlag(uint32_t FLASH_FLAG) +{ + FLASH->STATR = FLASH_FLAG; +} + +/********************************************************************* + * @fn FLASH_GetStatus + * + * @brief Returns the FLASH Status. + * + * @return FLASH Status - FLASH_BUSY, FLASH_ERROR_PG, + * FLASH_ERROR_WRP or FLASH_COMPLETE. + */ +FLASH_Status FLASH_GetStatus(void) +{ + FLASH_Status flashstatus = FLASH_COMPLETE; + + if((FLASH->STATR & FLASH_FLAG_BSY) == FLASH_FLAG_BSY) + { + flashstatus = FLASH_BUSY; + } + else + { + if((FLASH->STATR & FLASH_FLAG_WRPRTERR) != 0) + { + flashstatus = FLASH_ERROR_WRP; + } + else + { + flashstatus = FLASH_COMPLETE; + } + } + return flashstatus; +} + +/********************************************************************* + * @fn FLASH_GetBank1Status + * + * @brief Returns the FLASH Bank1 Status. + * + * @return FLASH Status - FLASH_BUSY, FLASH_ERROR_PG, + * FLASH_ERROR_WRP or FLASH_COMPLETE. + */ +FLASH_Status FLASH_GetBank1Status(void) +{ + FLASH_Status flashstatus = FLASH_COMPLETE; + + if((FLASH->STATR & FLASH_FLAG_BANK1_BSY) == FLASH_FLAG_BSY) + { + flashstatus = FLASH_BUSY; + } + else + { + if((FLASH->STATR & FLASH_FLAG_BANK1_WRPRTERR) != 0) + { + flashstatus = FLASH_ERROR_WRP; + } + else + { + flashstatus = FLASH_COMPLETE; + } + } + return flashstatus; +} + +/********************************************************************* + * @fn FLASH_WaitForLastOperation + * + * @brief Waits for a Flash operation to complete or a TIMEOUT to occur. + * + * @param Timeout - FLASH programming Timeout + * + * @return FLASH Status - FLASH_BUSY, FLASH_ERROR_PG, + * FLASH_ERROR_WRP or FLASH_COMPLETE. + */ +FLASH_Status FLASH_WaitForLastOperation(uint32_t Timeout) +{ + FLASH_Status status = FLASH_COMPLETE; + + status = FLASH_GetBank1Status(); + while((status == FLASH_BUSY) && (Timeout != 0x00)) + { + status = FLASH_GetBank1Status(); + Timeout--; + } + if(Timeout == 0x00) + { + status = FLASH_TIMEOUT; + } + return status; +} + +/********************************************************************* + * @fn FLASH_WaitForLastBank1Operation + * + * @brief Waits for a Flash operation on Bank1 to complete or a TIMEOUT to occur. + * + * @param Timeout - FLASH programming Timeout + * + * @return FLASH Status - FLASH_BUSY, FLASH_ERROR_PG, + * FLASH_ERROR_WRP or FLASH_COMPLETE. + */ +FLASH_Status FLASH_WaitForLastBank1Operation(uint32_t Timeout) +{ + FLASH_Status status = FLASH_COMPLETE; + + status = FLASH_GetBank1Status(); + while((status == FLASH_FLAG_BANK1_BSY) && (Timeout != 0x00)) + { + status = FLASH_GetBank1Status(); + Timeout--; + } + if(Timeout == 0x00) + { + status = FLASH_TIMEOUT; + } + return status; +} + +/********************************************************************* + * @fn FLASH_Unlock_Fast + * + * @brief Unlocks the Fast Program Erase Mode. + * + * @return none + */ +void FLASH_Unlock_Fast(void) +{ + /* Authorize the FPEC of Bank1 Access */ + FLASH->KEYR = FLASH_KEY1; + FLASH->KEYR = FLASH_KEY2; + + /* Fast program mode unlock */ + FLASH->MODEKEYR = FLASH_KEY1; + FLASH->MODEKEYR = FLASH_KEY2; +} + +/********************************************************************* + * @fn FLASH_Lock_Fast + * + * @brief Locks the Fast Program Erase Mode. + * + * @return none + */ +void FLASH_Lock_Fast(void) +{ + FLASH->CTLR |= CR_FLOCK_Set; +} + +/********************************************************************* + * @fn FLASH_BufReset + * + * @brief Flash Buffer reset. + * + * @return none + */ +void FLASH_BufReset(void) +{ + FLASH->CTLR &= (CR_OPTER_Reset & CR_PAGE_ER_Reset); + + FLASH->CTLR |= CR_PAGE_PG; + FLASH->CTLR |= CR_BUF_RST; + while(FLASH->STATR & SR_BSY) + ; + FLASH->CTLR &= ~CR_PAGE_PG; +} + +/********************************************************************* + * @fn FLASH_BufLoad + * + * @brief Flash Buffer load(4Byte). + * + * @param Address - specifies the address to be programmed. + * Data0 - specifies the data0 to be programmed. + * + * @return none + */ +void FLASH_BufLoad(uint32_t Address, uint32_t Data0) +{ + FLASH->CTLR &= (CR_OPTER_Reset & CR_PAGE_ER_Reset); + + FLASH->CTLR |= CR_PAGE_PG; + *(__IO uint32_t *)(Address) = Data0; + FLASH->CTLR |= CR_BUF_LOAD; + while(FLASH->STATR & SR_BSY) + ; + FLASH->CTLR &= ~CR_PAGE_PG; +} + +/********************************************************************* + * @fn FLASH_ErasePage_Fast + * + * @brief Erases a specified FLASH page (1page = 256Byte). + * + * @param Page_Address - The page address to be erased. + * + * @return none + */ +void FLASH_ErasePage_Fast(uint32_t Page_Address) +{ + FLASH->CTLR &= (CR_OPTER_Reset & CR_PAGE_ER_Reset); + + FLASH->CTLR |= CR_PAGE_ER; + FLASH->ADDR = Page_Address; + FLASH->CTLR |= CR_STRT_Set; + while(FLASH->STATR & SR_BSY) + ; + FLASH->CTLR &= ~CR_PAGE_ER; +} + +/********************************************************************* + * @fn FLASH_EraseBlock_32K_Fast + * + * @brief Erases a specified FLASH Block (1Block = 32KByte). + * + * @param Block_Address - The block address to be erased. + * + * @return none + */ +void FLASH_EraseBlock_32K_Fast(uint32_t Block_Address) +{ + FLASH->CTLR &= (CR_OPTER_Reset & CR_PAGE_ER_Reset); + + Block_Address &= 0xFFFF8000; + + FLASH->CTLR |= CR_BER32; + FLASH->ADDR = Block_Address; + FLASH->CTLR |= CR_STRT_Set; + while(FLASH->STATR & SR_BSY) + ; + FLASH->CTLR &= ~CR_BER32; +} + +/********************************************************************* + * @fn FLASH_ProgramPage_Fast + * + * @brief Program a specified FLASH page (1page = 256Byte). + * + * @param Page_Address - The page address to be programed. + * + * @return none + */ +void FLASH_ProgramPage_Fast(uint32_t Page_Address) +{ + FLASH->CTLR &= (CR_OPTER_Reset & CR_PAGE_ER_Reset); + + FLASH->CTLR |= CR_PAGE_PG; + FLASH->ADDR = Page_Address; + FLASH->CTLR |= CR_STRT_Set; + while(FLASH->STATR & SR_BSY) + ; + FLASH->CTLR &= ~CR_PAGE_PG; +} + +/********************************************************************* + * @fn ROM_ERASE + * + * @brief Select erases a specified FLASH . + * + * @param StartAddr - Erases Flash start address(StartAddr%256 == 0). + * Cnt - Erases count. + * Erase_Size - Erases size select.The returned value can be: + * Size_32KB, Size_1KB, Size_256B. + * + * @return none. + */ +static void ROM_ERASE(uint32_t StartAddr, uint32_t Cnt, uint32_t Erase_Size) +{ + FLASH->CTLR &= (CR_OPTER_Reset & CR_PAGE_ER_Reset); + + do{ + if(Erase_Size == Size_32KB) + { + FLASH->CTLR |= CR_BER32; + } + else if(Erase_Size == Size_1KB) + { + FLASH->CTLR |= CR_PER_Set; + } + else if(Erase_Size == Size_256B) + { + FLASH->CTLR |= CR_PAGE_ER; + } + + FLASH->ADDR = StartAddr; + FLASH->CTLR |= CR_STRT_Set; + while(FLASH->STATR & SR_BSY) + ; + + if(Erase_Size == Size_32KB) + { + FLASH->CTLR &= ~CR_BER32; + StartAddr += Size_32KB; + } + else if(Erase_Size == Size_1KB) + { + FLASH->CTLR &= ~CR_PER_Set; + StartAddr += Size_1KB; + } + else if(Erase_Size == Size_256B) + { + FLASH->CTLR &= ~CR_PAGE_ER; + StartAddr += Size_256B; + } + }while(--Cnt); +} + +/********************************************************************* + * @fn FLASH_ROM_ERASE + * + * @brief Erases a specified FLASH . + * + * @param StartAddr - Erases Flash start address(StartAddr%256 == 0). + * Length - Erases Flash start Length(Length%256 == 0). + * + * @return FLASH Status - The returned value can be: FLASH_ADR_RANGE_ERROR, + * FLASH_ALIGN_ERROR, FLASH_OP_RANGE_ERROR or FLASH_COMPLETE. + */ +FLASH_Status FLASH_ROM_ERASE(uint32_t StartAddr, uint32_t Length) +{ + uint32_t Addr0 = 0, Addr1 = 0, Length0 = 0, Length1 = 0; + + FLASH_Status status = FLASH_COMPLETE; + + if((StartAddr < ValidAddrStart) || (StartAddr >= ValidAddrEnd)) + { + return FLASH_ADR_RANGE_ERROR; + } + + if((StartAddr + Length) > ValidAddrEnd) + { + return FLASH_OP_RANGE_ERROR; + } + + if((StartAddr & (Size_256B-1)) || (Length & (Size_256B-1)) || (Length == 0)) + { + return FLASH_ALIGN_ERROR; + } + + /* Authorize the FPEC of Bank1 Access */ + FLASH->KEYR = FLASH_KEY1; + FLASH->KEYR = FLASH_KEY2; + + /* Fast mode unlock */ + FLASH->MODEKEYR = FLASH_KEY1; + FLASH->MODEKEYR = FLASH_KEY2; + + Addr0 = StartAddr; + + if(Length >= Size_32KB) + { + Length0 = Size_32KB - (Addr0 & (Size_32KB - 1)); + Addr1 = StartAddr + Length0; + Length1 = Length - Length0; + } + else if(Length >= Size_1KB) + { + Length0 = Size_1KB - (Addr0 & (Size_1KB - 1)); + Addr1 = StartAddr + Length0; + Length1 = Length - Length0; + } + else if(Length >= Size_256B) + { + Length0 = Length; + } + + /* Erase 32KB */ + if(Length0 >= Size_32KB)//front + { + Length = Length0; + if(Addr0 & (Size_32KB - 1)) + { + Length0 = Size_32KB - (Addr0 & (Size_32KB - 1)); + } + else + { + Length0 = 0; + } + + ROM_ERASE((Addr0 + Length0), ((Length - Length0) >> 15), Size_32KB); + } + + if(Length1 >= Size_32KB)//back + { + StartAddr = Addr1; + Length = Length1; + + if((Addr1 + Length1) & (Size_32KB - 1)) + { + Addr1 = ((StartAddr + Length1) & (~(Size_32KB - 1))); + Length1 = (StartAddr + Length1) & (Size_32KB - 1); + } + else + { + Length1 = 0; + } + + ROM_ERASE(StartAddr, ((Length - Length1) >> 15), Size_32KB); + } + + /* Erase 1KB */ + if(Length0 >= Size_1KB) //front + { + Length = Length0; + if(Addr0 & (Size_1KB - 1)) + { + Length0 = Size_1KB - (Addr0 & (Size_1KB - 1)); + } + else + { + Length0 = 0; + } + + ROM_ERASE((Addr0 + Length0), ((Length - Length0) >> 10), Size_1KB); + } + + if(Length1 >= Size_1KB) //back + { + StartAddr = Addr1; + Length = Length1; + + if((Addr1 + Length1) & (Size_1KB - 1)) + { + Addr1 = ((StartAddr + Length1) & (~(Size_1KB - 1))); + Length1 = (StartAddr + Length1) & (Size_1KB - 1); + } + else + { + Length1 = 0; + } + + ROM_ERASE(StartAddr, ((Length - Length1) >> 10), Size_1KB); + } + + /* Erase 256B */ + if(Length0)//front + { + ROM_ERASE(Addr0, (Length0 >> 8), Size_256B); + } + + if(Length1)//back + { + ROM_ERASE(Addr1, (Length1 >> 8), Size_256B); + } + + FLASH->CTLR |= CR_FLOCK_Set; + FLASH->CTLR |= CR_LOCK_Set; + + return status; +} + +/********************************************************************* + * @fn FLASH_ROM_WRITE + * + * @brief Writes a specified FLASH . + * + * @param StartAddr - Writes Flash start address(StartAddr%256 == 0). + * Length - Writes Flash start Length(Length%256 == 0). + * pbuf - Writes Flash value buffer. + * + * @return FLASH Status - The returned value can be: FLASH_ADR_RANGE_ERROR, + * FLASH_ALIGN_ERROR, FLASH_OP_RANGE_ERROR or FLASH_COMPLETE. + */ +FLASH_Status FLASH_ROM_WRITE(uint32_t StartAddr, uint32_t *pbuf, uint32_t Length) +{ + uint32_t i, adr; + uint8_t size; + + FLASH_Status status = FLASH_COMPLETE; + + if((StartAddr < ValidAddrStart) || (StartAddr >= ValidAddrEnd)) + { + return FLASH_ADR_RANGE_ERROR; + } + + if((StartAddr + Length) > ValidAddrEnd) + { + return FLASH_OP_RANGE_ERROR; + } + + if((StartAddr & (Size_256B-1)) || (Length & (Size_256B-1)) || (Length == 0)) + { + return FLASH_ALIGN_ERROR; + } + adr = StartAddr; + i = Length >> 8; + + /* Authorize the FPEC of Bank1 Access */ + FLASH->KEYR = FLASH_KEY1; + FLASH->KEYR = FLASH_KEY2; + + /* Fast program mode unlock */ + FLASH->MODEKEYR = FLASH_KEY1; + FLASH->MODEKEYR = FLASH_KEY2; + + FLASH->CTLR &= (CR_OPTER_Reset & CR_PAGE_ER_Reset); + + do{ + FLASH->CTLR |= CR_PAGE_PG; + FLASH->CTLR |= CR_BUF_RST; + while(FLASH->STATR & SR_BSY) + ; + size = 64; + while(size) + { + *(uint32_t *)StartAddr = *(uint32_t *)pbuf; + FLASH->CTLR |= CR_BUF_LOAD; + while(FLASH->STATR & SR_BSY) + ; + StartAddr += 4; + pbuf += 1; + size -= 1; + } + + FLASH->ADDR = adr; + FLASH->CTLR |= CR_STRT_Set; + while(FLASH->STATR & SR_BSY) + ; + FLASH->CTLR &= ~CR_PAGE_PG; + adr += 256; + }while(--i); + + FLASH->CTLR |= CR_FLOCK_Set; + FLASH->CTLR |= CR_LOCK_Set; + + return status; +} diff --git a/ZDBMS/BMS_CC/Peripheral/src/ch32l103_gpio.c b/ZDBMS/BMS_CC/Peripheral/src/ch32l103_gpio.c new file mode 100644 index 0000000..5745833 --- /dev/null +++ b/ZDBMS/BMS_CC/Peripheral/src/ch32l103_gpio.c @@ -0,0 +1,696 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32l103_gpio.c + * Author : WCH + * Version : V1.0.0 + * Date : 2024/11/06 + * Description : This file provides all the GPIO firmware functions. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#include "ch32l103_gpio.h" +#include "ch32l103_rcc.h" + +/* MASK */ +#define ECR_PORTPINCONFIG_MASK ((uint16_t)0xFF80) +#define LSB_MASK ((uint16_t)0xFFFF) +#define DBGAFR_POSITION_MASK ((uint32_t)0x000F0000) +#define DBGAFR_SWJCFG_MASK ((uint32_t)0xF8FFFFFF) +#define DBGAFR_LOCATION_MASK ((uint32_t)0x00200000) +#define DBGAFR_NUMBITS_MASK ((uint32_t)0x00100000) +#define REMAP_MASK ((uint32_t)0xC0000000) +#define REMAP_NUM_MASK ((uint32_t)0x38000000) + +uint32_t OPA_Trim = 0; +uint16_t ADC_Trim = 0; +uint32_t TS_Val = 0; +uint32_t CHIPID = 0; +uint16_t USBPD_CFG = 0; +/********************************************************************* + * @fn GPIO_DeInit + * + * @brief Deinitializes the GPIOx peripheral registers to their default + * reset values. + * + * @param GPIOx - where x can be (A..D) to select the GPIO peripheral. + * + * @return none + */ +void GPIO_DeInit(GPIO_TypeDef *GPIOx) +{ + if(GPIOx == GPIOA) + { + RCC_PB2PeriphResetCmd(RCC_PB2Periph_GPIOA, ENABLE); + RCC_PB2PeriphResetCmd(RCC_PB2Periph_GPIOA, DISABLE); + } + else if(GPIOx == GPIOB) + { + RCC_PB2PeriphResetCmd(RCC_PB2Periph_GPIOB, ENABLE); + RCC_PB2PeriphResetCmd(RCC_PB2Periph_GPIOB, DISABLE); + } + else if(GPIOx == GPIOC) + { + RCC_PB2PeriphResetCmd(RCC_PB2Periph_GPIOC, ENABLE); + RCC_PB2PeriphResetCmd(RCC_PB2Periph_GPIOC, DISABLE); + } + else if(GPIOx == GPIOD) + { + RCC_PB2PeriphResetCmd(RCC_PB2Periph_GPIOD, ENABLE); + RCC_PB2PeriphResetCmd(RCC_PB2Periph_GPIOD, DISABLE); + } +} + +/********************************************************************* + * @fn GPIO_AFIODeInit + * + * @brief Deinitializes the Alternate Functions (remap, event control + * and EXTI configuration) registers to their default reset values. + * + * @return none + */ +void GPIO_AFIODeInit(void) +{ + RCC_PB2PeriphResetCmd(RCC_PB2Periph_AFIO, ENABLE); + RCC_PB2PeriphResetCmd(RCC_PB2Periph_AFIO, DISABLE); +} + +/********************************************************************* + * @fn GPIO_Init + * + * @brief GPIOx - where x can be (A..D) to select the GPIO peripheral. + * + * @param GPIO_InitStruct - pointer to a GPIO_InitTypeDef structure that + * contains the configuration information for the specified GPIO peripheral. + * + * @return none + */ +void GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_InitStruct) +{ + uint32_t currentmode = 0x00, currentpin = 0x00, pinpos = 0x00, pos = 0x00; + uint32_t tmpreg = 0x00, pinmask = 0x00; + + currentmode = ((uint32_t)GPIO_InitStruct->GPIO_Mode) & ((uint32_t)0x0F); + + if((((uint32_t)GPIO_InitStruct->GPIO_Mode) & ((uint32_t)0x10)) != 0x00) + { + currentmode |= (uint32_t)GPIO_InitStruct->GPIO_Speed; + } + + if(((uint32_t)GPIO_InitStruct->GPIO_Pin & ((uint32_t)0x00FF)) != 0x00) + { + tmpreg = GPIOx->CFGLR; + + for(pinpos = 0x00; pinpos < 0x08; pinpos++) + { + pos = ((uint32_t)0x01) << pinpos; + currentpin = (GPIO_InitStruct->GPIO_Pin) & pos; + + if(currentpin == pos) + { + pos = pinpos << 2; + pinmask = ((uint32_t)0x0F) << pos; + tmpreg &= ~pinmask; + tmpreg |= (currentmode << pos); + + if(GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPD) + { + GPIOx->BCR = (((uint32_t)0x01) << pinpos); + } + else + { + if(GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPU) + { + GPIOx->BSHR = (((uint32_t)0x01) << pinpos); + } + } + } + } + GPIOx->CFGLR = tmpreg; + } + + if(GPIO_InitStruct->GPIO_Pin > 0x00FF) + { + tmpreg = GPIOx->CFGHR; + + for(pinpos = 0x00; pinpos < 0x08; pinpos++) + { + pos = (((uint32_t)0x01) << (pinpos + 0x08)); + currentpin = ((GPIO_InitStruct->GPIO_Pin) & pos); + + if(currentpin == pos) + { + pos = pinpos << 2; + pinmask = ((uint32_t)0x0F) << pos; + tmpreg &= ~pinmask; + tmpreg |= (currentmode << pos); + + if(GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPD) + { + GPIOx->BCR = (((uint32_t)0x01) << (pinpos + 0x08)); + } + + if(GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPU) + { + GPIOx->BSHR = (((uint32_t)0x01) << (pinpos + 0x08)); + } + } + } + GPIOx->CFGHR = tmpreg; + } +} + +/********************************************************************* + * @fn GPIO_StructInit + * + * @brief Fills each GPIO_InitStruct member with its default + * + * @param GPIO_InitStruct - pointer to a GPIO_InitTypeDef structure + * which will be initialized. + * + * @return none + */ +void GPIO_StructInit(GPIO_InitTypeDef *GPIO_InitStruct) +{ + GPIO_InitStruct->GPIO_Pin = GPIO_Pin_All; + GPIO_InitStruct->GPIO_Speed = GPIO_Speed_2MHz; + GPIO_InitStruct->GPIO_Mode = GPIO_Mode_IN_FLOATING; +} + +/********************************************************************* + * @fn GPIO_ReadInputDataBit + * + * @brief GPIOx - where x can be (A..D) to select the GPIO peripheral. + * + * @param GPIO_Pin - specifies the port bit to read. + * This parameter can be GPIO_Pin_x where x can be (0..15). + * + * @return The input port pin value. + */ +uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) +{ + uint8_t bitstatus = 0x00; + + if((GPIOx->INDR & GPIO_Pin) != (uint32_t)Bit_RESET) + { + bitstatus = (uint8_t)Bit_SET; + } + else + { + bitstatus = (uint8_t)Bit_RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn GPIO_ReadInputData + * + * @brief Reads the specified GPIO input data port. + * + * @param GPIOx - where x can be (A..D) to select the GPIO peripheral. + * + * @return The output port pin value. + */ +uint16_t GPIO_ReadInputData(GPIO_TypeDef *GPIOx) +{ + uint16_t val; + + val = ( uint16_t )GPIOx->INDR; + + return ( val ); +} + +/********************************************************************* + * @fn GPIO_ReadOutputDataBit + * + * @brief Reads the specified output data port bit. + * + * @param GPIOx - where x can be (A..D) to select the GPIO peripheral. + * GPIO_Pin - specifies the port bit to read. + * This parameter can be GPIO_Pin_x where x can be (0..15). + * + * @return none + */ +uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) +{ + uint8_t bitstatus = 0x00; + + if((GPIOx->OUTDR & GPIO_Pin) != (uint32_t)Bit_RESET) + { + bitstatus = (uint8_t)Bit_SET; + } + else + { + bitstatus = (uint8_t)Bit_RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn GPIO_ReadOutputData + * + * @brief Reads the specified GPIO output data port. + * + * @param GPIOx - where x can be (A..D) to select the GPIO peripheral. + * + * @return GPIO output port pin value. + */ +uint16_t GPIO_ReadOutputData(GPIO_TypeDef *GPIOx) +{ + uint16_t val; + + val = ( uint16_t )GPIOx->OUTDR; + + return ( val ); +} + +/********************************************************************* + * @fn GPIO_SetBits + * + * @brief Sets the selected data port bits. + * + * @param GPIOx - where x can be (A..D) to select the GPIO peripheral. + * GPIO_Pin - specifies the port bits to be written. + * This parameter can be any combination of GPIO_Pin_x where x can be (0..15). + * + * @return none + */ +void GPIO_SetBits(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) +{ + GPIOx->BSHR = GPIO_Pin; +} + +/********************************************************************* + * @fn GPIO_ResetBits + * + * @brief Clears the selected data port bits. + * + * @param GPIOx - where x can be (A..D) to select the GPIO peripheral. + * GPIO_Pin - specifies the port bits to be written. + * This parameter can be any combination of GPIO_Pin_x where x can be (0..15). + * + * @return none + */ +void GPIO_ResetBits(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) +{ + GPIOx->BCR = GPIO_Pin; +} + +/********************************************************************* + * @fn GPIO_WriteBit + * + * @brief Sets or clears the selected data port bit. + * + * @param GPIO_Pin - specifies the port bit to be written. + * This parameter can be one of GPIO_Pin_x where x can be (0..15). + * BitVal - specifies the value to be written to the selected bit. + * Bit_RESET - to clear the port pin. + * Bit_SET - to set the port pin. + * + * @return none + */ +void GPIO_WriteBit(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, BitAction BitVal) +{ + if(BitVal != Bit_RESET) + { + GPIOx->BSHR = GPIO_Pin; + } + else + { + GPIOx->BCR = GPIO_Pin; + } +} + +/********************************************************************* + * @fn GPIO_Write + * + * @brief Writes data to the specified GPIO data port. + * + * @param GPIOx - where x can be (A..D) to select the GPIO peripheral. + * PortVal - specifies the value to be written to the port output data register. + * + * @return none + */ +void GPIO_Write(GPIO_TypeDef *GPIOx, uint16_t PortVal) +{ + GPIOx->OUTDR = PortVal; +} + +/********************************************************************* + * @fn GPIO_PinLockConfig + * + * @brief Locks GPIO Pins configuration registers. + * + * @param GPIOx - where x can be (A..D) to select the GPIO peripheral. + * GPIO_Pin - specifies the port bit to be written. + * This parameter can be any combination of GPIO_Pin_x where x can be (0..15). + * + * @return none + */ +void GPIO_PinLockConfig(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) +{ + uint32_t tmp = 0x00010000; + + tmp |= GPIO_Pin; + GPIOx->LCKR = tmp; + GPIOx->LCKR = GPIO_Pin; + GPIOx->LCKR = tmp; + tmp = GPIOx->LCKR; + tmp = GPIOx->LCKR; +} + +/********************************************************************* + * @fn GPIO_EventOutputConfig + * + * @brief Selects the GPIO pin used as Event output. + * + * @param GPIO_PortSource - selects the GPIO port to be used as source + * for Event output. + * This parameter can be GPIO_PortSourceGPIOx where x can be (A..D). + * GPIO_PinSource - specifies the pin for the Event output. + * This parameter can be GPIO_PinSourcex where x can be (0..15). + * + * @return none + */ +void GPIO_EventOutputConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource) +{ + uint32_t tmpreg = 0x00; + + tmpreg = AFIO->ECR; + tmpreg &= ECR_PORTPINCONFIG_MASK; + tmpreg |= (uint32_t)GPIO_PortSource << 0x04; + tmpreg |= GPIO_PinSource; + AFIO->ECR = tmpreg; +} + +/********************************************************************* + * @fn GPIO_EventOutputCmd + * + * @brief Enables or disables the Event Output. + * + * @param NewState - ENABLE or DISABLE. + * + * @return none + */ +void GPIO_EventOutputCmd(FunctionalState NewState) +{ + if(NewState) + { + AFIO->ECR |= (1 << 7); + } + else + { + AFIO->ECR &= ~(1 << 7); + } +} + +/********************************************************************* + * @fn GPIO_PinRemapConfig + * + * @brief Changes the mapping of the specified pin. + * + * @param GPIO_Remap - selects the pin to remap. + * GPIO_PartialRemap1_SPI1 - SPI1 Partial1 Alternate Function mapping + * GPIO_PartialRemap2_SPI1 - SPI1 Partial2 Alternate Function mapping + * GPIO_FullRemap_SPI1 - SPI1 Full Alternate Function mapping + * GPIO_PartialRemap1_I2C1 - I2C1 Partial1 Alternate Function mapping + * GPIO_FullRemap_I2C1 - I2C1 Full Alternate Function mapping + * GPIO_PartialRemap1_USART1 - USART1 Partial1 Alternate Function mapping + * GPIO_PartialRemap2_USART1 - USART1 Partial2 Alternate Function mapping + * GPIO_PartialRemap3_USART1 - USART1 Partial3 Alternate Function mapping + * GPIO_PartialRemap4_USART1 - USART1 Partial4 Alternate Function mapping + * GPIO_FullRemap_USART1 - USART1 Full Alternate Function mapping + * GPIO_PartialRemap1_USART2 - USART2 Partial1 Alternate Function mapping + * GPIO_PartialRemap2_USART2 - USART2 Partial2 Alternate Function mapping + * GPIO_FullRemap_USART2 - USART2 Full Alternate Function mapping + * GPIO_PartialRemap1_TIM1 - TIM1 Partial1 Alternate Function mapping + * GPIO_PartialRemap2_TIM1 - TIM1 Partial2 Alternate Function mapping + * GPIO_PartialRemap3_TIM1 - TIM1 Partial3 Alternate Function mapping + * GPIO_PartialRemap4_TIM1 - TIM1 Partial4 Alternate Function mapping + * GPIO_PartialRemap5_TIM1 - TIM1 Partial5 Alternate Function mapping + * GPIO_FullRemap_TIM1 - TIM1 Full Alternate Function mapping + * GPIO_PartialRemap1_TIM2 - TIM2 Partial1 Alternate Function mapping + * GPIO_PartialRemap2_TIM2 - TIM2 Partial2 Alternate Function mapping + * GPIO_PartialRemap3_TIM2 - TIM2 Partial3 Alternate Function mapping + * GPIO_PartialRemap4_TIM2 - TIM2 Partial4 Alternate Function mapping + * GPIO_PartialRemap5_TIM2 - TIM2 Partial5 Alternate Function mapping + * GPIO_FullRemap_TIM2 - TIM2 Full Alternate Function mapping + * GPIO_PartialRemap_USART3 - USART3 Partial Alternate Function mapping + * GPIO_FullRemap_USART3 - USART3 Full Alternate Function mapping + * GPIO_Remap_TIM3 - TIM3 Alternate Function mapping + * GPIO_Remap_TIM4 - TIM4 Alternate Function mapping + * GPIO_Remap1_CAN1 - CAN1 Alternate Function mapping + * GPIO_Remap2_CAN1 - CAN1 Alternate Function mapping + * GPIO_Remap_PD01 - PD01 Alternate Function mapping + * GPIO_Remap_SWJ_Disable - Full SDI Disabled (SDI) + * GPIO_Remap_USART4 - USART4 Alternate Function mapping + * GPIO_Remap_LPTIM - LPTIM Alternate Function mapping + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void GPIO_PinRemapConfig(uint32_t GPIO_Remap, FunctionalState NewState) +{ + uint32_t tmp = 0x00, tmp1 = 0x00, tmpreg1 = 0x00, tmpreg2 = 0x00, tmpmask = 0x00; + + if((GPIO_Remap & 0xC0000000) == 0xC0000000) /* PCFR1 + PCFR2 */ + { + tmpreg1 = AFIO->PCFR1; + tmpreg2 = AFIO->PCFR2; + + /* Clear bit */ + tmp1 = ((GPIO_Remap & REMAP_NUM_MASK) >> 27); + + if(tmp1 == 0) + { + tmpreg1 &= ~(1<<0); + tmpreg2 &= ~(1<<24); + } + else if(tmp1 == 1) + { + tmpreg1 &= ~(1<<1); + tmpreg2 &= ~(1<<23); + } + else if(tmp1 == 2) + { + tmpreg1 &= ~(1<<2); + tmpreg2 &= ~(3<<19); + } + else if(tmp1 == 3) + { + tmpreg1 &= ~(1<<3); + tmpreg2 &= ~(1<<18); + } + else if(tmp1 == 4) + { + tmpreg1 &= ~(3<<6); + tmpreg2 &= ~(1<<22); + } + else if(tmp1 == 5) + { + tmpreg1 &= ~(3<<8); + tmpreg2 &= ~(1<<21); + } + + /* Set bit */ + if(NewState != DISABLE) + { + tmpreg1 |= (GPIO_Remap & 0x0000FFFF); + tmpreg2 |= (GPIO_Remap & 0x01FF0000); + } + + tmpreg1 |= ~DBGAFR_SWJCFG_MASK; + + AFIO->PCFR1 = tmpreg1; + AFIO->PCFR2 = tmpreg2; + } + else if((GPIO_Remap & 0xC0000000) == 0x40000000) /* PCFR2 */ + { + tmpreg2 = AFIO->PCFR2; + + /* Clear bit */ + tmp1 = ((GPIO_Remap & (~REMAP_MASK)) << 0x10); + tmpreg2 &= ~tmp1; + + /* Set bit */ + if(NewState != DISABLE) + { + tmpreg2 |= tmp1; + } + + AFIO->PCFR2 = tmpreg2; + } + else if((GPIO_Remap & 0xC0000000) == 0x00000000) /* PCFR1 */ + { + tmpreg1 = AFIO->PCFR1; + + /* Clear bit */ + tmpmask = (GPIO_Remap & DBGAFR_POSITION_MASK) >> 0x10; + tmp = GPIO_Remap & LSB_MASK; + + if((GPIO_Remap & (DBGAFR_LOCATION_MASK | DBGAFR_NUMBITS_MASK)) == (DBGAFR_LOCATION_MASK | DBGAFR_NUMBITS_MASK)) /* [26:24] 3bit SW_CFG */ + { + tmpreg1 &= DBGAFR_SWJCFG_MASK; + AFIO->PCFR1 &= DBGAFR_SWJCFG_MASK; + } + else if((GPIO_Remap & DBGAFR_NUMBITS_MASK) == DBGAFR_NUMBITS_MASK) /* [15:0] 2bit */ + { + tmp1 = ((uint32_t)0x03) << tmpmask; + tmpreg1 &= ~tmp1; + tmpreg1 |= ~DBGAFR_SWJCFG_MASK; + } + else /* [31:0] 1bit */ + { + tmpreg1 &= ~(tmp << ((GPIO_Remap >> 0x15) * 0x10)); + tmpreg1 |= ~DBGAFR_SWJCFG_MASK; + } + + /* Set bit */ + if(NewState != DISABLE) + { + tmpreg1 |= (tmp << (((GPIO_Remap & 0x7FFFFFFF )>> 0x15) * 0x10)); + } + + AFIO->PCFR1 = tmpreg1; + } +} + +/********************************************************************* + * @fn GPIO_EXTILineConfig + * + * @brief Selects the GPIO pin used as EXTI Line. + * + * @param GPIO_PortSource - selects the GPIO port to be used as source for EXTI lines. + * This parameter can be GPIO_PortSourceGPIOx where x can be (A..D). + * GPIO_PinSource - specifies the EXTI line to be configured. + * This parameter can be GPIO_PinSourcex where x can be (0..15). + * + * @return none + */ +void GPIO_EXTILineConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource) +{ + uint32_t tmp = 0x00; + + tmp = ((uint32_t)0x0F) << (0x04 * (GPIO_PinSource & (uint8_t)0x03)); + AFIO->EXTICR[GPIO_PinSource >> 0x02] &= ~tmp; + AFIO->EXTICR[GPIO_PinSource >> 0x02] |= (((uint32_t)GPIO_PortSource) << (0x04 * (GPIO_PinSource & (uint8_t)0x03))); +} + +/********************************************************************* + * @fn GPIO_IPD_Unused + * + * @brief Configure unused GPIO as input pull-down. + * + * @param none + * + * @return none + */ +void GPIO_IPD_Unused(void) +{ + GPIO_InitTypeDef GPIO_InitStructure = {0}; + uint32_t chip = 0; + + OPA_Trim = (((*(uint32_t *)OPA_TRIM_BASE & 0x0000001F) << 25) | (((*(uint32_t *)OPA_TRIM_BASE & 0x00008000)^0x00008000) << 9)) \ + | (((*(uint32_t *)OPA_TRIM_BASE & 0x001F0000) << 1) | (((*(uint32_t *)OPA_TRIM_BASE & 0x80000000)^0x80000000) >> 15)); + ADC_Trim = (*(uint16_t *)ADC_TRIM_BASE); + TS_Val = (*(uint32_t *)TS_BASE); + CHIPID = (*(uint32_t *)CHIPID_BASE); + USBPD_CFG = (*(uint16_t *)USBPD_CFG_BASE); + + RCC_PB2PeriphClockCmd(RCC_PB2Periph_GPIOA | RCC_PB2Periph_GPIOB | RCC_PB2Periph_GPIOC |RCC_PB2Periph_GPIOD |RCC_PB2Periph_AFIO,ENABLE); + chip = *( uint32_t * )CHIPID_BASE & (~0x000000F0); + switch(chip) + { + case 0x10320700: //CH32L103K8U6 + { + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_10\ + |GPIO_Pin_11|GPIO_Pin_12\ + |GPIO_Pin_13|GPIO_Pin_14; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; + GPIO_Init(GPIOB, &GPIO_InitStructure); + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_13; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; + GPIO_Init(GPIOC, &GPIO_InitStructure); + break; + } + case 0x103D0700: //CH32L103F8U6 + { + GPIO_PinRemapConfig(GPIO_Remap_PD01, ENABLE); + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_15; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; + GPIO_Init(GPIOA, &GPIO_InitStructure); + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_3\ + |GPIO_Pin_4|GPIO_Pin_5\ + |GPIO_Pin_8|GPIO_Pin_9\ + |GPIO_Pin_12; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; + GPIO_Init(GPIOB, &GPIO_InitStructure); + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPD; + GPIO_Init(GPIOB, &GPIO_InitStructure); + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_13|GPIO_Pin_14\ + |GPIO_Pin_15; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; + GPIO_Init(GPIOC, &GPIO_InitStructure); + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_1; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; + GPIO_Init(GPIOD, &GPIO_InitStructure); + break; + } + case 0x103B0700: //CH32L103G8R6 + { + GPIO_PinRemapConfig(GPIO_Remap_PD01, ENABLE); + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_15; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; + GPIO_Init(GPIOA, &GPIO_InitStructure); + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_4|GPIO_Pin_9; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; + GPIO_Init(GPIOB, &GPIO_InitStructure); + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPD; + GPIO_Init(GPIOB, &GPIO_InitStructure); + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_13|GPIO_Pin_14\ + |GPIO_Pin_15; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; + GPIO_Init(GPIOC, &GPIO_InitStructure); + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_1; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; + GPIO_Init(GPIOD, &GPIO_InitStructure); + break; + } + case 0x103A0700: //CH32L103F8P6 + { + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_8|GPIO_Pin_9\ + |GPIO_Pin_10|GPIO_Pin_15; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; + GPIO_Init(GPIOA, &GPIO_InitStructure); + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_3\ + |GPIO_Pin_4|GPIO_Pin_5\ + |GPIO_Pin_9|GPIO_Pin_10\ + |GPIO_Pin_11|GPIO_Pin_12\ + |GPIO_Pin_13|GPIO_Pin_14\ + |GPIO_Pin_15; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; + GPIO_Init(GPIOB, &GPIO_InitStructure); + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPD; + GPIO_Init(GPIOB, &GPIO_InitStructure); + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_13|GPIO_Pin_14\ + |GPIO_Pin_15; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; + GPIO_Init(GPIOC, &GPIO_InitStructure); + break; + } + case 0x10310700: //CH32L103C8T6 + { + break; + } + default: + { + break; + } + + } +} diff --git a/ZDBMS/BMS_CC/Peripheral/src/ch32l103_i2c.c b/ZDBMS/BMS_CC/Peripheral/src/ch32l103_i2c.c new file mode 100644 index 0000000..238badd --- /dev/null +++ b/ZDBMS/BMS_CC/Peripheral/src/ch32l103_i2c.c @@ -0,0 +1,1013 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32l103_i2c.c + * Author : WCH + * Version : V1.0.0 + * Date : 2024/01/19 + * Description : This file provides all the I2C firmware functions. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#include "ch32l103_i2c.h" +#include "ch32l103_rcc.h" + +/* I2C SPE mask */ +#define CTLR1_PE_Set ((uint16_t)0x0001) +#define CTLR1_PE_Reset ((uint16_t)0xFFFE) + +/* I2C START mask */ +#define CTLR1_START_Set ((uint16_t)0x0100) +#define CTLR1_START_Reset ((uint16_t)0xFEFF) + +/* I2C STOP mask */ +#define CTLR1_STOP_Set ((uint16_t)0x0200) +#define CTLR1_STOP_Reset ((uint16_t)0xFDFF) + +/* I2C ACK mask */ +#define CTLR1_ACK_Set ((uint16_t)0x0400) +#define CTLR1_ACK_Reset ((uint16_t)0xFBFF) + +/* I2C ENGC mask */ +#define CTLR1_ENGC_Set ((uint16_t)0x0040) +#define CTLR1_ENGC_Reset ((uint16_t)0xFFBF) + +/* I2C SWRST mask */ +#define CTLR1_SWRST_Set ((uint16_t)0x8000) +#define CTLR1_SWRST_Reset ((uint16_t)0x7FFF) + +/* I2C PEC mask */ +#define CTLR1_PEC_Set ((uint16_t)0x1000) +#define CTLR1_PEC_Reset ((uint16_t)0xEFFF) + +/* I2C ENPEC mask */ +#define CTLR1_ENPEC_Set ((uint16_t)0x0020) +#define CTLR1_ENPEC_Reset ((uint16_t)0xFFDF) + +/* I2C ENARP mask */ +#define CTLR1_ENARP_Set ((uint16_t)0x0010) +#define CTLR1_ENARP_Reset ((uint16_t)0xFFEF) + +/* I2C NOSTRETCH mask */ +#define CTLR1_NOSTRETCH_Set ((uint16_t)0x0080) +#define CTLR1_NOSTRETCH_Reset ((uint16_t)0xFF7F) + +/* I2C registers Masks */ +#define CTLR1_CLEAR_Mask ((uint16_t)0xFBF5) + +/* I2C DMAEN mask */ +#define CTLR2_DMAEN_Set ((uint16_t)0x0800) +#define CTLR2_DMAEN_Reset ((uint16_t)0xF7FF) + +/* I2C LAST mask */ +#define CTLR2_LAST_Set ((uint16_t)0x1000) +#define CTLR2_LAST_Reset ((uint16_t)0xEFFF) + +/* I2C FREQ mask */ +#define CTLR2_FREQ_Reset ((uint16_t)0xFFC0) + +/* I2C ADD0 mask */ +#define OADDR1_ADD0_Set ((uint16_t)0x0001) +#define OADDR1_ADD0_Reset ((uint16_t)0xFFFE) + +/* I2C ENDUAL mask */ +#define OADDR2_ENDUAL_Set ((uint16_t)0x0001) +#define OADDR2_ENDUAL_Reset ((uint16_t)0xFFFE) + +/* I2C ADD2 mask */ +#define OADDR2_ADD2_Reset ((uint16_t)0xFF01) + +/* I2C F/S mask */ +#define CKCFGR_FS_Set ((uint16_t)0x8000) + +/* I2C CCR mask */ +#define CKCFGR_CCR_Set ((uint16_t)0x0FFF) + +/* I2C FLAG mask */ +#define FLAG_Mask ((uint32_t)0x00FFFFFF) + +/* I2C Interrupt Enable mask */ +#define ITEN_Mask ((uint32_t)0x07000000) + +/********************************************************************* + * @fn I2C_DeInit + * + * @brief Deinitializes the I2Cx peripheral registers to their default + * reset values. + * + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * + * @return none + */ +void I2C_DeInit(I2C_TypeDef *I2Cx) +{ + if(I2Cx == I2C1) + { + RCC_PB1PeriphResetCmd(RCC_PB1Periph_I2C1, ENABLE); + RCC_PB1PeriphResetCmd(RCC_PB1Periph_I2C1, DISABLE); + } + else + { + RCC_PB1PeriphResetCmd(RCC_PB1Periph_I2C2, ENABLE); + RCC_PB1PeriphResetCmd(RCC_PB1Periph_I2C2, DISABLE); + } +} + +/********************************************************************* + * @fn I2C_Init + * + * @brief Initializes the I2Cx peripheral according to the specified + * parameters in the I2C_InitStruct. + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * I2C_InitStruct - pointer to a I2C_InitTypeDef structure that + * contains the configuration information for the specified I2C peripheral. + * + * @return none + */ +void I2C_Init(I2C_TypeDef *I2Cx, I2C_InitTypeDef *I2C_InitStruct) +{ + uint16_t tmpreg = 0, freqrange = 0; + uint16_t result = 0x04; + uint32_t pclk1 = 8000000; + + RCC_ClocksTypeDef rcc_clocks; + + tmpreg = I2Cx->CTLR2; + tmpreg &= CTLR2_FREQ_Reset; + RCC_GetClocksFreq(&rcc_clocks); + pclk1 = rcc_clocks.PCLK1_Frequency; + freqrange = (uint16_t)(pclk1 / 1000000); + if(freqrange > 60){ + freqrange =60; + } + tmpreg |= freqrange; + I2Cx->CTLR2 = tmpreg; + + I2Cx->CTLR1 &= CTLR1_PE_Reset; + tmpreg = 0; + + if(I2C_InitStruct->I2C_ClockSpeed <= 100000) + { + result = (uint16_t)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed << 1)); + + if(result < 0x04) + { + result = 0x04; + } + + tmpreg |= result; + I2Cx->RTR = freqrange + 1; + } + else + { + if(I2C_InitStruct->I2C_DutyCycle == I2C_DutyCycle_2) + { + result = (uint16_t)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed * 3)); + } + else + { + result = (uint16_t)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed * 25)); + result |= I2C_DutyCycle_16_9; + } + + if((result & CKCFGR_CCR_Set) == 0) + { + result |= (uint16_t)0x0001; + } + + tmpreg |= (uint16_t)(result | CKCFGR_FS_Set); + I2Cx->RTR = (uint16_t)(((freqrange * (uint16_t)300) / (uint16_t)1000) + (uint16_t)1); + } + + I2Cx->CKCFGR = tmpreg; + I2Cx->CTLR1 |= CTLR1_PE_Set; + + tmpreg = I2Cx->CTLR1; + tmpreg &= CTLR1_CLEAR_Mask; + tmpreg |= (uint16_t)((uint32_t)I2C_InitStruct->I2C_Mode | I2C_InitStruct->I2C_Ack); + I2Cx->CTLR1 = tmpreg; + + I2Cx->OADDR1 = (I2C_InitStruct->I2C_AcknowledgedAddress | I2C_InitStruct->I2C_OwnAddress1); +} + +/********************************************************************* + * @fn I2C_StructInit + * + * @brief Fills each I2C_InitStruct member with its default value. + * + * @param I2C_InitStruct - pointer to an I2C_InitTypeDef structure which + * will be initialized. + * + * @return none + */ +void I2C_StructInit(I2C_InitTypeDef *I2C_InitStruct) +{ + I2C_InitStruct->I2C_ClockSpeed = 5000; + I2C_InitStruct->I2C_Mode = I2C_Mode_I2C; + I2C_InitStruct->I2C_DutyCycle = I2C_DutyCycle_2; + I2C_InitStruct->I2C_OwnAddress1 = 0; + I2C_InitStruct->I2C_Ack = I2C_Ack_Disable; + I2C_InitStruct->I2C_AcknowledgedAddress = I2C_AcknowledgedAddress_7bit; +} + +/********************************************************************* + * @fn I2C_Cmd + * + * @brief Enables or disables the specified I2C peripheral. + * + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void I2C_Cmd(I2C_TypeDef *I2Cx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + I2Cx->CTLR1 |= CTLR1_PE_Set; + } + else + { + I2Cx->CTLR1 &= CTLR1_PE_Reset; + } +} + +/********************************************************************* + * @fn I2C_DMACmd + * + * @brief Enables or disables the specified I2C DMA requests. + * + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void I2C_DMACmd(I2C_TypeDef *I2Cx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + I2Cx->CTLR2 |= CTLR2_DMAEN_Set; + } + else + { + I2Cx->CTLR2 &= CTLR2_DMAEN_Reset; + } +} + +/********************************************************************* + * @fn I2C_DMALastTransferCmd + * + * @brief Specifies if the next DMA transfer will be the last one. + * + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void I2C_DMALastTransferCmd(I2C_TypeDef *I2Cx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + I2Cx->CTLR2 |= CTLR2_LAST_Set; + } + else + { + I2Cx->CTLR2 &= CTLR2_LAST_Reset; + } +} + +/********************************************************************* + * @fn I2C_GenerateSTART + * + * @brief Generates I2Cx communication START condition. + * + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void I2C_GenerateSTART(I2C_TypeDef *I2Cx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + I2Cx->CTLR1 |= CTLR1_START_Set; + } + else + { + I2Cx->CTLR1 &= CTLR1_START_Reset; + } +} + +/********************************************************************* + * @fn I2C_GenerateSTOP + * + * @brief Generates I2Cx communication STOP condition. + * + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void I2C_GenerateSTOP(I2C_TypeDef *I2Cx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + I2Cx->CTLR1 |= CTLR1_STOP_Set; + } + else + { + I2Cx->CTLR1 &= CTLR1_STOP_Reset; + } +} + +/********************************************************************* + * @fn I2C_AcknowledgeConfig + * + * @brief Enables or disables the specified I2C acknowledge feature. + * + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void I2C_AcknowledgeConfig(I2C_TypeDef *I2Cx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + I2Cx->CTLR1 |= CTLR1_ACK_Set; + } + else + { + I2Cx->CTLR1 &= CTLR1_ACK_Reset; + } +} + +/********************************************************************* + * @fn I2C_OwnAddress2Config + * + * @brief Configures the specified I2C own address2. + * + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * Address - specifies the 7bit I2C own address2. + * + * @return none + */ +void I2C_OwnAddress2Config(I2C_TypeDef *I2Cx, uint8_t Address) +{ + uint16_t tmpreg = 0; + + tmpreg = I2Cx->OADDR2; + tmpreg &= OADDR2_ADD2_Reset; + tmpreg |= (uint16_t)((uint16_t)Address & (uint16_t)0x00FE); + I2Cx->OADDR2 = tmpreg; +} + +/********************************************************************* + * @fn I2C_DualAddressCmd + * + * @brief Enables or disables the specified I2C dual addressing mode. + * + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void I2C_DualAddressCmd(I2C_TypeDef *I2Cx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + I2Cx->OADDR2 |= OADDR2_ENDUAL_Set; + } + else + { + I2Cx->OADDR2 &= OADDR2_ENDUAL_Reset; + } +} + +/********************************************************************* + * @fn I2C_GeneralCallCmd + * + * @brief Enables or disables the specified I2C general call feature. + * + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void I2C_GeneralCallCmd(I2C_TypeDef *I2Cx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + I2Cx->CTLR1 |= CTLR1_ENGC_Set; + } + else + { + I2Cx->CTLR1 &= CTLR1_ENGC_Reset; + } +} + +/********************************************************************* + * @fn I2C_ITConfig + * + * @brief Enables or disables the specified I2C interrupts. + * + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * I2C_IT - specifies the I2C interrupts sources to be enabled or disabled. + * I2C_IT_BUF - Buffer interrupt mask. + * I2C_IT_EVT - Event interrupt mask. + * I2C_IT_ERR - Error interrupt mask. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void I2C_ITConfig(I2C_TypeDef *I2Cx, uint16_t I2C_IT, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + I2Cx->CTLR2 |= I2C_IT; + } + else + { + I2Cx->CTLR2 &= (uint16_t)~I2C_IT; + } +} + +/********************************************************************* + * @fn I2C_SendData + * + * @brief Sends a data byte through the I2Cx peripheral. + * + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * Data - Byte to be transmitted. + * + * @return none + */ +void I2C_SendData(I2C_TypeDef *I2Cx, uint8_t Data) +{ + I2Cx->DATAR = Data; +} + +/********************************************************************* + * @fn I2C_ReceiveData + * + * @brief Returns the most recent received data by the I2Cx peripheral. + * + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * + * @return The value of the received data. + */ +uint8_t I2C_ReceiveData(I2C_TypeDef *I2Cx) +{ + return (uint8_t)I2Cx->DATAR; +} + +/********************************************************************* + * @fn I2C_Send7bitAddress + * + * @brief Transmits the address byte to select the slave device. + * + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * Address - specifies the slave address which will be transmitted. + * I2C_Direction - specifies whether the I2C device will be a + * Transmitter or a Receiver. + * I2C_Direction_Transmitter - Transmitter mode. + * I2C_Direction_Receiver - Receiver mode. + * + * @return none + */ +void I2C_Send7bitAddress(I2C_TypeDef *I2Cx, uint8_t Address, uint8_t I2C_Direction) +{ + if(I2C_Direction != I2C_Direction_Transmitter) + { + Address |= OADDR1_ADD0_Set; + } + else + { + Address &= OADDR1_ADD0_Reset; + } + + I2Cx->DATAR = Address; +} + +/********************************************************************* + * @fn I2C_ReadRegister + * + * @brief Reads the specified I2C register and returns its value. + * + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * I2C_Register - specifies the register to read. + * I2C_Register_CTLR1. + * I2C_Register_CTLR2. + * I2C_Register_OADDR1. + * I2C_Register_OADDR2. + * I2C_Register_DATAR. + * I2C_Register_STAR1. + * I2C_Register_STAR2. + * I2C_Register_CKCFGR. + * I2C_Register_RTR. + * + * @return none + */ +uint16_t I2C_ReadRegister(I2C_TypeDef *I2Cx, uint8_t I2C_Register) +{ + __IO uint32_t tmp = 0; + + tmp = (uint32_t)I2Cx; + tmp += I2C_Register; + + return (*(__IO uint16_t *)tmp); +} + +/********************************************************************* + * @fn I2C_SoftwareResetCmd + * + * @brief Enables or disables the specified I2C software reset. + * + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void I2C_SoftwareResetCmd(I2C_TypeDef *I2Cx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + I2Cx->CTLR1 |= CTLR1_SWRST_Set; + } + else + { + I2Cx->CTLR1 &= CTLR1_SWRST_Reset; + } +} + +/********************************************************************* + * @fn I2C_NACKPositionConfig + * + * @brief Selects the specified I2C NACK position in master receiver mode. + * + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * I2C_NACKPosition - specifies the NACK position. + * I2C_NACKPosition_Next - indicates that the next byte will be + * the last received byte. + * I2C_NACKPosition_Current - indicates that current byte is the + * last received byte. + * Note- + * This function configures the same bit (POS) as I2C_PECPositionConfig() + * but is intended to be used in I2C mode while I2C_PECPositionConfig() + * is intended to used in SMBUS mode. + * + * @return none + */ +void I2C_NACKPositionConfig(I2C_TypeDef *I2Cx, uint16_t I2C_NACKPosition) +{ + if(I2C_NACKPosition == I2C_NACKPosition_Next) + { + I2Cx->CTLR1 |= I2C_NACKPosition_Next; + } + else + { + I2Cx->CTLR1 &= I2C_NACKPosition_Current; + } +} + +/********************************************************************* + * @fn I2C_SMBusAlertConfig + * + * @brief Drives the SMBusAlert pin high or low for the specified I2C. + * + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * I2C_SMBusAlert - specifies SMBAlert pin level. + * I2C_SMBusAlert_Low - SMBAlert pin driven low. + * I2C_SMBusAlert_High - SMBAlert pin driven high. + * + * @return none + */ +void I2C_SMBusAlertConfig(I2C_TypeDef *I2Cx, uint16_t I2C_SMBusAlert) +{ + if(I2C_SMBusAlert == I2C_SMBusAlert_Low) + { + I2Cx->CTLR1 |= I2C_SMBusAlert_Low; + } + else + { + I2Cx->CTLR1 &= I2C_SMBusAlert_High; + } +} + +/********************************************************************* + * @fn I2C_TransmitPEC + * + * @brief Enables or disables the specified I2C PEC transfer. + * + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void I2C_TransmitPEC(I2C_TypeDef *I2Cx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + I2Cx->CTLR1 |= CTLR1_PEC_Set; + } + else + { + I2Cx->CTLR1 &= CTLR1_PEC_Reset; + } +} + +/********************************************************************* + * @fn I2C_PECPositionConfig + * + * @brief Selects the specified I2C PEC position. + * + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * I2C_PECPosition - specifies the PEC position. + * I2C_PECPosition_Next - indicates that the next byte is PEC. + * I2C_PECPosition_Current - indicates that current byte is PEC. + * + * @return none + */ +void I2C_PECPositionConfig(I2C_TypeDef *I2Cx, uint16_t I2C_PECPosition) +{ + if(I2C_PECPosition == I2C_PECPosition_Next) + { + I2Cx->CTLR1 |= I2C_PECPosition_Next; + } + else + { + I2Cx->CTLR1 &= I2C_PECPosition_Current; + } +} + +/********************************************************************* + * @fn I2C_CalculatePEC + * + * @brief Enables or disables the PEC value calculation of the transferred bytes. + * + * @param I2Cx- where x can be 1 or 2 to select the I2C peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void I2C_CalculatePEC(I2C_TypeDef *I2Cx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + I2Cx->CTLR1 |= CTLR1_ENPEC_Set; + } + else + { + I2Cx->CTLR1 &= CTLR1_ENPEC_Reset; + } +} + +/********************************************************************* + * @fn I2C_GetPEC + * + * @brief Returns the PEC value for the specified I2C. + * + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * + * @return The PEC value. + */ +uint8_t I2C_GetPEC(I2C_TypeDef *I2Cx) +{ + return ((I2Cx->STAR2) >> 8); +} + +/********************************************************************* + * @fn I2C_ARPCmd + * + * @brief Enables or disables the specified I2C ARP. + * + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * NewState - ENABLE or DISABLE. + * + * @return The PEC value. + */ +void I2C_ARPCmd(I2C_TypeDef *I2Cx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + I2Cx->CTLR1 |= CTLR1_ENARP_Set; + } + else + { + I2Cx->CTLR1 &= CTLR1_ENARP_Reset; + } +} + +/********************************************************************* + * @fn I2C_StretchClockCmd + * + * @brief Enables or disables the specified I2C Clock stretching. + * + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void I2C_StretchClockCmd(I2C_TypeDef *I2Cx, FunctionalState NewState) +{ + if(NewState == DISABLE) + { + I2Cx->CTLR1 |= CTLR1_NOSTRETCH_Set; + } + else + { + I2Cx->CTLR1 &= CTLR1_NOSTRETCH_Reset; + } +} + +/********************************************************************* + * @fn I2C_FastModeDutyCycleConfig + * + * @brief Selects the specified I2C fast mode duty cycle. + * + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * I2C_DutyCycle - specifies the fast mode duty cycle. + * I2C_DutyCycle_2 - I2C fast mode Tlow/Thigh = 2. + * I2C_DutyCycle_16_9 - I2C fast mode Tlow/Thigh = 16/9. + * + * @return none + */ +void I2C_FastModeDutyCycleConfig(I2C_TypeDef *I2Cx, uint16_t I2C_DutyCycle) +{ + if(I2C_DutyCycle != I2C_DutyCycle_16_9) + { + I2Cx->CKCFGR &= I2C_DutyCycle_2; + } + else + { + I2Cx->CKCFGR |= I2C_DutyCycle_16_9; + } +} + +/********************************************************************* + * @fn I2C_CheckEvent + * + * @brief Checks whether the last I2Cx Event is equal to the one passed + * as parameter. + * + * @param I2Cx- where x can be 1 or 2 to select the I2C peripheral. + * I2C_EVENT: specifies the event to be checked. + * I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED - EVT1. + * I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED - EVT1. + * I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED - EVT1. + * I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED - EVT1. + * I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED - EVT1. + * I2C_EVENT_SLAVE_BYTE_RECEIVED - EVT2. + * (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_DUALF) - EVT2. + * (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_GENCALL) - EVT2. + * I2C_EVENT_SLAVE_BYTE_TRANSMITTED - EVT3. + * (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_DUALF) - EVT3. + * (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_GENCALL) - EVT3. + * I2C_EVENT_SLAVE_ACK_FAILURE - EVT3_2. + * I2C_EVENT_SLAVE_STOP_DETECTED - EVT4. + * I2C_EVENT_MASTER_MODE_SELECT - EVT5. + * I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED - EVT6. + * I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED - EVT6. + * I2C_EVENT_MASTER_BYTE_RECEIVED - EVT7. + * I2C_EVENT_MASTER_BYTE_TRANSMITTING - EVT8. + * I2C_EVENT_MASTER_BYTE_TRANSMITTED - EVT8_2. + * I2C_EVENT_MASTER_MODE_ADDRESS10 - EVT9. + * + * @return ErrorStatus - READY or NoREADY. + */ +ErrorStatus I2C_CheckEvent(I2C_TypeDef *I2Cx, uint32_t I2C_EVENT) +{ + uint32_t lastevent = 0; + uint32_t flag1 = 0, flag2 = 0; + ErrorStatus status = NoREADY; + + flag1 = I2Cx->STAR1; + flag2 = I2Cx->STAR2; + flag2 = flag2 << 16; + + lastevent = (flag1 | flag2) & FLAG_Mask; + + if((lastevent & I2C_EVENT) == I2C_EVENT) + { + status = READY; + } + else + { + status = NoREADY; + } + + return status; +} + +/********************************************************************* + * @fn I2C_GetLastEvent + * + * @brief Returns the last I2Cx Event. + * + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * + * @return none + */ +uint32_t I2C_GetLastEvent(I2C_TypeDef *I2Cx) +{ + uint32_t lastevent = 0; + uint32_t flag1 = 0, flag2 = 0; + + flag1 = I2Cx->STAR1; + flag2 = I2Cx->STAR2; + flag2 = flag2 << 16; + lastevent = (flag1 | flag2) & FLAG_Mask; + + return lastevent; +} + +/********************************************************************* + * @fn I2C_GetFlagStatus + * + * @brief Checks whether the last I2Cx Event is equal to the one passed + * as parameter. + * + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * I2C_FLAG - specifies the flag to check. + * I2C_FLAG_DUALF - Dual flag (Slave mode). + * I2C_FLAG_SMBHOST - SMBus host header (Slave mode). + * I2C_FLAG_SMBDEFAULT - SMBus default header (Slave mode). + * I2C_FLAG_GENCALL - General call header flag (Slave mode). + * I2C_FLAG_TRA - Transmitter/Receiver flag. + * I2C_FLAG_BUSY - Bus busy flag. + * I2C_FLAG_MSL - Master/Slave flag. + * I2C_FLAG_SMBALERT - SMBus Alert flag. + * I2C_FLAG_TIMEOUT - Timeout or Tlow error flag. + * I2C_FLAG_PECERR - PEC error in reception flag. + * I2C_FLAG_OVR - Overrun/Underrun flag (Slave mode). + * I2C_FLAG_AF - Acknowledge failure flag. + * I2C_FLAG_ARLO - Arbitration lost flag (Master mode). + * I2C_FLAG_BERR - Bus error flag. + * I2C_FLAG_TXE - Data register empty flag (Transmitter). + * I2C_FLAG_RXNE- Data register not empty (Receiver) flag. + * I2C_FLAG_STOPF - Stop detection flag (Slave mode). + * I2C_FLAG_ADD10 - 10-bit header sent flag (Master mode). + * I2C_FLAG_BTF - Byte transfer finished flag. + * I2C_FLAG_ADDR - Address sent flag (Master mode) "ADSL" + * Address matched flag (Slave mode)"ENDA". + * I2C_FLAG_SB - Start bit flag (Master mode). + * + * @return FlagStatus - SET or RESET. + */ +FlagStatus I2C_GetFlagStatus(I2C_TypeDef *I2Cx, uint32_t I2C_FLAG) +{ + FlagStatus bitstatus = RESET; + __IO uint32_t i2creg = 0, i2cxbase = 0; + + i2cxbase = (uint32_t)I2Cx; + i2creg = I2C_FLAG >> 28; + I2C_FLAG &= FLAG_Mask; + + if(i2creg != 0) + { + i2cxbase += 0x14; + } + else + { + I2C_FLAG = (uint32_t)(I2C_FLAG >> 16); + i2cxbase += 0x18; + } + + if(((*(__IO uint32_t *)i2cxbase) & I2C_FLAG) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn I2C_ClearFlag + * + * @brief Clears the I2Cx's pending flags. + * + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * I2C_FLAG - specifies the flag to clear. + * I2C_FLAG_SMBALERT - SMBus Alert flag. + * I2C_FLAG_TIMEOUT - Timeout or Tlow error flag. + * I2C_FLAG_PECERR - PEC error in reception flag. + * I2C_FLAG_OVR - Overrun/Underrun flag (Slave mode). + * I2C_FLAG_AF - Acknowledge failure flag. + * I2C_FLAG_ARLO - Arbitration lost flag (Master mode). + * I2C_FLAG_BERR - Bus error flag. + * Note- + * - STOPF (STOP detection) is cleared by software sequence: a read operation + * to I2C_STAR1 register (I2C_GetFlagStatus()) followed by a write operation + * to I2C_CTLR1 register (I2C_Cmd() to re-enable the I2C peripheral). + * - ADD10 (10-bit header sent) is cleared by software sequence: a read + * operation to I2C_SATR1 (I2C_GetFlagStatus()) followed by writing the + * second byte of the address in DATAR register. + * - BTF (Byte Transfer Finished) is cleared by software sequence: a read + * operation to I2C_SATR1 register (I2C_GetFlagStatus()) followed by a + * read/write to I2C_DATAR register (I2C_SendData()). + * - ADDR (Address sent) is cleared by software sequence: a read operation to + * I2C_SATR1 register (I2C_GetFlagStatus()) followed by a read operation to + * I2C_SATR2 register ((void)(I2Cx->STAR2)). + * - SB (Start Bit) is cleared software sequence: a read operation to I2C_STAR1 + * register (I2C_GetFlagStatus()) followed by a write operation to I2C_DATAR + * register (I2C_SendData()). + * + * @return none + */ +void I2C_ClearFlag(I2C_TypeDef *I2Cx, uint32_t I2C_FLAG) +{ + uint32_t flagpos = 0; + + flagpos = I2C_FLAG & FLAG_Mask; + I2Cx->STAR1 = (uint16_t)~flagpos; +} + +/********************************************************************* + * @fn I2C_GetITStatus + * + * @brief Checks whether the specified I2C interrupt has occurred or not. + * + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * II2C_IT - specifies the interrupt source to check. + * I2C_IT_SMBALERT - SMBus Alert flag. + * I2C_IT_TIMEOUT - Timeout or Tlow error flag. + * I2C_IT_PECERR - PEC error in reception flag. + * I2C_IT_OVR - Overrun/Underrun flag (Slave mode). + * I2C_IT_AF - Acknowledge failure flag. + * I2C_IT_ARLO - Arbitration lost flag (Master mode). + * I2C_IT_BERR - Bus error flag. + * I2C_IT_TXE - Data register empty flag (Transmitter). + * I2C_IT_RXNE - Data register not empty (Receiver) flag. + * I2C_IT_STOPF - Stop detection flag (Slave mode). + * I2C_IT_ADD10 - 10-bit header sent flag (Master mode). + * I2C_IT_BTF - Byte transfer finished flag. + * I2C_IT_ADDR - Address sent flag (Master mode) "ADSL" Address matched + * flag (Slave mode)"ENDAD". + * I2C_IT_SB - Start bit flag (Master mode). + * + * @return none + */ +ITStatus I2C_GetITStatus(I2C_TypeDef *I2Cx, uint32_t I2C_IT) +{ + ITStatus bitstatus = RESET; + uint32_t enablestatus = 0; + + enablestatus = (uint32_t)(((I2C_IT & ITEN_Mask) >> 16) & (I2Cx->CTLR2)); + I2C_IT &= FLAG_Mask; + + if(((I2Cx->STAR1 & I2C_IT) != (uint32_t)RESET) && enablestatus) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn I2C_ClearITPendingBit + * + * @brief Clears the I2Cx interrupt pending bits. + * + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * I2C_IT - specifies the interrupt pending bit to clear. + * I2C_IT_SMBALERT - SMBus Alert interrupt. + * I2C_IT_TIMEOUT - Timeout or Tlow error interrupt. + * I2C_IT_PECERR - PEC error in reception interrupt. + * I2C_IT_OVR - Overrun/Underrun interrupt (Slave mode). + * I2C_IT_AF - Acknowledge failure interrupt. + * I2C_IT_ARLO - Arbitration lost interrupt (Master mode). + * I2C_IT_BERR - Bus error interrupt. + * Note- + * - STOPF (STOP detection) is cleared by software sequence: a read operation + * to I2C_STAR1 register (I2C_GetITStatus()) followed by a write operation to + * I2C_CTLR1 register (I2C_Cmd() to re-enable the I2C peripheral). + * - ADD10 (10-bit header sent) is cleared by software sequence: a read + * operation to I2C_STAR1 (I2C_GetITStatus()) followed by writing the second + * byte of the address in I2C_DATAR register. + * - BTF (Byte Transfer Finished) is cleared by software sequence: a read + * operation to I2C_STAR1 register (I2C_GetITStatus()) followed by a + * read/write to I2C_DATAR register (I2C_SendData()). + * - ADDR (Address sent) is cleared by software sequence: a read operation to + * I2C_STAR1 register (I2C_GetITStatus()) followed by a read operation to + * I2C_STAR2 register ((void)(I2Cx->STAR2)). + * - SB (Start Bit) is cleared by software sequence: a read operation to + * I2C_STAR1 register (I2C_GetITStatus()) followed by a write operation to + * I2C_DATAR register (I2C_SendData()). + * + * @return none + */ +void I2C_ClearITPendingBit(I2C_TypeDef *I2Cx, uint32_t I2C_IT) +{ + uint32_t flagpos = 0; + + flagpos = I2C_IT & FLAG_Mask; + I2Cx->STAR1 = (uint16_t)~flagpos; +} diff --git a/ZDBMS/BMS_CC/Peripheral/src/ch32l103_iwdg.c b/ZDBMS/BMS_CC/Peripheral/src/ch32l103_iwdg.c new file mode 100644 index 0000000..4779397 --- /dev/null +++ b/ZDBMS/BMS_CC/Peripheral/src/ch32l103_iwdg.c @@ -0,0 +1,123 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32l103_iwdg.c + * Author : WCH + * Version : V1.0.0 + * Date : 2024/03/26 + * Description : This file provides all the IWDG firmware functions. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#include "ch32l103_iwdg.h" + +/* CTLR register bit mask */ +#define CTLR_KEY_Reload ((uint16_t)0xAAAA) +#define CTLR_KEY_Enable ((uint16_t)0xCCCC) + +/********************************************************************* + * @fn IWDG_WriteAccessCmd + * + * @brief Enables or disables write access to IWDG_PSCR and IWDG_RLDR registers. + * + * @param WDG_WriteAccess - new state of write access to IWDG_PSCR and + * IWDG_RLDR registers. + * IWDG_WriteAccess_Enable - Enable write access to IWDG_PSCR and + * IWDG_RLDR registers. + * IWDG_WriteAccess_Disable - Disable write access to IWDG_PSCR + * and IWDG_RLDR registers. + * + * @return none + */ +void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess) +{ + IWDG->CTLR = IWDG_WriteAccess; +} + +/********************************************************************* + * @fn IWDG_SetPrescaler + * + * @brief Sets IWDG Prescaler value. + * + * @param IWDG_Prescaler - specifies the IWDG Prescaler value. + * IWDG_Prescaler_4 - IWDG prescaler set to 4. + * IWDG_Prescaler_8 - IWDG prescaler set to 8. + * IWDG_Prescaler_16 - IWDG prescaler set to 16. + * IWDG_Prescaler_32 - IWDG prescaler set to 32. + * IWDG_Prescaler_64 - IWDG prescaler set to 64. + * IWDG_Prescaler_128 - IWDG prescaler set to 128. + * IWDG_Prescaler_256 - IWDG prescaler set to 256. + * + * @return none + */ +void IWDG_SetPrescaler(uint8_t IWDG_Prescaler) +{ + IWDG->PSCR = IWDG_Prescaler; +} + +/********************************************************************* + * @fn IWDG_SetReload + * + * @brief Sets IWDG Reload value. + * + * @param Reload - specifies the IWDG Reload value. + * This parameter must be a number between 0 and 0x0FFF. + * + * @return none + */ +void IWDG_SetReload(uint16_t Reload) +{ + IWDG->RLDR = Reload; +} + +/********************************************************************* + * @fn IWDG_ReloadCounter + * + * @brief Reloads IWDG counter with value defined in the reload register. + * + * @return none + */ +void IWDG_ReloadCounter(void) +{ + IWDG->CTLR = CTLR_KEY_Reload; +} + +/********************************************************************* + * @fn IWDG_Enable + * + * @brief Enables IWDG (write access to IWDG_PSCR and IWDG_RLDR registers disabled). + * + * @return none + */ +void IWDG_Enable(void) +{ + IWDG->CTLR = CTLR_KEY_Enable; + while((RCC->RSTSCKR & 0x2) == RESET); +} + +/********************************************************************* + * @fn IWDG_GetFlagStatus + * + * @brief Checks whether the specified IWDG flag is set or not. + * + * @param IWDG_FLAG - specifies the flag to check. + * IWDG_FLAG_PVU - Prescaler Value Update on going. + * IWDG_FLAG_RVU - Reload Value Update on going. + * + * @return none + */ +FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG) +{ + FlagStatus bitstatus = RESET; + + if((IWDG->STATR & IWDG_FLAG) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} diff --git a/ZDBMS/BMS_CC/Peripheral/src/ch32l103_lptim.c b/ZDBMS/BMS_CC/Peripheral/src/ch32l103_lptim.c new file mode 100644 index 0000000..27597a7 --- /dev/null +++ b/ZDBMS/BMS_CC/Peripheral/src/ch32l103_lptim.c @@ -0,0 +1,363 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32l103_lptim.c + * Author : WCH + * Version : V1.0.0 + * Date : 2024/08/29 + * Description : This file provides all the TIM firmware functions. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#include "ch32l103_lptim.h" +#include "ch32l103_rcc.h" + + +/********************************************************************* + * @fn LPTIM_DeInit + * + * @brief Deinitializes the LPTIM peripheral registers to their default + * reset values. + * + * @param none + * + * @return none + */ +void LPTIM_DeInit(void) +{ + RCC_PB1PeriphResetCmd(RCC_PB1Periph_LPTIM, ENABLE); + RCC_PB1PeriphResetCmd(RCC_PB1Periph_LPTIM, DISABLE); +} + +/********************************************************************* + * @fn LPTIM_TimeBaseInit + * + * @brief Initializes the LPTIM Time Base Unit peripheral according to + * the specified parameters in the LPTIM_TimeBaseInitStruct. + * + * @param LPTIM_TimeBaseInitStruct - pointer to a LPTIM_TimeBaseInitTypeDef + * structure. + * + * @return none + */ +void LPTIM_TimeBaseInit(LPTIM_TimeBaseInitTypeDef *LPTIM_TimeBaseInitStruct) +{ + uint32_t temp1 = 0, temp2 = 0; + + temp2 = (LPTIM->CR & 0x00000001); + + if(LPTIM_TimeBaseInitStruct->LPTIM_Encoder == ENABLE) + { + temp1 |= LPTIM_TimeBaseInitStruct->LPTIM_EncoderMode; + } + else + { + temp1 |= LPTIM_TimeBaseInitStruct->LPTIM_ClockPolarity; + } + + temp1 |= LPTIM_TimeBaseInitStruct->LPTIM_ClockSource | LPTIM_TimeBaseInitStruct->LPTIM_ClockSampleTime \ + | LPTIM_TimeBaseInitStruct->LPTIM_TriggerSampleTime | LPTIM_TimeBaseInitStruct->LPTIM_ClockPrescaler \ + | LPTIM_TimeBaseInitStruct->LPTIM_TriggerSource | LPTIM_TimeBaseInitStruct->LPTIM_ExTriggerPolarity \ + | LPTIM_TimeBaseInitStruct->LPTIM_OutputPolarity | LPTIM_TimeBaseInitStruct->LPTIM_UpdateMode \ + | LPTIM_TimeBaseInitStruct->LPTIM_CountSource | LPTIM_TimeBaseInitStruct->LPTIM_InClockSource \ + | (LPTIM_TimeBaseInitStruct->LPTIM_TimeOut << 19) | (LPTIM_TimeBaseInitStruct->LPTIM_OnePulseMode << 20) \ + | (LPTIM_TimeBaseInitStruct->LPTIM_Encoder << 24) | (LPTIM_TimeBaseInitStruct->LPTIM_ForceOutHigh << 27); + + temp2 |= (LPTIM_TimeBaseInitStruct->LPTIM_SingleMode << 1) | (LPTIM_TimeBaseInitStruct->LPTIM_ContinuousMode << 2) \ + | (LPTIM_TimeBaseInitStruct->LPTIM_PWMOut << 3) | (LPTIM_TimeBaseInitStruct->LPTIM_CounterDirIndicat << 4); + + LPTIM->CFGR = temp1; + LPTIM->CR = temp2; + LPTIM->CMP = LPTIM_TimeBaseInitStruct->LPTIM_Pulse; + LPTIM->ARR = LPTIM_TimeBaseInitStruct->LPTIM_Period; +} + +/********************************************************************* + * @fn LPTIM_TimeBaseStructInit + * + * @brief Fills each LPTIM_TimeBaseInitStruct member with its default value. + * + * @param TIM_TimeBaseInitStruct - pointer to a LPTIM_TimeBaseInitTypeDef structure. + * + * @return none + */ +void LPTIM_TimeBaseStructInit(LPTIM_TimeBaseInitTypeDef *LPTIM_TimeBaseInitStruct) +{ + LPTIM_TimeBaseInitStruct->LPTIM_ClockSource = LPTIM_ClockSource_In; + LPTIM_TimeBaseInitStruct->LPTIM_ClockPolarity = LPTIM_ClockPolarity_Rising; + LPTIM_TimeBaseInitStruct->LPTIM_ClockSampleTime = LPTIM_ClockSampleTime_0T; + LPTIM_TimeBaseInitStruct->LPTIM_TriggerSampleTime = LPTIM_TriggerSampleTime_0T; + LPTIM_TimeBaseInitStruct->LPTIM_ClockPrescaler = LPTIM_TClockPrescaler_DIV1; + LPTIM_TimeBaseInitStruct->LPTIM_TriggerSource = LPTIM_TriggerSource_ETR; + LPTIM_TimeBaseInitStruct->LPTIM_ExTriggerPolarity = LPTIM_ExTriggerPolarity_Disable; + LPTIM_TimeBaseInitStruct->LPTIM_TimeOut = DISABLE; + LPTIM_TimeBaseInitStruct->LPTIM_OnePulseMode = DISABLE; + LPTIM_TimeBaseInitStruct->LPTIM_OutputPolarity = LPTIM_OutputPolarity_High; + LPTIM_TimeBaseInitStruct->LPTIM_UpdateMode = LPTIM_UpdateMode0; + LPTIM_TimeBaseInitStruct->LPTIM_CountSource = LPTIM_CountSource_Internal; + LPTIM_TimeBaseInitStruct->LPTIM_Encoder = DISABLE; + LPTIM_TimeBaseInitStruct->LPTIM_InClockSource = LPTIM_InClockSource_PCLK1; + LPTIM_TimeBaseInitStruct->LPTIM_ForceOutHigh = DISABLE; + LPTIM_TimeBaseInitStruct->LPTIM_SingleMode = DISABLE; + LPTIM_TimeBaseInitStruct->LPTIM_ContinuousMode = DISABLE; + LPTIM_TimeBaseInitStruct->LPTIM_PWMOut = DISABLE; + LPTIM_TimeBaseInitStruct->LPTIM_CounterDirIndicat = DISABLE; + LPTIM_TimeBaseInitStruct->LPTIM_Pulse = 0; + LPTIM_TimeBaseInitStruct->LPTIM_Period = 0x0001; +} + +/********************************************************************* + * @fn LPTIM_CounterDirIndicat_Cmd + * + * @brief Enable or Disable counter direction indicate function. + * + * @param NewState - ENABLE or DISABLE. + * + * @return none + */ +void LPTIM_CounterDirIndicat_Cmd(FunctionalState NewState) +{ + if(NewState) + { + LPTIM->CR |= (1<<3); + } + else{ + LPTIM->CR &= ~(1<<3); + } +} + +/********************************************************************* + * @fn LPTIM_OutCmd + * + * @brief Enable or Disable PWM out function. + * + * @param NewState - ENABLE or DISABLE. + * + * @return none + */ +void LPTIM_OutCmd(FunctionalState NewState) +{ + if(NewState) + { + LPTIM->CR |= (1<<3); + } + else{ + LPTIM->CR &= ~(1<<3); + } +} + +/********************************************************************* + * @fn LPTIM_Cmd + * + * @brief Enable or Disable LPTIM. + * + * @param NewState - ENABLE or DISABLE. + * + * @return none + */ +void LPTIM_Cmd(FunctionalState NewState) +{ + if(NewState) + { + LPTIM->CR |= (1<<0); + } + else{ + LPTIM->CR &= ~(1<<0); + } +} + +/********************************************************************* + * @fn LPTIM_GetCounter + * + * @brief Gets the LPTIM Counter value. + * + * @param none + * + * @return LPTIM->CNT - Counter Register value. + */ +uint16_t LPTIM_GetCounter(void) +{ + return LPTIM->CNT; +} + +/********************************************************************* + * @fn LPTIM_SetAutoreload + * + * @brief Sets the LPTIM Autoreload Register value. + * + * @param Autoreload - specifies the Autoreload register new value. + * + * @return none + */ +void LPTIM_SetAutoreload(uint16_t Autoreload) +{ + LPTIM->ARR = Autoreload; +} + +/********************************************************************* + * @fn LPTIM_SetCompare + * + * @brief Sets the LPTIM Capture Compare Register value. + * + * @param Compare - specifies the Capture Compare1 register new value. + * + * @return none + */ +void LPTIM_SetCompare(uint16_t Compare) +{ + LPTIM->CMP = Compare; +} + +/********************************************************************* + * @fn LPTIM_GetCapture + * + * @brief Gets the LPTIM Input Capture value. + * + * @param none + * + * @return LPTIM->CMP - Capture Compare Register value. + */ +uint16_t LPTIM_GetCapture(void) +{ + return LPTIM->CMP; +} + +/********************************************************************* + * @fn LPTIM_ITConfig + * + * @brief Enables or disables the specified LPTIM interrupts. + * + * @param LPTIM_IT - specifies the LPTIM interrupts sources to be enabled or disabled. + * LPTIM_IT_DOWN - LPTIM counter down Interrupt source. + * LPTIM_IT_UP - LPTIM counter up Interrupt source. + * LPTIM_IT_ARROK - LPTIM be loaded success Interrupt source. + * LPTIM_IT_CMPOK - LPTIM Capture Compare success Interrupt source. + * LPTIM_IT_EXTTRIG - TIM Trigger Interrupt source. + * LPTIM_IT_ARRM - TIM counter Count to ARR register Interrupt source. + * LPTIM_IT_CMPM - TIM counter Count to CMP register Interrupt source. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void LPTIM_ITConfig(uint32_t LPTIM_IT, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + LPTIM->IER |= LPTIM_IT; + } + else + { + LPTIM->IER &= (uint32_t)~LPTIM_IT; + } +} + +/********************************************************************* + * @fn LPTIM_GetFlagStatus + * + * @brief Checks whether the specified LPTIM flag is set or not. + * + * @param LPTIM_FLAG - specifies the flag to check. + * LPTIM_FLAG_DIR_SYNC - LPTIM counter direction indicate Flag. + * LPTIM_FLAG_DOWN - LPTIM counter down Flag. + * LPTIM_FLAG_UP - LPTIM counter up Flag. + * LPTIM_FLAG_ARROK - LPTIM be loaded success Flag. + * LPTIM_FLAG_CMPOK - LPTIM Capture Compare success Flag. + * LPTIM_FLAG_EXTTRIG - TIM Trigger Flag. + * LPTIM_FLAG_ARRM - TIM counter Count to ARR register Flag. + * LPTIM_FLAG_CMPM - TIM counter Count to CMP register Flag. + * + * @return none + */ +FlagStatus LPTIM_GetFlagStatus(uint32_t LPTIM_FLAG) +{ + FlagStatus bitstatus = RESET; + + if((LPTIM->ISR & LPTIM_FLAG) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn LPTIM_ClearFlag + * + * @brief Clears the LPTIM's pending flags. + * + * @param LPTIM_FLAG - specifies the flag to check. + * LPTIM_FLAG_DOWN - LPTIM counter down Flag. + * LPTIM_FLAG_UP - LPTIM counter up Flag. + * LPTIM_FLAG_ARROK - LPTIM be loaded success Flag. + * LPTIM_FLAG_CMPOK - LPTIM Capture Compare success Flag. + * LPTIM_FLAG_EXTTRIG - TIM Trigger Flag. + * LPTIM_FLAG_ARRM - TIM counter Count to ARR register Flag. + * LPTIM_FLAG_CMPM - TIM counter Count to CMP register Flag. + * + * @return none + */ +void LPTIM_ClearFlag(uint32_t LPTIM_FLAG) +{ + LPTIM->ICR |= (uint32_t)LPTIM_FLAG; +} + +/********************************************************************* + * @fn LPTIM_GetITStatus + * + * @brief Checks whether the LPTIM interrupt has occurred or not. + * + * @param LPTIM_IT - specifies the LPTIM interrupt source to check. + * LPTIM_FLAG_DIR_SYNC - LPTIM counter direction indicate Interrupt source. + * LPTIM_IT_DOWN - LPTIM counter down Interrupt source. + * LPTIM_IT_UP - LPTIM counter up Interrupt source. + * LPTIM_IT_ARROK - LPTIM be loaded success Interrupt source. + * LPTIM_IT_CMPOK - LPTIM Capture Compare success Interrupt source. + * LPTIM_IT_EXTTRIG - TIM Trigger Interrupt source. + * LPTIM_IT_ARRM - TIM counter Count to ARR register Interrupt source. + * LPTIM_IT_CMPM - TIM counter Count to CMP register Interrupt source. + * + * @return none + */ +ITStatus LPTIM_GetITStatus(uint32_t LPTIM_IT) +{ + ITStatus bitstatus = RESET; + + if((LPTIM->ISR & LPTIM_IT) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn LPTIM_ClearITPendingBit + * + * @brief Clears the LPTIM's interrupt pending bits. + * + * @param LPTIM_IT - specifies the LPTIM interrupt source to check. + * LPTIM_IT_DOWN - LPTIM counter down Interrupt source. + * LPTIM_IT_UP - LPTIM counter up Interrupt source. + * LPTIM_IT_ARROK - LPTIM be loaded success Interrupt source. + * LPTIM_IT_CMPOK - LPTIM Capture Compare success Interrupt source. + * LPTIM_IT_EXTTRIG - TIM Trigger Interrupt source. + * LPTIM_IT_ARRM - TIM counter Count to ARR register Interrupt source. + * LPTIM_IT_CMPM - TIM counter Count to CMP register Interrupt source. + * + * @return none + */ +void LPTIM_ClearITPendingBit(uint32_t LPTIM_IT) +{ + LPTIM->ICR |= (uint32_t)LPTIM_IT; +} + + + diff --git a/ZDBMS/BMS_CC/Peripheral/src/ch32l103_misc.c b/ZDBMS/BMS_CC/Peripheral/src/ch32l103_misc.c new file mode 100644 index 0000000..498f247 --- /dev/null +++ b/ZDBMS/BMS_CC/Peripheral/src/ch32l103_misc.c @@ -0,0 +1,81 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32l103_misc.c + * Author : WCH + * Version : V1.0.0 + * Date : 2023/12/26 + * Description : This file provides all the miscellaneous firmware functions . + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#include "ch32l103_misc.h" + +__IO uint32_t NVIC_Priority_Group = 0; + +/********************************************************************* + * @fn NVIC_PriorityGroupConfig + * + * @brief Configures the priority grouping - pre-emption priority and subpriority. + * + * @param NVIC_PriorityGroup - specifies the priority grouping bits length. + * NVIC_PriorityGroup_0 - 0 bits for pre-emption priority + * 3 bits for subpriority + * NVIC_PriorityGroup_1 - 1 bits for pre-emption priority + * 2 bits for subpriority + * + * @return none + */ +void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup) +{ + NVIC_Priority_Group = NVIC_PriorityGroup; +} + +/********************************************************************* + * @fn NVIC_Init + * + * @brief Initializes the NVIC peripheral according to the specified parameters in + * the NVIC_InitStruct. + * + * @param NVIC_InitStruct - pointer to a NVIC_InitTypeDef structure that contains the + * configuration information for the specified NVIC peripheral. + * interrupt nesting enable(CSR-0x804 bit1 = 1) + * NVIC_IRQChannelPreemptionPriority - range from 0 to 1. + * NVIC_IRQChannelSubPriority - range from 0 to 3. + * + * interrupt nesting disable(CSR-0x804 bit1 = 0) + * NVIC_IRQChannelPreemptionPriority - range is 0. + * NVIC_IRQChannelSubPriority - range from 0 to 7. + * + * @return none + */ +void NVIC_Init(NVIC_InitTypeDef *NVIC_InitStruct) +{ +#if (INTSYSCR_INEST == INTSYSCR_INEST_NoEN) + if(NVIC_Priority_Group == NVIC_PriorityGroup_0) + { + NVIC_SetPriority(NVIC_InitStruct->NVIC_IRQChannel, NVIC_InitStruct->NVIC_IRQChannelSubPriority << 4); + } +#else + if(NVIC_Priority_Group == NVIC_PriorityGroup_1) + { + if(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority == 1) + { + NVIC_SetPriority(NVIC_InitStruct->NVIC_IRQChannel, (1 << 7) | (NVIC_InitStruct->NVIC_IRQChannelSubPriority << 5)); + } + else if(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority == 0) + { + NVIC_SetPriority(NVIC_InitStruct->NVIC_IRQChannel, (0 << 7) | (NVIC_InitStruct->NVIC_IRQChannelSubPriority << 5)); + } + } +#endif + + if(NVIC_InitStruct->NVIC_IRQChannelCmd != DISABLE) + { + NVIC_EnableIRQ(NVIC_InitStruct->NVIC_IRQChannel); + } + else + { + NVIC_DisableIRQ(NVIC_InitStruct->NVIC_IRQChannel); + } +} diff --git a/ZDBMS/BMS_CC/Peripheral/src/ch32l103_opa.c b/ZDBMS/BMS_CC/Peripheral/src/ch32l103_opa.c new file mode 100644 index 0000000..ed39c5b --- /dev/null +++ b/ZDBMS/BMS_CC/Peripheral/src/ch32l103_opa.c @@ -0,0 +1,343 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32l103_opa.c + * Author : WCH + * Version : V1.0.0 + * Date : 2024/11/05 + * Description : This file provides all the OPA firmware functions. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#include "ch32l103_opa.h" + +/* FLASH Keys */ +#define OPCM_KEY1 ((uint32_t)0x45670123) +#define OPCM_KEY2 ((uint32_t)0xCDEF89AB) + +/* mask definition*/ +#define POLL_CNT_MASK ((uint16_t)0x7000) + +volatile uint32_t CTLR2_tmp = 0; + + +/******************************************************************************** + * @fn OPCM_Unlock + * + * @brief Unlocks the OPCM Controller. + * + * @return none + */ +void OPCM_Unlock(void) +{ + OPA->OPCMKEY = OPCM_KEY1; + OPA->OPCMKEY = OPCM_KEY2; +} + +/******************************************************************************** + * @fn OPCM_Lock + * + * @brief Locks the OPCM Controller. + * + * @return none + */ +void OPCM_Lock(void) +{ + OPA->CTLR1 |= (1<<7); +} + +/********************************************************************* + * @fn OPA_Init + * + * @brief Initializes the OPA peripheral according to the specified + * parameters in the OPA_InitStruct. + * + * @param OPA_InitStruct - pointer to a OPA_InitTypeDef structure + * + * @return none + */ +void OPA_Init(OPA_InitTypeDef *OPA_InitStruct) +{ + uint16_t tmp0 = 0, tmp1 = 0; + uint32_t tmp2 = 0; + + tmp0 = OPA->CFGR1; + tmp1 = OPA->CFGR2; + tmp2 = OPA->CTLR1; + + if(OPA_InitStruct->OPA_NUM == OPA1) + { + tmp1 &= 0xF800; + tmp2 &= 0x80000001; + + tmp1 |= (OPA_InitStruct->POLL_NUM << 9); + tmp2 |= (OPA_InitStruct->Mode << 1) | (OPA_InitStruct->PSEL << 4) \ + | (OPA_InitStruct->FB << 7) | (OPA_InitStruct->NSEL << 8) \ + | OPA_Trim; + } + + tmp0 |= (OPA_InitStruct->PSEL_POLL) | (OPA_InitStruct->BKIN_EN << 2) + | (OPA_InitStruct->RST_EN << 4) | (OPA_InitStruct->OUT_IE << 8) + | (OPA_InitStruct->CNT_IE << 10) | (OPA_InitStruct->NMI_IE << 11); + tmp1 |= OPA_InitStruct->OPA_POLL_Interval; + + OPA->CFGR1 = tmp0; + OPA->CFGR2 = tmp1; + OPA->CTLR1 = tmp2; +} + +/********************************************************************* + * @fn OPA_StructInit + * + * @brief Fills each OPA_StructInit member with its reset value. + * + * @param OPA_StructInit - pointer to a OPA_InitTypeDef structure + * + * @return none + */ +void OPA_StructInit(OPA_InitTypeDef *OPA_InitStruct) +{ + OPA_InitStruct->OPA_POLL_Interval = 0; + OPA_InitStruct->OPA_NUM = OPA1; + OPA_InitStruct->Mode = OUT_IO_OFF; + OPA_InitStruct->PSEL = CHP_OFF; + OPA_InitStruct->FB = FB_OFF; + OPA_InitStruct->NSEL = CHN_OFF; + OPA_InitStruct->PSEL_POLL = CHP_OPA1_OFF; + OPA_InitStruct->BKIN_EN = BKIN_OPA1_OFF; + OPA_InitStruct->RST_EN = RST_OPA1_OFF; + OPA_InitStruct->OUT_IE = OUT_IE_OPA1_OFF; + OPA_InitStruct->CNT_IE = CNT_IE_OFF; + OPA_InitStruct->NMI_IE = NMI_IE_OFF; + OPA_InitStruct->POLL_NUM = CHP_POLL_NUM_1; +} + +/********************************************************************* + * @fn OPA_Cmd + * + * @brief Enables or disables the specified OPA peripheral. + * + * @param OPA_NUM - Select OPA + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void OPA_Cmd(OPA_Num_TypeDef OPA_NUM, FunctionalState NewState) +{ + if(NewState == ENABLE) + { + OPA->CTLR1 |= (uint32_t)(1 << (OPA_NUM*16)); + } + else + { + OPA->CTLR1 &= ~(uint32_t)(1 << (OPA_NUM*16)); + } +} + +/********************************************************************* + * @fn OPA_LP_Cmd + * + * @brief Enables or disables the OPA enter low power mode. + * + * @param NewState - new state of the OPA enter low power mode + * (ENABLE or DISABLE). + * + * @return none + */ +void OPA_LP_Cmd(FunctionalState NewState) +{ + if(NewState) + { + OPA->CTLR1 |= (1 << 12); + } + else + { + OPA->CTLR1 &= ~(1 << 12); + } +} + +/********************************************************************* + * @fn OPA_CMP_Init + * + * @brief Initializes the CMP peripheral according to the specified + * parameters in the CMP_InitTypeDef. + * + * @param CMP_InitStruct - pointer to a CMP_InitTypeDef structure + * + * @return none + */ +void OPA_CMP_Init(CMP_InitTypeDef *CMP_InitStruct) +{ + uint32_t tmp1 = 0; + + tmp1 = CTLR2_tmp; + + if(CMP_InitStruct->CMP_NUM == CMP1) + { + tmp1 &= 0xFFFFFFC1; + tmp1 |= (CMP_InitStruct->Mode << 1) | (CMP_InitStruct->NSEL << 3) + | (CMP_InitStruct->PSEL << 4) | (CMP_InitStruct->HYEN <<5); + } + else if(CMP_InitStruct->CMP_NUM == CMP2) + { + tmp1 &= 0xFFFFC1FF; + tmp1 |= (CMP_InitStruct->Mode << 9) | (CMP_InitStruct->NSEL << 11) + | (CMP_InitStruct->PSEL << 12) | (CMP_InitStruct->HYEN <<13); + } + else if(CMP_InitStruct->CMP_NUM == CMP3) + { + tmp1 &= 0xFFC1FFFF; + tmp1 |= (CMP_InitStruct->Mode << 17) | (CMP_InitStruct->NSEL << 19) + | (CMP_InitStruct->PSEL << 20) | (CMP_InitStruct->HYEN <<21); + } + + CTLR2_tmp = tmp1; + OPA->CTLR2 = tmp1; +} + +/********************************************************************* + * @fn OPA_CMP_StructInit + * + * @brief Fills each OPA_CMP_StructInit member with its reset value. + * + * @param CMP_StructInit - pointer to a OPA_CMP_StructInit structure + * + * @return none + */ +void OPA_CMP_StructInit(CMP_InitTypeDef *CMP_InitStruct) +{ + CMP_InitStruct->CMP_NUM = CMP1; + CMP_InitStruct->Mode = OUT_IO0; + CMP_InitStruct->NSEL = CMP_CHN0; + CMP_InitStruct->PSEL = CMP_CHP_0; +} + +/********************************************************************* + * @fn OPA_CMP_Cmd + * + * @brief Enables or disables the specified CMP peripheral. + * + * @param CMP_NUM - Select CMP + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void OPA_CMP_Cmd(CMP_Num_TypeDef CMP_NUM, FunctionalState NewState) +{ + if(NewState == ENABLE) + { + CTLR2_tmp |= (uint32_t)(1 << (CMP_NUM*8)); + } + else + { + CTLR2_tmp &= ~(uint32_t)(1 << (CMP_NUM*8)); + } + + OPA->CTLR2 = CTLR2_tmp; +} + +/********************************************************************* + * @fn OPA_CMP_LP_Cmd + * + * @brief Enables or disables the CMP enter low power mode. + * + * @param CMP_NUM - Select CMP + * NewState - new state of the CMP enter low power mode + * (ENABLE or DISABLE). + * + * @return none + */ +void OPA_CMP_LP_Cmd(CMP_Num_TypeDef CMP_NUM, FunctionalState NewState) +{ + uint8_t tmp1 = 0; + + tmp1 = 6 + CMP_NUM * 8; + + if(NewState) + { + OPA->CTLR2 |= (1 << tmp1); + } + else + { + OPA->CTLR2 &= ~(1 << tmp1); + } +} + +/********************************************************************* + * @fn OPA_CMP_WakeUp_ModeConfig + * + * @brief Configures the CMP wake up Mode. + * + * @param CMP_WakeUP_Mode - Specifies the trigger signal active edge for wake up of the CMP. + * CMP_WakeUp_Rising_Falling - the trigger signal rise and fall edge for wake up. + * CMP_WakeUp_Rising - the trigger signal rise edge for wake up. + * CMP_WakeUp_Falling - the trigger signal fall edge for wake up. + * + * @return none + */ +void OPA_CMP_WakeUp_ModeConfig(uint32_t CMP_WakeUP_Mode) +{ + OPA->CTLR2 &= ~CMP_WakeUp_Falling; + OPA->CTLR2 |= CMP_WakeUP_Mode; +} + +/********************************************************************* + * @fn OPA_GetFlagStatus + * + * @brief Checks whether the OPA flag is set or not. + * + * @param OPA_FLAG - specifies the OPA flag to check. + * OPA_FLAG_OUT_OPA1 - OPA1 out flag + * OPA_FLAG_OUT_CNT - OPA out flag rising edge of sampling data + * + * @return FlagStatus - SET or RESET. + */ +FlagStatus OPA_GetFlagStatus(uint16_t OPA_FLAG) +{ + FlagStatus bitstatus = RESET; + + if((OPA->CFGR1 & OPA_FLAG) != (uint16_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn OPA_ClearFlag + * + * @brief Clears the OPA flag. + * + * @param OPA_FLAG - specifies the OPA flag to clear. + * OPA_FLAG_OUT_OPA1 - OPA1 out flag + * OPA_FLAG_OUT_CNT - OPA out flag rising edge of sampling data + * + * @return none + */ +void OPA_ClearFlag(uint16_t OPA_FLAG) +{ + OPA->CFGR1 &= (uint16_t)~OPA_FLAG; +} + +/********************************************************************* + * @fn OPA_POLL_CNT + * + * @brief Displays the current channel being polled by the OPA + * + * @param none + * + * @return OPA_POLL_NUM_TypeDef - Current channel for OPA polling + */ +OPA_POLL_NUM_TypeDef OPA_POLL_CNT(void) +{ + uint16_t tmp1 = 0; + tmp1 = OPA->CFGR2; + tmp1 &= POLL_CNT_MASK; + tmp1 = tmp1 >> 12; + return tmp1; +} diff --git a/ZDBMS/BMS_CC/Peripheral/src/ch32l103_pwr.c b/ZDBMS/BMS_CC/Peripheral/src/ch32l103_pwr.c new file mode 100644 index 0000000..550fd6d --- /dev/null +++ b/ZDBMS/BMS_CC/Peripheral/src/ch32l103_pwr.c @@ -0,0 +1,466 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32l103_pwr.c + * Author : WCH + * Version : V1.0.0 + * Date : 2024/01/22 + * Description : This file provides all the PWR firmware functions. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#include "ch32l103_pwr.h" +#include "ch32l103_rcc.h" + +/* PWR registers bit mask */ +/* CTLR register bit mask */ +#define CTLR_DS_MASK ((uint32_t)0xFFFFFFFC) +#define CTLR_PLS_MASK ((uint32_t)0xFFFFFF1F) + +/********************************************************************* + * @fn PWR_DeInit + * + * @brief Deinitializes the PWR peripheral registers to their default + * reset values. + * + * @return none + */ +void PWR_DeInit(void) +{ + RCC_PB1PeriphResetCmd(RCC_PB1Periph_PWR, ENABLE); + RCC_PB1PeriphResetCmd(RCC_PB1Periph_PWR, DISABLE); +} + +/********************************************************************* + * @fn PWR_BackupAccessCmd + * + * @brief Enables or disables access to the RTC and backup registers. + * + * @param NewState - new state of the access to the RTC and backup registers, + * This parameter can be: ENABLE or DISABLE. + * + * @return none + */ +void PWR_BackupAccessCmd(FunctionalState NewState) +{ + if(NewState) + { + PWR->CTLR |= (1 << 8); + } + else + { + PWR->CTLR &= ~(1 << 8); + } +} + +/********************************************************************* + * @fn PWR_PVDCmd + * + * @brief Enables or disables the Power Voltage Detector(PVD). + * + * @param NewState - new state of the PVD(ENABLE or DISABLE). + * + * @return none + */ +void PWR_PVDCmd(FunctionalState NewState) +{ + if(NewState) + { + PWR->CTLR |= (1 << 4); + } + else + { + PWR->CTLR &= ~(1 << 4); + } +} + +/********************************************************************* + * @fn PWR_PVDLevelConfig + * + * @brief Configures the voltage threshold detected by the Power Voltage + * Detector(PVD). + * + * @param PWR_PVDLevel - specifies the PVD detection level + * PWR_PVDLevel_0 - PVD detection level set to mode 0. + * PWR_PVDLevel_1 - PVD detection level set to mode 1. + * PWR_PVDLevel_2 - PVD detection level set to mode 2. + * PWR_PVDLevel_3 - PVD detection level set to mode 3. + * PWR_PVDLevel_4 - PVD detection level set to mode 4. + * PWR_PVDLevel_5 - PVD detection level set to mode 5. + * PWR_PVDLevel_6 - PVD detection level set to mode 6. + * PWR_PVDLevel_7 - PVD detection level set to mode 7. + * + * @return none + */ +void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel) +{ + uint32_t tmpreg = 0; + tmpreg = PWR->CTLR; + tmpreg &= CTLR_PLS_MASK; + tmpreg |= PWR_PVDLevel; + PWR->CTLR = tmpreg; +} + +/********************************************************************* + * @fn PWR_WakeUpPinCmd + * + * @brief Enables or disables the WakeUp Pin functionality. + * + * @param NewState - new state of the WakeUp Pin functionality + * (ENABLE or DISABLE). + * + * @return none + */ +void PWR_WakeUpPinCmd(FunctionalState NewState) +{ + if(NewState) + { + PWR->CSR |= (1 << 8); + } + else + { + PWR->CSR &= ~(1 << 8); + } +} + +/********************************************************************* + * @fn PWR_EnterSTOPMode + * + * @brief Enters STOP mode. + * + * @param PWR_Regulator - specifies the regulator state in STOP mode. + * PWR_Regulator_ON - STOP mode with regulator ON + * PWR_Regulator_LowPower - STOP mode with regulator in low power mode + * PWR_STOPEntry - specifies if STOP mode in entered with WFI or WFE instruction. + * PWR_STOPEntry_WFI - enter STOP mode with WFI instruction + * PWR_STOPEntry_WFE - enter STOP mode with WFE instruction + * + * @return none + */ +void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry) +{ + uint32_t tmpreg = 0; + tmpreg = PWR->CTLR; + tmpreg &= CTLR_DS_MASK; + tmpreg |= PWR_Regulator; + if(PWR_Regulator==PWR_Regulator_LowPower) + { + tmpreg &= ~(3 << 10); + tmpreg |= (1 <<11); + } + PWR->CTLR = tmpreg; + + NVIC->SCTLR |= (1 << 2); + + if(PWR_STOPEntry == PWR_STOPEntry_WFI) + { + __WFI(); + } + else + { + __WFE(); + } + + NVIC->SCTLR &= ~(1 << 2); +} + +/********************************************************************* + * @fn PWR_EnterSTANDBYMode + * + * @brief Enters STANDBY mode. + * + * @return none + */ +void PWR_EnterSTANDBYMode(void) +{ + uint32_t tmpreg = 0; + tmpreg = PWR->CTLR; + /* flash low power mode 1 */ + tmpreg &= ~(3 << 10); + tmpreg |= (1 << 11); + + tmpreg |= PWR_CTLR_CWUF; + tmpreg |= PWR_CTLR_PDDS; + + PWR->CTLR = tmpreg; + + NVIC->SCTLR |= (1 << 2); + + __WFI(); +} + +/********************************************************************* + * @fn PWR_GetFlagStatus + * + * @brief Checks whether the specified PWR flag is set or not. + * + * @param PWR_FLAG - specifies the flag to check. + * PWR_FLAG_WU - Wake Up flag + * PWR_FLAG_SB - StandBy flag + * PWR_FLAG_PVDO - PVD Output + * + * @return none + */ +FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG) +{ + FlagStatus bitstatus = RESET; + + if((PWR->CSR & PWR_FLAG) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/********************************************************************* + * @fn PWR_ClearFlag + * + * @brief Clears the PWR's pending flags. + * + * @param PWR_FLAG - specifies the flag to clear. + * PWR_FLAG_WU - Wake Up flag + * PWR_FLAG_SB - StandBy flag + * + * @return none + */ +void PWR_ClearFlag(uint32_t PWR_FLAG) +{ + PWR->CTLR |= PWR_FLAG << 2; +} + +/********************************************************************* + * @fn PWR_EnterSTANDBYMode_RAM + * + * @brief Enters STANDBY mode with RAM data retention function on. + * + * @return none + */ +void PWR_EnterSTANDBYMode_RAM(void) +{ + uint32_t tmpreg = 0; + tmpreg = PWR->CTLR; + + /* flash low power mode 1 */ + tmpreg &= ~(3 << 10); + tmpreg |= (1 << 11); + + tmpreg |= PWR_CTLR_CWUF; + tmpreg |= PWR_CTLR_PDDS; + + //2K+18K in standby power. + tmpreg |= (0x1 << 16) | (0x1 << 17); + + PWR->CTLR = tmpreg; + + NVIC->SCTLR |= (1 << 2); + + __WFI(); +} + +/********************************************************************* + * @fn PWR_EnterSTANDBYMode_RAM_LV + * + * @brief Enters STANDBY mode with RAM data retention function and LV mode on. + * + * @return none + */ +void PWR_EnterSTANDBYMode_RAM_LV(void) +{ + uint32_t tmpreg = 0; + tmpreg = PWR->CTLR; + + /* flash low power mode 1 */ + tmpreg &= ~(3 << 10); + tmpreg |= (1 << 11); + + tmpreg |= PWR_CTLR_CWUF; + tmpreg |= PWR_CTLR_PDDS; + + //2K+18K in standby power. + tmpreg |= (0x1 << 16) | (0x1 << 17); + //2K+18K in standby LV . + tmpreg |= (0x1 << 20); + + PWR->CTLR = tmpreg; + + NVIC->SCTLR |= (1 << 2); + + __WFI(); +} + +/********************************************************************* + * @fn PWR_EnterSTANDBYMode_RAM_VBAT_EN + * + * @brief Enters STANDBY mode with RAM data retention function on (VBAT Enable). + * + * @return none + */ +void PWR_EnterSTANDBYMode_RAM_VBAT_EN(void) +{ + uint32_t tmpreg = 0; + tmpreg = PWR->CTLR; + + /* flash low power mode 1 */ + tmpreg &= ~(3 << 10); + tmpreg |= (1 << 11); + + tmpreg |= PWR_CTLR_CWUF; + tmpreg |= PWR_CTLR_PDDS; + + //2K+18K in standby power (VBAT Enable). + tmpreg |= (0x1 << 18) | (0x1 << 19); + + PWR->CTLR = tmpreg; + + NVIC->SCTLR |= (1 << 2); + + __WFI(); +} + +/********************************************************************* + * @fn PWR_EnterSTANDBYMode_RAM_LV_VBAT_EN + * + * @brief Enters STANDBY mode with RAM data retention function and LV mode on(VBAT Enable). + * + * @return none + */ +void PWR_EnterSTANDBYMode_RAM_LV_VBAT_EN(void) +{ + uint32_t tmpreg = 0; + tmpreg = PWR->CTLR; + + /* flash low power mode 1 */ + tmpreg &= ~(3 << 10); + tmpreg |= (1 << 11); + + tmpreg |= PWR_CTLR_CWUF; + tmpreg |= PWR_CTLR_PDDS; + + //2K+18K in standby power (VBAT Enable). + tmpreg |= (0x1 << 18) | (0x1 << 19); + //2K+18K in standby LV . + tmpreg |= (0x1 << 20); + + PWR->CTLR = tmpreg; + + NVIC->SCTLR |= (1 << 2); + + __WFI(); +} + + +/********************************************************************* + * @fn PWR_EnterSTOPMode_RAM_LV + * + * @brief Enters STOP mode with RAM data retention function and LV mode on. + * + * @param PWR_Regulator - specifies the regulator state in STOP mode. + * PWR_Regulator_ON - STOP mode with regulator ON + * PWR_Regulator_LowPower - STOP mode with regulator in low power mode + * PWR_STOPEntry - specifies if STOP mode in entered with WFI or WFE instruction. + * PWR_STOPEntry_WFI - enter STOP mode with WFI instruction + * PWR_STOPEntry_WFE - enter STOP mode with WFE instruction + * + * @return none + */ +void PWR_EnterSTOPMode_RAM_LV(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry) +{ + uint32_t tmpreg = 0; + tmpreg = PWR->CTLR; + tmpreg &= CTLR_DS_MASK; + tmpreg |= PWR_Regulator; + tmpreg |= (0x1 << 20); + + if(PWR_Regulator==PWR_Regulator_LowPower) + { + tmpreg &= ~(3 << 10); + tmpreg |= (1 << 11); + } + + PWR->CTLR = tmpreg; + + NVIC->SCTLR |= (1 << 2); + + if(PWR_STOPEntry == PWR_STOPEntry_WFI) + { + __WFI(); + } + else + { + __WFE(); + } + + NVIC->SCTLR &= ~(1 << 2); +} + +/********************************************************************* + * @fn PWR_LDO_LP_Cmd + * + * @brief Enables or disables the LDO low power mode. + * + * @param NewState - new state of the LDO low power mode(ENABLE or DISABLE). + * + * @return none + */ +void PWR_LDO_LP_Cmd(FunctionalState NewState) +{ + if(NewState) + { + PWR->CTLR |= (1 << 13); + } + else + { + PWR->CTLR &= ~(1 << 13); + } +} + +/********************************************************************* + * @fn PWR_STOPMode_Auto_LDO_LP_Cmd + * + * @brief Enables or disables the LDO auto enter low power mode in + * stop mode. + * + * @param NewState - new state of the LDO auto enter low power mode + * in stop mode(ENABLE or DISABLE). + * + * @return none + */ +void PWR_STOPMode_Auto_LDO_LP_Cmd(FunctionalState NewState) +{ + if(NewState) + { + PWR->CTLR |= (1 << 12); + } + else + { + PWR->CTLR &= ~(1 << 12); + } +} + +/********************************************************************* + * @fn PWR_FLASH_LP_Cmd + * + * @brief Enables or disables the FLASH enter low power mode 0. + * + * @param NewState - new state of the FLASH enter low power mode 0. + * (ENABLE or DISABLE). + * + * @return none + */ +void PWR_FLASH_LP_Cmd(FunctionalState NewState) +{ + if(NewState) + { + PWR->CTLR |= (7 << 9); + } + else + { + PWR->CTLR &= ~(1 << 9); + } +} + + diff --git a/ZDBMS/BMS_CC/Peripheral/src/ch32l103_rcc.c b/ZDBMS/BMS_CC/Peripheral/src/ch32l103_rcc.c new file mode 100644 index 0000000..b701f1d --- /dev/null +++ b/ZDBMS/BMS_CC/Peripheral/src/ch32l103_rcc.c @@ -0,0 +1,1045 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32l103_rcc.c + * Author : WCH + * Version : V1.0.0 + * Date : 2023/07/08 + * Description : This file provides all the RCC firmware functions. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#include "ch32l103_rcc.h" + +/* RCC registers bit address in the alias region */ +#define RCC_OFFSET (RCC_BASE - PERIPH_BASE) + +/* BDCTLR Register */ +#define BDCTLR_OFFSET (RCC_OFFSET + 0x20) + +/* RCC registers bit mask */ + +/* CTLR register bit mask */ +#define CTLR_HSEBYP_Reset ((uint32_t)0xFFFBFFFF) +#define CTLR_HSEBYP_Set ((uint32_t)0x00040000) +#define CTLR_HSEON_Reset ((uint32_t)0xFFFEFFFF) +#define CTLR_HSEON_Set ((uint32_t)0x00010000) +#define CTLR_HSITRIM_Mask ((uint32_t)0xFFFFFF07) + +/* CFGR0 register bit mask */ +#define CFGR0_PLL_Mask ((uint32_t)0xFFC0FFFF) +#define CFGR0_PLLMull_Mask ((uint32_t)0x003C0000) +#define CFGR0_PLLSRC_Mask ((uint32_t)0x00010000) +#define CFGR0_PLLXTPRE_Mask ((uint32_t)0x00020000) +#define CFGR0_SWS_Mask ((uint32_t)0x0000000C) +#define CFGR0_SW_Mask ((uint32_t)0xFFFFFFFC) +#define CFGR0_HPRE_Reset_Mask ((uint32_t)0xFFFFFF0F) +#define CFGR0_HPRE_Set_Mask ((uint32_t)0x000000F0) +#define CFGR0_PPRE1_Reset_Mask ((uint32_t)0xFFFFF8FF) +#define CFGR0_PPRE1_Set_Mask ((uint32_t)0x00000700) +#define CFGR0_PPRE2_Reset_Mask ((uint32_t)0xFFFFC7FF) +#define CFGR0_PPRE2_Set_Mask ((uint32_t)0x00003800) +#define CFGR0_ADCPRE_Reset_Mask ((uint32_t)0x7FFF3FFF) +#define CFGR0_ADCPRE_Set_Mask ((uint32_t)0x0000C000) +#define CFGR0_ADCDUTY_Reset_Mask ((uint32_t)0x8FFFFFFF) + +/* RSTSCKR register bit mask */ +#define RSTSCKR_RMVF_Set ((uint32_t)0x01000000) + +/* RCC Flag Mask */ +#define FLAG_Mask ((uint8_t)0x1F) + +/* INTR register byte 2 (Bits[15:8]) base address */ +#define INTR_BYTE2_ADDRESS ((uint32_t)0x40021009) + +/* INTR register byte 3 (Bits[23:16]) base address */ +#define INTR_BYTE3_ADDRESS ((uint32_t)0x4002100A) + +/* CFGR0 register byte 4 (Bits[31:24]) base address */ +#define CFGR0_BYTE4_ADDRESS ((uint32_t)0x40021007) + +/* BDCTLR register base address */ +#define BDCTLR_ADDRESS (PERIPH_BASE + BDCTLR_OFFSET) + + +static __I uint8_t PBHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9}; +static __I uint8_t ADCPrescTable[4] = {2, 4, 6, 8}; + +/********************************************************************* + * @fn RCC_DeInit + * + * @brief Resets the RCC clock configuration to the default reset state. + * Note- + * HSE can not be stopped if it is used directly or through the PLL as system clock. + * @return none + */ +void RCC_DeInit(void) +{ + RCC->CTLR |= (uint32_t)0x00000001; + RCC->CFGR0 &= (uint32_t)0x08FF0000; + RCC->CTLR &= (uint32_t)0xFEF6FFFB; + RCC->CTLR &= (uint32_t)0xFFFBFFFF; + RCC->CFGR0 &= (uint32_t)0xFF00FFFF; + RCC->INTR = 0x009F0000; +} + +/********************************************************************* + * @fn RCC_HSEConfig + * + * @brief Configures the External High Speed oscillator (HSE). + * + * @param RCC_HSE - + * RCC_HSE_OFF - HSE oscillator OFF. + * RCC_HSE_ON - HSE oscillator ON. + * RCC_HSE_Bypass - HSE oscillator bypassed with external clock. + * Note - + * HSE can not be stopped if it is used directly or through the PLL as system clock. + * @return none + */ +void RCC_HSEConfig(uint32_t RCC_HSE) +{ + RCC->CTLR &= CTLR_HSEON_Reset; + RCC->CTLR &= CTLR_HSEBYP_Reset; + + switch(RCC_HSE) + { + case RCC_HSE_ON: + RCC->CTLR |= CTLR_HSEON_Set; + break; + + case RCC_HSE_Bypass: + RCC->CTLR |= CTLR_HSEBYP_Set | CTLR_HSEON_Set; + break; + + default: + break; + } +} + +/********************************************************************* + * @fn RCC_WaitForHSEStartUp + * + * @brief Waits for HSE start-up. + * + * @return READY - HSE oscillator is stable and ready to use. + * NoREADY - HSE oscillator not yet ready. + */ +ErrorStatus RCC_WaitForHSEStartUp(void) +{ + __IO uint32_t StartUpCounter = 0; + + ErrorStatus status = NoREADY; + FlagStatus HSEStatus = RESET; + + do + { + HSEStatus = RCC_GetFlagStatus(RCC_FLAG_HSERDY); + StartUpCounter++; + } while((StartUpCounter != HSE_STARTUP_TIMEOUT) && (HSEStatus == RESET)); + + if (RCC_GetFlagStatus(RCC_FLAG_HSERDY) != RESET) + { + status = READY; + } + else + { + status = NoREADY; + } + + return (status); +} + +/********************************************************************* + * @fn RCC_AdjustHSICalibrationValue + * + * @brief Adjusts the Internal High Speed oscillator (HSI) calibration value. + * + * @param HSICalibrationValue - specifies the calibration trimming value. + * This parameter must be a number between 0 and 0x1F. + * + * @return none + */ +void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue) +{ + uint32_t tmpreg = 0; + + tmpreg = RCC->CTLR; + tmpreg &= CTLR_HSITRIM_Mask; + tmpreg |= (uint32_t)HSICalibrationValue << 3; + RCC->CTLR = tmpreg; +} + +/********************************************************************* + * @fn RCC_HSICmd + * + * @brief Enables or disables the Internal High Speed oscillator (HSI). + * + * @param NewState - ENABLE or DISABLE. + * + * @return none + */ +void RCC_HSICmd(FunctionalState NewState) +{ + if(NewState) + { + RCC->CTLR |= (1<<0); + } + else + { + RCC->CTLR &= ~(1<<0); + } +} + +/********************************************************************* + * @fn RCC_PLLConfig + * + * @brief Configures the PLL clock source and multiplication factor. + * + * @param RCC_PLLSource - specifies the PLL entry clock source. + * RCC_PLLSource_HSI_Div2 - HSI oscillator clock divided by 2 + * selected as PLL clock entry. + * RCC_PLLSource_HSE_Div1 - HSI oscillator clock as PLL clock + * entry. + * RCC_PLLSource_HSE_Div2 - HSI oscillator clock divided by 2 + * as PLL clock entry. + * RCC_PLLMul - specifies the PLL multiplication factor. + * This parameter can be RCC_PLLMul_x where x:[2,16]. + * RCC_PLLMul_2 + * RCC_PLLMul_3 + * RCC_PLLMul_4 + * RCC_PLLMul_5 + * RCC_PLLMul_6 + * RCC_PLLMul_7 + * RCC_PLLMul_8 + * RCC_PLLMul_9 + * RCC_PLLMul_10 + * RCC_PLLMul_11 + * RCC_PLLMul_12 + * RCC_PLLMul_13 + * RCC_PLLMul_14 + * RCC_PLLMul_15 + * RCC_PLLMul_16 + * RCC_PLLMul_18 + * + * @return none + */ +void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t RCC_PLLMul) +{ + uint32_t tmpreg = 0; + + tmpreg = RCC->CFGR0; + + tmpreg &= CFGR0_PLL_Mask; + tmpreg |= RCC_PLLSource | RCC_PLLMul; + RCC->CFGR0 = tmpreg; +} + +/********************************************************************* + * @fn RCC_PLLCmd + * + * @brief Enables or disables the PLL. + * Note-The PLL can not be disabled if it is used as system clock. + * + * @param NewState - ENABLE or DISABLE. + * + * @return none + */ +void RCC_PLLCmd(FunctionalState NewState) +{ + if(NewState) + { + RCC->CTLR |= (1<<24); + } + else + { + RCC->CTLR &= ~(1<<24); + } +} + +/********************************************************************* + * @fn RCC_SYSCLKConfig + * + * @brief Configures the system clock (SYSCLK). + * + * @param RCC_SYSCLKSource - specifies the clock source used as system clock. + * RCC_SYSCLKSource_HSI - HSI selected as system clock. + * RCC_SYSCLKSource_HSE - HSE selected as system clock. + * RCC_SYSCLKSource_PLLCLK - PLL selected as system clock. + * + * @return none + */ +void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource) +{ + uint32_t tmpreg = 0; + + tmpreg = RCC->CFGR0; + tmpreg &= CFGR0_SW_Mask; + tmpreg |= RCC_SYSCLKSource; + RCC->CFGR0 = tmpreg; +} + +/********************************************************************* + * @fn RCC_GetSYSCLKSource + * + * @brief Returns the clock source used as system clock. + * + * @return 0x00 - HSI used as system clock. + * 0x04 - HSE used as system clock. + * 0x08 - PLL used as system clock. + */ +uint8_t RCC_GetSYSCLKSource(void) +{ + return ((uint8_t)(RCC->CFGR0 & CFGR0_SWS_Mask)); +} + +/********************************************************************* + * @fn RCC_HCLKConfig + * + * @brief Configures the HB clock (HCLK). + * + * @param RCC_SYSCLK - defines the HB clock divider. This clock is derived from + * the system clock (SYSCLK). + * RCC_SYSCLK_Div1 - HB clock = SYSCLK. + * RCC_SYSCLK_Div2 - HB clock = SYSCLK/2. + * RCC_SYSCLK_Div4 - HB clock = SYSCLK/4. + * RCC_SYSCLK_Div8 - HB clock = SYSCLK/8. + * RCC_SYSCLK_Div16 - HB clock = SYSCLK/16. + * RCC_SYSCLK_Div64 - HB clock = SYSCLK/64. + * RCC_SYSCLK_Div128 - HB clock = SYSCLK/128. + * RCC_SYSCLK_Div256 - HB clock = SYSCLK/256. + * RCC_SYSCLK_Div512 - HB clock = SYSCLK/512. + * + * @return none + */ +void RCC_HCLKConfig(uint32_t RCC_SYSCLK) +{ + uint32_t tmpreg = 0; + + tmpreg = RCC->CFGR0; + tmpreg &= CFGR0_HPRE_Reset_Mask; + tmpreg |= RCC_SYSCLK; + RCC->CFGR0 = tmpreg; +} + +/********************************************************************* + * @fn RCC_PCLK1Config + * + * @brief Configures the Low Speed PB clock (PCLK1). + * + * @param RCC_HCLK - defines the PB1 clock divider. This clock is derived from + * the HB clock (HCLK). + * RCC_HCLK_Div1 - PB1 clock = HCLK. + * RCC_HCLK_Div2 - PB1 clock = HCLK/2. + * RCC_HCLK_Div4 - PB1 clock = HCLK/4. + * RCC_HCLK_Div8 - PB1 clock = HCLK/8. + * RCC_HCLK_Div16 - PB1 clock = HCLK/16. + * + * @return none + */ +void RCC_PCLK1Config(uint32_t RCC_HCLK) +{ + uint32_t tmpreg = 0; + + tmpreg = RCC->CFGR0; + tmpreg &= CFGR0_PPRE1_Reset_Mask; + tmpreg |= RCC_HCLK; + RCC->CFGR0 = tmpreg; +} + +/********************************************************************* + * @fn RCC_PCLK2Config + * + * @brief Configures the High Speed PB clock (PCLK2). + * + * @param RCC_HCLK - defines the PB2 clock divider. This clock is derived from + * the HB clock (HCLK). + * RCC_HCLK_Div1 - PB2 clock = HCLK. + * RCC_HCLK_Div2 - PB2 clock = HCLK/2. + * RCC_HCLK_Div4 - PB2 clock = HCLK/4. + * RCC_HCLK_Div8 - PB2 clock = HCLK/8. + * RCC_HCLK_Div16 - PB2 clock = HCLK/16. + * @return none + */ +void RCC_PCLK2Config(uint32_t RCC_HCLK) +{ + uint32_t tmpreg = 0; + + tmpreg = RCC->CFGR0; + tmpreg &= CFGR0_PPRE2_Reset_Mask; + tmpreg |= RCC_HCLK << 3; + RCC->CFGR0 = tmpreg; +} + +/********************************************************************* + * @fn RCC_ITConfig + * + * @brief Enables or disables the specified RCC interrupts. + * + * @param RCC_IT - specifies the RCC interrupt sources to be enabled or disabled. + * RCC_IT_LSIRDY - LSI ready interrupt. + * RCC_IT_LSERDY - LSE ready interrupt. + * RCC_IT_HSIRDY - HSI ready interrupt. + * RCC_IT_HSERDY - HSE ready interrupt. + * RCC_IT_PLLRDY - PLL ready interrupt. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState) +{ + if (NewState != DISABLE) + { + *(__IO uint8_t *) INTR_BYTE2_ADDRESS |= RCC_IT; + } + else + { + *(__IO uint8_t *) INTR_BYTE2_ADDRESS &= (uint8_t)~RCC_IT; + } +} + +/********************************************************************* + * @fn RCC_USBCLKConfig + * + * @brief Configures the USB clock (USBCLK). + * + * @param RCC_USBCLKSource: specifies the USB clock source. This clock is + * derived from the PLL output. + * RCC_USBCLKSource_PLLCLK_Div1 - PLL clock selected as USB clock source(48Mhz). + * RCC_USBCLKSource_PLLCLK_Div2 - PLL clock selected as USB clock source(96MHz). + * RCC_USBCLKSource_PLLCLK_Div1_5 - PLL clock selected as USB clock source(72MHz). + * + * @return none + */ +void RCC_USBCLKConfig(uint32_t RCC_USBCLKSource) +{ + RCC->CFGR0 &= ~((uint32_t)3<<22); + RCC->CFGR0 |= RCC_USBCLKSource; +} + +/********************************************************************* + * @fn RCC_ADCCLKConfig + * + * @brief Configures the ADC clock (ADCCLK). + * + * @param ADC_CLK_S - defines the ADC clock. + * RCC_PCLK2_Div2 - ADC clock = PCLK2/2. + * RCC_PCLK2_Div4 - ADC clock = PCLK2/4. + * RCC_PCLK2_Div6 - ADC clock = PCLK2/6. + * RCC_PCLK2_Div8 - ADC clock = PCLK2/8. + * RCC_HCLK_ADC - ADC clock = HCLK. + * + * @return none + */ +void RCC_ADCCLKConfig(uint32_t ADC_CLK_S) +{ + uint32_t tmpreg = 0; + + tmpreg = RCC->CFGR0; + tmpreg &= CFGR0_ADCPRE_Reset_Mask; + tmpreg |= ADC_CLK_S; + RCC->CFGR0 = tmpreg; +} + +/********************************************************************* + * @fn RCC_LSEConfig + * + * @brief Configures the External Low Speed oscillator (LSE). + * + * @param RCC_LSE - specifies the new state of the LSE. + * RCC_LSE_OFF - LSE oscillator OFF. + * RCC_LSE_ON - LSE oscillator ON. + * RCC_LSE_Bypass - LSE oscillator bypassed with external clock. + * + * @return none + */ +void RCC_LSEConfig(uint8_t RCC_LSE) +{ + *(__IO uint8_t *) BDCTLR_ADDRESS = RCC_LSE_OFF; + *(__IO uint8_t *) BDCTLR_ADDRESS = RCC_LSE_OFF; + + switch(RCC_LSE) + { + case RCC_LSE_ON: + *(__IO uint8_t *) BDCTLR_ADDRESS = RCC_LSE_ON; + break; + + case RCC_LSE_Bypass: + *(__IO uint8_t *) BDCTLR_ADDRESS = RCC_LSE_Bypass | RCC_LSE_ON; + break; + + default: + break; + } +} + +/********************************************************************* + * @fn RCC_LSICmd + * + * @brief Enables or disables the Internal Low Speed oscillator (LSI). + * Note- + * LSI can not be disabled if the IWDG is running. + * + * @param NewState - ENABLE or DISABLE. + * + * @return none + */ +void RCC_LSICmd(FunctionalState NewState) +{ + if(NewState) + { + RCC->RSTSCKR |= (1<<0); + } + else{ + RCC->RSTSCKR &= ~(1<<0); + } +} + +/********************************************************************* + * @fn RCC_RTCCLKConfig + * + * @brief Once the RTC clock is selected it can't be changed unless the Backup domain is reset. + * + * @param RCC_RTCCLKSource - specifies the RTC clock source. + * RCC_RTCCLKSource_LSE - LSE selected as RTC clock. + * RCC_RTCCLKSource_LSI - LSI selected as RTC clock. + * RCC_RTCCLKSource_HSE_Div128 - HSE clock divided by 128 selected as RTC clock. + * Note- + * Once the RTC clock is selected it can't be changed unless the Backup domain is reset. + * + * @return none + */ +void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource) +{ + RCC->BDCTLR |= RCC_RTCCLKSource; +} + +/********************************************************************* + * @fn RCC_RTCCLKCmd + * + * @brief This function must be used only after the RTC clock was selected + * using the RCC_RTCCLKConfig function. + * + * @param NewState - ENABLE or DISABLE. + * + * @return none + */ +void RCC_RTCCLKCmd(FunctionalState NewState) +{ + if(NewState) + { + RCC->BDCTLR |= (1<<15); + } + else + { + RCC->BDCTLR &= ~(1<<15); + } +} + +/********************************************************************* + * @fn RCC_GetClocksFreq + * + * @brief The result of this function could be not correct when using + * fractional value for HSE crystal. + * + * @param RCC_Clocks - pointer to a RCC_ClocksTypeDef structure which will hold + * the clocks frequencies. + * + * @return none + */ +void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks) +{ + uint32_t tmp = 0, pllmull = 0, pllsource = 0, presc = 0; + + tmp = RCC->CFGR0 & CFGR0_SWS_Mask; + + switch (tmp) + { + case 0x00: + if(RCC->CTLR & (1<<2)) + { + RCC_Clocks->SYSCLK_Frequency = HSI_LP_VALUE; + } + else + { + RCC_Clocks->SYSCLK_Frequency = HSI_VALUE; + } + break; + + case 0x04: + RCC_Clocks->SYSCLK_Frequency = HSE_VALUE; + break; + + case 0x08: + pllmull = RCC->CFGR0 & CFGR0_PLLMull_Mask; + pllsource = RCC->CFGR0 & CFGR0_PLLSRC_Mask; + + pllmull = ( pllmull >> 18) + 2; + + if(pllmull == 17) pllmull = 18; + + + if (pllsource == 0x00) + { + if(EXTEN->EXTEN_CTR & EXTEN_PLL_HSI_PRE){ + RCC_Clocks->SYSCLK_Frequency = (HSI_VALUE) * pllmull; + } + else{ + RCC_Clocks->SYSCLK_Frequency = (HSI_VALUE >>1) * pllmull; + } + } + else + { + if ((RCC->CFGR0 & CFGR0_PLLXTPRE_Mask) != (uint32_t)RESET) + { + RCC_Clocks->SYSCLK_Frequency = (HSE_VALUE >> 1) * pllmull; + } + else + { + RCC_Clocks->SYSCLK_Frequency = HSE_VALUE * pllmull; + + } + } + + break; + + default: + RCC_Clocks->SYSCLK_Frequency = HSI_VALUE; + break; + } + + tmp = RCC->CFGR0 & CFGR0_HPRE_Set_Mask; + tmp = tmp >> 4; + presc = PBHBPrescTable[tmp]; + RCC_Clocks->HCLK_Frequency = RCC_Clocks->SYSCLK_Frequency >> presc; + tmp = RCC->CFGR0 & CFGR0_PPRE1_Set_Mask; + tmp = tmp >> 8; + presc = PBHBPrescTable[tmp]; + RCC_Clocks->PCLK1_Frequency = RCC_Clocks->HCLK_Frequency >> presc; + tmp = RCC->CFGR0 & CFGR0_PPRE2_Set_Mask; + tmp = tmp >> 11; + presc = PBHBPrescTable[tmp]; + RCC_Clocks->PCLK2_Frequency = RCC_Clocks->HCLK_Frequency >> presc; + + if(RCC->CFGR0 & (1<<31)) + { + RCC_Clocks->ADCCLK_Frequency = RCC_Clocks->HCLK_Frequency; + } + else + { + tmp = RCC->CFGR0 & CFGR0_ADCPRE_Set_Mask; + tmp = tmp >> 14; + presc = ADCPrescTable[tmp]; + RCC_Clocks->ADCCLK_Frequency = RCC_Clocks->PCLK2_Frequency / presc; + } +} + +/********************************************************************* + * @fn RCC_HBPeriphClockCmd + * + * @brief Enables or disables the HB peripheral clock. + * + * @param RCC_HBPeriph - specifies the HB peripheral to gates its clock. + * RCC_HBPeriph_DMA1. + * RCC_HBPeriph_SRAM. + * RCC_HBPeriph_CRC. + * RCC_HBPeriph_USBFS. + * RCC_HBPeriph_USBPD. + * Note- + * SRAM clock can be disabled only during sleep mode. + * NewState: ENABLE or DISABLE. + * + * @return none + */ +void RCC_HBPeriphClockCmd(uint32_t RCC_HBPeriph, FunctionalState NewState) +{ + if (NewState != DISABLE) + { + RCC->HBPCENR |= RCC_HBPeriph; + } + else + { + RCC->HBPCENR &= ~RCC_HBPeriph; + } +} + +/********************************************************************* + * @fn RCC_PB2PeriphClockCmd + * + * @brief Enables or disables the High Speed PB (PB2) peripheral clock. + * + * @param RCC_PB2Periph - specifies the PB2 peripheral to gates its clock. + * RCC_PB2Periph_AFIO. + * RCC_PB2Periph_GPIOA. + * RCC_PB2Periph_GPIOB. + * RCC_PB2Periph_GPIOC. + * RCC_PB2Periph_GPIOD. + * RCC_PB2Periph_ADC1. + * RCC_PB2Periph_TIM1. + * RCC_PB2Periph_SPI1. + * RCC_PB2Periph_TIM8 + * RCC_PB2Periph_USART1. + * NewState - ENABLE or DISABLE + * + * @return none + */ +void RCC_PB2PeriphClockCmd(uint32_t RCC_PB2Periph, FunctionalState NewState) +{ + if (NewState != DISABLE) + { + RCC->PB2PCENR |= RCC_PB2Periph; + } + else + { + RCC->PB2PCENR &= ~RCC_PB2Periph; + } +} + +/********************************************************************* + * @fn RCC_PB1PeriphClockCmd + * + * @brief Enables or disables the Low Speed PB (PB1) peripheral clock. + * + * @param RCC_PB1Periph - specifies the PB1 peripheral to gates its clock. + * RCC_PB1Periph_TIM2. + * RCC_PB1Periph_TIM3. + * RCC_PB1Periph_TIM4. + * RCC_PB1Periph_WWDG. + * RCC_PB1Periph_SPI2. + * RCC_PB1Periph_USART2. + * RCC_PB1Periph_USART3. + * RCC_PB1Periph_USART4 + * RCC_PB1Periph_I2C1. + * RCC_PB1Periph_I2C2. + * RCC_PB1Periph_CAN1. + * RCC_PB1Periph_BKP. + * RCC_PB1Periph_PWR. + * RCC_PB1Periph_LPTIM. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void RCC_PB1PeriphClockCmd(uint32_t RCC_PB1Periph, FunctionalState NewState) +{ + if (NewState != DISABLE) + { + RCC->PB1PCENR |= RCC_PB1Periph; + } + else + { + RCC->PB1PCENR &= ~RCC_PB1Periph; + } +} + +/********************************************************************* + * @fn RCC_PB2PeriphResetCmd + * + * @brief Forces or releases High Speed PB (PB2) peripheral reset. + * + * @param RCC_PB2Periph - specifies the PB2 peripheral to reset. + * RCC_PB2Periph_AFIO. + * RCC_PB2Periph_GPIOA. + * RCC_PB2Periph_GPIOB. + * RCC_PB2Periph_GPIOC. + * RCC_PB2Periph_GPIOD. + * RCC_PB2Periph_ADC1. + * RCC_PB2Periph_TIM1. + * RCC_PB2Periph_SPI1. + * RCC_PB2Periph_TIM8 + * RCC_PB2Periph_USART1. + * NewState - ENABLE or DISABLE + * + * @return none + */ +void RCC_PB2PeriphResetCmd(uint32_t RCC_PB2Periph, FunctionalState NewState) +{ + if (NewState != DISABLE) + { + RCC->PB2PRSTR |= RCC_PB2Periph; + } + else + { + RCC->PB2PRSTR &= ~RCC_PB2Periph; + } +} + +/********************************************************************* + * @fn RCC_PB1PeriphResetCmd + * + * @brief Forces or releases Low Speed PB (PB1) peripheral reset. + * + * @param RCC_PB1Periph - specifies the PB1 peripheral to reset. + * RCC_PB1Periph_TIM2. + * RCC_PB1Periph_TIM3. + * RCC_PB1Periph_TIM4. + * RCC_PB1Periph_WWDG. + * RCC_PB1Periph_SPI2. + * RCC_PB1Periph_USART2. + * RCC_PB1Periph_USART3. + * RCC_PB1Periph_USART4 + * RCC_PB1Periph_I2C1. + * RCC_PB1Periph_I2C2. + * RCC_PB1Periph_CAN1. + * RCC_PB1Periph_BKP. + * RCC_PB1Periph_PWR. + * RCC_PB1Periph_LPTIM. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void RCC_PB1PeriphResetCmd(uint32_t RCC_PB1Periph, FunctionalState NewState) +{ + if (NewState != DISABLE) + { + RCC->PB1PRSTR |= RCC_PB1Periph; + } + else + { + RCC->PB1PRSTR &= ~RCC_PB1Periph; + } +} + +/********************************************************************* + * @fn RCC_BackupResetCmd + * + * @brief Forces or releases the Backup domain reset. + * + * @param NewState - ENABLE or DISABLE. + * + * @return none + */ +void RCC_BackupResetCmd(FunctionalState NewState) +{ + if(NewState) + { + RCC->BDCTLR |= (1<<16); + } + else{ + RCC->BDCTLR &= ~(1<<16); + } +} + +/******************************************************************************* +* Function Name : RCC_ClockSecuritySystemCmd +* Description : Enables or disables the Clock Security System. +* Input : NewState: ENABLE or DISABLE. +* Return : None +*******************************************************************************/ +void RCC_ClockSecuritySystemCmd(FunctionalState NewState) +{ + if(NewState) + { + RCC->CTLR |= (1<<19); + } + else{ + RCC->CTLR &= ~(1<<19); + } +} + +/********************************************************************* + * @fn RCC_MCOConfig + * + * @brief Selects the clock source to output on MCO pin. + * + * @param RCC_MCO - specifies the clock source to output. + * RCC_MCO_NoClock - No clock selected. + * RCC_MCO_SYSCLK - System clock selected. + * RCC_MCO_HSI - HSI oscillator clock selected. + * RCC_MCO_HSE - HSE oscillator clock selected. + * RCC_MCO_PLLCLK_Div2 - PLL clock divided by 2 selected. + * + * @return none + */ +void RCC_MCOConfig(uint8_t RCC_MCO) +{ + *(__IO uint8_t *) CFGR0_BYTE4_ADDRESS = RCC_MCO; +} + +/********************************************************************* + * @fn RCC_GetFlagStatus + * + * @brief Checks whether the specified RCC flag is set or not. + * + * @param RCC_FLAG - specifies the flag to check. + * RCC_FLAG_HSIRDY - HSI oscillator clock ready. + * RCC_FLAG_HSERDY - HSE oscillator clock ready. + * RCC_FLAG_PLLRDY - PLL clock ready. + * RCC_FLAG_LSERDY - LSE oscillator clock ready. + * RCC_FLAG_LSIRDY - LSI oscillator clock ready. + * RCC_FLAG_PINRST - Pin reset. + * RCC_FLAG_PORRST - POR/PDR reset. + * RCC_FLAG_SFTRST - Software reset. + * RCC_FLAG_IWDGRST - Independent Watchdog reset. + * RCC_FLAG_WWDGRST - Window Watchdog reset. + * RCC_FLAG_LPWRRST - Low Power reset. + * + * @return FlagStatus - SET or RESET. + */ +FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG) +{ + uint32_t tmp = 0; + uint32_t statusreg = 0; + + FlagStatus bitstatus = RESET; + tmp = RCC_FLAG >> 5; + + if (tmp == 1) + { + statusreg = RCC->CTLR; + } + else if (tmp == 2) + { + statusreg = RCC->BDCTLR; + } + else + { + statusreg = RCC->RSTSCKR; + } + + tmp = RCC_FLAG & FLAG_Mask; + + if ((statusreg & ((uint32_t)1 << tmp)) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn RCC_ClearFlag + * + * @brief Clears the RCC reset flags. + * Note- + * The reset flags are: RCC_FLAG_PINRST, RCC_FLAG_PORRST, RCC_FLAG_SFTRST, + * RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST + * + * @return none + */ +void RCC_ClearFlag(void) +{ + RCC->RSTSCKR |= RSTSCKR_RMVF_Set; +} + +/********************************************************************* + * @fn RCC_GetITStatus + * + * @brief Checks whether the specified RCC interrupt has occurred or not. + * + * @param RCC_IT - specifies the RCC interrupt source to check. + * RCC_IT_LSIRDY - LSI ready interrupt. + * RCC_IT_LSERDY - LSE ready interrupt. + * RCC_IT_HSIRDY - HSI ready interrupt. + * RCC_IT_HSERDY - HSE ready interrupt. + * RCC_IT_PLLRDY - PLL ready interrupt. + * RCC_IT_CSS - Clock Security System interrupt. + * + * @return ITStatus - SET or RESET. + */ +ITStatus RCC_GetITStatus(uint8_t RCC_IT) +{ + ITStatus bitstatus = RESET; + + if ((RCC->INTR & RCC_IT) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn RCC_ClearITPendingBit + * + * @brief Clears the RCC's interrupt pending bits. + * + * @param RCC_IT - specifies the interrupt pending bit to clear. + * RCC_IT_LSIRDY - LSI ready interrupt. + * RCC_IT_LSERDY - LSE ready interrupt. + * RCC_IT_HSIRDY - HSI ready interrupt. + * RCC_IT_HSERDY - HSE ready interrupt. + * RCC_IT_PLLRDY - PLL ready interrupt. + * RCC_IT_CSS - Clock Security System interrupt. + * + * @return none + */ +void RCC_ClearITPendingBit(uint8_t RCC_IT) +{ + *(__IO uint8_t *) INTR_BYTE3_ADDRESS = RCC_IT; +} + +/********************************************************************* + * @fn RCC_ADCCLKDutyCycleConfig + * + * @brief Configures the ADC clock high level duty cycle. + * + * @param RCC_DutyCycle - high level duty cycle. + * RCC_ADC_H_Level_Mode0 - ADC clock high-level duty cycle is mode 0. + * RCC_ADC_H_Level_Mode1 - ADC clock high-level duty cycle is mode 1. + * RCC_ADC_H_Level_Mode2 - ADC clock high-level duty cycle is mode 2. + * RCC_ADC_H_Level_Mode3 - ADC clock high-level duty cycle is mode 3. + * RCC_ADC_H_Level_Mode4 - ADC clock high-level duty cycle is mode 4. + * RCC_ADC_H_Level_Mode5 - ADC clock high-level duty cycle is mode 5. + * RCC_ADC_H_Level_Mode6 - ADC clock high-level duty cycle is mode 6. + * RCC_ADC_H_Level_Mode7 - ADC clock high-level duty cycle is mode 7. + * + * @return none + */ +void RCC_ADCCLKDutyCycleConfig(uint32_t RCC_DutyCycle) +{ + RCC->CFGR0 &= CFGR0_ADCDUTY_Reset_Mask; + RCC->CFGR0 |= RCC_DutyCycle; +} + +/********************************************************************* + * @fn RCC_HSE_LP_Cmd + * + * @brief Enables or disables low power mode of the External High Speed + * oscillator (HSE). + * + * @param NewState - ENABLE or DISABLE. + * + * @return none + */ +void RCC_HSE_LP_Cmd(FunctionalState NewState) +{ + if(NewState) + { + RCC->CTLR |= (1<<20); + } + else + { + RCC->CTLR &= ~(1<<20); + } +} + +/********************************************************************* + * @fn RCC_HSI_LP_Cmd + * + * @brief Enables or disables low power mode of the Internal High Speed + * oscillator (HSI) . + * + * @param NewState - ENABLE or DISABLE. + * + * @return none + */ +void RCC_HSI_LP_Cmd(FunctionalState NewState) +{ + if(NewState) + { + RCC->CTLR |= (1<<2); + } + else + { + RCC->CTLR &= ~(1<<2); + } +} + + diff --git a/ZDBMS/BMS_CC/Peripheral/src/ch32l103_rtc.c b/ZDBMS/BMS_CC/Peripheral/src/ch32l103_rtc.c new file mode 100644 index 0000000..f4d6b8e --- /dev/null +++ b/ZDBMS/BMS_CC/Peripheral/src/ch32l103_rtc.c @@ -0,0 +1,281 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32l103_rtc.c + * Author : WCH + * Version : V1.0.0 + * Date : 2023/07/08 + * Description : This file provides all the RTC firmware functions. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#include "ch32l103_rtc.h" + +/* RTC_Private_Defines */ +#define RTC_LSB_MASK ((uint32_t)0x0000FFFF) /* RTC LSB Mask */ +#define PRLH_MSB_MASK ((uint32_t)0x000F0000) /* RTC Prescaler MSB Mask */ + +/********************************************************************* + * @fn RTC_ITConfig + * + * @brief Enables or disables the specified RTC interrupts. + * + * @param RTC_IT - specifies the RTC interrupts sources to be enabled or disabled. + * RTC_IT_OW - Overflow interrupt + * RTC_IT_ALR - Alarm interrupt + * RTC_IT_SEC - Second interrupt + * + * @return NewState - new state of the specified RTC interrupts(ENABLE or DISABLE). + */ +void RTC_ITConfig(uint16_t RTC_IT, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + RTC->CTLRH |= RTC_IT; + } + else + { + RTC->CTLRH &= (uint16_t)~RTC_IT; + } +} + +/********************************************************************* + * @fn RTC_EnterConfigMode + * + * @brief Enters the RTC configuration mode. + * + * @return none + */ +void RTC_EnterConfigMode(void) +{ + RTC->CTLRL |= RTC_CTLRL_CNF; +} + +/********************************************************************* + * @fn RTC_ExitConfigMode + * + * @brief Exits from the RTC configuration mode. + * + * @return none + */ +void RTC_ExitConfigMode(void) +{ + RTC->CTLRL &= (uint16_t) ~((uint16_t)RTC_CTLRL_CNF); +} + +/********************************************************************* + * @fn RTC_GetCounter + * + * @brief Gets the RTC counter value + * + * @return RTC counter value + */ +uint32_t RTC_GetCounter(void) +{ + uint16_t high1 = 0, high2 = 0, low = 0; + + high1 = RTC->CNTH; + low = RTC->CNTL; + high2 = RTC->CNTH; + + if(high1 != high2) + { + return (((uint32_t)high2 << 16) | RTC->CNTL); + } + else + { + return (((uint32_t)high1 << 16) | low); + } +} + +/********************************************************************* + * @fn RTC_SetCounter + * + * @brief Sets the RTC counter value. + * + * @param CounterValue - RTC counter new value. + * + * @return RTC counter value + */ +void RTC_SetCounter(uint32_t CounterValue) +{ + RTC_EnterConfigMode(); + RTC->CNTH = CounterValue >> 16; + RTC->CNTL = (CounterValue & RTC_LSB_MASK); + RTC_ExitConfigMode(); +} + +/********************************************************************* + * @fn RTC_SetPrescaler + * + * @brief Sets the RTC prescaler value + * + * @param PrescalerValue - RTC prescaler new value + * + * @return none + */ +void RTC_SetPrescaler(uint32_t PrescalerValue) +{ + RTC_EnterConfigMode(); + RTC->PSCRH = (PrescalerValue & PRLH_MSB_MASK) >> 16; + RTC->PSCRL = (PrescalerValue & RTC_LSB_MASK); + RTC_ExitConfigMode(); +} + +/********************************************************************* + * @fn RTC_SetAlarm + * + * @brief Sets the RTC alarm value + * + * @param AlarmValue - RTC alarm new value + * + * @return none + */ +void RTC_SetAlarm(uint32_t AlarmValue) +{ + RTC_EnterConfigMode(); + RTC->ALRMH = AlarmValue >> 16; + RTC->ALRML = (AlarmValue & RTC_LSB_MASK); + RTC_ExitConfigMode(); +} + +/********************************************************************* + * @fn RTC_GetDivider + * + * @brief Gets the RTC divider value + * + * @return RTC Divider value + */ +uint32_t RTC_GetDivider(void) +{ + uint32_t tmp = 0x00; + tmp = ((uint32_t)RTC->DIVH & (uint32_t)0x000F) << 16; + tmp |= RTC->DIVL; + return tmp; +} + +/********************************************************************* + * @fn RTC_WaitForLastTask + * + * @brief Waits until last write operation on RTC registers has finished + * Note- + * This function must be called before any write to RTC registers. + * @return none + */ +void RTC_WaitForLastTask(void) +{ + while((RTC->CTLRL & RTC_FLAG_RTOFF) == (uint16_t)RESET) + { + } +} + +/********************************************************************* + * @fn RTC_WaitForSynchro + * + * @brief Waits until the RTC registers are synchronized with RTC PB clock + * Note- + * This function must be called before any read operation after an PB reset + * or an PB clock stop. + * + * @return none + */ +void RTC_WaitForSynchro(void) +{ + RTC->CTLRL &= (uint16_t)~RTC_FLAG_RSF; + while((RTC->CTLRL & RTC_FLAG_RSF) == (uint16_t)RESET) + { + } +} + +/********************************************************************* + * @fn RTC_GetFlagStatus + * + * @brief Checks whether the specified RTC flag is set or not + * + * @param RTC_FLAG- specifies the flag to check + * RTC_FLAG_RTOFF - RTC Operation OFF flag + * RTC_FLAG_RSF - Registers Synchronized flag + * RTC_FLAG_OW - Overflow flag + * RTC_FLAG_ALR - Alarm flag + * RTC_FLAG_SEC - Second flag + * + * @return The new state of RTC_FLAG (SET or RESET) + */ +FlagStatus RTC_GetFlagStatus(uint16_t RTC_FLAG) +{ + FlagStatus bitstatus = RESET; + if((RTC->CTLRL & RTC_FLAG) != (uint16_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/********************************************************************* + * @fn RTC_ClearFlag + * + * @brief Clears the RTC's pending flags + * + * @param RTC_FLAG - specifies the flag to clear + * RTC_FLAG_RSF - Registers Synchronized flag + * RTC_FLAG_OW - Overflow flag + * RTC_FLAG_ALR - Alarm flag + * RTC_FLAG_SEC - Second flag + * + * @return none + */ +void RTC_ClearFlag(uint16_t RTC_FLAG) +{ + RTC->CTLRL &= (uint16_t)~RTC_FLAG; +} + +/********************************************************************* + * @fn RTC_GetITStatus + * + * @brief Checks whether the specified RTC interrupt has occurred or not + * + * @param RTC_IT - specifies the RTC interrupts sources to check + * RTC_FLAG_OW - Overflow interrupt + * RTC_FLAG_ALR - Alarm interrupt + * RTC_FLAG_SEC - Second interrupt + * + * @return The new state of the RTC_IT (SET or RESET) + */ +ITStatus RTC_GetITStatus(uint16_t RTC_IT) +{ + ITStatus bitstatus = RESET; + + bitstatus = (ITStatus)(RTC->CTLRL & RTC_IT); + if(((RTC->CTLRH & RTC_IT) != (uint16_t)RESET) && (bitstatus != (uint16_t)RESET)) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/********************************************************************* + * @fn RTC_ClearITPendingBit + * + * @brief Clears the RTC's interrupt pending bits + * + * @param RTC_IT - specifies the interrupt pending bit to clear + * RTC_FLAG_OW - Overflow interrupt + * RTC_FLAG_ALR - Alarm interrupt + * RTC_FLAG_SEC - Second interrupt + * + * @return none + */ +void RTC_ClearITPendingBit(uint16_t RTC_IT) +{ + RTC->CTLRL &= (uint16_t)~RTC_IT; +} + + diff --git a/ZDBMS/BMS_CC/Peripheral/src/ch32l103_spi.c b/ZDBMS/BMS_CC/Peripheral/src/ch32l103_spi.c new file mode 100644 index 0000000..9197c02 --- /dev/null +++ b/ZDBMS/BMS_CC/Peripheral/src/ch32l103_spi.c @@ -0,0 +1,536 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32l103_spi.c + * Author : WCH + * Version : V1.0.0 + * Date : 2024/06/05 + * Description : This file provides all the SPI firmware functions. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#include "ch32l103_spi.h" +#include "ch32l103_rcc.h" + +/* SPI SPE mask */ +#define CTLR1_SPE_Set ((uint16_t)0x0040) +#define CTLR1_SPE_Reset ((uint16_t)0xFFBF) + +/* SPI CRCNext mask */ +#define CTLR1_CRCNext_Set ((uint16_t)0x1000) + +/* SPI CRCEN mask */ +#define CTLR1_CRCEN_Set ((uint16_t)0x2000) +#define CTLR1_CRCEN_Reset ((uint16_t)0xDFFF) + +/* SPI SSOE mask */ +#define CTLR2_SSOE_Set ((uint16_t)0x0004) +#define CTLR2_SSOE_Reset ((uint16_t)0xFFFB) + +/* SPI registers Masks */ +#define CTLR1_CLEAR_Mask ((uint16_t)0x3040) +#define I2SCFGR_CLEAR_Mask ((uint16_t)0xF040) + +/********************************************************************* + * @fn SPI_I2S_DeInit + * + * @brief Deinitializes the SPIx peripheral registers to their default + * reset values. + * + * @param SPIx - where x can be 1 or 2 to select the SPI peripheral. + * + * @return none + */ +void SPI_I2S_DeInit(SPI_TypeDef *SPIx) +{ + if(SPIx == SPI1) + { + RCC_PB2PeriphResetCmd(RCC_PB2Periph_SPI1, ENABLE); + RCC_PB2PeriphResetCmd(RCC_PB2Periph_SPI1, DISABLE); + } + else if(SPIx == SPI2) + { + RCC_PB1PeriphResetCmd(RCC_PB1Periph_SPI2, ENABLE); + RCC_PB1PeriphResetCmd(RCC_PB1Periph_SPI2, DISABLE); + } +} + +/********************************************************************* + * @fn SPI_Init + * + * @brief Initializes the SPIx peripheral according to the specified + * parameters in the SPI_InitStruct. + * When using SPI slave mode to send data, the CPOL bit should be set to 1. + * + * @param SPIx - where x can be 1 or 2 to select the SPI peripheral. + * SPI_InitStruct - pointer to a SPI_InitTypeDef structure that + * contains the configuration information for the specified SPI peripheral. + * + * @return none + */ +void SPI_Init(SPI_TypeDef *SPIx, SPI_InitTypeDef *SPI_InitStruct) +{ + uint16_t tmpreg = 0; + + tmpreg = SPIx->CTLR1; + tmpreg &= CTLR1_CLEAR_Mask; + tmpreg |= (uint16_t)((uint32_t)SPI_InitStruct->SPI_Direction | SPI_InitStruct->SPI_Mode | + SPI_InitStruct->SPI_DataSize | SPI_InitStruct->SPI_CPOL | + SPI_InitStruct->SPI_CPHA | SPI_InitStruct->SPI_NSS | + SPI_InitStruct->SPI_BaudRatePrescaler | SPI_InitStruct->SPI_FirstBit); + + SPIx->CTLR1 = tmpreg; + SPIx->CRCR = SPI_InitStruct->SPI_CRCPolynomial; +} + +/********************************************************************* + * @fn SPI_StructInit + * + * @brief Fills each SPI_InitStruct member with its default value. + * + * @param SPI_InitStruct - pointer to a SPI_InitTypeDef structure which + * will be initialized. + * + * @return none + */ +void SPI_StructInit(SPI_InitTypeDef *SPI_InitStruct) +{ + SPI_InitStruct->SPI_Direction = SPI_Direction_2Lines_FullDuplex; + SPI_InitStruct->SPI_Mode = SPI_Mode_Slave; + SPI_InitStruct->SPI_DataSize = SPI_DataSize_8b; + SPI_InitStruct->SPI_CPOL = SPI_CPOL_Low; + SPI_InitStruct->SPI_CPHA = SPI_CPHA_1Edge; + SPI_InitStruct->SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_2; + SPI_InitStruct->SPI_FirstBit = SPI_FirstBit_MSB; + SPI_InitStruct->SPI_CRCPolynomial = 7; +} + +/********************************************************************* + * @fn SPI_Cmd + * + * @brief Enables or disables the specified SPI peripheral. + * + * @param SPIx - where x can be 1 or 2 to select the SPI peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void SPI_Cmd(SPI_TypeDef *SPIx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + SPIx->CTLR1 |= CTLR1_SPE_Set; + } + else + { + SPIx->CTLR1 &= CTLR1_SPE_Reset; + } +} + +/********************************************************************* + * @fn SPI_I2S_ITConfig + * + * @brief Enables or disables the specified SPI interrupts. + * + * @param SPIx - where x can be + * - 1 or 2 in SPI mode. + * SPI_I2S_IT - specifies the SPI/I2S interrupt source to be + * enabled or disabled. + * SPI_I2S_IT_TXE - Tx buffer empty interrupt mask. + * SPI_I2S_IT_RXNE - Rx buffer not empty interrupt mask. + * SPI_I2S_IT_ERR - Error interrupt mask. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void SPI_I2S_ITConfig(SPI_TypeDef *SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState) +{ + uint16_t itpos = 0, itmask = 0; + + itpos = SPI_I2S_IT >> 4; + itmask = (uint16_t)1 << (uint16_t)itpos; + + if(NewState != DISABLE) + { + SPIx->CTLR2 |= itmask; + } + else + { + SPIx->CTLR2 &= (uint16_t)~itmask; + } +} + +/********************************************************************* + * @fn SPI_I2S_DMACmd + * + * @brief Enables or disables the SPIx DMA interface. + * + * @param SPIx - where x can be + * - 1 or 2 in SPI mode. + * SPI_I2S_DMAReq - specifies the SPI DMA transfer request to + * be enabled or disabled. + * SPI_I2S_DMAReq_Tx - Tx buffer DMA transfer request. + * SPI_I2S_DMAReq_Rx - Rx buffer DMA transfer request. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void SPI_I2S_DMACmd(SPI_TypeDef *SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + SPIx->CTLR2 |= SPI_I2S_DMAReq; + } + else + { + SPIx->CTLR2 &= (uint16_t)~SPI_I2S_DMAReq; + } +} + +/********************************************************************* + * @fn SPI_I2S_SendData + * + * @brief Transmits a Data through the SPIx peripheral. + * + * @param SPIx - where x can be + * - 1 or 2 in SPI mode. + * Data - Data to be transmitted. + * + * @return none + */ +void SPI_I2S_SendData(SPI_TypeDef *SPIx, uint16_t Data) +{ + SPIx->DATAR = Data; +} + +/********************************************************************* + * @fn SPI_I2S_ReceiveData + * + * @brief Returns the most recent received data by the SPIx peripheral. + * + * @param SPIx - where x can be + * - 1 or 2 in SPI mode. + * Data - Data to be transmitted. + * + * @return SPIx->DATAR - The value of the received data. + */ +uint16_t SPI_I2S_ReceiveData(SPI_TypeDef *SPIx) +{ + return SPIx->DATAR; +} + +/********************************************************************* + * @fn SPI_NSSInternalSoftwareConfig + * + * @brief Configures internally by software the NSS pin for the selected SPI. + * + * @param SPIx - where x can be 1 or 2 to select the SPI peripheral. + * SPI_NSSInternalSoft - + * SPI_NSSInternalSoft_Set - Set NSS pin internally. + * SPI_NSSInternalSoft_Reset - Reset NSS pin internally. + * + * @return none + */ +void SPI_NSSInternalSoftwareConfig(SPI_TypeDef *SPIx, uint16_t SPI_NSSInternalSoft) +{ + if(SPI_NSSInternalSoft != SPI_NSSInternalSoft_Reset) + { + SPIx->CTLR1 |= SPI_NSSInternalSoft_Set; + } + else + { + SPIx->CTLR1 &= SPI_NSSInternalSoft_Reset; + } +} + +/********************************************************************* + * @fn SPI_SSOutputCmd + * + * @brief Enables or disables the SS output for the selected SPI. + * + * @param SPIx - where x can be 1 or 2 to select the SPI peripheral. + * NewState - new state of the SPIx SS output. + * + * @return none + */ +void SPI_SSOutputCmd(SPI_TypeDef *SPIx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + SPIx->CTLR2 |= CTLR2_SSOE_Set; + } + else + { + SPIx->CTLR2 &= CTLR2_SSOE_Reset; + } +} + +/********************************************************************* + * @fn SPI_DataSizeConfig + * + * @brief Configures the data size for the selected SPI. + * + * @param SPIx - where x can be 1 or 2 to select the SPI peripheral. + * SPI_DataSize - specifies the SPI data size. + * SPI_DataSize_16b - Set data frame format to 16bit. + * SPI_DataSize_8b - Set data frame format to 8bit. + * + * @return none + */ +void SPI_DataSizeConfig(SPI_TypeDef *SPIx, uint16_t SPI_DataSize) +{ + SPIx->CTLR1 &= (uint16_t)~SPI_DataSize_16b; + SPIx->CTLR1 |= SPI_DataSize; +} + +/********************************************************************* + * @fn SPI_TransmitCRC + * + * @brief Transmit the SPIx CRC value. + * + * @param SPIx - where x can be 1 or 2 to select the SPI peripheral. + * + * @return none + */ +void SPI_TransmitCRC(SPI_TypeDef *SPIx) +{ + SPIx->CTLR1 |= CTLR1_CRCNext_Set; +} + +/********************************************************************* + * @fn SPI_CalculateCRC + * + * @brief Enables or disables the CRC value calculation of the transferred bytes. + * + * @param SPIx - where x can be 1 or 2 to select the SPI peripheral. + * NewState - new state of the SPIx CRC value calculation. + * + * @return none + */ +void SPI_CalculateCRC(SPI_TypeDef *SPIx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + SPIx->CTLR1 |= CTLR1_CRCEN_Set; + } + else + { + SPIx->CTLR1 &= CTLR1_CRCEN_Reset; + } +} + +/********************************************************************* + * @fn SPI_GetCRC + * + * @brief Returns the transmit or the receive CRC register value for the specified SPI. + * + * @param SPIx - where x can be 1 or 2 to select the SPI peripheral. + * SPI_CRC - specifies the CRC register to be read. + * SPI_CRC_Tx - Selects Tx CRC register. + * SPI_CRC_Rx - Selects Rx CRC register. + * + * @return crcreg - The selected CRC register value. + */ +uint16_t SPI_GetCRC(SPI_TypeDef *SPIx, uint8_t SPI_CRC) +{ + uint16_t crcreg = 0; + + if(SPI_CRC != SPI_CRC_Rx) + { + crcreg = SPIx->TCRCR; + } + else + { + crcreg = SPIx->RCRCR; + } + + return crcreg; +} + +/********************************************************************* + * @fn SPI_GetCRCPolynomial + * + * @brief Returns the CRC Polynomial register value for the specified SPI. + * + * @param SPIx - where x can be 1 or 2 to select the SPI peripheral. + * + * @return SPIx->CRCR - The CRC Polynomial register value. + */ +uint16_t SPI_GetCRCPolynomial(SPI_TypeDef *SPIx) +{ + return SPIx->CRCR; +} + +/********************************************************************* + * @fn SPI_BiDirectionalLineConfig + * + * @brief Selects the data transfer direction in bi-directional mode + * for the specified SPI. + * + * @param SPIx - where x can be 1 or 2 to select the SPI peripheral. + * SPI_Direction - specifies the data transfer direction in + * bi-directional mode. + * SPI_Direction_Tx - Selects Tx transmission direction. + * SPI_Direction_Rx - Selects Rx receive direction. + * + * @return none + */ +void SPI_BiDirectionalLineConfig(SPI_TypeDef *SPIx, uint16_t SPI_Direction) +{ + if(SPI_Direction == SPI_Direction_Tx) + { + SPIx->CTLR1 |= SPI_Direction_Tx; + } + else + { + SPIx->CTLR1 &= SPI_Direction_Rx; + } +} + +/********************************************************************* + * @fn SPI_I2S_GetFlagStatus + * + * @brief Checks whether the specified SPI flag is set or not. + * + * @param SPIx - where x can be + * - 1 or 2 in SPI mode. + * SPI_I2S_FLAG - specifies the SPI flag to check. + * SPI_I2S_FLAG_TXE - Transmit buffer empty flag. + * SPI_I2S_FLAG_RXNE - Receive buffer not empty flag. + * SPI_I2S_FLAG_BSY - Busy flag. + * SPI_I2S_FLAG_OVR - Overrun flag. + * SPI_FLAG_MODF - Mode Fault flag. + * SPI_FLAG_CRCERR - CRC Error flag. + * + * @return FlagStatus - SET or RESET. + */ +FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef *SPIx, uint16_t SPI_I2S_FLAG) +{ + FlagStatus bitstatus = RESET; + + if((SPIx->STATR & SPI_I2S_FLAG) != (uint16_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn SPI_I2S_ClearFlag + * + * @brief Clears the SPIx CRC Error (CRCERR) flag. + * + * @param SPIx - where x can be + * - 1 or 2 in SPI mode. + * SPI_I2S_FLAG - specifies the SPI flag to clear. + * SPI_FLAG_CRCERR - CRC Error flag. + * Note- + * - OVR (OverRun error) flag is cleared by software sequence - a read + * operation to SPI_DATAR register (SPI_I2S_ReceiveData()) followed by a read + * operation to SPI_STATR register (SPI_I2S_GetFlagStatus()). + * - MODF (Mode Fault) flag is cleared by software sequence - a read/write + * operation to SPI_STATR register (SPI_I2S_GetFlagStatus()) followed by a + * write operation to SPI_CTLR1 register (SPI_Cmd() to enable the SPI). + * @return FlagStatus - SET or RESET. + */ +void SPI_I2S_ClearFlag(SPI_TypeDef *SPIx, uint16_t SPI_I2S_FLAG) +{ + SPIx->STATR = (uint16_t)~SPI_I2S_FLAG; +} + +/********************************************************************* + * @fn SPI_I2S_GetITStatus + * + * @brief Checks whether the specified SPI interrupt has occurred or not. + * + * @param SPIx - where x can be + * - 1 or 2 in SPI mode. + * SPI_I2S_IT - specifies the SPI interrupt source to check.. + * SPI_I2S_IT_TXE - Transmit buffer empty interrupt. + * SPI_I2S_IT_RXNE - Receive buffer not empty interrupt. + * SPI_I2S_IT_OVR - Overrun interrupt. + * SPI_IT_MODF - Mode Fault interrupt. + * SPI_IT_CRCERR - CRC Error interrupt. + * + * @return FlagStatus - SET or RESET. + */ +ITStatus SPI_I2S_GetITStatus(SPI_TypeDef *SPIx, uint8_t SPI_I2S_IT) +{ + ITStatus bitstatus = RESET; + uint16_t itpos = 0, itmask = 0, enablestatus = 0; + + itpos = 0x01 << (SPI_I2S_IT & 0x0F); + itmask = SPI_I2S_IT >> 4; + itmask = 0x01 << itmask; + enablestatus = (SPIx->CTLR2 & itmask); + + if(((SPIx->STATR & itpos) != (uint16_t)RESET) && enablestatus) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn SPI_I2S_ClearITPendingBit + * + * @brief Clears the SPIx CRC Error (CRCERR) interrupt pending bit. + * + * @param SPIx - where x can be + * - 1 or 2 in SPI mode. + * SPI_I2S_IT - specifies the SPI interrupt pending bit to clear. + * SPI_IT_CRCERR - CRC Error interrupt. + * Note- + * - OVR (OverRun Error) interrupt pending bit is cleared by software + * sequence - a read operation to SPI_DATAR register (SPI_I2S_ReceiveData()) + * followed by a read operation to SPI_STATR register (SPI_I2S_GetITStatus()). + * - MODF (Mode Fault) interrupt pending bit is cleared by software sequence: + * a read/write operation to SPI_STATR register (SPI_I2S_GetITStatus()) + * followed by a write operation to SPI_CTLR1 register (SPI_Cmd() to enable + * the SPI). + * + * @return none + */ +void SPI_I2S_ClearITPendingBit(SPI_TypeDef *SPIx, uint8_t SPI_I2S_IT) +{ + uint16_t itpos = 0; + + itpos = 0x01 << (SPI_I2S_IT & 0x0F); + SPIx->STATR = (uint16_t)~itpos; +} + +/********************************************************************* + * @fn SPI_HighSpeedRead_Cmd + * + * @brief Enables or disables the SPI high speed read mode. + * Note - + * Read enable in SPI high-speed mode (CLK is more than + * or equal to 36MHz). This mode is valid only when clock + * is divided by 2 (BR in CTLR1 = 000). + * + * @param SPIx - where x can be 1 or 2 to select the SPI peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void SPI_HighSpeedRead_Cmd(SPI_TypeDef *SPIx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + SPIx->HSCR |= (1 << 0); + } + else + { + SPIx->HSCR &= ~(1 << 0); + } +} diff --git a/ZDBMS/BMS_CC/Peripheral/src/ch32l103_tim.c b/ZDBMS/BMS_CC/Peripheral/src/ch32l103_tim.c new file mode 100644 index 0000000..b16233f --- /dev/null +++ b/ZDBMS/BMS_CC/Peripheral/src/ch32l103_tim.c @@ -0,0 +1,2412 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32l103_tim.c + * Author : WCH + * Version : V1.0.0 + * Date : 2023/07/08 + * Description : This file provides all the TIM firmware functions. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#include "ch32l103_tim.h" +#include "ch32l103_rcc.h" + +/* TIM registers bit mask */ +#define SMCFGR_ETR_Mask ((uint16_t)0x00FF) +#define CHCTLR_Offset ((uint16_t)0x0018) +#define CCER_CCE_Set ((uint16_t)0x0001) +#define CCER_CCNE_Set ((uint16_t)0x0004) + +static void TI1_Config(TIM_TypeDef *TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, + uint16_t TIM_ICFilter); +static void TI2_Config(TIM_TypeDef *TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, + uint16_t TIM_ICFilter); +static void TI3_Config(TIM_TypeDef *TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, + uint16_t TIM_ICFilter); +static void TI4_Config(TIM_TypeDef *TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, + uint16_t TIM_ICFilter); + +/********************************************************************* + * @fn TIM_DeInit + * + * @brief Deinitializes the TIMx peripheral registers to their default + * reset values. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * + * @return none + */ +void TIM_DeInit(TIM_TypeDef *TIMx) +{ + if(TIMx == TIM1) + { + RCC_PB2PeriphResetCmd(RCC_PB2Periph_TIM1, ENABLE); + RCC_PB2PeriphResetCmd(RCC_PB2Periph_TIM1, DISABLE); + } + else if(TIMx == TIM2) + { + RCC_PB1PeriphResetCmd(RCC_PB1Periph_TIM2, ENABLE); + RCC_PB1PeriphResetCmd(RCC_PB1Periph_TIM2, DISABLE); + } + else if(TIMx == TIM3) + { + RCC_PB1PeriphResetCmd(RCC_PB1Periph_TIM3, ENABLE); + RCC_PB1PeriphResetCmd(RCC_PB1Periph_TIM3, DISABLE); + } + else if(TIMx == TIM4) + { + RCC_PB1PeriphResetCmd(RCC_PB1Periph_TIM4, ENABLE); + RCC_PB1PeriphResetCmd(RCC_PB1Periph_TIM4, DISABLE); + } +} + +/********************************************************************* + * @fn TIM_TimeBaseInit + * + * @brief Initializes the TIMx Time Base Unit peripheral according to + * the specified parameters in the TIM_TimeBaseInitStruct. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_TimeBaseInitStruct - pointer to a TIM_TimeBaseInitTypeDef + * structure. + * + * @return none + */ +void TIM_TimeBaseInit(TIM_TypeDef *TIMx, TIM_TimeBaseInitTypeDef *TIM_TimeBaseInitStruct) +{ + uint16_t tmpcr1 = 0; + + tmpcr1 = TIMx->CTLR1; + + if((TIMx == TIM1) || (TIMx == TIM2) || (TIMx == TIM3) || (TIMx == TIM4)) + { + tmpcr1 &= (uint16_t)(~((uint16_t)(TIM_DIR | TIM_CMS))); + tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->TIM_CounterMode; + } + + tmpcr1 &= (uint16_t)(~((uint16_t)TIM_CTLR1_CKD)); + tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->TIM_ClockDivision; + + TIMx->CTLR1 = tmpcr1; + + if(TIMx == TIM4) TIMx->ATRLR_TIM4 = TIM_TimeBaseInitStruct->TIM_Period; + else TIMx->ATRLR = (uint16_t)TIM_TimeBaseInitStruct->TIM_Period; + + TIMx->PSC = TIM_TimeBaseInitStruct->TIM_Prescaler; + + if((TIMx == TIM1)) + { + TIMx->RPTCR = TIM_TimeBaseInitStruct->TIM_RepetitionCounter; + } + + TIMx->SWEVGR = TIM_PSCReloadMode_Immediate; +} + +/********************************************************************* + * @fn TIM_OC1Init + * + * @brief Initializes the TIMx Channel1 according to the specified + * parameters in the TIM_OCInitStruct. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_OCInitStruct - pointer to a TIM_OCInitTypeDef structure. + * + * @return none + */ +void TIM_OC1Init(TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct) +{ + uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; + + TIMx->CCER &= (uint16_t)(~(uint16_t)TIM_CC1E); + tmpccer = TIMx->CCER; + tmpcr2 = TIMx->CTLR2; + tmpccmrx = TIMx->CHCTLR1; + tmpccmrx &= (uint16_t)(~((uint16_t)TIM_OC1M)); + tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CC1S)); + tmpccmrx |= TIM_OCInitStruct->TIM_OCMode; + tmpccer &= (uint16_t)(~((uint16_t)TIM_CC1P)); + tmpccer |= TIM_OCInitStruct->TIM_OCPolarity; + tmpccer |= TIM_OCInitStruct->TIM_OutputState; + + if((TIMx == TIM1)) + { + tmpccer &= (uint16_t)(~((uint16_t)TIM_CC1NP)); + tmpccer |= TIM_OCInitStruct->TIM_OCNPolarity; + + tmpccer &= (uint16_t)(~((uint16_t)TIM_CC1NE)); + tmpccer |= TIM_OCInitStruct->TIM_OutputNState; + + tmpcr2 &= (uint16_t)(~((uint16_t)TIM_OIS1)); + tmpcr2 &= (uint16_t)(~((uint16_t)TIM_OIS1N)); + + tmpcr2 |= TIM_OCInitStruct->TIM_OCIdleState; + tmpcr2 |= TIM_OCInitStruct->TIM_OCNIdleState; + } + + TIMx->CTLR2 = tmpcr2; + TIMx->CHCTLR1 = tmpccmrx; + if(TIMx == TIM4) TIMx->CH1CVR_TIM4 = TIM_OCInitStruct->TIM_Pulse; + else TIMx->CH1CVR = (uint16_t)TIM_OCInitStruct->TIM_Pulse; + TIMx->CCER = tmpccer; +} + +/********************************************************************* + * @fn TIM_OC2Init + * + * @brief Initializes the TIMx Channel2 according to the specified + * parameters in the TIM_OCInitStruct. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_OCInitStruct - pointer to a TIM_OCInitTypeDef structure. + * + * @return none + */ +void TIM_OC2Init(TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct) +{ + uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; + + TIMx->CCER &= (uint16_t)(~((uint16_t)TIM_CC2E)); + tmpccer = TIMx->CCER; + tmpcr2 = TIMx->CTLR2; + tmpccmrx = TIMx->CHCTLR1; + tmpccmrx &= (uint16_t)(~((uint16_t)TIM_OC2M)); + tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CC2S)); + tmpccmrx |= (uint16_t)(TIM_OCInitStruct->TIM_OCMode << 8); + tmpccer &= (uint16_t)(~((uint16_t)TIM_CC2P)); + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 4); + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 4); + + if((TIMx == TIM1)) + { + tmpccer &= (uint16_t)(~((uint16_t)TIM_CC2NP)); + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCNPolarity << 4); + tmpccer &= (uint16_t)(~((uint16_t)TIM_CC2NE)); + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputNState << 4); + + tmpcr2 &= (uint16_t)(~((uint16_t)TIM_OIS2)); + tmpcr2 &= (uint16_t)(~((uint16_t)TIM_OIS2N)); + tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 2); + tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCNIdleState << 2); + } + + TIMx->CTLR2 = tmpcr2; + TIMx->CHCTLR1 = tmpccmrx; + if(TIMx == TIM4) TIMx->CH2CVR_TIM4 = TIM_OCInitStruct->TIM_Pulse; + else TIMx->CH2CVR = (uint16_t)TIM_OCInitStruct->TIM_Pulse; + TIMx->CCER = tmpccer; +} + +/********************************************************************* + * @fn TIM_OC3Init + * + * @brief Initializes the TIMx Channel3 according to the specified + * parameters in the TIM_OCInitStruct. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_OCInitStruct - pointer to a TIM_OCInitTypeDef structure. + * + * @return none + */ +void TIM_OC3Init(TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct) +{ + uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; + + TIMx->CCER &= (uint16_t)(~((uint16_t)TIM_CC3E)); + tmpccer = TIMx->CCER; + tmpcr2 = TIMx->CTLR2; + tmpccmrx = TIMx->CHCTLR2; + tmpccmrx &= (uint16_t)(~((uint16_t)TIM_OC3M)); + tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CC3S)); + tmpccmrx |= TIM_OCInitStruct->TIM_OCMode; + tmpccer &= (uint16_t)(~((uint16_t)TIM_CC3P)); + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 8); + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 8); + + if((TIMx == TIM1)) + { + tmpccer &= (uint16_t)(~((uint16_t)TIM_CC3NP)); + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCNPolarity << 8); + tmpccer &= (uint16_t)(~((uint16_t)TIM_CC3NE)); + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputNState << 8); + tmpcr2 &= (uint16_t)(~((uint16_t)TIM_OIS3)); + tmpcr2 &= (uint16_t)(~((uint16_t)TIM_OIS3N)); + tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 4); + tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCNIdleState << 4); + } + + TIMx->CTLR2 = tmpcr2; + TIMx->CHCTLR2 = tmpccmrx; + if(TIMx == TIM4) TIMx->CH3CVR_TIM4 = TIM_OCInitStruct->TIM_Pulse; + else TIMx->CH3CVR = (uint16_t)TIM_OCInitStruct->TIM_Pulse; + TIMx->CCER = tmpccer; +} + +/********************************************************************* + * @fn TIM_OC4Init + * + * @brief Initializes the TIMx Channel4 according to the specified + * parameters in the TIM_OCInitStruct. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_OCInitStruct - pointer to a TIM_OCInitTypeDef structure. + * + * @return none + */ +void TIM_OC4Init(TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct) +{ + uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; + + TIMx->CCER &= (uint16_t)(~((uint16_t)TIM_CC4E)); + tmpccer = TIMx->CCER; + tmpcr2 = TIMx->CTLR2; + tmpccmrx = TIMx->CHCTLR2; + tmpccmrx &= (uint16_t)(~((uint16_t)TIM_OC4M)); + tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CC4S)); + tmpccmrx |= (uint16_t)(TIM_OCInitStruct->TIM_OCMode << 8); + tmpccer &= (uint16_t)(~((uint16_t)TIM_CC4P)); + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 12); + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 12); + + if((TIMx == TIM1)) + { + tmpcr2 &= (uint16_t)(~((uint16_t)TIM_OIS4)); + tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 6); + } + + TIMx->CTLR2 = tmpcr2; + TIMx->CHCTLR2 = tmpccmrx; + if(TIMx == TIM4) TIMx->CH4CVR_TIM4 = TIM_OCInitStruct->TIM_Pulse; + else TIMx->CH4CVR = (uint16_t)TIM_OCInitStruct->TIM_Pulse; + TIMx->CCER = tmpccer; +} + +/********************************************************************* + * @fn TIM_ICInit + * + * @brief IInitializes the TIM peripheral according to the specified + * parameters in the TIM_ICInitStruct. + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_ICInitStruct - pointer to a TIM_ICInitTypeDef structure. + * + * @return none + */ +void TIM_ICInit(TIM_TypeDef *TIMx, TIM_ICInitTypeDef *TIM_ICInitStruct) +{ + if(TIM_ICInitStruct->TIM_Channel == TIM_Channel_1) + { + TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, + TIM_ICInitStruct->TIM_ICSelection, + TIM_ICInitStruct->TIM_ICFilter); + TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + } + else if(TIM_ICInitStruct->TIM_Channel == TIM_Channel_2) + { + TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, + TIM_ICInitStruct->TIM_ICSelection, + TIM_ICInitStruct->TIM_ICFilter); + TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + } + else if(TIM_ICInitStruct->TIM_Channel == TIM_Channel_3) + { + TI3_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, + TIM_ICInitStruct->TIM_ICSelection, + TIM_ICInitStruct->TIM_ICFilter); + TIM_SetIC3Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + } + else + { + TI4_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, + TIM_ICInitStruct->TIM_ICSelection, + TIM_ICInitStruct->TIM_ICFilter); + TIM_SetIC4Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + } +} + +/********************************************************************* + * @fn TIM_PWMIConfig + * + * @brief Configures the TIM peripheral according to the specified + * parameters in the TIM_ICInitStruct to measure an external + * PWM signal. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_ICInitStruct - pointer to a TIM_ICInitTypeDef structure. + * + * @return none + */ +void TIM_PWMIConfig(TIM_TypeDef *TIMx, TIM_ICInitTypeDef *TIM_ICInitStruct) +{ + uint16_t icoppositepolarity = TIM_ICPolarity_Rising; + uint16_t icoppositeselection = TIM_ICSelection_DirectTI; + + if(TIM_ICInitStruct->TIM_ICPolarity == TIM_ICPolarity_Rising) + { + icoppositepolarity = TIM_ICPolarity_Falling; + } + else + { + icoppositepolarity = TIM_ICPolarity_Rising; + } + + if(TIM_ICInitStruct->TIM_ICSelection == TIM_ICSelection_DirectTI) + { + icoppositeselection = TIM_ICSelection_IndirectTI; + } + else + { + icoppositeselection = TIM_ICSelection_DirectTI; + } + + if(TIM_ICInitStruct->TIM_Channel == TIM_Channel_1) + { + TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection, + TIM_ICInitStruct->TIM_ICFilter); + TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + TI2_Config(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter); + TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + } + else + { + TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection, + TIM_ICInitStruct->TIM_ICFilter); + TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + TI1_Config(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter); + TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + } +} + +/********************************************************************* + * @fn TIM_BDTRConfig + * + * @brief Configures the: Break feature, dead time, Lock level, the OSSI, + * the OSSR State and the AOE(automatic output enable). + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_BDTRInitStruct - pointer to a TIM_BDTRInitTypeDef structure. + * + * @return none + */ +void TIM_BDTRConfig(TIM_TypeDef *TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct) +{ + TIMx->BDTR = (uint32_t)TIM_BDTRInitStruct->TIM_OSSRState | TIM_BDTRInitStruct->TIM_OSSIState | + TIM_BDTRInitStruct->TIM_LOCKLevel | TIM_BDTRInitStruct->TIM_DeadTime | + TIM_BDTRInitStruct->TIM_Break | TIM_BDTRInitStruct->TIM_BreakPolarity | + TIM_BDTRInitStruct->TIM_AutomaticOutput; +} + +/********************************************************************* + * @fn TIM_TimeBaseStructInit + * + * @brief Fills each TIM_TimeBaseInitStruct member with its default value. + * + * @param TIM_TimeBaseInitStruct - pointer to a TIM_TimeBaseInitTypeDef structure. + * + * @return none + */ +void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef *TIM_TimeBaseInitStruct) +{ + TIM_TimeBaseInitStruct->TIM_Period = 0xFFFF; + TIM_TimeBaseInitStruct->TIM_Prescaler = 0x0000; + TIM_TimeBaseInitStruct->TIM_ClockDivision = TIM_CKD_DIV1; + TIM_TimeBaseInitStruct->TIM_CounterMode = TIM_CounterMode_Up; + TIM_TimeBaseInitStruct->TIM_RepetitionCounter = 0x0000; +} + +/********************************************************************* + * @fn TIM_OCStructInit + * + * @brief Fills each TIM_OCInitStruct member with its default value. + * + * @param TIM_OCInitStruct - pointer to a TIM_OCInitTypeDef structure. + * + * @return none + */ +void TIM_OCStructInit(TIM_OCInitTypeDef *TIM_OCInitStruct) +{ + TIM_OCInitStruct->TIM_OCMode = TIM_OCMode_Timing; + TIM_OCInitStruct->TIM_OutputState = TIM_OutputState_Disable; + TIM_OCInitStruct->TIM_OutputNState = TIM_OutputNState_Disable; + TIM_OCInitStruct->TIM_Pulse = 0x0000; + TIM_OCInitStruct->TIM_OCPolarity = TIM_OCPolarity_High; + TIM_OCInitStruct->TIM_OCNPolarity = TIM_OCPolarity_High; + TIM_OCInitStruct->TIM_OCIdleState = TIM_OCIdleState_Reset; + TIM_OCInitStruct->TIM_OCNIdleState = TIM_OCNIdleState_Reset; +} + +/********************************************************************* + * @fn TIM_ICStructInit + * + * @brief Fills each TIM_ICInitStruct member with its default value. + * + * @param TIM_ICInitStruct - pointer to a TIM_ICInitTypeDef structure. + * + * @return none + */ +void TIM_ICStructInit(TIM_ICInitTypeDef *TIM_ICInitStruct) +{ + TIM_ICInitStruct->TIM_Channel = TIM_Channel_1; + TIM_ICInitStruct->TIM_ICPolarity = TIM_ICPolarity_Rising; + TIM_ICInitStruct->TIM_ICSelection = TIM_ICSelection_DirectTI; + TIM_ICInitStruct->TIM_ICPrescaler = TIM_ICPSC_DIV1; + TIM_ICInitStruct->TIM_ICFilter = 0x00; +} + +/********************************************************************* + * @fn TIM_BDTRStructInit + * + * @brief Fills each TIM_BDTRInitStruct member with its default value. + * + * @param TIM_BDTRInitStruct - pointer to a TIM_BDTRInitTypeDef structure. + * + * @return none + */ +void TIM_BDTRStructInit(TIM_BDTRInitTypeDef *TIM_BDTRInitStruct) +{ + TIM_BDTRInitStruct->TIM_OSSRState = TIM_OSSRState_Disable; + TIM_BDTRInitStruct->TIM_OSSIState = TIM_OSSIState_Disable; + TIM_BDTRInitStruct->TIM_LOCKLevel = TIM_LOCKLevel_OFF; + TIM_BDTRInitStruct->TIM_DeadTime = 0x00; + TIM_BDTRInitStruct->TIM_Break = TIM_Break_Disable; + TIM_BDTRInitStruct->TIM_BreakPolarity = TIM_BreakPolarity_Low; + TIM_BDTRInitStruct->TIM_AutomaticOutput = TIM_AutomaticOutput_Disable; +} + +/********************************************************************* + * @fn TIM_Cmd + * + * @brief Enables or disables the specified TIM peripheral. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void TIM_Cmd(TIM_TypeDef *TIMx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + TIMx->CTLR1 |= TIM_CEN; + } + else + { + TIMx->CTLR1 &= (uint16_t)(~((uint16_t)TIM_CEN)); + } +} + +/********************************************************************* + * @fn TIM_CtrlPWMOutputs + * + * @brief Enables or disables the TIM peripheral Main Outputs. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void TIM_CtrlPWMOutputs(TIM_TypeDef *TIMx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + TIMx->BDTR |= TIM_MOE; + } + else + { + TIMx->BDTR &= (uint16_t)(~((uint16_t)TIM_MOE)); + } +} + +/********************************************************************* + * @fn TIM_ITConfig + * + * @brief Enables or disables the specified TIM interrupts. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_IT - specifies the TIM interrupts sources to be enabled or disabled. + * TIM_IT_Update - TIM update Interrupt source. + * TIM_IT_CC1 - TIM Capture Compare 1 Interrupt source. + * TIM_IT_CC2 - TIM Capture Compare 2 Interrupt source + * TIM_IT_CC3 - TIM Capture Compare 3 Interrupt source. + * TIM_IT_CC4 - TIM Capture Compare 4 Interrupt source. + * TIM_IT_COM - TIM Commutation Interrupt source. + * TIM_IT_Trigger - TIM Trigger Interrupt source. + * TIM_IT_Break - TIM Break Interrupt source. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void TIM_ITConfig(TIM_TypeDef *TIMx, uint16_t TIM_IT, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + TIMx->DMAINTENR |= TIM_IT; + } + else + { + TIMx->DMAINTENR &= (uint16_t)~TIM_IT; + } +} + +/******************************************************************************* + * @fn TIM_GenerateEvent + * + * @brief Configures the TIMx event to be generate by software. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_EventSource - specifies the event source. + * TIM_EventSource_Update - Timer update Event source. + * TIM_EventSource_CC1 - Timer Capture Compare 1 Event source. + * TIM_EventSource_CC2 - Timer Capture Compare 2 Event source. + * TIM_EventSource_CC3 - Timer Capture Compare 3 Event source. + * TIM_EventSource_CC4 - Timer Capture Compare 4 Event source. + * TIM_EventSource_COM - Timer COM event source. + * TIM_EventSource_Trigger - Timer Trigger Event source. + * TIM_EventSource_Break - Timer Break event source. + * + * @return None + */ +void TIM_GenerateEvent(TIM_TypeDef *TIMx, uint16_t TIM_EventSource) +{ + TIMx->SWEVGR = TIM_EventSource; +} + +/********************************************************************* + * @fn TIM_DMAConfig + * + * @brief Configures the TIMx's DMA interface. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_DMABase - DMA Base address. + * TIM_DMABase_CR. + * TIM_DMABase_CR2. + * TIM_DMABase_SMCR. + * TIM_DMABase_DIER. + * TIM1_DMABase_SR. + * TIM_DMABase_EGR. + * TIM_DMABase_CCMR1. + * TIM_DMABase_CCMR2. + * TIM_DMABase_CCER. + * TIM_DMABase_CNT. + * TIM_DMABase_PSC. + * TIM_DMABase_CCR1. + * TIM_DMABase_CCR2. + * TIM_DMABase_CCR3. + * TIM_DMABase_CCR4. + * TIM_DMABase_BDTR. + * TIM_DMABase_DCR. + * TIM_DMABurstLength - DMA Burst length. + * TIM_DMABurstLength_1Transfer. + * TIM_DMABurstLength_18Transfers. + * + * @return none + */ +void TIM_DMAConfig(TIM_TypeDef *TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength) +{ + TIMx->DMACFGR = TIM_DMABase | TIM_DMABurstLength; +} + +/********************************************************************* + * @fn TIM_DMACmd + * + * @brief Enables or disables the TIMx's DMA Requests. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_DMASource - specifies the DMA Request sources. + * TIM_DMA_Update - TIM update Interrupt source. + * TIM_DMA_CC1 - TIM Capture Compare 1 DMA source. + * TIM_DMA_CC2 - TIM Capture Compare 2 DMA source. + * TIM_DMA_CC3 - TIM Capture Compare 3 DMA source. + * TIM_DMA_CC4 - TIM Capture Compare 4 DMA source. + * TIM_DMA_COM - TIM Commutation DMA source. + * TIM_DMA_Trigger - TIM Trigger DMA source. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void TIM_DMACmd(TIM_TypeDef *TIMx, uint16_t TIM_DMASource, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + TIMx->DMAINTENR |= TIM_DMASource; + } + else + { + TIMx->DMAINTENR &= (uint16_t)~TIM_DMASource; + } +} + +/********************************************************************* + * @fn TIM_InternalClockConfig + * + * @brief Configures the TIMx internal Clock. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * + * @return none + */ +void TIM_InternalClockConfig(TIM_TypeDef *TIMx) +{ + TIMx->SMCFGR &= (uint16_t)(~((uint16_t)TIM_SMS)); +} + +/********************************************************************* + * @fn TIM_ITRxExternalClockConfig + * + * @brief Configures the TIMx Internal Trigger as External Clock. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_InputTriggerSource: Trigger source. + * TIM_TS_ITR0 - Internal Trigger 0. + * TIM_TS_ITR1 - Internal Trigger 1. + * TIM_TS_ITR2 - Internal Trigger 2. + * TIM_TS_ITR3 - Internal Trigger 3. + * + * @return none + */ +void TIM_ITRxExternalClockConfig(TIM_TypeDef *TIMx, uint16_t TIM_InputTriggerSource) +{ + TIM_SelectInputTrigger(TIMx, TIM_InputTriggerSource); + TIMx->SMCFGR |= TIM_SlaveMode_External1; +} + +/********************************************************************* + * @fn TIM_TIxExternalClockConfig + * + * @brief Configures the TIMx Trigger as External Clock. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_TIxExternalCLKSource - Trigger source. + * TIM_TIxExternalCLK1Source_TI1ED - TI1 Edge Detector. + * TIM_TIxExternalCLK1Source_TI1 - Filtered Timer Input 1. + * TIM_TIxExternalCLK1Source_TI2 - Filtered Timer Input 2. + * TIM_ICPolarity - specifies the TIx Polarity. + * TIM_ICPolarity_Rising. + * TIM_ICPolarity_Falling. + * TIM_DMA_COM - TIM Commutation DMA source. + * TIM_DMA_Trigger - TIM Trigger DMA source. + * ICFilter - specifies the filter value. + * This parameter must be a value between 0x0 and 0xF. + * + * @return none + */ +void TIM_TIxExternalClockConfig(TIM_TypeDef *TIMx, uint16_t TIM_TIxExternalCLKSource, + uint16_t TIM_ICPolarity, uint16_t ICFilter) +{ + if(TIM_TIxExternalCLKSource == TIM_TIxExternalCLK1Source_TI2) + { + TI2_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter); + } + else + { + TI1_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter); + } + + TIM_SelectInputTrigger(TIMx, TIM_TIxExternalCLKSource); + TIMx->SMCFGR |= TIM_SlaveMode_External1; +} + +/********************************************************************* + * @fn TIM_ETRClockMode1Config + * + * @brief Configures the External clock Mode1. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_ExtTRGPrescaler - The external Trigger Prescaler. + * TIM_ExtTRGPSC_OFF - ETRP Prescaler OFF. + * TIM_ExtTRGPSC_DIV2 - ETRP frequency divided by 2. + * TIM_ExtTRGPSC_DIV4 - ETRP frequency divided by 4. + * TIM_ExtTRGPSC_DIV8 - ETRP frequency divided by 8. + * TIM_ExtTRGPolarity - The external Trigger Polarity. + * TIM_ExtTRGPolarity_Inverted - active low or falling edge active. + * TIM_ExtTRGPolarity_NonInverted - active high or rising edge active. + * ExtTRGFilter - External Trigger Filter. + * This parameter must be a value between 0x0 and 0xF. + * + * @return none + */ +void TIM_ETRClockMode1Config(TIM_TypeDef *TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, + uint16_t ExtTRGFilter) +{ + uint16_t tmpsmcr = 0; + + TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter); + tmpsmcr = TIMx->SMCFGR; + tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMS)); + tmpsmcr |= TIM_SlaveMode_External1; + tmpsmcr &= (uint16_t)(~((uint16_t)TIM_TS)); + tmpsmcr |= TIM_TS_ETRF; + TIMx->SMCFGR = tmpsmcr; +} + +/********************************************************************* + * @fn TIM_ETRClockMode2Config + * + * @brief Configures the External clock Mode2. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_ExtTRGPrescaler - The external Trigger Prescaler. + * TIM_ExtTRGPSC_OFF - ETRP Prescaler OFF. + * TIM_ExtTRGPSC_DIV2 - ETRP frequency divided by 2. + * TIM_ExtTRGPSC_DIV4 - ETRP frequency divided by 4. + * TIM_ExtTRGPSC_DIV8 - ETRP frequency divided by 8. + * TIM_ExtTRGPolarity - The external Trigger Polarity. + * TIM_ExtTRGPolarity_Inverted - active low or falling edge active. + * TIM_ExtTRGPolarity_NonInverted - active high or rising edge active. + * ExtTRGFilter - External Trigger Filter. + * This parameter must be a value between 0x0 and 0xF. + * + * @return none + */ +void TIM_ETRClockMode2Config(TIM_TypeDef *TIMx, uint16_t TIM_ExtTRGPrescaler, + uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter) +{ + TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter); + TIMx->SMCFGR |= TIM_ECE; +} + +/********************************************************************* + * @fn TIM_ETRConfig + * + * @brief Configures the TIMx External Trigger (ETR). + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_ExtTRGPrescaler - The external Trigger Prescaler. + * TIM_ExtTRGPSC_OFF - ETRP Prescaler OFF. + * TIM_ExtTRGPSC_DIV2 - ETRP frequency divided by 2. + * TIM_ExtTRGPSC_DIV4 - ETRP frequency divided by 4. + * TIM_ExtTRGPSC_DIV8 - ETRP frequency divided by 8. + * TIM_ExtTRGPolarity - The external Trigger Polarity. + * TIM_ExtTRGPolarity_Inverted - active low or falling edge active. + * TIM_ExtTRGPolarity_NonInverted - active high or rising edge active. + * ExtTRGFilter - External Trigger Filter. + * This parameter must be a value between 0x0 and 0xF. + * + * @return none + */ +void TIM_ETRConfig(TIM_TypeDef *TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, + uint16_t ExtTRGFilter) +{ + uint16_t tmpsmcr = 0; + + tmpsmcr = TIMx->SMCFGR; + tmpsmcr &= SMCFGR_ETR_Mask; + tmpsmcr |= (uint16_t)(TIM_ExtTRGPrescaler | (uint16_t)(TIM_ExtTRGPolarity | (uint16_t)(ExtTRGFilter << (uint16_t)8))); + TIMx->SMCFGR = tmpsmcr; +} + +/********************************************************************* + * @fn TIM_PrescalerConfig + * + * @brief Configures the TIMx Prescaler. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * Prescaler - specifies the Prescaler Register value. + * TIM_PSCReloadMode - specifies the TIM Prescaler Reload mode. + * TIM_PSCReloadMode - specifies the TIM Prescaler Reload mode. + * TIM_PSCReloadMode_Update - The Prescaler is loaded at the update event. + * TIM_PSCReloadMode_Immediate - The Prescaler is loaded immediately. + * + * @return none + */ +void TIM_PrescalerConfig(TIM_TypeDef *TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode) +{ + TIMx->PSC = Prescaler; + TIMx->SWEVGR = TIM_PSCReloadMode; +} + +/********************************************************************* + * @fn TIM_CounterModeConfig + * + * @brief Specifies the TIMx Counter Mode to be used. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_CounterMode - specifies the Counter Mode to be used. + * TIM_CounterMode_Up - TIM Up Counting Mode. + * TIM_CounterMode_Down - TIM Down Counting Mode. + * TIM_CounterMode_CenterAligned1 - TIM Center Aligned Mode1. + * TIM_CounterMode_CenterAligned2 - TIM Center Aligned Mode2. + * TIM_CounterMode_CenterAligned3 - TIM Center Aligned Mode3. + * + * @return none + */ +void TIM_CounterModeConfig(TIM_TypeDef *TIMx, uint16_t TIM_CounterMode) +{ + uint16_t tmpcr1 = 0; + + tmpcr1 = TIMx->CTLR1; + tmpcr1 &= (uint16_t)(~((uint16_t)(TIM_DIR | TIM_CMS))); + tmpcr1 |= TIM_CounterMode; + TIMx->CTLR1 = tmpcr1; +} + +/********************************************************************* + * @fn TIM_SelectInputTrigger + * + * @brief Selects the Input Trigger source. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_InputTriggerSource - The Input Trigger source. + * TIM_TS_ITR0 - Internal Trigger 0. + * TIM_TS_ITR1 - Internal Trigger 1. + * TIM_TS_ITR2 - Internal Trigger 2. + * TIM_TS_ITR3 - Internal Trigger 3. + * TIM_TS_TI1F_ED - TI1 Edge Detector. + * TIM_TS_TI1FP1 - Filtered Timer Input 1. + * TIM_TS_TI2FP2 - Filtered Timer Input 2. + * TIM_TS_ETRF - External Trigger input. + * + * @return none + */ +void TIM_SelectInputTrigger(TIM_TypeDef *TIMx, uint16_t TIM_InputTriggerSource) +{ + uint16_t tmpsmcr = 0; + + tmpsmcr = TIMx->SMCFGR; + tmpsmcr &= (uint16_t)(~((uint16_t)TIM_TS)); + tmpsmcr |= TIM_InputTriggerSource; + TIMx->SMCFGR = tmpsmcr; +} + +/********************************************************************* + * @fn TIM_EncoderInterfaceConfig + * + * @brief Configures the TIMx Encoder Interface. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_EncoderMode - specifies the TIMx Encoder Mode. + * TIM_EncoderMode_TI1 - Counter counts on TI1FP1 edge depending + * on TI2FP2 level. + * TIM_EncoderMode_TI2 - Counter counts on TI2FP2 edge depending + * on TI1FP1 level. + * TIM_EncoderMode_TI12 - Counter counts on both TI1FP1 and + * TI2FP2 edges depending. + * TIM_IC1Polarity - specifies the IC1 Polarity. + * TIM_ICPolarity_Falling - IC Falling edge. + * TTIM_ICPolarity_Rising - IC Rising edge. + * TIM_IC2Polarity - specifies the IC2 Polarity. + * TIM_ICPolarity_Falling - IC Falling edge. + * TIM_ICPolarity_Rising - IC Rising edge. + * + * @return none + */ +void TIM_EncoderInterfaceConfig(TIM_TypeDef *TIMx, uint16_t TIM_EncoderMode, + uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity) +{ + uint16_t tmpsmcr = 0; + uint16_t tmpccmr1 = 0; + uint16_t tmpccer = 0; + + tmpsmcr = TIMx->SMCFGR; + tmpccmr1 = TIMx->CHCTLR1; + tmpccer = TIMx->CCER; + tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMS)); + tmpsmcr |= TIM_EncoderMode; + tmpccmr1 &= (uint16_t)(((uint16_t) ~((uint16_t)TIM_CC1S)) & (uint16_t)(~((uint16_t)TIM_CC2S))); + tmpccmr1 |= TIM_CC1S_0 | TIM_CC2S_0; + tmpccer &= (uint16_t)(((uint16_t) ~((uint16_t)TIM_CC1P)) & ((uint16_t) ~((uint16_t)TIM_CC2P))); + tmpccer |= (uint16_t)(TIM_IC1Polarity | (uint16_t)(TIM_IC2Polarity << (uint16_t)4)); + TIMx->SMCFGR = tmpsmcr; + TIMx->CHCTLR1 = tmpccmr1; + TIMx->CCER = tmpccer; +} + +/********************************************************************* + * @fn TIM_ForcedOC1Config + * + * @brief Forces the TIMx output 1 waveform to active or inactive level. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_ForcedAction - specifies the forced Action to be set to the + * output waveform. + * TIM_ForcedAction_Active - Force active level on OC1REF. + * TIM_ForcedAction_InActive - Force inactive level on OC1REF. + * + * @return none + */ +void TIM_ForcedOC1Config(TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction) +{ + uint16_t tmpccmr1 = 0; + + tmpccmr1 = TIMx->CHCTLR1; + tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_OC1M); + tmpccmr1 |= TIM_ForcedAction; + TIMx->CHCTLR1 = tmpccmr1; +} + +/********************************************************************* + * @fn TIM_ForcedOC2Config + * + * @brief Forces the TIMx output 2 waveform to active or inactive level. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_ForcedAction - specifies the forced Action to be set to the + * output waveform. + * TIM_ForcedAction_Active - Force active level on OC2REF. + * TIM_ForcedAction_InActive - Force inactive level on OC2REF. + * + * @return none + */ +void TIM_ForcedOC2Config(TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction) +{ + uint16_t tmpccmr1 = 0; + + tmpccmr1 = TIMx->CHCTLR1; + tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_OC2M); + tmpccmr1 |= (uint16_t)(TIM_ForcedAction << 8); + TIMx->CHCTLR1 = tmpccmr1; +} + +/********************************************************************* + * @fn TIM_ForcedOC3Config + * + * @brief Forces the TIMx output 3 waveform to active or inactive level. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_ForcedAction - specifies the forced Action to be set to the + * output waveform. + * TIM_ForcedAction_Active - Force active level on OC3REF. + * TIM_ForcedAction_InActive - Force inactive level on OC3REF. + * + * @return none + */ +void TIM_ForcedOC3Config(TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction) +{ + uint16_t tmpccmr2 = 0; + + tmpccmr2 = TIMx->CHCTLR2; + tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_OC3M); + tmpccmr2 |= TIM_ForcedAction; + TIMx->CHCTLR2 = tmpccmr2; +} + +/********************************************************************* + * @fn TIM_ForcedOC4Config + * + * @brief Forces the TIMx output 4 waveform to active or inactive level. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_ForcedAction - specifies the forced Action to be set to the + * output waveform. + * TIM_ForcedAction_Active - Force active level on OC4REF. + * TIM_ForcedAction_InActive - Force inactive level on OC4REF. + * + * @return none + */ +void TIM_ForcedOC4Config(TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction) +{ + uint16_t tmpccmr2 = 0; + + tmpccmr2 = TIMx->CHCTLR2; + tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_OC4M); + tmpccmr2 |= (uint16_t)(TIM_ForcedAction << 8); + TIMx->CHCTLR2 = tmpccmr2; +} + +/********************************************************************* + * @fn TIM_ARRPreloadConfig + * + * @brief Enables or disables TIMx peripheral Preload register on ARR. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void TIM_ARRPreloadConfig(TIM_TypeDef *TIMx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + TIMx->CTLR1 |= TIM_ARPE; + } + else + { + TIMx->CTLR1 &= (uint16_t) ~((uint16_t)TIM_ARPE); + } +} + +/********************************************************************* + * @fn TIM_SelectCOM + * + * @brief Selects the TIM peripheral Commutation event. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void TIM_SelectCOM(TIM_TypeDef *TIMx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + TIMx->CTLR2 |= TIM_CCUS; + } + else + { + TIMx->CTLR2 &= (uint16_t) ~((uint16_t)TIM_CCUS); + } +} + +/********************************************************************* + * @fn TIM_SelectCCDMA + * + * @brief Selects the TIMx peripheral Capture Compare DMA source. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void TIM_SelectCCDMA(TIM_TypeDef *TIMx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + TIMx->CTLR2 |= TIM_CCDS; + } + else + { + TIMx->CTLR2 &= (uint16_t) ~((uint16_t)TIM_CCDS); + } +} + +/********************************************************************* + * @fn TIM_CCPreloadControl + * + * @brief DSets or Resets the TIM peripheral Capture Compare Preload Control bit. + * reset values. + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void TIM_CCPreloadControl(TIM_TypeDef *TIMx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + TIMx->CTLR2 |= TIM_CCPC; + } + else + { + TIMx->CTLR2 &= (uint16_t) ~((uint16_t)TIM_CCPC); + } +} + +/********************************************************************* + * @fn TIM_OC1PreloadConfig + * + * @brief Enables or disables the TIMx peripheral Preload register on CCR1. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_OCPreload - new state of the TIMx peripheral Preload register. + * TIM_OCPreload_Enable. + * TIM_OCPreload_Disable. + * + * @return none + */ +void TIM_OC1PreloadConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPreload) +{ + uint16_t tmpccmr1 = 0; + + tmpccmr1 = TIMx->CHCTLR1; + tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_OC1PE); + tmpccmr1 |= TIM_OCPreload; + TIMx->CHCTLR1 = tmpccmr1; +} + +/********************************************************************* + * @fn TIM_OC2PreloadConfig + * + * @brief Enables or disables the TIMx peripheral Preload register on CCR2. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_OCPreload - new state of the TIMx peripheral Preload register. + * TIM_OCPreload_Enable. + * TIM_OCPreload_Disable. + * + * @return none + */ +void TIM_OC2PreloadConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPreload) +{ + uint16_t tmpccmr1 = 0; + + tmpccmr1 = TIMx->CHCTLR1; + tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_OC2PE); + tmpccmr1 |= (uint16_t)(TIM_OCPreload << 8); + TIMx->CHCTLR1 = tmpccmr1; +} + +/********************************************************************* + * @fn TIM_OC3PreloadConfig + * + * @brief Enables or disables the TIMx peripheral Preload register on CCR3. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_OCPreload - new state of the TIMx peripheral Preload register. + * TIM_OCPreload_Enable. + * TIM_OCPreload_Disable. + * + * @return none + */ +void TIM_OC3PreloadConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPreload) +{ + uint16_t tmpccmr2 = 0; + + tmpccmr2 = TIMx->CHCTLR2; + tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_OC3PE); + tmpccmr2 |= TIM_OCPreload; + TIMx->CHCTLR2 = tmpccmr2; +} + +/********************************************************************* + * @fn TIM_OC4PreloadConfig + * + * @brief Enables or disables the TIMx peripheral Preload register on CCR4. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_OCPreload - new state of the TIMx peripheral Preload register. + * TIM_OCPreload_Enable. + * TIM_OCPreload_Disable. + * + * @return none + */ +void TIM_OC4PreloadConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPreload) +{ + uint16_t tmpccmr2 = 0; + + tmpccmr2 = TIMx->CHCTLR2; + tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_OC4PE); + tmpccmr2 |= (uint16_t)(TIM_OCPreload << 8); + TIMx->CHCTLR2 = tmpccmr2; +} + +/********************************************************************* + * @fn TIM_OC1FastConfig + * + * @brief Configures the TIMx Output Compare 1 Fast feature. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_OCFast - new state of the Output Compare Fast Enable Bit. + * TIM_OCFast_Enable - TIM output compare fast enable. + * TIM_OCFast_Disable - TIM output compare fast disable. + * + * @return none + */ +void TIM_OC1FastConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCFast) +{ + uint16_t tmpccmr1 = 0; + + tmpccmr1 = TIMx->CHCTLR1; + tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_OC1FE); + tmpccmr1 |= TIM_OCFast; + TIMx->CHCTLR1 = tmpccmr1; +} + +/********************************************************************* + * @fn TIM_OC2FastConfig + * + * @brief Configures the TIMx Output Compare 2 Fast feature. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_OCFast - new state of the Output Compare Fast Enable Bit. + * TIM_OCFast_Enable - TIM output compare fast enable. + * TIM_OCFast_Disable - TIM output compare fast disable. + * + * @return none + */ +void TIM_OC2FastConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCFast) +{ + uint16_t tmpccmr1 = 0; + + tmpccmr1 = TIMx->CHCTLR1; + tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_OC2FE); + tmpccmr1 |= (uint16_t)(TIM_OCFast << 8); + TIMx->CHCTLR1 = tmpccmr1; +} + +/********************************************************************* + * @fn TIM_OC3FastConfig + * + * @brief Configures the TIMx Output Compare 3 Fast feature. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_OCFast - new state of the Output Compare Fast Enable Bit. + * TIM_OCFast_Enable - TIM output compare fast enable. + * TIM_OCFast_Disable - TIM output compare fast disable. + * + * @return none + */ +void TIM_OC3FastConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCFast) +{ + uint16_t tmpccmr2 = 0; + + tmpccmr2 = TIMx->CHCTLR2; + tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_OC3FE); + tmpccmr2 |= TIM_OCFast; + TIMx->CHCTLR2 = tmpccmr2; +} + +/********************************************************************* + * @fn TIM_OC4FastConfig + * + * @brief Configures the TIMx Output Compare 4 Fast feature. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_OCFast - new state of the Output Compare Fast Enable Bit. + * TIM_OCFast_Enable - TIM output compare fast enable. + * TIM_OCFast_Disable - TIM output compare fast disable. + * + * @return none + */ +void TIM_OC4FastConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCFast) +{ + uint16_t tmpccmr2 = 0; + + tmpccmr2 = TIMx->CHCTLR2; + tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_OC4FE); + tmpccmr2 |= (uint16_t)(TIM_OCFast << 8); + TIMx->CHCTLR2 = tmpccmr2; +} + +/********************************************************************* + * @fn TIM_ClearOC1Ref + * + * @brief Clears or safeguards the OCREF1 signal on an external event. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_OCClear - new state of the Output Compare Clear Enable Bit. + * TIM_OCClear_Enable - TIM Output clear enable. + * TIM_OCClear_Disable - TIM Output clear disable. + * + * @return none + */ +void TIM_ClearOC1Ref(TIM_TypeDef *TIMx, uint16_t TIM_OCClear) +{ + uint16_t tmpccmr1 = 0; + + tmpccmr1 = TIMx->CHCTLR1; + tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_OC1CE); + tmpccmr1 |= TIM_OCClear; + TIMx->CHCTLR1 = tmpccmr1; +} + +/********************************************************************* + * @fn TIM_ClearOC2Ref + * + * @brief Clears or safeguards the OCREF2 signal on an external event. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_OCClear - new state of the Output Compare Clear Enable Bit. + * TIM_OCClear_Enable - TIM Output clear enable. + * TIM_OCClear_Disable - TIM Output clear disable. + * + * @return none + */ +void TIM_ClearOC2Ref(TIM_TypeDef *TIMx, uint16_t TIM_OCClear) +{ + uint16_t tmpccmr1 = 0; + + tmpccmr1 = TIMx->CHCTLR1; + tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_OC2CE); + tmpccmr1 |= (uint16_t)(TIM_OCClear << 8); + TIMx->CHCTLR1 = tmpccmr1; +} + +/********************************************************************* + * @fn TIM_ClearOC3Ref + * + * @brief Clears or safeguards the OCREF3 signal on an external event. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_OCClear - new state of the Output Compare Clear Enable Bit. + * TIM_OCClear_Enable - TIM Output clear enable. + * TIM_OCClear_Disable - TIM Output clear disable. + * + * @return none + */ +void TIM_ClearOC3Ref(TIM_TypeDef *TIMx, uint16_t TIM_OCClear) +{ + uint16_t tmpccmr2 = 0; + + tmpccmr2 = TIMx->CHCTLR2; + tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_OC3CE); + tmpccmr2 |= TIM_OCClear; + TIMx->CHCTLR2 = tmpccmr2; +} + +/********************************************************************* + * @fn TIM_ClearOC4Ref + * + * @brief Clears or safeguards the OCREF4 signal on an external event. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_OCClear - new state of the Output Compare Clear Enable Bit. + * TIM_OCClear_Enable - TIM Output clear enable. + * TIM_OCClear_Disable - TIM Output clear disable. + * + * @return none + */ +void TIM_ClearOC4Ref(TIM_TypeDef *TIMx, uint16_t TIM_OCClear) +{ + uint16_t tmpccmr2 = 0; + + tmpccmr2 = TIMx->CHCTLR2; + tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_OC4CE); + tmpccmr2 |= (uint16_t)(TIM_OCClear << 8); + TIMx->CHCTLR2 = tmpccmr2; +} + +/********************************************************************* + * @fn TIM_OC1PolarityConfig + * + * @brief Configures the TIMx channel 1 polarity. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_OCPolarity - specifies the OC1 Polarity. + * TIM_OCPolarity_High - Output Compare active high. + * TIM_OCPolarity_Low - Output Compare active low. + * + * @return none + */ +void TIM_OC1PolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity) +{ + uint16_t tmpccer = 0; + + tmpccer = TIMx->CCER; + tmpccer &= (uint16_t) ~((uint16_t)TIM_CC1P); + tmpccer |= TIM_OCPolarity; + TIMx->CCER = tmpccer; +} + +/********************************************************************* + * @fn TIM_OC1NPolarityConfig + * + * @brief Configures the TIMx channel 1 polarity. + * + * @param TIMx - where x can be 1 to select the TIM peripheral. + * TIM_OCNPolarity - specifies the OC1N Polarity. + * TIM_OCNPolarity_High - Output Compare active high. + * TIM_OCNPolarity_Low - Output Compare active low. + * + * @return none + */ +void TIM_OC1NPolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCNPolarity) +{ + uint16_t tmpccer = 0; + + tmpccer = TIMx->CCER; + tmpccer &= (uint16_t) ~((uint16_t)TIM_CC1NP); + tmpccer |= TIM_OCNPolarity; + TIMx->CCER = tmpccer; +} + +/********************************************************************* + * @fn TIM_OC2PolarityConfig + * + * @brief Configures the TIMx channel 2 polarity. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_OCPolarity - specifies the OC2 Polarity. + * TIM_OCPolarity_High - Output Compare active high. + * TIM_OCPolarity_Low - Output Compare active low. + * + * @return none + */ +void TIM_OC2PolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity) +{ + uint16_t tmpccer = 0; + + tmpccer = TIMx->CCER; + tmpccer &= (uint16_t) ~((uint16_t)TIM_CC2P); + tmpccer |= (uint16_t)(TIM_OCPolarity << 4); + TIMx->CCER = tmpccer; +} + +/********************************************************************* + * @fn TIM_OC2NPolarityConfig + * + * @brief Configures the TIMx channel 2 polarity. + * + * @param TIMx - where x can be 1 to select the TIM peripheral. + * TIM_OCNPolarity - specifies the OC1N Polarity. + * TIM_OCNPolarity_High - Output Compare active high. + * TIM_OCNPolarity_Low - Output Compare active low. + * + * @return none + */ +void TIM_OC2NPolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCNPolarity) +{ + uint16_t tmpccer = 0; + + tmpccer = TIMx->CCER; + tmpccer &= (uint16_t) ~((uint16_t)TIM_CC2NP); + tmpccer |= (uint16_t)(TIM_OCNPolarity << 4); + TIMx->CCER = tmpccer; +} + +/********************************************************************* + * @fn TIM_OC3PolarityConfig + * + * @brief Configures the TIMx Channel 3 polarity. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * TIM_OCPolarit - specifies the OC3 Polarity. + * TIM_OCPolarity_High - Output Compare active high. + * TIM_OCPolarity_Low - Output Compare active low. + * + * @return none + */ +void TIM_OC3PolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity) +{ + uint16_t tmpccer = 0; + + tmpccer = TIMx->CCER; + tmpccer &= (uint16_t) ~((uint16_t)TIM_CC3P); + tmpccer |= (uint16_t)(TIM_OCPolarity << 8); + TIMx->CCER = tmpccer; +} + +/********************************************************************* + * @fn TIM_OC3NPolarityConfig + * + * @brief Configures the TIMx Channel 3N polarity. + * + * @param TIMx - where x can be 1 to select the TIM peripheral. + * TIM_OCNPolarity - specifies the OC2N Polarity. + * TIM_OCNPolarity_High - Output Compare active high. + * TIM_OCNPolarity_Low - Output Compare active low. + * + * @return none + */ +void TIM_OC3NPolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCNPolarity) +{ + uint16_t tmpccer = 0; + + tmpccer = TIMx->CCER; + tmpccer &= (uint16_t) ~((uint16_t)TIM_CC3NP); + tmpccer |= (uint16_t)(TIM_OCNPolarity << 8); + TIMx->CCER = tmpccer; +} + +/********************************************************************* + * @fn TIM_OC4PolarityConfig + * + * @brief Configures the TIMx Channel 4 polarity. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * TIM_OCPolarit - specifies the OC3 Polarity. + * TIM_OCPolarity_High - Output Compare active high. + * TIM_OCPolarity_Low - Output Compare active low. + * + * @return none + */ +void TIM_OC4PolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity) +{ + uint16_t tmpccer = 0; + + tmpccer = TIMx->CCER; + tmpccer &= (uint16_t) ~((uint16_t)TIM_CC4P); + tmpccer |= (uint16_t)(TIM_OCPolarity << 12); + TIMx->CCER = tmpccer; +} + +/********************************************************************* + * @fn TIM_CCxCmd + * + * @brief Enables or disables the TIM Capture Compare Channel x. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * TIM_Channel - specifies the TIM Channel. + * TIM_Channel_1 - TIM Channel 1. + * TIM_Channel_2 - TIM Channel 2. + * TIM_Channel_3 - TIM Channel 3. + * TIM_Channel_4 - TIM Channel 4. + * TIM_CCx - specifies the TIM Channel CCxE bit new state. + * TIM_CCx_Enable. + * TIM_CCx_Disable. + * + * @return none + */ +void TIM_CCxCmd(TIM_TypeDef *TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx) +{ + uint16_t tmp = 0; + + tmp = CCER_CCE_Set << TIM_Channel; + TIMx->CCER &= (uint16_t)~tmp; + TIMx->CCER |= (uint16_t)(TIM_CCx << TIM_Channel); +} + +/********************************************************************* + * @fn TIM_CCxNCmd + * + * @brief Enables or disables the TIM Capture Compare Channel xN. + * + * @param TIMx - where x can be 1 select the TIM peripheral. + * TIM_Channel - specifies the TIM Channel. + * TIM_Channel_1 - TIM Channel 1. + * TIM_Channel_2 - TIM Channel 2. + * TIM_Channel_3 - TIM Channel 3. + * TIM_CCxN - specifies the TIM Channel CCxNE bit new state. + * TIM_CCxN_Enable. + * TIM_CCxN_Disable. + * + * @return none + */ +void TIM_CCxNCmd(TIM_TypeDef *TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN) +{ + uint16_t tmp = 0; + + tmp = CCER_CCNE_Set << TIM_Channel; + TIMx->CCER &= (uint16_t)~tmp; + TIMx->CCER |= (uint16_t)(TIM_CCxN << TIM_Channel); +} + +/********************************************************************* + * @fn TIM_SelectOCxM + * + * @brief Selects the TIM Output Compare Mode. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * TIM_Channel - specifies the TIM Channel. + * TIM_Channel_1 - TIM Channel 1. + * TIM_Channel_2 - TIM Channel 2. + * TIM_Channel_3 - TIM Channel 3. + * TIM_Channel_4 - TIM Channel 4. + * TIM_OCMode - specifies the TIM Output Compare Mode. + * TIM_OCMode_Timing. + * TIM_OCMode_Active. + * TIM_OCMode_Toggle. + * TIM_OCMode_PWM1. + * TIM_OCMode_PWM2. + * TIM_ForcedAction_Active. + * TIM_ForcedAction_InActive. + * + * @return none + */ +void TIM_SelectOCxM(TIM_TypeDef *TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode) +{ + uint32_t tmp = 0; + uint16_t tmp1 = 0; + + tmp = (uint32_t)TIMx; + tmp += CHCTLR_Offset; + tmp1 = CCER_CCE_Set << (uint16_t)TIM_Channel; + TIMx->CCER &= (uint16_t)~tmp1; + + if((TIM_Channel == TIM_Channel_1) || (TIM_Channel == TIM_Channel_3)) + { + tmp += (TIM_Channel >> 1); + *(__IO uint32_t *)tmp &= (uint32_t) ~((uint32_t)TIM_OC1M); + *(__IO uint32_t *)tmp |= TIM_OCMode; + } + else + { + tmp += (uint16_t)(TIM_Channel - (uint16_t)4) >> (uint16_t)1; + *(__IO uint32_t *)tmp &= (uint32_t) ~((uint32_t)TIM_OC2M); + *(__IO uint32_t *)tmp |= (uint16_t)(TIM_OCMode << 8); + } +} + +/********************************************************************* + * @fn TIM_UpdateDisableConfig + * + * @brief Enables or Disables the TIMx Update event. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void TIM_UpdateDisableConfig(TIM_TypeDef *TIMx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + TIMx->CTLR1 |= TIM_UDIS; + } + else + { + TIMx->CTLR1 &= (uint16_t) ~((uint16_t)TIM_UDIS); + } +} + +/********************************************************************* + * @fn TIM_UpdateRequestConfig + * + * @brief Configures the TIMx Update Request Interrupt source. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * TIM_UpdateSource - specifies the Update source. + * TIM_UpdateSource_Regular. + * TIM_UpdateSource_Global. + * + * @return none + */ +void TIM_UpdateRequestConfig(TIM_TypeDef *TIMx, uint16_t TIM_UpdateSource) +{ + if(TIM_UpdateSource != TIM_UpdateSource_Global) + { + TIMx->CTLR1 |= TIM_URS; + } + else + { + TIMx->CTLR1 &= (uint16_t) ~((uint16_t)TIM_URS); + } +} + +/********************************************************************* + * @fn TIM_SelectHallSensor + * + * @brief Enables or disables the TIMx's Hall sensor interface. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void TIM_SelectHallSensor(TIM_TypeDef *TIMx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + TIMx->CTLR2 |= TIM_TI1S; + } + else + { + TIMx->CTLR2 &= (uint16_t) ~((uint16_t)TIM_TI1S); + } +} + +/********************************************************************* + * @fn TIM_SelectOnePulseMode + * + * @brief Selects the TIMx's One Pulse Mode. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * TIM_OPMode - specifies the OPM Mode to be used. + * TIM_OPMode_Single. + * TIM_OPMode_Repetitive. + * + * @return none + */ +void TIM_SelectOnePulseMode(TIM_TypeDef *TIMx, uint16_t TIM_OPMode) +{ + TIMx->CTLR1 &= (uint16_t) ~((uint16_t)TIM_OPM); + TIMx->CTLR1 |= TIM_OPMode; +} + +/********************************************************************* + * @fn TIM_SelectOutputTrigger + * + * @brief Selects the TIMx Trigger Output Mode. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * TIM_TRGOSource - specifies the Trigger Output source. + * TIM_TRGOSource_Reset - The UG bit in the TIM_EGR register is + * used as the trigger output (TRGO). + * TIM_TRGOSource_Enable - The Counter Enable CEN is used as the + * trigger output (TRGO). + * TIM_TRGOSource_Update - The update event is selected as the + * trigger output (TRGO). + * TIM_TRGOSource_OC1 - The trigger output sends a positive pulse + * when the CC1IF flag is to be set, as soon as a capture or compare match occurs (TRGO). + * TIM_TRGOSource_OC1Ref - OC1REF signal is used as the trigger output (TRGO). + * TIM_TRGOSource_OC2Ref - OC2REF signal is used as the trigger output (TRGO). + * TIM_TRGOSource_OC3Ref - OC3REF signal is used as the trigger output (TRGO). + * TIM_TRGOSource_OC4Ref - OC4REF signal is used as the trigger output (TRGO). + * + * @return none + */ +void TIM_SelectOutputTrigger(TIM_TypeDef *TIMx, uint16_t TIM_TRGOSource) +{ + TIMx->CTLR2 &= (uint16_t) ~((uint16_t)TIM_MMS); + TIMx->CTLR2 |= TIM_TRGOSource; +} + +/********************************************************************* + * @fn TIM_SelectSlaveMode + * + * @brief Selects the TIMx Slave Mode. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * TIM_SlaveMode - specifies the Timer Slave Mode. + * TIM_SlaveMode_Reset - Rising edge of the selected trigger + * signal (TRGI) re-initializes. + * TIM_SlaveMode_Gated - The counter clock is enabled when the + * trigger signal (TRGI) is high. + * TIM_SlaveMode_Trigger - The counter starts at a rising edge + * of the trigger TRGI. + * TIM_SlaveMode_External1 - Rising edges of the selected trigger + * (TRGI) clock the counter. + * + * @return none + */ +void TIM_SelectSlaveMode(TIM_TypeDef *TIMx, uint16_t TIM_SlaveMode) +{ + TIMx->SMCFGR &= (uint16_t) ~((uint16_t)TIM_SMS); + TIMx->SMCFGR |= TIM_SlaveMode; +} + +/********************************************************************* + * @fn TIM_SelectMasterSlaveMode + * + * @brief Sets or Resets the TIMx Master/Slave Mode. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * TIM_MasterSlaveMode - specifies the Timer Master Slave Mode. + * TIM_MasterSlaveMode_Enable - synchronization between the current + * timer and its slaves (through TRGO). + * TIM_MasterSlaveMode_Disable - No action. + * + * @return none + */ +void TIM_SelectMasterSlaveMode(TIM_TypeDef *TIMx, uint16_t TIM_MasterSlaveMode) +{ + TIMx->SMCFGR &= (uint16_t) ~((uint16_t)TIM_MSM); + TIMx->SMCFGR |= TIM_MasterSlaveMode; +} + +/********************************************************************* + * @fn TIM_SetCounter + * + * @brief Sets the TIMx Counter Register value. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * Counter - specifies the Counter register new value. + * + * @return none + */ +void TIM_SetCounter(TIM_TypeDef *TIMx, uint32_t Counter) +{ + if(TIMx == TIM4) TIMx->CNT_TIM4 = Counter; + else TIMx->CNT = (uint16_t)Counter; +} + +/********************************************************************* + * @fn TIM_SetAutoreload + * + * @brief Sets the TIMx Autoreload Register value. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * Autoreload - specifies the Autoreload register new value. + * + * @return none + */ +void TIM_SetAutoreload(TIM_TypeDef *TIMx, uint32_t Autoreload) +{ + if(TIMx == TIM4) TIMx->ATRLR_TIM4 = Autoreload; + else TIMx->ATRLR = (uint16_t)Autoreload; +} + +/********************************************************************* + * @fn TIM_SetCompare1 + * + * @brief Sets the TIMx Capture Compare1 Register value. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * Compare1 - specifies the Capture Compare1 register new value. + * + * @return none + */ +void TIM_SetCompare1(TIM_TypeDef *TIMx, uint32_t Compare1) +{ + if(TIMx == TIM4) TIMx->CH1CVR_TIM4 = Compare1; + else TIMx->CH1CVR = (uint16_t)Compare1; +} + +/********************************************************************* + * @fn TIM_SetCompare2 + * + * @brief Sets the TIMx Capture Compare2 Register value. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * Compare1 - specifies the Capture Compare1 register new value. + * + * @return none + */ +void TIM_SetCompare2(TIM_TypeDef *TIMx, uint32_t Compare2) +{ + if(TIMx == TIM4) TIMx->CH2CVR_TIM4 = Compare2; + else TIMx->CH2CVR = (uint16_t)Compare2; +} + +/********************************************************************* + * @fn TIM_SetCompare3 + * + * @brief Sets the TIMx Capture Compare3 Register value. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * Compare1 - specifies the Capture Compare1 register new value. + * + * @return none + */ +void TIM_SetCompare3(TIM_TypeDef *TIMx, uint32_t Compare3) +{ + if(TIMx == TIM4) TIMx->CH3CVR_TIM4 = Compare3; + else TIMx->CH3CVR = (uint16_t)Compare3; +} + +/********************************************************************* + * @fn TIM_SetCompare4 + * + * @brief Sets the TIMx Capture Compare4 Register value. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * Compare1 - specifies the Capture Compare1 register new value. + * + * @return none + */ +void TIM_SetCompare4(TIM_TypeDef *TIMx, uint32_t Compare4) +{ + if(TIMx == TIM4) TIMx->CH4CVR_TIM4 = Compare4; + else TIMx->CH4CVR = (uint16_t)Compare4; +} + +/********************************************************************* + * @fn TIM_SetIC1Prescaler + * + * @brief Sets the TIMx Input Capture 1 prescaler. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * TIM_ICPSC - specifies the Input Capture1 prescaler new value. + * TIM_ICPSC_DIV1 - no prescaler. + * TIM_ICPSC_DIV2 - capture is done once every 2 events. + * TIM_ICPSC_DIV4 - capture is done once every 4 events. + * TIM_ICPSC_DIV8 - capture is done once every 8 events. + * + * @return none + */ +void TIM_SetIC1Prescaler(TIM_TypeDef *TIMx, uint16_t TIM_ICPSC) +{ + TIMx->CHCTLR1 &= (uint16_t) ~((uint16_t)TIM_IC1PSC); + TIMx->CHCTLR1 |= TIM_ICPSC; +} + +/********************************************************************* + * @fn TIM_SetIC2Prescaler + * + * @brief Sets the TIMx Input Capture 2 prescaler. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * TIM_ICPSC - specifies the Input Capture1 prescaler new value. + * TIM_ICPSC_DIV1 - no prescaler. + * TIM_ICPSC_DIV2 - capture is done once every 2 events. + * TIM_ICPSC_DIV4 - capture is done once every 4 events. + * TIM_ICPSC_DIV8 - capture is done once every 8 events. + * + * @return none + */ +void TIM_SetIC2Prescaler(TIM_TypeDef *TIMx, uint16_t TIM_ICPSC) +{ + TIMx->CHCTLR1 &= (uint16_t) ~((uint16_t)TIM_IC2PSC); + TIMx->CHCTLR1 |= (uint16_t)(TIM_ICPSC << 8); +} + +/********************************************************************* + * @fn TIM_SetIC3Prescaler + * + * @brief Sets the TIMx Input Capture 3 prescaler. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * TIM_ICPSC - specifies the Input Capture1 prescaler new value. + * TIM_ICPSC_DIV1 - no prescaler. + * TIM_ICPSC_DIV2 - capture is done once every 2 events. + * TIM_ICPSC_DIV4 - capture is done once every 4 events. + * TIM_ICPSC_DIV8 - capture is done once every 8 events. + * + * @return none + */ +void TIM_SetIC3Prescaler(TIM_TypeDef *TIMx, uint16_t TIM_ICPSC) +{ + TIMx->CHCTLR2 &= (uint16_t) ~((uint16_t)TIM_IC3PSC); + TIMx->CHCTLR2 |= TIM_ICPSC; +} + +/********************************************************************* + * @fn TIM_SetIC4Prescaler + * + * @brief Sets the TIMx Input Capture 4 prescaler. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * TIM_ICPSC - specifies the Input Capture1 prescaler new value. + * TIM_ICPSC_DIV1 - no prescaler. + * TIM_ICPSC_DIV2 - capture is done once every 2 events. + * TIM_ICPSC_DIV4 - capture is done once every 4 events. + * TIM_ICPSC_DIV8 - capture is done once every 8 events. + * + * @return none + */ +void TIM_SetIC4Prescaler(TIM_TypeDef *TIMx, uint16_t TIM_ICPSC) +{ + TIMx->CHCTLR2 &= (uint16_t) ~((uint16_t)TIM_IC4PSC); + TIMx->CHCTLR2 |= (uint16_t)(TIM_ICPSC << 8); +} + +/********************************************************************* + * @fn TIM_SetClockDivision + * + * @brief Sets the TIMx Clock Division value. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * TIM_CKD - specifies the clock division value. + * TIM_CKD_DIV1 - TDTS = Tck_tim. + * TIM_CKD_DIV2 - TDTS = 2*Tck_tim. + * TIM_CKD_DIV4 - TDTS = 4*Tck_tim. + * + * @return none + */ +void TIM_SetClockDivision(TIM_TypeDef *TIMx, uint16_t TIM_CKD) +{ + TIMx->CTLR1 &= (uint16_t) ~((uint16_t)TIM_CTLR1_CKD); + TIMx->CTLR1 |= TIM_CKD; +} + +/********************************************************************* + * @fn TIM_GetCapture1 + * + * @brief Gets the TIMx Input Capture 1 value. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * + * @return TIMx->CH1CVR - Capture Compare 1 Register value. + */ +uint32_t TIM_GetCapture1(TIM_TypeDef *TIMx) +{ + if(TIMx == TIM4) return TIMx->CH1CVR_TIM4; + else return TIMx->CH1CVR; +} + +/********************************************************************* + * @fn TIM_GetCapture2 + * + * @brief Gets the TIMx Input Capture 2 value. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * + * @return TIMx->CH2CVR - Capture Compare 2 Register value. + */ +uint32_t TIM_GetCapture2(TIM_TypeDef *TIMx) +{ + if(TIMx == TIM4) return TIMx->CH2CVR_TIM4; + else return TIMx->CH2CVR; +} + +/********************************************************************* + * @fn TIM_GetCapture3 + * + * @brief Gets the TIMx Input Capture 3 value. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * + * @return TIMx->CH3CVR - Capture Compare 3 Register value. + */ +uint32_t TIM_GetCapture3(TIM_TypeDef *TIMx) +{ + if(TIMx == TIM4) return TIMx->CH3CVR_TIM4; + else return TIMx->CH3CVR; +} + +/********************************************************************* + * @fn TIM_GetCapture4 + * + * @brief Gets the TIMx Input Capture 4 value. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * + * @return TIMx->CH4CVR - Capture Compare 4 Register value. + */ +uint32_t TIM_GetCapture4(TIM_TypeDef *TIMx) +{ + if(TIMx == TIM4) return TIMx->CH4CVR_TIM4; + else return TIMx->CH4CVR; +} + +/********************************************************************* + * @fn TIM_GetCounter + * + * @brief Gets the TIMx Counter value. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * + * @return TIMx->CNT - Counter Register value. + */ +uint32_t TIM_GetCounter(TIM_TypeDef *TIMx) +{ + if(TIMx == TIM4) return TIMx->CNT_TIM4; + else return TIMx->CNT; +} + +/********************************************************************* + * @fn TIM_GetPrescaler + * + * @brief Gets the TIMx Prescaler value. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * + * @return TIMx->PSC - Prescaler Register value. + */ +uint16_t TIM_GetPrescaler(TIM_TypeDef *TIMx) +{ + return TIMx->PSC; +} + +/********************************************************************* + * @fn TIM_GetFlagStatus + * + * @brief Checks whether the specified TIM flag is set or not. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * TIM_FLAG - specifies the flag to check. + * TIM_FLAG_Update - TIM update Flag. + * TIM_FLAG_CC1 - TIM Capture Compare 1 Flag. + * TIM_FLAG_CC2 - TIM Capture Compare 2 Flag. + * TIM_FLAG_CC3 - TIM Capture Compare 3 Flag. + * TIM_FLAG_CC4 - TIM Capture Compare 4 Flag. + * TIM_FLAG_COM - TIM Commutation Flag. + * TIM_FLAG_Trigger - TIM Trigger Flag. + * TIM_FLAG_Break - TIM Break Flag. + * TIM_FLAG_CC1OF - TIM Capture Compare 1 overcapture Flag. + * TIM_FLAG_CC2OF - TIM Capture Compare 2 overcapture Flag. + * TIM_FLAG_CC3OF - TIM Capture Compare 3 overcapture Flag. + * TIM_FLAG_CC4OF - TIM Capture Compare 4 overcapture Flag. + * + * @return none + */ +FlagStatus TIM_GetFlagStatus(TIM_TypeDef *TIMx, uint16_t TIM_FLAG) +{ + ITStatus bitstatus = RESET; + + if((TIMx->INTFR & TIM_FLAG) != (uint16_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn TIM_ClearFlag + * + * @brief Clears the TIMx's pending flags. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * TIM_FLAG - specifies the flag to check. + * TIM_FLAG_Update - TIM update Flag. + * TIM_FLAG_CC1 - TIM Capture Compare 1 Flag. + * TIM_FLAG_CC2 - TIM Capture Compare 2 Flag. + * TIM_FLAG_CC3 - TIM Capture Compare 3 Flag. + * TIM_FLAG_CC4 - TIM Capture Compare 4 Flag. + * TIM_FLAG_COM - TIM Commutation Flag. + * TIM_FLAG_Trigger - TIM Trigger Flag. + * TIM_FLAG_Break - TIM Break Flag. + * TIM_FLAG_CC1OF - TIM Capture Compare 1 overcapture Flag. + * TIM_FLAG_CC2OF - TIM Capture Compare 2 overcapture Flag. + * TIM_FLAG_CC3OF - TIM Capture Compare 3 overcapture Flag. + * TIM_FLAG_CC4OF - TIM Capture Compare 4 overcapture Flag. + * + * @return none + */ +void TIM_ClearFlag(TIM_TypeDef *TIMx, uint16_t TIM_FLAG) +{ + TIMx->INTFR = (uint16_t)~TIM_FLAG; +} + +/********************************************************************* + * @fn TIM_GetITStatus + * + * @brief Checks whether the TIM interrupt has occurred or not. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * TIM_IT - specifies the TIM interrupt source to check. + * TIM_IT_Update - TIM update Interrupt source. + * TIM_IT_CC1 - TIM Capture Compare 1 Interrupt source. + * TIM_IT_CC2 - TIM Capture Compare 2 Interrupt source. + * TIM_IT_CC3 - TIM Capture Compare 3 Interrupt source. + * TIM_IT_CC4 - TIM Capture Compare 4 Interrupt source. + * TIM_IT_COM - TIM Commutation Interrupt source. + * TIM_IT_Trigger - TIM Trigger Interrupt source. + * TIM_IT_Break - TIM Break Interrupt source. + * + * @return none + */ +ITStatus TIM_GetITStatus(TIM_TypeDef *TIMx, uint16_t TIM_IT) +{ + ITStatus bitstatus = RESET; + uint16_t itstatus = 0x0, itenable = 0x0; + + itstatus = TIMx->INTFR & TIM_IT; + + itenable = TIMx->DMAINTENR & TIM_IT; + if((itstatus != (uint16_t)RESET) && (itenable != (uint16_t)RESET)) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn TIM_ClearITPendingBit + * + * @brief Clears the TIMx's interrupt pending bits. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * TIM_IT - specifies the TIM interrupt source to check. + * TIM_IT_Update - TIM update Interrupt source. + * TIM_IT_CC1 - TIM Capture Compare 1 Interrupt source. + * TIM_IT_CC2 - TIM Capture Compare 2 Interrupt source. + * TIM_IT_CC3 - TIM Capture Compare 3 Interrupt source. + * TIM_IT_CC4 - TIM Capture Compare 4 Interrupt source. + * TIM_IT_COM - TIM Commutation Interrupt source. + * TIM_IT_Trigger - TIM Trigger Interrupt source. + * TIM_IT_Break - TIM Break Interrupt source. + * + * @return none + */ +void TIM_ClearITPendingBit(TIM_TypeDef *TIMx, uint16_t TIM_IT) +{ + TIMx->INTFR = (uint16_t)~TIM_IT; +} + +/********************************************************************* + * @fn TI1_Config + * + * @brief Configure the TI1 as Input. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * IM_ICPolarity - The Input Polarity. + * TIM_ICPolarity_Rising. + * TIM_ICPolarity_Falling. + * TIM_ICSelection - specifies the input to be used. + * TIM_ICSelection_DirectTI - TIM Input 1 is selected to be + * connected to IC1. + * TIM_ICSelection_IndirectTI - TIM Input 1 is selected to be + * connected to IC2. + * TIM_ICSelection_TRC - TIM Input 1 is selected to be connected + * to TRC. + * TIM_ICFilter - Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * + * @return none + */ +static void TI1_Config(TIM_TypeDef *TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, + uint16_t TIM_ICFilter) +{ + uint16_t tmpccmr1 = 0, tmpccer = 0; + + TIMx->CCER &= (uint16_t) ~((uint16_t)TIM_CC1E); + tmpccmr1 = TIMx->CHCTLR1; + tmpccer = TIMx->CCER; + tmpccmr1 &= (uint16_t)(((uint16_t) ~((uint16_t)TIM_CC1S)) & ((uint16_t) ~((uint16_t)TIM_IC1F))); + tmpccmr1 |= (uint16_t)(TIM_ICSelection | (uint16_t)(TIM_ICFilter << (uint16_t)4)); + + if((TIMx == TIM1) || (TIMx == TIM2) || (TIMx == TIM3) || (TIMx == TIM4)) + { + tmpccer &= (uint16_t) ~((uint16_t)(TIM_CC1P)); + tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CC1E); + } + else + { + tmpccer &= (uint16_t) ~((uint16_t)(TIM_CC1P | TIM_CC1NP)); + tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CC1E); + } + + TIMx->CHCTLR1 = tmpccmr1; + TIMx->CCER = tmpccer; +} + +/********************************************************************* + * @fn TI2_Config + * + * @brief Configure the TI2 as Input. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * IM_ICPolarity - The Input Polarity. + * TIM_ICPolarity_Rising. + * TIM_ICPolarity_Falling. + * TIM_ICSelection - specifies the input to be used. + * TIM_ICSelection_DirectTI - TIM Input 1 is selected to be + * connected to IC1. + * TIM_ICSelection_IndirectTI - TIM Input 1 is selected to be + * connected to IC2. + * TIM_ICSelection_TRC - TIM Input 1 is selected to be connected + * to TRC. + * TIM_ICFilter - Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * + * @return none + */ +static void TI2_Config(TIM_TypeDef *TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, + uint16_t TIM_ICFilter) +{ + uint16_t tmpccmr1 = 0, tmpccer = 0, tmp = 0; + + TIMx->CCER &= (uint16_t) ~((uint16_t)TIM_CC2E); + tmpccmr1 = TIMx->CHCTLR1; + tmpccer = TIMx->CCER; + tmp = (uint16_t)(TIM_ICPolarity << 4); + tmpccmr1 &= (uint16_t)(((uint16_t) ~((uint16_t)TIM_CC2S)) & ((uint16_t) ~((uint16_t)TIM_IC2F))); + tmpccmr1 |= (uint16_t)(TIM_ICFilter << 12); + tmpccmr1 |= (uint16_t)(TIM_ICSelection << 8); + + if((TIMx == TIM1) || (TIMx == TIM2) || (TIMx == TIM3) || (TIMx == TIM4)) + { + tmpccer &= (uint16_t) ~((uint16_t)(TIM_CC2P)); + tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CC2E); + } + else + { + tmpccer &= (uint16_t) ~((uint16_t)(TIM_CC2P | TIM_CC2NP)); + tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CC2E); + } + + TIMx->CHCTLR1 = tmpccmr1; + TIMx->CCER = tmpccer; +} + +/********************************************************************* + * @fn TI3_Config + * + * @brief Configure the TI3 as Input. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * IM_ICPolarity - The Input Polarity. + * TIM_ICPolarity_Rising. + * TIM_ICPolarity_Falling. + * TIM_ICSelection - specifies the input to be used. + * TIM_ICSelection_DirectTI - TIM Input 1 is selected to be + * connected to IC1. + * TIM_ICSelection_IndirectTI - TIM Input 1 is selected to be + * connected to IC2. + * TIM_ICSelection_TRC - TIM Input 1 is selected to be connected + * to TRC. + * TIM_ICFilter - Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * + * @return none + */ +static void TI3_Config(TIM_TypeDef *TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, + uint16_t TIM_ICFilter) +{ + uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0; + + TIMx->CCER &= (uint16_t) ~((uint16_t)TIM_CC3E); + tmpccmr2 = TIMx->CHCTLR2; + tmpccer = TIMx->CCER; + tmp = (uint16_t)(TIM_ICPolarity << 8); + tmpccmr2 &= (uint16_t)(((uint16_t) ~((uint16_t)TIM_CC3S)) & ((uint16_t) ~((uint16_t)TIM_IC3F))); + tmpccmr2 |= (uint16_t)(TIM_ICSelection | (uint16_t)(TIM_ICFilter << (uint16_t)4)); + + if((TIMx == TIM1) || (TIMx == TIM2) || (TIMx == TIM3) || (TIMx == TIM4)) + { + tmpccer &= (uint16_t) ~((uint16_t)(TIM_CC3P)); + tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CC3E); + } + else + { + tmpccer &= (uint16_t) ~((uint16_t)(TIM_CC3P | TIM_CC3NP)); + tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CC3E); + } + + TIMx->CHCTLR2 = tmpccmr2; + TIMx->CCER = tmpccer; +} + +/********************************************************************* + * @fn TI4_Config + * + * @brief Configure the TI4 as Input. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * TIM_ICPolarity - The Input Polarity. + * TIM_ICPolarity_Rising. + * TIM_ICPolarity_Falling. + * TIM_ICSelection - specifies the input to be used. + * TIM_ICSelection_DirectTI - TIM Input 1 is selected to be + * connected to IC1. + * TIM_ICSelection_IndirectTI - TIM Input 1 is selected to be + * connected to IC2. + * TIM_ICSelection_TRC - TIM Input 1 is selected to be connected + * to TRC. + * TIM_ICFilter - Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * + * @return none + */ +static void TI4_Config(TIM_TypeDef *TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, + uint16_t TIM_ICFilter) +{ + uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0; + + TIMx->CCER &= (uint16_t) ~((uint16_t)TIM_CC4E); + tmpccmr2 = TIMx->CHCTLR2; + tmpccer = TIMx->CCER; + tmp = (uint16_t)(TIM_ICPolarity << 12); + tmpccmr2 &= (uint16_t)((uint16_t)(~(uint16_t)TIM_CC4S) & ((uint16_t) ~((uint16_t)TIM_IC4F))); + tmpccmr2 |= (uint16_t)(TIM_ICSelection << 8); + tmpccmr2 |= (uint16_t)(TIM_ICFilter << 12); + + if((TIMx == TIM1) || (TIMx == TIM2) || (TIMx == TIM3) || (TIMx == TIM4)) + { + tmpccer &= (uint16_t) ~((uint16_t)(TIM_CC4P)); + tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CC4E); + } + else + { + tmpccer &= (uint16_t) ~((uint16_t)(TIM_CC3P)); + tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CC4E); + } + + TIMx->CHCTLR2 = tmpccmr2; + TIMx->CCER = tmpccer; +} + +/********************************************************************* + * @fn TIM_CaptureLevelIndicate_Cmd + * + * @brief Enables or disables the TIMx Capture Level Indicate function. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void TIM_CaptureLevelIndicate_Cmd(TIM_TypeDef *TIMx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + TIMx->CTLR1 |= (1 << 15); + } + else + { + TIMx->CTLR1 &= ~(1 << 15); + } +} + +/********************************************************************* + * @fn TIM_CaptureModeConfig + * + * @brief Configures the TIMx capture mode. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * TIM_CaptureMode - the TIMx capture mode. + * TIM_Capture_Mode0 - When the counter overflows, capture count + * as actual count value. + * TIM_Capture_Mode1 - When the counter overflows, capture count + * as 0xFFFF. + * + * @return none + */ +void TIM_CaptureModeConfig(TIM_TypeDef *TIMx, uint16_t TIM_CaptureMode) +{ + TIMx->CTLR1 &= ~(TIM_Capture_Mode1); + + if(TIM_CaptureMode == TIM_Capture_Mode1) + { + TIMx->CTLR1 |= TIM_Capture_Mode1; + } +} diff --git a/ZDBMS/BMS_CC/Peripheral/src/ch32l103_usart.c b/ZDBMS/BMS_CC/Peripheral/src/ch32l103_usart.c new file mode 100644 index 0000000..07d0dca --- /dev/null +++ b/ZDBMS/BMS_CC/Peripheral/src/ch32l103_usart.c @@ -0,0 +1,816 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32l103_usart.c + * Author : WCH + * Version : V1.0.0 + * Date : 2023/07/08 + * Description : This file provides all the USART firmware functions. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#include "ch32l103_usart.h" +#include "ch32l103_rcc.h" + +/* USART_Private_Defines */ +#define CTLR1_UE_Set ((uint16_t)0x2000) /* USART Enable Mask */ +#define CTLR1_UE_Reset ((uint16_t)0xDFFF) /* USART Disable Mask */ + +#define CTLR1_WAKE_Mask ((uint16_t)0xF7FF) /* USART WakeUp Method Mask */ + +#define CTLR1_RWU_Set ((uint16_t)0x0002) /* USART mute mode Enable Mask */ +#define CTLR1_RWU_Reset ((uint16_t)0xFFFD) /* USART mute mode Enable Mask */ +#define CTLR1_SBK_Set ((uint16_t)0x0001) /* USART Break Character send Mask */ +#define CTLR1_CLEAR_Mask ((uint16_t)0xE9F3) /* USART CTLR1 Mask */ +#define CTLR2_Address_Mask ((uint16_t)0xFFF0) /* USART address Mask */ + +#define CTLR2_LINEN_Set ((uint16_t)0x4000) /* USART LIN Enable Mask */ +#define CTLR2_LINEN_Reset ((uint16_t)0xBFFF) /* USART LIN Disable Mask */ + +#define CTLR2_LBDL_Mask ((uint16_t)0xFFDF) /* USART LIN Break detection Mask */ +#define CTLR2_STOP_CLEAR_Mask ((uint16_t)0xCFFF) /* USART CTLR2 STOP Bits Mask */ +#define CTLR2_CLOCK_CLEAR_Mask ((uint16_t)0xF0FF) /* USART CTLR2 Clock Mask */ + +#define CTLR3_SCEN_Set ((uint16_t)0x0020) /* USART SC Enable Mask */ +#define CTLR3_SCEN_Reset ((uint16_t)0xFFDF) /* USART SC Disable Mask */ + +#define CTLR3_NACK_Set ((uint16_t)0x0010) /* USART SC NACK Enable Mask */ +#define CTLR3_NACK_Reset ((uint16_t)0xFFEF) /* USART SC NACK Disable Mask */ + +#define CTLR3_HDSEL_Set ((uint16_t)0x0008) /* USART Half-Duplex Enable Mask */ +#define CTLR3_HDSEL_Reset ((uint16_t)0xFFF7) /* USART Half-Duplex Disable Mask */ + +#define CTLR3_IRLP_Mask ((uint16_t)0xFFFB) /* USART IrDA LowPower mode Mask */ +#define CTLR3_CLEAR_Mask ((uint16_t)0xFCFF) /* USART CTLR3 Mask */ + +#define CTLR3_IREN_Set ((uint16_t)0x0002) /* USART IrDA Enable Mask */ +#define CTLR3_IREN_Reset ((uint16_t)0xFFFD) /* USART IrDA Disable Mask */ +#define GPR_LSB_Mask ((uint16_t)0x00FF) /* Guard Time Register LSB Mask */ +#define GPR_MSB_Mask ((uint16_t)0xFF00) /* Guard Time Register MSB Mask */ +#define IT_Mask ((uint16_t)0x001F) /* USART Interrupt Mask */ + +/* USART OverSampling-8 Mask */ +#define CTLR1_OVER8_Set ((uint16_t)0x8000) /* USART OVER8 mode Enable Mask */ +#define CTLR1_OVER8_Reset ((uint16_t)0x7FFF) /* USART OVER8 mode Disable Mask */ + +/* USART One Bit Sampling Mask */ +#define CTLR3_ONEBITE_Set ((uint16_t)0x0800) /* USART ONEBITE mode Enable Mask */ +#define CTLR3_ONEBITE_Reset ((uint16_t)0xF7FF) /* USART ONEBITE mode Disable Mask */ + +/********************************************************************* + * @fn USART_DeInit + * + * @brief Deinitializes the USARTx peripheral registers to their default + * reset values. + * + * @param USARTx - where x can be 1, 2, 3 or 4 to select the UART peripheral. + * + * @return none + */ +void USART_DeInit(USART_TypeDef *USARTx) +{ + if(USARTx == USART1) + { + RCC_PB2PeriphResetCmd(RCC_PB2Periph_USART1, ENABLE); + RCC_PB2PeriphResetCmd(RCC_PB2Periph_USART1, DISABLE); + } + else if(USARTx == USART2) + { + RCC_PB1PeriphResetCmd(RCC_PB1Periph_USART2, ENABLE); + RCC_PB1PeriphResetCmd(RCC_PB1Periph_USART2, DISABLE); + } + else if(USARTx == USART3) + { + RCC_PB1PeriphResetCmd(RCC_PB1Periph_USART3, ENABLE); + RCC_PB1PeriphResetCmd(RCC_PB1Periph_USART3, DISABLE); + } + else if(USARTx == USART4) + { + RCC_PB1PeriphResetCmd(RCC_PB1Periph_USART4, ENABLE); + RCC_PB1PeriphResetCmd(RCC_PB1Periph_USART4, DISABLE); + } +} + +/********************************************************************* + * @fn USART_Init + * + * @brief Initializes the USARTx peripheral according to the specified + * parameters in the USART_InitStruct. + * + * @param USARTx - where x can be 1, 2, 3 or 4 to select the UART peripheral. + * USART_InitStruct - pointer to a USART_InitTypeDef structure + * that contains the configuration information for the specified + * USART peripheral. + * + * @return none + */ +void USART_Init(USART_TypeDef *USARTx, USART_InitTypeDef *USART_InitStruct) +{ + uint32_t tmpreg = 0x00, PBclock = 0x00; + uint32_t integerdivider = 0x00; + uint32_t fractionaldivider = 0x00; + uint32_t usartxbase = 0; + RCC_ClocksTypeDef RCC_ClocksStatus; + + if(USART_InitStruct->USART_HardwareFlowControl != USART_HardwareFlowControl_None) + { + } + + usartxbase = (uint32_t)USARTx; + tmpreg = USARTx->CTLR2; + tmpreg &= CTLR2_STOP_CLEAR_Mask; + tmpreg |= (uint32_t)USART_InitStruct->USART_StopBits; + + USARTx->CTLR2 = (uint16_t)tmpreg; + tmpreg = USARTx->CTLR1; + tmpreg &= CTLR1_CLEAR_Mask; + tmpreg |= (uint32_t)USART_InitStruct->USART_WordLength | USART_InitStruct->USART_Parity | + USART_InitStruct->USART_Mode; + USARTx->CTLR1 = (uint16_t)tmpreg; + + tmpreg = USARTx->CTLR3; + tmpreg &= CTLR3_CLEAR_Mask; + tmpreg |= USART_InitStruct->USART_HardwareFlowControl; + USARTx->CTLR3 = (uint16_t)tmpreg; + + RCC_GetClocksFreq(&RCC_ClocksStatus); + + if(usartxbase == USART1_BASE) + { + PBclock = RCC_ClocksStatus.PCLK2_Frequency; + } + else + { + PBclock = RCC_ClocksStatus.PCLK1_Frequency; + } + + if((USARTx->CTLR1 & CTLR1_OVER8_Set) != 0) + { + integerdivider = ((25 * PBclock) / (2 * (USART_InitStruct->USART_BaudRate))); + } + else + { + integerdivider = ((25 * PBclock) / (4 * (USART_InitStruct->USART_BaudRate))); + } + tmpreg = (integerdivider / 100) << 4; + + fractionaldivider = integerdivider - (100 * (tmpreg >> 4)); + + if((USARTx->CTLR1 & CTLR1_OVER8_Set) != 0) + { + tmpreg |= ((((fractionaldivider * 8) + 50) / 100)) & ((uint8_t)0x07); + } + else + { + tmpreg |= ((((fractionaldivider * 16) + 50) / 100)) & ((uint8_t)0x0F); + } + + USARTx->BRR = (uint16_t)tmpreg; +} + +/********************************************************************* + * @fn USART_StructInit + * + * @brief Fills each USART_InitStruct member with its default value. + * + * @param USART_InitStruct: pointer to a USART_InitTypeDef structure + * which will be initialized. + * + * @return none + */ +void USART_StructInit(USART_InitTypeDef *USART_InitStruct) +{ + USART_InitStruct->USART_BaudRate = 9600; + USART_InitStruct->USART_WordLength = USART_WordLength_8b; + USART_InitStruct->USART_StopBits = USART_StopBits_1; + USART_InitStruct->USART_Parity = USART_Parity_No; + USART_InitStruct->USART_Mode = USART_Mode_Rx | USART_Mode_Tx; + USART_InitStruct->USART_HardwareFlowControl = USART_HardwareFlowControl_None; +} + +/********************************************************************* + * @fn USART_ClockInit + * + * @brief Initializes the USARTx peripheral Clock according to the + * specified parameters in the USART_ClockInitStruct . + * + * @param USARTx - where x can be 1, 2, 3 or 4 to select the USART peripheral. + * USART_ClockInitStruct - pointer to a USART_ClockInitTypeDef + * structure that contains the configuration information for the specified + * USART peripheral. + * + * @return none + */ +void USART_ClockInit(USART_TypeDef *USARTx, USART_ClockInitTypeDef *USART_ClockInitStruct) +{ + uint32_t tmpreg = 0x00; + + tmpreg = USARTx->CTLR2; + tmpreg &= CTLR2_CLOCK_CLEAR_Mask; + tmpreg |= (uint32_t)USART_ClockInitStruct->USART_Clock | USART_ClockInitStruct->USART_CPOL | + USART_ClockInitStruct->USART_CPHA | USART_ClockInitStruct->USART_LastBit; + USARTx->CTLR2 = (uint16_t)tmpreg; +} + +/********************************************************************* + * @fn USART_ClockStructInit + * + * @brief Fills each USART_ClockStructInit member with its default value. + * + * @param USART_ClockInitStruct - pointer to a USART_ClockInitTypeDef + * structure which will be initialized. + * + * @return none + */ +void USART_ClockStructInit(USART_ClockInitTypeDef *USART_ClockInitStruct) +{ + USART_ClockInitStruct->USART_Clock = USART_Clock_Disable; + USART_ClockInitStruct->USART_CPOL = USART_CPOL_Low; + USART_ClockInitStruct->USART_CPHA = USART_CPHA_1Edge; + USART_ClockInitStruct->USART_LastBit = USART_LastBit_Disable; +} + +/********************************************************************* + * @fn USART_Cmd + * + * @brief Enables or disables the specified USART peripheral. + * + * @param USARTx - where x can be 1, 2, 3 or 4 to select the USART peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void USART_Cmd(USART_TypeDef *USARTx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + USARTx->CTLR1 |= CTLR1_UE_Set; + } + else + { + USARTx->CTLR1 &= CTLR1_UE_Reset; + } +} + +/********************************************************************* + * @fn USART_ITConfig + * + * @brief Enables or disables the specified USART interrupts. + * reset values. + * + * @param USARTx - where x can be 1, 2, 3 or 4 to select the USART peripheral. + * USART_IT - specifies the USART interrupt sources to be enabled or disabled. + * USART_IT_LBD - LIN Break detection interrupt. + * USART_IT_TXE - Transmit Data Register empty interrupt. + * USART_IT_TC - Transmission complete interrupt. + * USART_IT_RXNE - Receive Data register not empty interrupt. + * USART_IT_IDLE - Idle line detection interrupt. + * USART_IT_PE - Parity Error interrupt. + * USART_IT_ERR - Error interrupt. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void USART_ITConfig(USART_TypeDef *USARTx, uint16_t USART_IT, FunctionalState NewState) +{ + uint32_t usartreg = 0x00, itpos = 0x00, itmask = 0x00; + uint32_t usartxbase = 0x00; + + usartxbase = (uint32_t)USARTx; + usartreg = (((uint8_t)USART_IT) >> 0x05); + itpos = USART_IT & IT_Mask; + itmask = (((uint32_t)0x01) << itpos); + + if(usartreg == 0x01) + { + usartxbase += 0x0C; + } + else if(usartreg == 0x02) + { + usartxbase += 0x10; + } + else + { + usartxbase += 0x14; + } + + if(NewState != DISABLE) + { + *(__IO uint32_t *)usartxbase |= itmask; + } + else + { + *(__IO uint32_t *)usartxbase &= ~itmask; + } +} + +/********************************************************************* + * @fn USART_DMACmd + * + * @brief Enables or disables the USART DMA interface. + * + * @param USARTx - where x can be 1, 2, 3 or 4 to select the USART peripheral. + * USART_DMAReq - specifies the DMA request. + * USART_DMAReq_Tx - USART DMA transmit request. + * USART_DMAReq_Rx - USART DMA receive request. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void USART_DMACmd(USART_TypeDef *USARTx, uint16_t USART_DMAReq, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + USARTx->CTLR3 |= USART_DMAReq; + } + else + { + USARTx->CTLR3 &= (uint16_t)~USART_DMAReq; + } +} + +/********************************************************************* + * @fn USART_SetAddress + * + * @brief Sets the address of the USART node. + * + * @param USARTx - where x can be 1, 2, 3 or 4 to select the USART peripheral. + * USART_Address - Indicates the address of the USART node. + * + * @return none + */ +void USART_SetAddress(USART_TypeDef *USARTx, uint8_t USART_Address) +{ + USARTx->CTLR2 &= CTLR2_Address_Mask; + USARTx->CTLR2 |= USART_Address; +} + +/********************************************************************* + * @fn USART_WakeUpConfig + * + * @brief Selects the USART WakeUp method. + * + * @param USARTx - where x can be 1, 2, 3 or 4 to select the USART peripheral. + * USART_WakeUp - specifies the USART wakeup method. + * USART_WakeUp_IdleLine - WakeUp by an idle line detection. + * USART_WakeUp_AddressMark - WakeUp by an address mark. + * + * @return none + */ +void USART_WakeUpConfig(USART_TypeDef *USARTx, uint16_t USART_WakeUp) +{ + USARTx->CTLR1 &= CTLR1_WAKE_Mask; + USARTx->CTLR1 |= USART_WakeUp; +} + +/********************************************************************* + * @fn USART_ReceiverWakeUpCmd + * + * @brief Determines if the USART is in mute mode or not. + * + * @param USARTx - where x can be 1, 2, 3 or 4 to select the USART peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void USART_ReceiverWakeUpCmd(USART_TypeDef *USARTx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + USARTx->CTLR1 |= CTLR1_RWU_Set; + } + else + { + USARTx->CTLR1 &= CTLR1_RWU_Reset; + } +} + +/********************************************************************* + * @fn USART_LINBreakDetectLengthConfig + * + * @brief Sets the USART LIN Break detection length. + * + * @param USARTx - where x can be 1, 2, 3 or 4 to select the USART peripheral. + * USART_LINBreakDetectLength - specifies the LIN break detection length. + * USART_LINBreakDetectLength_10b - 10-bit break detection. + * USART_LINBreakDetectLength_11b - 11-bit break detection. + * + * @return none + */ +void USART_LINBreakDetectLengthConfig(USART_TypeDef *USARTx, uint16_t USART_LINBreakDetectLength) +{ + USARTx->CTLR2 &= CTLR2_LBDL_Mask; + USARTx->CTLR2 |= USART_LINBreakDetectLength; +} + +/********************************************************************* + * @fn USART_LINCmd + * + * @brief Enables or disables the USART LIN mode. + * + * @param USARTx - where x can be 1, 2, 3 or 4 to select the USART peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void USART_LINCmd(USART_TypeDef *USARTx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + USARTx->CTLR2 |= CTLR2_LINEN_Set; + } + else + { + USARTx->CTLR2 &= CTLR2_LINEN_Reset; + } +} + +/********************************************************************* + * @fn USART_SendData + * + * @brief Transmits single data through the USARTx peripheral. + * + * @param USARTx - where x can be 1, 2, 3 or 4 to select the USART peripheral. + * Data - the data to transmit. + * + * @return none + */ +void USART_SendData(USART_TypeDef *USARTx, uint16_t Data) +{ + USARTx->DATAR = (Data & (uint16_t)0x01FF); +} + +/********************************************************************* + * @fn USART_ReceiveData + * + * @brief Returns the most recent received data by the USARTx peripheral. + * + * @param USARTx - where x can be 1, 2, 3 or 4 to select the USART peripheral. + * + * @return The received data. + */ +uint16_t USART_ReceiveData(USART_TypeDef *USARTx) +{ + return (uint16_t)(USARTx->DATAR & (uint16_t)0x01FF); +} + +/********************************************************************* + * @fn USART_SendBreak + * + * @brief Transmits break characters. + * + * @param USARTx - where x can be 1, 2, 3 or 4 to select the USART peripheral. + * + * @return none + */ +void USART_SendBreak(USART_TypeDef *USARTx) +{ + USARTx->CTLR1 |= CTLR1_SBK_Set; +} + +/********************************************************************* + * @fn USART_SetGuardTime + * + * @brief Sets the specified USART guard time. + * + * @param USARTx - where x can be 1, 2, 3 or 4 to select the USART peripheral. + * USART_GuardTime - specifies the guard time. + * + * @return none + */ +void USART_SetGuardTime(USART_TypeDef *USARTx, uint8_t USART_GuardTime) +{ + USARTx->GPR &= GPR_LSB_Mask; + USARTx->GPR |= (uint16_t)((uint16_t)USART_GuardTime << 0x08); +} + +/********************************************************************* + * @fn USART_SetPrescaler + * + * @brief Sets the system clock prescaler. + * + * @param USARTx - where x can be 1, 2, 3 or 4 to select the USART peripheral. + * USART_Prescaler - specifies the prescaler clock. + * + * @return none + */ +void USART_SetPrescaler(USART_TypeDef *USARTx, uint8_t USART_Prescaler) +{ + USARTx->GPR &= GPR_MSB_Mask; + USARTx->GPR |= USART_Prescaler; +} + +/********************************************************************* + * @fn USART_SmartCardCmd + * + * @brief Enables or disables the USART Smart Card mode. + * + * @param USARTx - where x can be 1, 2, 3 or 4 to select the USART peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void USART_SmartCardCmd(USART_TypeDef *USARTx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + USARTx->CTLR3 |= CTLR3_SCEN_Set; + } + else + { + USARTx->CTLR3 &= CTLR3_SCEN_Reset; + } +} + +/********************************************************************* + * @fn USART_SmartCardNACKCmd + * + * @brief Enables or disables NACK transmission. + * + * @param USARTx - where x can be 1, 2, 3 or 4 to select the USART peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void USART_SmartCardNACKCmd(USART_TypeDef *USARTx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + USARTx->CTLR3 |= CTLR3_NACK_Set; + } + else + { + USARTx->CTLR3 &= CTLR3_NACK_Reset; + } +} + +/********************************************************************* + * @fn USART_HalfDuplexCmd + * + * @brief Enables or disables the USART Half Duplex communication. + * + * @param USARTx - where x can be 1, 2, 3 or 4 to select the USART peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void USART_HalfDuplexCmd(USART_TypeDef *USARTx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + USARTx->CTLR3 |= CTLR3_HDSEL_Set; + } + else + { + USARTx->CTLR3 &= CTLR3_HDSEL_Reset; + } +} + +/********************************************************************* + * @fn USART_OverSampling8Cmd + * + * @brief Enables or disables the USART's 8x oversampling mode. + * + * @param USARTx - where x can be 1, 2, 3 or 4 to select the USART peripheral. + * NewState - ENABLE or DISABLE. + * Note- + * This function has to be called before calling USART_Init() + * function in order to have correct baudrate Divider value. + * @return none + */ +void USART_OverSampling8Cmd(USART_TypeDef *USARTx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + USARTx->CTLR1 |= CTLR1_OVER8_Set; + } + else + { + USARTx->CTLR1 &= CTLR1_OVER8_Reset; + } +} + +/********************************************************************* + * @fn USART_OneBitMethodCmd + * + * @brief Enables or disables the USART's one bit sampling method. + * + * @param USARTx - where x can be 1, 2, 3 or 4 to select the USART peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void USART_OneBitMethodCmd(USART_TypeDef *USARTx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + USARTx->CTLR3 |= CTLR3_ONEBITE_Set; + } + else + { + USARTx->CTLR3 &= CTLR3_ONEBITE_Reset; + } +} + +/********************************************************************* + * @fn USART_IrDAConfig + * + * @brief Configures the USART's IrDA interface. + * + * @param USARTx - where x can be 1, 2, 3 or 4 to select the USART peripheral. + * USART_IrDAMode - specifies the IrDA mode. + * USART_IrDAMode_LowPower. + * USART_IrDAMode_Normal. + * + * @return none + */ +void USART_IrDAConfig(USART_TypeDef *USARTx, uint16_t USART_IrDAMode) +{ + USARTx->CTLR3 &= CTLR3_IRLP_Mask; + USARTx->CTLR3 |= USART_IrDAMode; +} + +/********************************************************************* + * @fn USART_IrDACmd + * + * @brief Enables or disables the USART's IrDA interface. + * + * @param USARTx - where x can be 1, 2, 3 or 4 to select the USART peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void USART_IrDACmd(USART_TypeDef *USARTx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + USARTx->CTLR3 |= CTLR3_IREN_Set; + } + else + { + USARTx->CTLR3 &= CTLR3_IREN_Reset; + } +} + +/********************************************************************* + * @fn USART_GetFlagStatus + * + * @brief Checks whether the specified USART flag is set or not. + * + * @param USARTx - where x can be 1, 2, 3 or 4 to select the USART peripheral. + * USART_FLAG - specifies the flag to check. + * USART_FLAG_RX_BUSY - Receive data busy flag. + * USART_FLAG_CTS - CTS state detection flag. + * USART_FLAG_LBD - LIN Break detection flag. + * USART_FLAG_TXE - Transmit data register empty flag. + * USART_FLAG_TC - Transmission Complete flag. + * USART_FLAG_RXNE - Receive data register not empty flag. + * USART_FLAG_IDLE - Idle Line detection flag. + * USART_FLAG_ORE - OverRun Error flag. + * USART_FLAG_NE - Noise Error flag. + * USART_FLAG_FE - Framing Error flag. + * USART_FLAG_PE - Parity Error flag. + * + * @return bitstatus: SET or RESET + */ +FlagStatus USART_GetFlagStatus(USART_TypeDef *USARTx, uint16_t USART_FLAG) +{ + FlagStatus bitstatus = RESET; + + + if((USARTx->STATR & USART_FLAG) != (uint16_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn USART_ClearFlag + * + * @brief Clears the USARTx's pending flags. + * + * @param USARTx - where x can be 1, 2, 3 or 4 to select the USART peripheral. + * USART_FLAG - specifies the flag to clear. + * USART_FLAG_CTS - CTS state detection flag. + * USART_FLAG_LBD - LIN Break detection flag. + * USART_FLAG_TC - Transmission Complete flag. + * USART_FLAG_RXNE - Receive data register not empty flag. + * Note- + * - PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun + * error) and IDLE (Idle line detected) flags are cleared by software + * sequence: a read operation to USART_STATR register (USART_GetFlagStatus()) + * followed by a read operation to USART_DATAR register (USART_ReceiveData()). + * - RXNE flag can be also cleared by a read to the USART_DATAR register + * (USART_ReceiveData()). + * - TC flag can be also cleared by software sequence: a read operation to + * USART_STATR register (USART_GetFlagStatus()) followed by a write operation + * to USART_DATAR register (USART_SendData()). + * - TXE flag is cleared only by a write to the USART_DATAR register + * (USART_SendData()). + * @return none + */ +void USART_ClearFlag(USART_TypeDef *USARTx, uint16_t USART_FLAG) +{ + USARTx->STATR = (uint16_t)~USART_FLAG; +} + +/********************************************************************* + * @fn USART_GetITStatus + * + * @brief Checks whether the specified USART interrupt has occurred or not. + * + * @param USARTx - where x can be 1, 2, 3 or 4 to select the USART peripheral. + * USART_IT - specifies the USART interrupt source to check. + * USART_IT_CTS - CTS state detection interrupt. + * USART_IT_LBD - LIN Break detection interrupt. + * USART_IT_TXE - Tansmit Data Register empty interrupt. + * USART_IT_TC - Transmission complete interrupt. + * USART_IT_RXNE - Receive Data register not empty interrupt. + * USART_IT_IDLE - Idle line detection interrupt. + * USART_IT_ORE_RX - OverRun Error interrupt if the RXNEIE bit is set. + * USART_IT_ORE_ER - OverRun Error interrupt if the EIE bit is set. + * USART_IT_NE - Noise Error interrupt. + * USART_IT_FE - Framing Error interrupt. + * USART_IT_PE - Parity Error interrupt. + * + * @return bitstatus - SET or RESET. + */ +ITStatus USART_GetITStatus(USART_TypeDef *USARTx, uint16_t USART_IT) +{ + uint32_t bitpos = 0x00, itmask = 0x00, usartreg = 0x00; + ITStatus bitstatus = RESET; + + usartreg = (((uint8_t)USART_IT) >> 0x05); + itmask = USART_IT & IT_Mask; + itmask = (uint32_t)0x01 << itmask; + + if(usartreg == 0x01) + { + itmask &= USARTx->CTLR1; + } + else if(usartreg == 0x02) + { + itmask &= USARTx->CTLR2; + } + else + { + itmask &= USARTx->CTLR3; + } + + bitpos = USART_IT >> 0x08; + bitpos = (uint32_t)0x01 << bitpos; + bitpos &= USARTx->STATR; + + if((itmask != (uint16_t)RESET) && (bitpos != (uint16_t)RESET)) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn USART_ClearITPendingBit + * + * @brief Clears the USARTx's interrupt pending bits. + * + * @param USARTx - where x can be 1, 2, 3 or 4 to select the USART peripheral. + * USART_IT - specifies the interrupt pending bit to clear. + * USART_IT_CTS - CTS state detection interrupt. + * USART_IT_LBD - LIN Break detection interrupt. + * USART_IT_TC - Transmission complete interrupt. + * USART_IT_RXNE - Receive Data register not empty interrupt. + * Note- + * - PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun + * error) and IDLE (Idle line detected) pending bits are cleared by + * software sequence: a read operation to USART_STATR register + * (USART_GetITStatus()) followed by a read operation to USART_DATAR register + * (USART_ReceiveData()). + * - RXNE pending bit can be also cleared by a read to the USART_DATAR register + * (USART_ReceiveData()). + * - TC pending bit can be also cleared by software sequence: a read + * operation to USART_STATR register (USART_GetITStatus()) followed by a write + * operation to USART_DATAR register (USART_SendData()). + * - TXE pending bit is cleared only by a write to the USART_DATAR register + * (USART_SendData()). + * + * @return none + */ +void USART_ClearITPendingBit(USART_TypeDef *USARTx, uint16_t USART_IT) +{ + uint16_t bitpos = 0x00, itmask = 0x00; + + bitpos = USART_IT >> 0x08; + itmask = ((uint16_t)0x01 << (uint16_t)bitpos); + USARTx->STATR = (uint16_t)~itmask; +} diff --git a/ZDBMS/BMS_CC/Peripheral/src/ch32l103_wwdg.c b/ZDBMS/BMS_CC/Peripheral/src/ch32l103_wwdg.c new file mode 100644 index 0000000..566a71c --- /dev/null +++ b/ZDBMS/BMS_CC/Peripheral/src/ch32l103_wwdg.c @@ -0,0 +1,142 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32l103_wwdg.c + * Author : WCH + * Version : V1.0.0 + * Date : 2023/07/08 + * Description : This file provides all the WWDG firmware functions. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#include "ch32l103_wwdg.h" +#include "ch32l103_rcc.h" + +/* CTLR register bit mask */ +#define CTLR_WDGA_Set ((uint32_t)0x00000080) + +/* CFGR register bit mask */ +#define CFGR_WDGTB_Mask ((uint32_t)0xFFFFFE7F) +#define CFGR_W_Mask ((uint32_t)0xFFFFFF80) +#define BIT_Mask ((uint8_t)0x7F) + +/********************************************************************* + * @fn WWDG_DeInit + * + * @brief Deinitializes the WWDG peripheral registers to their default reset values + * + * @return none + */ +void WWDG_DeInit(void) +{ + RCC_PB1PeriphResetCmd(RCC_PB1Periph_WWDG, ENABLE); + RCC_PB1PeriphResetCmd(RCC_PB1Periph_WWDG, DISABLE); +} + +/********************************************************************* + * @fn WWDG_SetPrescaler + * + * @brief Sets the WWDG Prescaler + * + * @param WWDG_Prescaler - specifies the WWDG Prescaler + * WWDG_Prescaler_1 - WWDG counter clock = (PCLK1/4096)/1 + * WWDG_Prescaler_2 - WWDG counter clock = (PCLK1/4096)/2 + * WWDG_Prescaler_4 - WWDG counter clock = (PCLK1/4096)/4 + * WWDG_Prescaler_8 - WWDG counter clock = (PCLK1/4096)/8 + * + * @return none + */ +void WWDG_SetPrescaler(uint32_t WWDG_Prescaler) +{ + uint32_t tmpreg = 0; + tmpreg = WWDG->CFGR & CFGR_WDGTB_Mask; + tmpreg |= WWDG_Prescaler; + WWDG->CFGR = tmpreg; +} + +/********************************************************************* + * @fn WWDG_SetWindowValue + * + * @brief Sets the WWDG window value + * + * @param WindowValue - specifies the window value to be compared to the + * downcounter,which must be lower than 0x80 + * + * @return none + */ +void WWDG_SetWindowValue(uint8_t WindowValue) +{ + __IO uint32_t tmpreg = 0; + + tmpreg = WWDG->CFGR & CFGR_W_Mask; + + tmpreg |= WindowValue & (uint32_t)BIT_Mask; + + WWDG->CFGR = tmpreg; +} + +/********************************************************************* + * @fn WWDG_EnableIT + * + * @brief Enables the WWDG Early Wakeup interrupt(EWI) + * + * @return none + */ +void WWDG_EnableIT(void) +{ + WWDG->CFGR |= (1 << 9); +} + +/********************************************************************* + * @fn WWDG_SetCounter + * + * @brief Sets the WWDG counter value + * + * @param Counter - specifies the watchdog counter value,which must be a + * number between 0x40 and 0x7F + * + * @return none + */ +void WWDG_SetCounter(uint8_t Counter) +{ + WWDG->CTLR = Counter & BIT_Mask; +} + +/********************************************************************* + * @fn WWDG_Enable + * + * @brief Enables WWDG and load the counter value + * + * @param Counter - specifies the watchdog counter value,which must be a + * number between 0x40 and 0x7F + * + * @return none + */ +void WWDG_Enable(uint8_t Counter) +{ + WWDG->CTLR = CTLR_WDGA_Set | Counter; +} + +/********************************************************************* + * @fn WWDG_GetFlagStatus + * + * @brief Checks whether the Early Wakeup interrupt flag is set or not + * + * @return The new state of the Early Wakeup interrupt flag (SET or RESET) + */ +FlagStatus WWDG_GetFlagStatus(void) +{ + return (FlagStatus)(WWDG->STATR); +} + +/********************************************************************* + * @fn WWDG_ClearFlag + * + * @brief Clears Early Wakeup interrupt flag + * + * @return none + */ +void WWDG_ClearFlag(void) +{ + WWDG->STATR = (uint32_t)RESET; +} diff --git a/ZDBMS/BMS_CC/Startup/startup_ch32l103.S b/ZDBMS/BMS_CC/Startup/startup_ch32l103.S new file mode 100644 index 0000000..fbe5f97 --- /dev/null +++ b/ZDBMS/BMS_CC/Startup/startup_ch32l103.S @@ -0,0 +1,269 @@ +;/********************************** (C) COPYRIGHT ******************************* +;* File Name : startup_ch32l103.s +;* Author : WCH +;* Version : V1.0.0 +;* Date : 2024/05/06 +;* Description : CH32L103 vector table for eclipse toolchain. +;********************************************************************************* +;* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +;* Attention: This software (modified or not) and binary are used for +;* microcontroller manufactured by Nanjing Qinheng Microelectronics. +;*******************************************************************************/ + + .section .init,"ax",@progbits + .global _start + .align 1 +_start: + j handle_reset + + .section .vector,"ax",@progbits + .align 1 +_vector_base: + .option norvc; + .word _start + .word 0 + .word NMI_Handler /* NMI */ + .word HardFault_Handler /* Hard Fault */ + .word 0 + .word Ecall_M_Mode_Handler /* Ecall M Mode */ + .word 0 + .word 0 + .word Ecall_U_Mode_Handler /* Ecall U Mode */ + .word Break_Point_Handler /* Break Point */ + .word 0 + .word 0 + .word SysTick_Handler /* SysTick */ + .word 0 + .word SW_Handler /* SW */ + .word 0 + /* External Interrupts */ + .word WWDG_IRQHandler /* Window Watchdog */ + .word PVD_IRQHandler /* PVD through EXTI Line detect */ + .word TAMPER_IRQHandler /* TAMPER */ + .word RTC_IRQHandler /* RTC */ + .word FLASH_IRQHandler /* Flash */ + .word RCC_IRQHandler /* RCC */ + .word EXTI0_IRQHandler /* EXTI Line 0 */ + .word EXTI1_IRQHandler /* EXTI Line 1 */ + .word EXTI2_IRQHandler /* EXTI Line 2 */ + .word EXTI3_IRQHandler /* EXTI Line 3 */ + .word EXTI4_IRQHandler /* EXTI Line 4 */ + .word DMA1_Channel1_IRQHandler /* DMA1 Channel 1 */ + .word DMA1_Channel2_IRQHandler /* DMA1 Channel 2 */ + .word DMA1_Channel3_IRQHandler /* DMA1 Channel 3 */ + .word DMA1_Channel4_IRQHandler /* DMA1 Channel 4 */ + .word DMA1_Channel5_IRQHandler /* DMA1 Channel 5 */ + .word DMA1_Channel6_IRQHandler /* DMA1 Channel 6 */ + .word DMA1_Channel7_IRQHandler /* DMA1 Channel 7 */ + .word ADC_IRQHandler /* ADC */ + .word USB_HP_CAN1_TX_IRQHandler /* USB HP and CAN1 TX */ + .word USB_LP_CAN1_RX0_IRQHandler /* USB LP and CAN1RX0 */ + .word CAN1_RX1_IRQHandler /* CAN1 RX1 */ + .word CAN1_SCE_IRQHandler /* CAN1 SCE */ + .word EXTI9_5_IRQHandler /* EXTI Line 9..5 */ + .word TIM1_BRK_IRQHandler /* TIM1 Break */ + .word TIM1_UP_IRQHandler /* TIM1 Update */ + .word TIM1_TRG_COM_IRQHandler /* TIM1 Trigger and Commutation */ + .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */ + .word TIM2_IRQHandler /* TIM2 */ + .word TIM3_IRQHandler /* TIM3 */ + .word TIM4_IRQHandler /* TIM4 */ + .word I2C1_EV_IRQHandler /* I2C1 Event */ + .word I2C1_ER_IRQHandler /* I2C1 Error */ + .word I2C2_EV_IRQHandler /* I2C2 Event */ + .word I2C2_ER_IRQHandler /* I2C2 Error */ + .word SPI1_IRQHandler /* SPI1 */ + .word SPI2_IRQHandler /* SPI2 */ + .word USART1_IRQHandler /* USART1 */ + .word USART2_IRQHandler /* USART2 */ + .word USART3_IRQHandler /* USART3 */ + .word EXTI15_10_IRQHandler /* EXTI Line 15..10 */ + .word RTCAlarm_IRQHandler /* RTC Alarm through EXTI Line */ + .word LPTIMWakeUp_IRQHandler /* LPTIM Wake up */ + .word USBFS_IRQHandler /* USBFS Break */ + .word USBFSWakeUp_IRQHandler /* USBFS Wake up from suspend */ + .word USART4_IRQHandler /* USART4 */ + .word DMA1_Channel8_IRQHandler /* DMA1 Channel8 */ + .word LPTIM_IRQHandler /* LPTIM */ + .word OPA_IRQHandler /* OPA */ + .word USBPD_IRQHandler /* USBPD */ + .word 0 + .word USBPDWakeUp_IRQHandler /* USBPD Wake Up */ + .word CMPWakeUp_IRQHandler /* CMP Wake Up */ + + .option rvc; + .section .text.vector_handler, "ax", @progbits + .weak NMI_Handler /* NMI */ + .weak HardFault_Handler /* Hard Fault */ + .weak Ecall_M_Mode_Handler /* Ecall M Mode */ + .weak Ecall_U_Mode_Handler /* Ecall U Mode */ + .weak Break_Point_Handler /* Break Point */ + .weak SysTick_Handler /* SysTick */ + .weak SW_Handler /* SW */ + .weak WWDG_IRQHandler /* Window Watchdog */ + .weak PVD_IRQHandler /* PVD through EXTI Line detect */ + .weak TAMPER_IRQHandler /* TAMPER */ + .weak RTC_IRQHandler /* RTC */ + .weak FLASH_IRQHandler /* Flash */ + .weak RCC_IRQHandler /* RCC */ + .weak EXTI0_IRQHandler /* EXTI Line 0 */ + .weak EXTI1_IRQHandler /* EXTI Line 1 */ + .weak EXTI2_IRQHandler /* EXTI Line 2 */ + .weak EXTI3_IRQHandler /* EXTI Line 3 */ + .weak EXTI4_IRQHandler /* EXTI Line 4 */ + .weak DMA1_Channel1_IRQHandler /* DMA1 Channel 1 */ + .weak DMA1_Channel2_IRQHandler /* DMA1 Channel 2 */ + .weak DMA1_Channel3_IRQHandler /* DMA1 Channel 3 */ + .weak DMA1_Channel4_IRQHandler /* DMA1 Channel 4 */ + .weak DMA1_Channel5_IRQHandler /* DMA1 Channel 5 */ + .weak DMA1_Channel6_IRQHandler /* DMA1 Channel 6 */ + .weak DMA1_Channel7_IRQHandler /* DMA1 Channel 7 */ + .weak ADC_IRQHandler /* ADC */ + .weak USB_HP_CAN1_TX_IRQHandler /* USB HP and CAN1 TX */ + .weak USB_LP_CAN1_RX0_IRQHandler /* USB LP and CAN1RX0 */ + .weak CAN1_RX1_IRQHandler /* CAN1 RX1 */ + .weak CAN1_SCE_IRQHandler /* CAN1 SCE */ + .weak EXTI9_5_IRQHandler /* EXTI Line 9..5 */ + .weak TIM1_BRK_IRQHandler /* TIM1 Break */ + .weak TIM1_UP_IRQHandler /* TIM1 Update */ + .weak TIM1_TRG_COM_IRQHandler /* TIM1 Trigger and Commutation */ + .weak TIM1_CC_IRQHandler /* TIM1 Capture Compare */ + .weak TIM2_IRQHandler /* TIM2 */ + .weak TIM3_IRQHandler /* TIM3 */ + .weak TIM4_IRQHandler /* TIM4 */ + .weak I2C1_EV_IRQHandler /* I2C1 Event */ + .weak I2C1_ER_IRQHandler /* I2C1 Error */ + .weak I2C2_EV_IRQHandler /* I2C2 Event */ + .weak I2C2_ER_IRQHandler /* I2C2 Error */ + .weak SPI1_IRQHandler /* SPI1 */ + .weak SPI2_IRQHandler /* SPI2 */ + .weak USART1_IRQHandler /* USART1 */ + .weak USART2_IRQHandler /* USART2 */ + .weak USART3_IRQHandler /* USART3 */ + .weak EXTI15_10_IRQHandler /* EXTI Line 15..10 */ + .weak RTCAlarm_IRQHandler /* RTC Alarm through EXTI Line */ + .weak LPTIMWakeUp_IRQHandler /* LPTIM Wake up */ + .weak USBFS_IRQHandler /* USBFS */ + .weak USBFSWakeUp_IRQHandler /* USBFS Wake Up */ + .weak USART4_IRQHandler /* USART4 */ + .weak DMA1_Channel8_IRQHandler /* DMA1 Channel8 */ + .weak LPTIM_IRQHandler /* LPTIM */ + .weak OPA_IRQHandler /* OPA */ + .weak USBPD_IRQHandler /* USBPD */ + .weak USBPDWakeUp_IRQHandler /* USBPD Wake Up */ + .weak CMPWakeUp_IRQHandler /* CMP Wake Up */ + +NMI_Handler: +HardFault_Handler: +Ecall_M_Mode_Handler: +Ecall_U_Mode_Handler: +Break_Point_Handler: +SysTick_Handler: +SW_Handler: +WWDG_IRQHandler: +PVD_IRQHandler: +TAMPER_IRQHandler: +RTC_IRQHandler: +FLASH_IRQHandler: +RCC_IRQHandler: +EXTI0_IRQHandler: +EXTI1_IRQHandler: +EXTI2_IRQHandler: +EXTI3_IRQHandler: +EXTI4_IRQHandler: +DMA1_Channel1_IRQHandler: +DMA1_Channel2_IRQHandler: +DMA1_Channel3_IRQHandler: +DMA1_Channel4_IRQHandler: +DMA1_Channel5_IRQHandler: +DMA1_Channel6_IRQHandler: +DMA1_Channel7_IRQHandler: +ADC_IRQHandler: +USB_HP_CAN1_TX_IRQHandler: +USB_LP_CAN1_RX0_IRQHandler: +CAN1_RX1_IRQHandler: +CAN1_SCE_IRQHandler: +EXTI9_5_IRQHandler: +TIM1_BRK_IRQHandler: +TIM1_UP_IRQHandler: +TIM1_TRG_COM_IRQHandler: +TIM1_CC_IRQHandler: +TIM2_IRQHandler: +TIM3_IRQHandler: +TIM4_IRQHandler: +I2C1_EV_IRQHandler: +I2C1_ER_IRQHandler: +I2C2_EV_IRQHandler: +I2C2_ER_IRQHandler: +SPI1_IRQHandler: +SPI2_IRQHandler: +USART1_IRQHandler: +USART2_IRQHandler: +USART3_IRQHandler: +EXTI15_10_IRQHandler: +RTCAlarm_IRQHandler: +LPTIMWakeUp_IRQHandler: +USBFS_IRQHandler: +USBFSWakeUp_IRQHandler: +USART4_IRQHandler: +DMA1_Channel8_IRQHandler: +LPTIM_IRQHandler: +OPA_IRQHandler: +USBPD_IRQHandler: +USBPDWakeUp_IRQHandler: +CMPWakeUp_IRQHandler: +1: + j 1b + + .section .text.handle_reset,"ax",@progbits + .weak handle_reset + .align 1 +handle_reset: +.option push +.option norelax + la gp, __global_pointer$ +.option pop +1: + la sp, _eusrstack +2: +/* Load data section from flash to RAM */ + la a0, _data_lma + la a1, _data_vma + la a2, _edata + bgeu a1, a2, 2f +1: + lw t0, (a0) + sw t0, (a1) + addi a0, a0, 4 + addi a1, a1, 4 + bltu a1, a2, 1b +2: +/* Clear bss section */ + la a0, _sbss + la a1, _ebss + bgeu a0, a1, 2f +1: + sw zero, (a0) + addi a0, a0, 4 + bltu a0, a1, 1b +2: +/* Configure pipelining and instruction prediction */ + li t0, 0x1f + csrw 0xbc0, t0 +/* Enable interrupt nesting and hardware stack */ + li t0, 0x3 + csrw 0x804, t0 +/* Enable global interrupt and configure privileged mode */ + li t0, 0x88 + csrw mstatus, t0 +/* Configure the interrupt vector table recognition mode and entry address mode */ + la t0, _vector_base + ori t0, t0, 3 + csrw mtvec, t0 + + jal SystemInit + la t0, main + csrw mepc, t0 + mret + + diff --git a/ZDBMS/BMS_CC/User/ch32l103_conf.h b/ZDBMS/BMS_CC/User/ch32l103_conf.h new file mode 100644 index 0000000..70a29b3 --- /dev/null +++ b/ZDBMS/BMS_CC/User/ch32l103_conf.h @@ -0,0 +1,38 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32l103_conf.h + * Author : WCH + * Version : V1.0.0 + * Date : 2023/07/08 + * Description : Library configuration file. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#ifndef __CH32L103_CONF_H +#define __CH32L103_CONF_H + +#include "ch32l103_adc.h" +#include "ch32l103_bkp.h" +#include "ch32l103_can.h" +#include "ch32l103_crc.h" +#include "ch32l103_dbgmcu.h" +#include "ch32l103_dma.h" +#include "ch32l103_exti.h" +#include "ch32l103_flash.h" +#include "ch32l103_gpio.h" +#include "ch32l103_i2c.h" +#include "ch32l103_iwdg.h" +#include "ch32l103_pwr.h" +#include "ch32l103_rcc.h" +#include "ch32l103_rtc.h" +#include "ch32l103_spi.h" +#include "ch32l103_tim.h" +#include "ch32l103_usart.h" +#include "ch32l103_wwdg.h" +#include "ch32l103_it.h" +#include "ch32l103_misc.h" +#include "ch32l103_lptim.h" +#include "ch32l103_opa.h" + +#endif diff --git a/ZDBMS/BMS_CC/User/ch32l103_it.c b/ZDBMS/BMS_CC/User/ch32l103_it.c new file mode 100644 index 0000000..7a8f132 --- /dev/null +++ b/ZDBMS/BMS_CC/User/ch32l103_it.c @@ -0,0 +1,47 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32l103_it.c + * Author : WCH + * Version : V1.0.0 + * Date : 2024/10/30 + * Description : Main Interrupt Service Routines. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#include "ch32l103_it.h" + +void NMI_Handler(void) __attribute__((interrupt("WCH-Interrupt-fast"))); +void HardFault_Handler(void) __attribute__((interrupt("WCH-Interrupt-fast"))); + +/********************************************************************* + * @fn NMI_Handler + * + * @brief This function handles NMI exception. + * + * @return none + */ +void NMI_Handler(void) +{ + while (1) + { + } +} + + +/********************************************************************* + * @fn HardFault_Handler + * + * @brief This function handles Hard Fault exception. + * + * @return none + */ +void HardFault_Handler(void) +{ + NVIC_SystemReset(); + while (1) + { + } +} + + diff --git a/ZDBMS/BMS_CC/User/ch32l103_it.h b/ZDBMS/BMS_CC/User/ch32l103_it.h new file mode 100644 index 0000000..9b40759 --- /dev/null +++ b/ZDBMS/BMS_CC/User/ch32l103_it.h @@ -0,0 +1,17 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32l103_it.h + * Author : WCH + * Version : V1.0.0 + * Date : 2023/07/08 + * Description : This file contains the headers of the interrupt handlers. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#ifndef __CH32L103_IT_H +#define __CH32L103_IT_H + +#include "debug.h" + +#endif diff --git a/ZDBMS/BMS_CC/User/main.c b/ZDBMS/BMS_CC/User/main.c new file mode 100644 index 0000000..0009698 --- /dev/null +++ b/ZDBMS/BMS_CC/User/main.c @@ -0,0 +1,50 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : main.c + * Author : WCH + * Version : V1.0.0 + * Date : 2023/12/26 + * Description : Main program body. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ + +/* + *@Note + *USART Print debugging routine: + *USART1_Tx(PA9). + *This example demonstrates using USART1(PA9) as a print debug port output. + * + */ + +#include "debug.h" + +/* Global typedef */ + +/* Global define */ + +/* Global Variable */ + +/********************************************************************* + * @fn main + * + * @brief Main program. + * + * @return none + */ +int main(void) +{ + NVIC_PriorityGroupConfig(NVIC_PriorityGroup_1); + SystemCoreClockUpdate(); + Delay_Init(); + USART_Printf_Init(115200); + printf("SystemClk:%d\r\n", SystemCoreClock); + printf( "ChipID:%08x\r\n", DBGMCU_GetCHIPID() ); + + while(1) + { + Delay_Ms(1000); + printf("This is printf example cc\r\n"); + } +} diff --git a/ZDBMS/BMS_CC/User/system_ch32l103.c b/ZDBMS/BMS_CC/User/system_ch32l103.c new file mode 100644 index 0000000..73ec2c8 --- /dev/null +++ b/ZDBMS/BMS_CC/User/system_ch32l103.c @@ -0,0 +1,754 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : system_ch32l103.c + * Author : WCH + * Version : V1.0.0 + * Date : 2024/01/22 + * Description : Device Peripheral Access Layer System Source File. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#include "ch32l103.h" + +/* +* Uncomment the line corresponding to the desired System clock (SYSCLK) frequency (after +* reset the HSI is used as SYSCLK source). +* If none of the define below is enabled, the HSI is used as System clock source. +*/ +//#define SYSCLK_FREQ_HSE HSE_VALUE +//#define SYSCLK_FREQ_48MHz_HSE 48000000 +//#define SYSCLK_FREQ_56MHz_HSE 56000000 +//#define SYSCLK_FREQ_72MHz_HSE 72000000 +//#define SYSCLK_FREQ_96MHz_HSE 96000000 +//#define SYSCLK_FREQ_HSI HSI_VALUE +//#define SYSCLK_FREQ_48MHz_HSI 48000000 +//#define SYSCLK_FREQ_56MHz_HSI 56000000 +//#define SYSCLK_FREQ_72MHz_HSI 72000000 +#define SYSCLK_FREQ_96MHz_HSI 96000000 +//#define SYSCLK_FREQ_HSI_LP HSI_LP_VALUE /* Baud rate support less than 62.5Kbps when using UART */ + +/* Clock Definitions */ +#ifdef SYSCLK_FREQ_HSE +uint32_t SystemCoreClock = SYSCLK_FREQ_HSE; /* System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_48MHz_HSE +uint32_t SystemCoreClock = SYSCLK_FREQ_48MHz_HSE; /* System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_56MHz_HSE +uint32_t SystemCoreClock = SYSCLK_FREQ_56MHz_HSE; /* System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_72MHz_HSE +uint32_t SystemCoreClock = SYSCLK_FREQ_72MHz_HSE; /* System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_96MHz_HSE +uint32_t SystemCoreClock = SYSCLK_FREQ_96MHz_HSE; /* System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_48MHz_HSI +uint32_t SystemCoreClock = SYSCLK_FREQ_48MHz_HSI; /* System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_56MHz_HSI +uint32_t SystemCoreClock = SYSCLK_FREQ_56MHz_HSI; /* System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_72MHz_HSI +uint32_t SystemCoreClock = SYSCLK_FREQ_72MHz_HSI; /* System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_96MHz_HSI +uint32_t SystemCoreClock = SYSCLK_FREQ_96MHz_HSI; /* System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_HSI_LP +uint32_t SystemCoreClock = SYSCLK_FREQ_HSI_LP; /* System Clock Frequency (Core Clock) */ +#else +uint32_t SystemCoreClock = HSI_VALUE; /* System Clock Frequency (Core Clock) */ + +#endif + +__I uint8_t HBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; + + +/* system_private_function_proto_types */ +static void SetSysClock(void); + +#ifdef SYSCLK_FREQ_HSE +static void SetSysClockToHSE( void ); +#elif defined SYSCLK_FREQ_48MHz_HSE +static void SetSysClockTo48_HSE( void ); +#elif defined SYSCLK_FREQ_56MHz_HSE +static void SetSysClockTo56_HSE( void ); +#elif defined SYSCLK_FREQ_72MHz_HSE +static void SetSysClockTo72_HSE( void ); +#elif defined SYSCLK_FREQ_96MHz_HSE +static void SetSysClockTo96_HSE( void ); +#elif defined SYSCLK_FREQ_48MHz_HSI +static void SetSysClockTo48_HSI( void ); +#elif defined SYSCLK_FREQ_56MHz_HSI +static void SetSysClockTo56_HSI( void ); +#elif defined SYSCLK_FREQ_72MHz_HSI +static void SetSysClockTo72_HSI( void ); +#elif defined SYSCLK_FREQ_96MHz_HSI +static void SetSysClockTo96_HSI( void ); +#elif defined SYSCLK_FREQ_HSI_LP +static void SetSysClockToHSI_LP( void ); + +#endif + +/********************************************************************* + * @fn SystemInit + * + * @brief Setup the microcontroller system Initialize the Embedded Flash Interface, + * the PLL and update the SystemCoreClock variable. + * + * @return none + */ +void SystemInit (void) +{ + RCC->CTLR |= (uint32_t)0x00000001; + RCC->CFGR0 &= (uint32_t)0x08FF0000; + RCC->CTLR &= (uint32_t)0xFEF6FFFB; + RCC->CTLR &= (uint32_t)0xFFFBFFFF; + RCC->CFGR0 &= (uint32_t)0xFF00FFFF; + RCC->INTR = 0x009F0000; + SetSysClock(); +} + +/********************************************************************* + * @fn SystemCoreClockUpdate + * + * @brief Update SystemCoreClock variable according to Clock Register Values. + * + * @return none + */ +void SystemCoreClockUpdate (void) +{ + uint32_t tmp = 0, pllmull = 0, pllsource = 0; + + tmp = RCC->CFGR0 & RCC_SWS; + + switch (tmp) + { + case 0x00: + if(RCC->CTLR & (1<<2)) + { + SystemCoreClock = HSI_LP_VALUE; + } + else { + SystemCoreClock = HSI_VALUE; + } + break; + case 0x04: + SystemCoreClock = HSE_VALUE; + break; + case 0x08: + pllmull = RCC->CFGR0 & RCC_PLLMULL; + pllsource = RCC->CFGR0 & RCC_PLLSRC; + pllmull = ( pllmull >> 18) + 2; + + if(pllmull == 17) pllmull = 18; + + if (pllsource == 0x00) + { + if(EXTEN->EXTEN_CTR & EXTEN_PLL_HSI_PRE){ + SystemCoreClock = HSI_VALUE * pllmull; + } + else{ + SystemCoreClock = (HSI_VALUE >> 1) * pllmull; + } + } + else + { + if ((RCC->CFGR0 & RCC_PLLXTPRE) != (uint32_t)RESET) + { + SystemCoreClock = (HSE_VALUE >> 1) * pllmull; + } + else + { + SystemCoreClock = HSE_VALUE * pllmull; + } + } + + break; + default: + SystemCoreClock = HSI_VALUE; + break; + } + + tmp = HBPrescTable[((RCC->CFGR0 & RCC_HPRE) >> 4)]; + SystemCoreClock >>= tmp; +} + +/********************************************************************* + * @fn SetSysClock + * + * @brief Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers. + * + * @return none + */ +static void SetSysClock(void) +{ + GPIO_IPD_Unused(); + +#ifdef SYSCLK_FREQ_HSE + SetSysClockToHSE(); +#elif defined SYSCLK_FREQ_48MHz_HSE + SetSysClockTo48_HSE(); +#elif defined SYSCLK_FREQ_56MHz_HSE + SetSysClockTo56_HSE(); +#elif defined SYSCLK_FREQ_72MHz_HSE + SetSysClockTo72_HSE(); +#elif defined SYSCLK_FREQ_96MHz_HSE + SetSysClockTo96_HSE(); +#elif defined SYSCLK_FREQ_48MHz_HSI + SetSysClockTo48_HSI(); +#elif defined SYSCLK_FREQ_56MHz_HSI + SetSysClockTo56_HSI(); +#elif defined SYSCLK_FREQ_72MHz_HSI + SetSysClockTo72_HSI(); +#elif defined SYSCLK_FREQ_96MHz_HSI + SetSysClockTo96_HSI(); +#elif defined SYSCLK_FREQ_HSI_LP + SetSysClockToHSI_LP(); + +#endif + + /* If none of the define above is enabled, the HSI is used as System clock + * source (default after reset) + */ +} + + +#ifdef SYSCLK_FREQ_HSE + +/********************************************************************* + * @fn SetSysClockToHSE + * + * @brief Sets HSE as System clock source and configure HCLK, PCLK2 and PCLK1 prescalers. + * + * @return none + */ +static void SetSysClockToHSE(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* Flash 0 wait state */ + FLASH->ACTLR = (uint32_t)FLASH_ACTLR_LATENCY_0; + + RCC->CTLR |= ((uint32_t)RCC_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CTLR & RCC_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CTLR & RCC_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* HCLK = SYSCLK */ + RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; + /* PCLK2 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1; + /* PCLK1 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV1; + + /* Select HSE as system clock source */ + RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW)); + RCC->CFGR0 |= (uint32_t)RCC_SW_HSE; + + /* Wait till HSE is used as system clock source */ + while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x04) + { + } + } + else + { + /* Flash 0 wait state */ + FLASH->ACTLR &= (uint32_t)((uint32_t)~FLASH_ACTLR_LATENCY); + + /* If HSE fails to start-up, the application will have wrong clock + * configuration. User can add here some code to deal with this error + */ + } +} + +#elif defined SYSCLK_FREQ_48MHz_HSE + +/********************************************************************* + * @fn SetSysClockTo48_HSE + * + * @brief Sets System clock frequency to 48MHz and configure HCLK, PCLK2 and PCLK1 prescalers. + * + * @return none + */ +static void SetSysClockTo48_HSE(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* Flash 1 wait state */ + FLASH->ACTLR = (uint32_t)FLASH_ACTLR_LATENCY_1; + + RCC->CTLR |= ((uint32_t)RCC_HSEON); + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CTLR & RCC_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CTLR & RCC_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* HCLK = SYSCLK */ + RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; + /* PCLK2 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1; + /* PCLK1 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2; + + /* PLL configuration: PLLCLK = HSE * 6 = 48 MHz (HSE=8MHZ) */ + RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL)); + RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL6); + + /* Enable PLL */ + RCC->CTLR |= RCC_PLLON; + /* Wait till PLL is ready */ + while((RCC->CTLR & RCC_PLLRDY) == 0) + { + } + /* Select PLL as system clock source */ + RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW)); + RCC->CFGR0 |= (uint32_t)RCC_SW_PLL; + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08) + { + } + } + else + { + /* Flash 0 wait state */ + FLASH->ACTLR &= (uint32_t)((uint32_t)~FLASH_ACTLR_LATENCY); + + /* If HSE fails to start-up, the application will have wrong clock + * configuration. User can add here some code to deal with this error + */ + } +} + +#elif defined SYSCLK_FREQ_56MHz_HSE + +/********************************************************************* + * @fn SetSysClockTo56_HSE + * + * @brief Sets System clock frequency to 56MHz and configure HCLK, PCLK2 and PCLK1 prescalers. + * + * @return none + */ +static void SetSysClockTo56_HSE(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* Flash 1 wait state */ + FLASH->ACTLR = (uint32_t)FLASH_ACTLR_LATENCY_1; + + RCC->CTLR |= ((uint32_t)RCC_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CTLR & RCC_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CTLR & RCC_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* HCLK = SYSCLK */ + RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; + /* PCLK2 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1; + /* PCLK1 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2; + + /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz (HSE=8MHZ) */ + RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL)); + RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL7); + + /* Enable PLL */ + RCC->CTLR |= RCC_PLLON; + /* Wait till PLL is ready */ + while((RCC->CTLR & RCC_PLLRDY) == 0) + { + } + + /* Select PLL as system clock source */ + RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW)); + RCC->CFGR0 |= (uint32_t)RCC_SW_PLL; + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08) + { + } + } + else + { + /* Flash 0 wait state */ + FLASH->ACTLR &= (uint32_t)((uint32_t)~FLASH_ACTLR_LATENCY); + + /* If HSE fails to start-up, the application will have wrong clock + * configuration. User can add here some code to deal with this error + */ + } +} + +#elif defined SYSCLK_FREQ_72MHz_HSE + +/********************************************************************* + * @fn SetSysClockTo72_HSE + * + * @brief Sets System clock frequency to 72MHz and configure HCLK, PCLK2 and PCLK1 prescalers. + * + * @return none + */ +static void SetSysClockTo72_HSE(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* Flash 1 wait state */ + FLASH->ACTLR = (uint32_t)FLASH_ACTLR_LATENCY_1; + + RCC->CTLR |= ((uint32_t)RCC_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CTLR & RCC_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CTLR & RCC_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* HCLK = SYSCLK */ + RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; + /* PCLK2 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1; + /* PCLK1 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2; + + /* PLL configuration: PLLCLK = HSE * 9 = 72 MHz (HSE=8MHZ) */ + RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL)); + RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL9); + + /* Enable PLL */ + RCC->CTLR |= RCC_PLLON; + /* Wait till PLL is ready */ + while((RCC->CTLR & RCC_PLLRDY) == 0) + { + } + /* Select PLL as system clock source */ + RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW)); + RCC->CFGR0 |= (uint32_t)RCC_SW_PLL; + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08) + { + } + } + else + { + /* Flash 0 wait state */ + FLASH->ACTLR &= (uint32_t)((uint32_t)~FLASH_ACTLR_LATENCY); + + /* If HSE fails to start-up, the application will have wrong clock + * configuration. User can add here some code to deal with this error + */ + } +} + + +#elif defined SYSCLK_FREQ_96MHz_HSE + +/********************************************************************* + * @fn SetSysClockTo96_HSE + * + * @brief Sets System clock frequency to 96MHz and configure HCLK, PCLK2 and PCLK1 prescalers. + * + * @return none + */ +static void SetSysClockTo96_HSE(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* Flash 2 wait state */ + FLASH->ACTLR = (uint32_t)FLASH_ACTLR_LATENCY_2; + + RCC->CTLR |= ((uint32_t)RCC_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CTLR & RCC_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CTLR & RCC_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* HCLK = SYSCLK */ + RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; + /* PCLK2 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1; + /* PCLK1 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2; + + /* PLL configuration: PLLCLK = HSE * 12 = 96 MHz (HSE=8MHZ) */ + RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL)); + RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL12); + + /* Enable PLL */ + RCC->CTLR |= RCC_PLLON; + /* Wait till PLL is ready */ + while((RCC->CTLR & RCC_PLLRDY) == 0) + { + } + /* Select PLL as system clock source */ + RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW)); + RCC->CFGR0 |= (uint32_t)RCC_SW_PLL; + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08) + { + } + } + else + { + /* Flash 0 wait state */ + FLASH->ACTLR &= (uint32_t)((uint32_t)~FLASH_ACTLR_LATENCY); + + /* If HSE fails to start-up, the application will have wrong clock + * configuration. User can add here some code to deal with this error + */ + } +} + +#elif defined SYSCLK_FREQ_48MHz_HSI + +/********************************************************************* + * @fn SetSysClockTo48_HSI + * + * @brief Sets System clock frequency to 48MHz and configure HCLK, PCLK2 and PCLK1 prescalers. + * + * @return none + */ +static void SetSysClockTo48_HSI(void) +{ + /* Flash 1 wait state */ + FLASH->ACTLR = (uint32_t)FLASH_ACTLR_LATENCY_1; + + EXTEN->EXTEN_CTR |= EXTEN_PLL_HSI_PRE; + + /* HCLK = SYSCLK */ + RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; + /* PCLK2 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1; + /* PCLK1 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2; + + /* PLL configuration: PLLCLK = HSI * 6 = 48 MHz */ + RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL)); + RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL6); + + /* Enable PLL */ + RCC->CTLR |= RCC_PLLON; + /* Wait till PLL is ready */ + while((RCC->CTLR & RCC_PLLRDY) == 0) + { + } + /* Select PLL as system clock source */ + RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW)); + RCC->CFGR0 |= (uint32_t)RCC_SW_PLL; + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08) + { + } +} + +#elif defined SYSCLK_FREQ_56MHz_HSI + +/********************************************************************* + * @fn SetSysClockTo56_HSI + * + * @brief Sets System clock frequency to 56MHz and configure HCLK, PCLK2 and PCLK1 prescalers. + * + * @return none + */ +static void SetSysClockTo56_HSI(void) +{ + /* Flash 1 wait state */ + FLASH->ACTLR = (uint32_t)FLASH_ACTLR_LATENCY_1; + + EXTEN->EXTEN_CTR |= EXTEN_PLL_HSI_PRE; + + /* HCLK = SYSCLK */ + RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; + /* PCLK2 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1; + /* PCLK1 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2; + + /* PLL configuration: PLLCLK = HSI * 7 = 56 MHz */ + RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL)); + RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL7); + + /* Enable PLL */ + RCC->CTLR |= RCC_PLLON; + /* Wait till PLL is ready */ + while((RCC->CTLR & RCC_PLLRDY) == 0) + { + } + /* Select PLL as system clock source */ + RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW)); + RCC->CFGR0 |= (uint32_t)RCC_SW_PLL; + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08) + { + } +} + +#elif defined SYSCLK_FREQ_72MHz_HSI + +/********************************************************************* + * @fn SetSysClockTo72_HSI + * + * @brief Sets System clock frequency to 72MHz and configure HCLK, PCLK2 and PCLK1 prescalers. + * + * @return none + */ +static void SetSysClockTo72_HSI(void) +{ + /* Flash 1 wait state */ + FLASH->ACTLR = (uint32_t)FLASH_ACTLR_LATENCY_1; + + EXTEN->EXTEN_CTR |= EXTEN_PLL_HSI_PRE; + + /* HCLK = SYSCLK */ + RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; + /* PCLK2 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1; + /* PCLK1 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2; + + /* PLL configuration: PLLCLK = HSI * 9 = 72 MHz */ + RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL)); + RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL9); + + /* Enable PLL */ + RCC->CTLR |= RCC_PLLON; + /* Wait till PLL is ready */ + while((RCC->CTLR & RCC_PLLRDY) == 0) + { + } + /* Select PLL as system clock source */ + RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW)); + RCC->CFGR0 |= (uint32_t)RCC_SW_PLL; + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08) + { + } +} + +#elif defined SYSCLK_FREQ_96MHz_HSI + +/********************************************************************* + * @fn SetSysClockTo96_HSI + * + * @brief Sets System clock frequency to 96MHz and configure HCLK, PCLK2 and PCLK1 prescalers. + * + * @return none + */ +static void SetSysClockTo96_HSI(void) +{ + /* Flash 2 wait state */ + FLASH->ACTLR = (uint32_t)FLASH_ACTLR_LATENCY_2; + + EXTEN->EXTEN_CTR |= EXTEN_PLL_HSI_PRE; + + /* HCLK = SYSCLK */ + RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; + /* PCLK2 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1; + /* PCLK1 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2; + + /* PLL configuration: PLLCLK = HSI * 12 = 96 MHz */ + RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL)); + RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL12); + + /* Enable PLL */ + RCC->CTLR |= RCC_PLLON; + /* Wait till PLL is ready */ + while((RCC->CTLR & RCC_PLLRDY) == 0) + { + } + /* Select PLL as system clock source */ + RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW)); + RCC->CFGR0 |= (uint32_t)RCC_SW_PLL; + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08) + { + } +} + +#elif defined SYSCLK_FREQ_HSI_LP + +/********************************************************************* + * @fn SetSysClockToHSI_LP + * + * @brief Sets HSI as System clock source of Low power and configure HCLK, PCLK2 and PCLK1 prescalers. + * In this mode, HSI is 1MHz and Baud rate support less than 62.5Kbps when using UART. + * + * @return none + */ +static void SetSysClockToHSI_LP(void) +{ + RCC_HSI_LP_Cmd(ENABLE); + + /* HCLK = SYSCLK */ + RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; + /* PCLK2 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1; + /* PCLK1 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV1; + /* Low power mode HSI */ + RCC_AdjustHSICalibrationValue((*(uint8_t*)HSI_LP_TRIM_BASE)&0x1F); +} + +#endif diff --git a/ZDBMS/BMS_CC/User/system_ch32l103.h b/ZDBMS/BMS_CC/User/system_ch32l103.h new file mode 100644 index 0000000..0143c56 --- /dev/null +++ b/ZDBMS/BMS_CC/User/system_ch32l103.h @@ -0,0 +1,29 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : system_ch32l103.h + * Author : WCH + * Version : V1.0.0 + * Date : 2023/07/08 + * Description : CH32L103 Device Peripheral Access Layer System Header File. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#ifndef __SYSTEM_ch32l103_H +#define __SYSTEM_ch32l103_H + +#ifdef __cplusplus +extern "C" { +#endif + +extern uint32_t SystemCoreClock; /* System Clock Frequency (Core Clock) */ + +/* System_Exported_Functions */ +extern void SystemInit(void); +extern void SystemCoreClockUpdate(void); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/ZDBMS/BMS_CC/obj/BMS_CC.elf b/ZDBMS/BMS_CC/obj/BMS_CC.elf new file mode 100644 index 0000000000000000000000000000000000000000..8edf5b7c5ccf3f8c6e57886bfe81d8fb3b85793f GIT binary patch literal 101624 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0000 unimp + 38: 0000 unimp + 3a: 0000 unimp + 3c: 040a slli s0,s0,0x2 + 3e: 0000 unimp + 40: 0000 unimp + 42: 0000 unimp + 44: 040a slli s0,s0,0x2 + 46: 0000 unimp + 48: 040a slli s0,s0,0x2 + 4a: 0000 unimp + 4c: 040a slli s0,s0,0x2 + 4e: 0000 unimp + 50: 040a slli s0,s0,0x2 + 52: 0000 unimp + 54: 040a slli s0,s0,0x2 + 56: 0000 unimp + 58: 040a slli s0,s0,0x2 + 5a: 0000 unimp + 5c: 040a slli s0,s0,0x2 + 5e: 0000 unimp + 60: 040a slli s0,s0,0x2 + 62: 0000 unimp + 64: 040a slli s0,s0,0x2 + 66: 0000 unimp + 68: 040a slli s0,s0,0x2 + 6a: 0000 unimp + 6c: 040a slli s0,s0,0x2 + 6e: 0000 unimp + 70: 040a slli s0,s0,0x2 + 72: 0000 unimp + 74: 040a slli s0,s0,0x2 + 76: 0000 unimp + 78: 040a slli s0,s0,0x2 + 7a: 0000 unimp + 7c: 040a slli s0,s0,0x2 + 7e: 0000 unimp + 80: 040a slli s0,s0,0x2 + 82: 0000 unimp + 84: 040a slli s0,s0,0x2 + 86: 0000 unimp + 88: 040a slli s0,s0,0x2 + 8a: 0000 unimp + 8c: 040a slli s0,s0,0x2 + 8e: 0000 unimp + 90: 040a slli s0,s0,0x2 + 92: 0000 unimp + 94: 040a slli s0,s0,0x2 + 96: 0000 unimp + 98: 040a slli s0,s0,0x2 + 9a: 0000 unimp + 9c: 040a slli s0,s0,0x2 + 9e: 0000 unimp + a0: 040a slli s0,s0,0x2 + a2: 0000 unimp + a4: 040a slli s0,s0,0x2 + a6: 0000 unimp + a8: 040a slli s0,s0,0x2 + aa: 0000 unimp + ac: 040a slli s0,s0,0x2 + ae: 0000 unimp + b0: 040a slli s0,s0,0x2 + b2: 0000 unimp + b4: 040a slli s0,s0,0x2 + b6: 0000 unimp + b8: 040a slli s0,s0,0x2 + ba: 0000 unimp + bc: 040a slli s0,s0,0x2 + be: 0000 unimp + c0: 040a slli s0,s0,0x2 + c2: 0000 unimp + c4: 040a slli s0,s0,0x2 + c6: 0000 unimp + c8: 040a slli s0,s0,0x2 + ca: 0000 unimp + cc: 040a slli s0,s0,0x2 + ce: 0000 unimp + d0: 040a slli s0,s0,0x2 + d2: 0000 unimp + d4: 040a slli s0,s0,0x2 + d6: 0000 unimp + d8: 040a slli s0,s0,0x2 + da: 0000 unimp + dc: 040a slli s0,s0,0x2 + de: 0000 unimp + e0: 040a slli s0,s0,0x2 + e2: 0000 unimp + e4: 040a slli s0,s0,0x2 + e6: 0000 unimp + e8: 040a slli s0,s0,0x2 + ea: 0000 unimp + ec: 040a slli s0,s0,0x2 + ee: 0000 unimp + f0: 040a slli s0,s0,0x2 + f2: 0000 unimp + f4: 040a slli s0,s0,0x2 + f6: 0000 unimp + f8: 040a slli s0,s0,0x2 + fa: 0000 unimp + fc: 040a slli s0,s0,0x2 + fe: 0000 unimp + 100: 040a slli s0,s0,0x2 + 102: 0000 unimp + 104: 040a slli s0,s0,0x2 + 106: 0000 unimp + 108: 040a slli s0,s0,0x2 + 10a: 0000 unimp + 10c: 0000 unimp + 10e: 0000 unimp + 110: 040a slli s0,s0,0x2 + 112: 0000 unimp + 114: 040a slli s0,s0,0x2 + ... + +Disassembly of section .text: + +00000140 <__riscv_save_12>: + 140: 7139 addi sp,sp,-64 + 142: 4301 li t1,0 + 144: c66e sw s11,12(sp) + 146: a019 j 14c <__riscv_save_10+0x4> + +00000148 <__riscv_save_10>: + 148: 7139 addi sp,sp,-64 + 14a: 5341 li t1,-16 + 14c: c86a sw s10,16(sp) + 14e: ca66 sw s9,20(sp) + 150: cc62 sw s8,24(sp) + 152: ce5e sw s7,28(sp) + 154: a019 j 15a <__riscv_save_4+0x4> + +00000156 <__riscv_save_4>: + 156: 7139 addi sp,sp,-64 + 158: 5301 li t1,-32 + 15a: d05a sw s6,32(sp) + 15c: d256 sw s5,36(sp) + 15e: d452 sw s4,40(sp) + 160: d64e sw s3,44(sp) + 162: d84a sw s2,48(sp) + 164: da26 sw s1,52(sp) + 166: dc22 sw s0,56(sp) + 168: de06 sw ra,60(sp) + 16a: 40610133 sub sp,sp,t1 + 16e: 8282 jr t0 + +00000170 <__riscv_save_0>: + 170: 1141 addi sp,sp,-16 + 172: c04a sw s2,0(sp) + 174: c226 sw s1,4(sp) + 176: c422 sw s0,8(sp) + 178: c606 sw ra,12(sp) + 17a: 8282 jr t0 + +0000017c <__riscv_restore_12>: + 17c: 4db2 lw s11,12(sp) + 17e: 0141 addi sp,sp,16 + +00000180 <__riscv_restore_10>: + 180: 4d02 lw s10,0(sp) + 182: 4c92 lw s9,4(sp) + 184: 4c22 lw s8,8(sp) + 186: 4bb2 lw s7,12(sp) + 188: 0141 addi sp,sp,16 + +0000018a <__riscv_restore_4>: + 18a: 4b02 lw s6,0(sp) + 18c: 4a92 lw s5,4(sp) + 18e: 4a22 lw s4,8(sp) + 190: 49b2 lw s3,12(sp) + 192: 0141 addi sp,sp,16 + +00000194 <__riscv_restore_0>: + 194: 4902 lw s2,0(sp) + 196: 4492 lw s1,4(sp) + 198: 4422 lw s0,8(sp) + 19a: 40b2 lw ra,12(sp) + 19c: 0141 addi sp,sp,16 + 19e: 8082 ret + +000001a0 : + 1a0: 433d li t1,15 + 1a2: 872a mv a4,a0 + 1a4: 02c37363 bgeu t1,a2,1ca + 1a8: 00f77793 andi a5,a4,15 + 1ac: efbd bnez a5,22a + 1ae: e5ad bnez a1,218 + 1b0: ff067693 andi a3,a2,-16 + 1b4: 8a3d andi a2,a2,15 + 1b6: 96ba add a3,a3,a4 + 1b8: c30c sw a1,0(a4) + 1ba: c34c sw a1,4(a4) + 1bc: c70c sw a1,8(a4) + 1be: c74c sw a1,12(a4) + 1c0: 0741 addi a4,a4,16 + 1c2: fed76be3 bltu a4,a3,1b8 + 1c6: e211 bnez a2,1ca + 1c8: 8082 ret + 1ca: 40c306b3 sub a3,t1,a2 + 1ce: 068a slli a3,a3,0x2 + 1d0: 00000297 auipc t0,0x0 + 1d4: 9696 add a3,a3,t0 + 1d6: 00a68067 jr 10(a3) + 1da: 00b70723 sb a1,14(a4) + 1de: 00b706a3 sb a1,13(a4) + 1e2: 00b70623 sb a1,12(a4) + 1e6: 00b705a3 sb a1,11(a4) + 1ea: 00b70523 sb a1,10(a4) + 1ee: 00b704a3 sb a1,9(a4) + 1f2: 00b70423 sb a1,8(a4) + 1f6: 00b703a3 sb a1,7(a4) + 1fa: 00b70323 sb a1,6(a4) + 1fe: 00b702a3 sb a1,5(a4) + 202: 00b70223 sb a1,4(a4) + 206: 00b701a3 sb a1,3(a4) + 20a: 00b70123 sb a1,2(a4) + 20e: 00b700a3 sb a1,1(a4) + 212: 00b70023 sb a1,0(a4) + 216: 8082 ret + 218: 0ff5f593 andi a1,a1,255 + 21c: 00859693 slli a3,a1,0x8 + 220: 8dd5 or a1,a1,a3 + 222: 01059693 slli a3,a1,0x10 + 226: 8dd5 or a1,a1,a3 + 228: b761 j 1b0 + 22a: 00279693 slli a3,a5,0x2 + 22e: 00000297 auipc t0,0x0 + 232: 9696 add a3,a3,t0 + 234: 8286 mv t0,ra + 236: fa8680e7 jalr -88(a3) + 23a: 8096 mv ra,t0 + 23c: 17c1 addi a5,a5,-16 + 23e: 8f1d sub a4,a4,a5 + 240: 963e add a2,a2,a5 + 242: f8c374e3 bgeu t1,a2,1ca + 246: b7a5 j 1ae + +00000248 : + 248: a001 j 248 + +0000024a : + 24a: beef07b7 lui a5,0xbeef0 + 24e: e000e737 lui a4,0xe000e + 252: 08078793 addi a5,a5,128 # beef0080 <_eusrstack+0x9eeeb080> + 256: c73c sw a5,72(a4) + 258: a001 j 258 + +0000025a
: + 25a: f17ff2ef jal t0,170 <__riscv_save_0> + 25e: 4505 li a0,1 + 260: 23dd jal 846 + 262: 2211 jal 366 + 264: 7be000ef jal ra,a22 + 268: 6571 lui a0,0x1c + 26a: 20050513 addi a0,a0,512 # 1c200 <_data_lma+0x1a448> + 26e: 00b000ef jal ra,a78 + 272: 200007b7 lui a5,0x20000 + 276: 0807a583 lw a1,128(a5) # 20000080 + 27a: 00002537 lui a0,0x2 + 27e: ce050513 addi a0,a0,-800 # 1ce0 <_read+0xe> + 282: 0a9000ef jal ra,b2a + 286: 2431 jal 492 + 288: 85aa mv a1,a0 + 28a: 00002537 lui a0,0x2 + 28e: cf050513 addi a0,a0,-784 # 1cf0 <_read+0x1e> + 292: 099000ef jal ra,b2a + 296: 00002437 lui s0,0x2 + 29a: 3e800513 li a0,1000 + 29e: 7a4000ef jal ra,a42 + 2a2: d0040513 addi a0,s0,-768 # 1d00 <_read+0x2e> + 2a6: 199000ef jal ra,c3e + 2aa: bfc5 j 29a + +000002ac : + 2ac: ec5ff2ef jal t0,170 <__riscv_save_0> + 2b0: 40021437 lui s0,0x40021 + 2b4: 401c lw a5,0(s0) + 2b6: 08ff0737 lui a4,0x8ff0 + 2ba: 0017e793 ori a5,a5,1 + 2be: c01c sw a5,0(s0) + 2c0: 405c lw a5,4(s0) + 2c2: 8ff9 and a5,a5,a4 + 2c4: c05c sw a5,4(s0) + 2c6: 401c lw a5,0(s0) + 2c8: fef70737 lui a4,0xfef70 + 2cc: 176d addi a4,a4,-5 + 2ce: 8ff9 and a5,a5,a4 + 2d0: c01c sw a5,0(s0) + 2d2: 401c lw a5,0(s0) + 2d4: fffc0737 lui a4,0xfffc0 + 2d8: 177d addi a4,a4,-1 + 2da: 8ff9 and a5,a5,a4 + 2dc: c01c sw a5,0(s0) + 2de: 405c lw a5,4(s0) + 2e0: ff010737 lui a4,0xff010 + 2e4: 177d addi a4,a4,-1 + 2e6: 8ff9 and a5,a5,a4 + 2e8: c05c sw a5,4(s0) + 2ea: 009f07b7 lui a5,0x9f0 + 2ee: c41c sw a5,8(s0) + 2f0: 2e51 jal 684 + 2f2: 400227b7 lui a5,0x40022 + 2f6: 4709 li a4,2 + 2f8: c398 sw a4,0(a5) + 2fa: 40024737 lui a4,0x40024 + 2fe: 80072783 lw a5,-2048(a4) # 40023800 <_eusrstack+0x2001e800> + 302: 0107e793 ori a5,a5,16 + 306: 80f72023 sw a5,-2048(a4) + 30a: 405c lw a5,4(s0) + 30c: ffc10737 lui a4,0xffc10 + 310: 177d addi a4,a4,-1 + 312: c05c sw a5,4(s0) + 314: 405c lw a5,4(s0) + 316: c05c sw a5,4(s0) + 318: 405c lw a5,4(s0) + 31a: 4007e793 ori a5,a5,1024 + 31e: c05c sw a5,4(s0) + 320: 405c lw a5,4(s0) + 322: 8ff9 and a5,a5,a4 + 324: c05c sw a5,4(s0) + 326: 405c lw a5,4(s0) + 328: 00280737 lui a4,0x280 + 32c: 8fd9 or a5,a5,a4 + 32e: c05c sw a5,4(s0) + 330: 401c lw a5,0(s0) + 332: 01000737 lui a4,0x1000 + 336: 8fd9 or a5,a5,a4 + 338: c01c sw a5,0(s0) + 33a: 400217b7 lui a5,0x40021 + 33e: 4398 lw a4,0(a5) + 340: 00671693 slli a3,a4,0x6 + 344: fe06dde3 bgez a3,33e + 348: 43d8 lw a4,4(a5) + 34a: 400216b7 lui a3,0x40021 + 34e: 9b71 andi a4,a4,-4 + 350: c3d8 sw a4,4(a5) + 352: 43d8 lw a4,4(a5) + 354: 00276713 ori a4,a4,2 + 358: c3d8 sw a4,4(a5) + 35a: 4721 li a4,8 + 35c: 42dc lw a5,4(a3) + 35e: 8bb1 andi a5,a5,12 + 360: fee79ee3 bne a5,a4,35c + 364: bd05 j 194 <__riscv_restore_0> + +00000366 : + 366: 400216b7 lui a3,0x40021 + 36a: 42dc lw a5,4(a3) + 36c: 20000737 lui a4,0x20000 + 370: 4611 li a2,4 + 372: 8bb1 andi a5,a5,12 + 374: 08070713 addi a4,a4,128 # 20000080 + 378: 02c78f63 beq a5,a2,3b6 + 37c: 4621 li a2,8 + 37e: 04c78163 beq a5,a2,3c0 + 382: eb95 bnez a5,3b6 + 384: 429c lw a5,0(a3) + 386: 8b91 andi a5,a5,4 + 388: c79d beqz a5,3b6 + 38a: 000f47b7 lui a5,0xf4 + 38e: 24078793 addi a5,a5,576 # f4240 <_data_lma+0xf2488> + 392: c31c sw a5,0(a4) + 394: 400217b7 lui a5,0x40021 + 398: 43dc lw a5,4(a5) + 39a: 8391 srli a5,a5,0x4 + 39c: 00f7f693 andi a3,a5,15 + 3a0: 200007b7 lui a5,0x20000 + 3a4: 00078793 mv a5,a5 + 3a8: 97b6 add a5,a5,a3 + 3aa: 2394 lbu a3,0(a5) + 3ac: 431c lw a5,0(a4) + 3ae: 00d7d7b3 srl a5,a5,a3 + 3b2: c31c sw a5,0(a4) + 3b4: 8082 ret + 3b6: 007a17b7 lui a5,0x7a1 + 3ba: 20078793 addi a5,a5,512 # 7a1200 <_data_lma+0x79f448> + 3be: bfd1 j 392 + 3c0: 42dc lw a5,4(a3) + 3c2: 42d4 lw a3,4(a3) + 3c4: 6641 lui a2,0x10 + 3c6: 83c9 srli a5,a5,0x12 + 3c8: 8bbd andi a5,a5,15 + 3ca: 8ef1 and a3,a3,a2 + 3cc: 0789 addi a5,a5,2 + 3ce: 4645 li a2,17 + 3d0: 00c79363 bne a5,a2,3d6 + 3d4: 47c9 li a5,18 + 3d6: ee81 bnez a3,3ee + 3d8: 400246b7 lui a3,0x40024 + 3dc: 8006a683 lw a3,-2048(a3) # 40023800 <_eusrstack+0x2001e800> + 3e0: 8ac1 andi a3,a3,16 + 3e2: ce89 beqz a3,3fc + 3e4: 007a16b7 lui a3,0x7a1 + 3e8: 20068693 addi a3,a3,512 # 7a1200 <_data_lma+0x79f448> + 3ec: a821 j 404 + 3ee: 400216b7 lui a3,0x40021 + 3f2: 42d4 lw a3,4(a3) + 3f4: 00e69613 slli a2,a3,0xe + 3f8: fe0656e3 bgez a2,3e4 + 3fc: 003d16b7 lui a3,0x3d1 + 400: 90068693 addi a3,a3,-1792 # 3d0900 <_data_lma+0x3ceb48> + 404: 02d787b3 mul a5,a5,a3 + 408: b769 j 392 + +0000040a : + 40a: a001 j 40a + +0000040c : + 40c: 20000197 auipc gp,0x20000 + 410: 47418193 addi gp,gp,1140 # 20000880 <__global_pointer$> + 414: 20005117 auipc sp,0x20005 + 418: bec10113 addi sp,sp,-1044 # 20005000 <_eusrstack> + 41c: 00002517 auipc a0,0x2 + 420: 99c50513 addi a0,a0,-1636 # 1db8 <_data_lma> + 424: 20000597 auipc a1,0x20000 + 428: bdc58593 addi a1,a1,-1060 # 20000000 <_data_vma> + 42c: 81818613 addi a2,gp,-2024 # 20000098 <_edata> + 430: 00c5fa63 bgeu a1,a2,444 + 434: 00052283 lw t0,0(a0) + 438: 0055a023 sw t0,0(a1) + 43c: 0511 addi a0,a0,4 + 43e: 0591 addi a1,a1,4 + 440: fec5eae3 bltu a1,a2,434 + 444: 81818513 addi a0,gp,-2024 # 20000098 <_edata> + 448: 84018593 addi a1,gp,-1984 # 200000c0 <_ebss> + 44c: 00b57763 bgeu a0,a1,45a + 450: 00052023 sw zero,0(a0) + 454: 0511 addi a0,a0,4 + 456: feb56de3 bltu a0,a1,450 + 45a: 42fd li t0,31 + 45c: bc029073 csrw 0xbc0,t0 + 460: 428d li t0,3 + 462: 80429073 csrw 0x804,t0 + 466: 08800293 li t0,136 + 46a: 30029073 csrw mstatus,t0 + 46e: 00000297 auipc t0,0x0 + 472: b9628293 addi t0,t0,-1130 # 4 <_einit> + 476: 0032e293 ori t0,t0,3 + 47a: 30529073 csrw mtvec,t0 + 47e: e2fff0ef jal ra,2ac + 482: 00000297 auipc t0,0x0 + 486: dd828293 addi t0,t0,-552 # 25a
+ 48a: 34129073 csrw mepc,t0 + 48e: 30200073 mret + +00000492 : + 492: 81c1a503 lw a0,-2020(gp) # 2000009c + 496: 8082 ret + +00000498 : + 498: 459c lw a5,8(a1) + 49a: 0107f713 andi a4,a5,16 + 49e: 00f7f813 andi a6,a5,15 + 4a2: c701 beqz a4,4aa + 4a4: 41d8 lw a4,4(a1) + 4a6: 00e86833 or a6,a6,a4 + 4aa: 218e lhu a1,0(a1) + 4ac: 0ff5f713 andi a4,a1,255 + 4b0: c339 beqz a4,4f6 + 4b2: 4118 lw a4,0(a0) + 4b4: 4681 li a3,0 + 4b6: 4e85 li t4,1 + 4b8: 4f3d li t5,15 + 4ba: 02800f93 li t6,40 + 4be: 04800293 li t0,72 + 4c2: 4e21 li t3,8 + 4c4: 00de9633 sll a2,t4,a3 + 4c8: 00c5f8b3 and a7,a1,a2 + 4cc: 03161163 bne a2,a7,4ee + 4d0: 00269893 slli a7,a3,0x2 + 4d4: 011f1333 sll t1,t5,a7 + 4d8: fff34313 not t1,t1 + 4dc: 00e37733 and a4,t1,a4 + 4e0: 011818b3 sll a7,a6,a7 + 4e4: 00e8e733 or a4,a7,a4 + 4e8: 05f79f63 bne a5,t6,546 + 4ec: c950 sw a2,20(a0) + 4ee: 0685 addi a3,a3,1 + 4f0: fdc69ae3 bne a3,t3,4c4 + 4f4: c118 sw a4,0(a0) + 4f6: 0ff00713 li a4,255 + 4fa: 04b77563 bgeu a4,a1,544 + 4fe: 4154 lw a3,4(a0) + 500: 4621 li a2,8 + 502: 4e85 li t4,1 + 504: 4f3d li t5,15 + 506: 02800f93 li t6,40 + 50a: 04800293 li t0,72 + 50e: 4e41 li t3,16 + 510: 00ce98b3 sll a7,t4,a2 + 514: 0115f733 and a4,a1,a7 + 518: 02e89263 bne a7,a4,53c + 51c: 00261713 slli a4,a2,0x2 + 520: 1701 addi a4,a4,-32 + 522: 00ef1333 sll t1,t5,a4 + 526: fff34313 not t1,t1 + 52a: 00d376b3 and a3,t1,a3 + 52e: 00e81733 sll a4,a6,a4 + 532: 8ed9 or a3,a3,a4 + 534: 01f79d63 bne a5,t6,54e + 538: 01152a23 sw a7,20(a0) + 53c: 0605 addi a2,a2,1 + 53e: fdc619e3 bne a2,t3,510 + 542: c154 sw a3,4(a0) + 544: 8082 ret + 546: fa5794e3 bne a5,t0,4ee + 54a: c910 sw a2,16(a0) + 54c: b74d j 4ee + 54e: fe5797e3 bne a5,t0,53c + 552: 01152823 sw a7,16(a0) + 556: b7dd j 53c + +00000558 : + 558: c0000737 lui a4,0xc0000 + 55c: 00e577b3 and a5,a0,a4 + 560: 08e79563 bne a5,a4,5ea + 564: 40010737 lui a4,0x40010 + 568: 435c lw a5,4(a4) + 56a: 01b55693 srli a3,a0,0x1b + 56e: 4f58 lw a4,28(a4) + 570: 8a9d andi a3,a3,7 + 572: e69d bnez a3,5a0 + 574: 9bf9 andi a5,a5,-2 + 576: ff0006b7 lui a3,0xff000 + 57a: 16fd addi a3,a3,-1 + 57c: 8f75 and a4,a4,a3 + 57e: c989 beqz a1,590 + 580: 01051693 slli a3,a0,0x10 + 584: 82c1 srli a3,a3,0x10 + 586: 8fd5 or a5,a5,a3 + 588: 01ff06b7 lui a3,0x1ff0 + 58c: 8d75 and a0,a0,a3 + 58e: 8f49 or a4,a4,a0 + 590: 070006b7 lui a3,0x7000 + 594: 8fd5 or a5,a5,a3 + 596: 400106b7 lui a3,0x40010 + 59a: c2dc sw a5,4(a3) + 59c: ced8 sw a4,28(a3) + 59e: 8082 ret + 5a0: 4605 li a2,1 + 5a2: 00c69663 bne a3,a2,5ae + 5a6: 9bf5 andi a5,a5,-3 + 5a8: ff8006b7 lui a3,0xff800 + 5ac: b7f9 j 57a + 5ae: 4609 li a2,2 + 5b0: 00c69663 bne a3,a2,5bc + 5b4: 9bed andi a5,a5,-5 + 5b6: ffe806b7 lui a3,0xffe80 + 5ba: b7c1 j 57a + 5bc: 460d li a2,3 + 5be: 00c69663 bne a3,a2,5ca + 5c2: 9bdd andi a5,a5,-9 + 5c4: fffc06b7 lui a3,0xfffc0 + 5c8: bf4d j 57a + 5ca: 4611 li a2,4 + 5cc: 00c69763 bne a3,a2,5da + 5d0: f3f7f793 andi a5,a5,-193 + 5d4: ffc006b7 lui a3,0xffc00 + 5d8: b74d j 57a + 5da: 4615 li a2,5 + 5dc: fac691e3 bne a3,a2,57e + 5e0: cff7f793 andi a5,a5,-769 + 5e4: ffe006b7 lui a3,0xffe00 + 5e8: bf49 j 57a + 5ea: 40000737 lui a4,0x40000 + 5ee: 02e79163 bne a5,a4,610 + 5f2: 400107b7 lui a5,0x40010 + 5f6: 4fd8 lw a4,28(a5) + 5f8: 0542 slli a0,a0,0x10 + 5fa: 00a767b3 or a5,a4,a0 + 5fe: e589 bnez a1,608 + 600: fff54513 not a0,a0 + 604: 00e577b3 and a5,a0,a4 + 608: 40010737 lui a4,0x40010 + 60c: cf5c sw a5,28(a4) + 60e: 8082 ret + 610: e3a9 bnez a5,652 + 612: 40010837 lui a6,0x40010 + 616: 003007b7 lui a5,0x300 + 61a: 00482603 lw a2,4(a6) # 40010004 <_eusrstack+0x2000b004> + 61e: 01051713 slli a4,a0,0x10 + 622: 00f576b3 and a3,a0,a5 + 626: 8341 srli a4,a4,0x10 + 628: 02f69663 bne a3,a5,654 + 62c: f90006b7 lui a3,0xf9000 + 630: 16fd addi a3,a3,-1 + 632: 00d677b3 and a5,a2,a3 + 636: 00482603 lw a2,4(a6) + 63a: 8ef1 and a3,a3,a2 + 63c: 00d82223 sw a3,4(a6) + 640: c591 beqz a1,64c + 642: 8155 srli a0,a0,0x15 + 644: 0512 slli a0,a0,0x4 + 646: 00a71533 sll a0,a4,a0 + 64a: 8fc9 or a5,a5,a0 + 64c: 40010737 lui a4,0x40010 + 650: c35c sw a5,4(a4) + 652: 8082 ret + 654: 00b51793 slli a5,a0,0xb + 658: 0207d063 bgez a5,678 + 65c: 01055793 srli a5,a0,0x10 + 660: 00f7f693 andi a3,a5,15 + 664: 478d li a5,3 + 666: 00d797b3 sll a5,a5,a3 + 66a: fff7c793 not a5,a5 + 66e: 8ff1 and a5,a5,a2 + 670: 070006b7 lui a3,0x7000 + 674: 8fd5 or a5,a5,a3 + 676: b7e9 j 640 + 678: 01555793 srli a5,a0,0x15 + 67c: 0792 slli a5,a5,0x4 + 67e: 00f717b3 sll a5,a4,a5 + 682: b7e5 j 66a + +00000684 : + 684: aedff2ef jal t0,170 <__riscv_save_0> + 688: 1ffff437 lui s0,0x1ffff + 68c: 72442703 lw a4,1828(s0) # 1ffff724 <_data_lma+0x1fffd96c> + 690: 3e000637 lui a2,0x3e000 + 694: 1141 addi sp,sp,-16 + 696: 01971793 slli a5,a4,0x19 + 69a: fff74693 not a3,a4 + 69e: 8ff1 and a5,a5,a2 + 6a0: 0706 slli a4,a4,0x1 + 6a2: 003e0637 lui a2,0x3e0 + 6a6: 8f71 and a4,a4,a2 + 6a8: 8fd9 or a5,a5,a4 + 6aa: 01000637 lui a2,0x1000 + 6ae: 00969713 slli a4,a3,0x9 + 6b2: 8f71 and a4,a4,a2 + 6b4: 8fd9 or a5,a5,a4 + 6b6: 82bd srli a3,a3,0xf + 6b8: 6741 lui a4,0x10 + 6ba: 8ef9 and a3,a3,a4 + 6bc: c202 sw zero,4(sp) + 6be: c402 sw zero,8(sp) + 6c0: c602 sw zero,12(sp) + 6c2: 8fd5 or a5,a5,a3 + 6c4: 82f1a023 sw a5,-2016(gp) # 200000a0 + 6c8: 72845703 lhu a4,1832(s0) + 6cc: 4585 li a1,1 + 6ce: 80e19c23 sh a4,-2024(gp) # 20000098 <_edata> + 6d2: 72042703 lw a4,1824(s0) + 6d6: 03d00513 li a0,61 + 6da: 82e1a223 sw a4,-2012(gp) # 200000a4 + 6de: 70442703 lw a4,1796(s0) + 6e2: 80e1ae23 sw a4,-2020(gp) # 2000009c + 6e6: 73045703 lhu a4,1840(s0) + 6ea: 82e19423 sh a4,-2008(gp) # 200000a8 + 6ee: 2c15 jal 922 + 6f0: 70442783 lw a5,1796(s0) + 6f4: 103a0737 lui a4,0x103a0 + 6f8: 70070713 addi a4,a4,1792 # 103a0700 <_data_lma+0x1039e948> + 6fc: f0f7f793 andi a5,a5,-241 + 700: 10e78363 beq a5,a4,806 <__stack_size+0x6> + 704: 00f76a63 bltu a4,a5,718 + 708: 10320737 lui a4,0x10320 + 70c: 70070713 addi a4,a4,1792 # 10320700 <_data_lma+0x1031e948> + 710: 06e78f63 beq a5,a4,78e + 714: 0141 addi sp,sp,16 + 716: bcbd j 194 <__riscv_restore_0> + 718: 103b0737 lui a4,0x103b0 + 71c: 70070713 addi a4,a4,1792 # 103b0700 <_data_lma+0x103ae948> + 720: 08e78b63 beq a5,a4,7b6 + 724: 103d0737 lui a4,0x103d0 + 728: 70070713 addi a4,a4,1792 # 103d0700 <_data_lma+0x103ce948> + 72c: fee794e3 bne a5,a4,714 + 730: 4585 li a1,1 + 732: 6521 lui a0,0x8 + 734: 3515 jal 558 + 736: 40011437 lui s0,0x40011 + 73a: 77e1 lui a5,0xffff8 + 73c: 04800493 li s1,72 + 740: 004c addi a1,sp,4 + 742: 80040513 addi a0,s0,-2048 # 40010800 <_eusrstack+0x2000b800> + 746: 827c sh a5,4(sp) + 748: c626 sw s1,12(sp) + 74a: 33b9 jal 498 + 74c: 6785 lui a5,0x1 + 74e: 33878793 addi a5,a5,824 # 1338 <_free_r+0x9a> + 752: 004c addi a1,sp,4 + 754: c0040513 addi a0,s0,-1024 + 758: 827c sh a5,4(sp) + 75a: c626 sw s1,12(sp) + 75c: 3b35 jal 498 + 75e: 4791 li a5,4 + 760: 827c sh a5,4(sp) + 762: 004c addi a1,sp,4 + 764: 02800793 li a5,40 + 768: c0040513 addi a0,s0,-1024 + 76c: c63e sw a5,12(sp) + 76e: 332d jal 498 + 770: 77f9 lui a5,0xffffe + 772: 004c addi a1,sp,4 + 774: 40011537 lui a0,0x40011 + 778: 827c sh a5,4(sp) + 77a: c626 sw s1,12(sp) + 77c: 3b31 jal 498 + 77e: 478d li a5,3 + 780: 827c sh a5,4(sp) + 782: c626 sw s1,12(sp) + 784: 004c addi a1,sp,4 + 786: 40040513 addi a0,s0,1024 + 78a: 3339 jal 498 + 78c: b761 j 714 + 78e: 77e1 lui a5,0xffff8 + 790: 40011537 lui a0,0x40011 + 794: c007c793 xori a5,a5,-1024 + 798: 04800413 li s0,72 + 79c: 004c addi a1,sp,4 + 79e: c0050513 addi a0,a0,-1024 # 40010c00 <_eusrstack+0x2000bc00> + 7a2: 827c sh a5,4(sp) + 7a4: c622 sw s0,12(sp) + 7a6: 39cd jal 498 + 7a8: 6789 lui a5,0x2 + 7aa: 827c sh a5,4(sp) + 7ac: c622 sw s0,12(sp) + 7ae: 004c addi a1,sp,4 + 7b0: 40011537 lui a0,0x40011 + 7b4: bfd9 j 78a + 7b6: 4585 li a1,1 + 7b8: 6521 lui a0,0x8 + 7ba: 3b79 jal 558 + 7bc: 40011437 lui s0,0x40011 + 7c0: 77e1 lui a5,0xffff8 + 7c2: 04800493 li s1,72 + 7c6: 004c addi a1,sp,4 + 7c8: 80040513 addi a0,s0,-2048 # 40010800 <_eusrstack+0x2000b800> + 7cc: 827c sh a5,4(sp) + 7ce: c626 sw s1,12(sp) + 7d0: 31e1 jal 498 + 7d2: 21000793 li a5,528 + 7d6: 004c addi a1,sp,4 + 7d8: c0040513 addi a0,s0,-1024 + 7dc: 827c sh a5,4(sp) + 7de: c626 sw s1,12(sp) + 7e0: 3965 jal 498 + 7e2: 4791 li a5,4 + 7e4: 827c sh a5,4(sp) + 7e6: 004c addi a1,sp,4 + 7e8: 02800793 li a5,40 + 7ec: c0040513 addi a0,s0,-1024 + 7f0: c63e sw a5,12(sp) + 7f2: 315d jal 498 + 7f4: 77f9 lui a5,0xffffe + 7f6: 004c addi a1,sp,4 + 7f8: 40011537 lui a0,0x40011 + 7fc: 827c sh a5,4(sp) + 7fe: c626 sw s1,12(sp) + 800: 3961 jal 498 + 802: 4789 li a5,2 + 804: bfb5 j 780 + 806: 400114b7 lui s1,0x40011 + 80a: 77e1 lui a5,0xffff8 + 80c: 70078793 addi a5,a5,1792 # ffff8700 <_eusrstack+0xdfff3700> + 810: 04800413 li s0,72 + 814: 004c addi a1,sp,4 + 816: 80048513 addi a0,s1,-2048 # 40010800 <_eusrstack+0x2000b800> + 81a: 827c sh a5,4(sp) + 81c: c622 sw s0,12(sp) + 81e: 39ad jal 498 + 820: e3900793 li a5,-455 + 824: 004c addi a1,sp,4 + 826: c0048513 addi a0,s1,-1024 + 82a: 827c sh a5,4(sp) + 82c: c622 sw s0,12(sp) + 82e: 31ad jal 498 + 830: 4791 li a5,4 + 832: 827c sh a5,4(sp) + 834: 004c addi a1,sp,4 + 836: 02800793 li a5,40 + 83a: c0048513 addi a0,s1,-1024 + 83e: c63e sw a5,12(sp) + 840: 39a1 jal 498 + 842: 77f9 lui a5,0xffffe + 844: b79d j 7aa + +00000846 : + 846: 82a1a623 sw a0,-2004(gp) # 200000ac + 84a: 8082 ret + +0000084c : + 84c: 40021737 lui a4,0x40021 + 850: 435c lw a5,4(a4) + 852: 4691 li a3,4 + 854: 8bb1 andi a5,a5,12 + 856: 06d78c63 beq a5,a3,8ce + 85a: 46a1 li a3,8 + 85c: 06d78e63 beq a5,a3,8d8 + 860: e7bd bnez a5,8ce + 862: 431c lw a5,0(a4) + 864: 8b91 andi a5,a5,4 + 866: c7a5 beqz a5,8ce + 868: 000f47b7 lui a5,0xf4 + 86c: 24078793 addi a5,a5,576 # f4240 <_data_lma+0xf2488> + 870: c11c sw a5,0(a0) + 872: 40021637 lui a2,0x40021 + 876: 425c lw a5,4(a2) + 878: 20000737 lui a4,0x20000 + 87c: 01070713 addi a4,a4,16 # 20000010 + 880: 8391 srli a5,a5,0x4 + 882: 8bbd andi a5,a5,15 + 884: 97ba add a5,a5,a4 + 886: 2394 lbu a3,0(a5) + 888: 411c lw a5,0(a0) + 88a: 00d7d7b3 srl a5,a5,a3 + 88e: c15c sw a5,4(a0) + 890: 4254 lw a3,4(a2) + 892: 82a1 srli a3,a3,0x8 + 894: 8a9d andi a3,a3,7 + 896: 96ba add a3,a3,a4 + 898: 2294 lbu a3,0(a3) + 89a: 00d7d6b3 srl a3,a5,a3 + 89e: c514 sw a3,8(a0) + 8a0: 4254 lw a3,4(a2) + 8a2: 82ad srli a3,a3,0xb + 8a4: 8a9d andi a3,a3,7 + 8a6: 9736 add a4,a4,a3 + 8a8: 2314 lbu a3,0(a4) + 8aa: 00d7d6b3 srl a3,a5,a3 + 8ae: c554 sw a3,12(a0) + 8b0: 4258 lw a4,4(a2) + 8b2: 00074c63 bltz a4,8ca + 8b6: 425c lw a5,4(a2) + 8b8: 83b9 srli a5,a5,0xe + 8ba: 0037f713 andi a4,a5,3 + 8be: 80418793 addi a5,gp,-2044 # 20000084 + 8c2: 97ba add a5,a5,a4 + 8c4: 239c lbu a5,0(a5) + 8c6: 02f6d7b3 divu a5,a3,a5 + 8ca: c91c sw a5,16(a0) + 8cc: 8082 ret + 8ce: 007a17b7 lui a5,0x7a1 + 8d2: 20078793 addi a5,a5,512 # 7a1200 <_data_lma+0x79f448> + 8d6: bf69 j 870 + 8d8: 435c lw a5,4(a4) + 8da: 4358 lw a4,4(a4) + 8dc: 66c1 lui a3,0x10 + 8de: 83c9 srli a5,a5,0x12 + 8e0: 8bbd andi a5,a5,15 + 8e2: 8f75 and a4,a4,a3 + 8e4: 0789 addi a5,a5,2 + 8e6: 46c5 li a3,17 + 8e8: 00d79363 bne a5,a3,8ee + 8ec: 47c9 li a5,18 + 8ee: ef01 bnez a4,906 + 8f0: 40024737 lui a4,0x40024 + 8f4: 80072703 lw a4,-2048(a4) # 40023800 <_eusrstack+0x2001e800> + 8f8: 8b41 andi a4,a4,16 + 8fa: cf09 beqz a4,914 + 8fc: 007a1737 lui a4,0x7a1 + 900: 20070713 addi a4,a4,512 # 7a1200 <_data_lma+0x79f448> + 904: a821 j 91c + 906: 40021737 lui a4,0x40021 + 90a: 4358 lw a4,4(a4) + 90c: 00e71693 slli a3,a4,0xe + 910: fe06d6e3 bgez a3,8fc + 914: 003d1737 lui a4,0x3d1 + 918: 90070713 addi a4,a4,-1792 # 3d0900 <_data_lma+0x3ceb48> + 91c: 02e787b3 mul a5,a5,a4 + 920: bf81 j 870 + +00000922 : + 922: c599 beqz a1,930 + 924: 40021737 lui a4,0x40021 + 928: 4f1c lw a5,24(a4) + 92a: 8d5d or a0,a0,a5 + 92c: cf08 sw a0,24(a4) + 92e: 8082 ret + 930: 400217b7 lui a5,0x40021 + 934: 4f98 lw a4,24(a5) + 936: fff54513 not a0,a0 + 93a: 8d79 and a0,a0,a4 + 93c: cf88 sw a0,24(a5) + 93e: 8082 ret + +00000940 : + 940: 831ff2ef jal t0,170 <__riscv_save_0> + 944: 2916 lhu a3,16(a0) + 946: 77f5 lui a5,0xffffd + 948: 17fd addi a5,a5,-1 + 94a: 8ff5 and a5,a5,a3 + 94c: 21f6 lhu a3,6(a1) + 94e: 25da lhu a4,12(a1) + 950: 7179 addi sp,sp,-48 + 952: 8fd5 or a5,a5,a3 + 954: a91e sh a5,16(a0) + 956: 2556 lhu a3,12(a0) + 958: 77fd lui a5,0xfffff + 95a: 9f378793 addi a5,a5,-1549 # ffffe9f3 <_eusrstack+0xdfff99f3> + 95e: 8ff5 and a5,a5,a3 + 960: 21d6 lhu a3,4(a1) + 962: 842a mv s0,a0 + 964: c62e sw a1,12(sp) + 966: 8fd5 or a5,a5,a3 + 968: 2596 lhu a3,8(a1) + 96a: 8fd5 or a5,a5,a3 + 96c: 25b6 lhu a3,10(a1) + 96e: 8fd5 or a5,a5,a3 + 970: a55e sh a5,12(a0) + 972: 295e lhu a5,20(a0) + 974: 07c2 slli a5,a5,0x10 + 976: 83c1 srli a5,a5,0x10 + 978: cff7f793 andi a5,a5,-769 + 97c: 8fd9 or a5,a5,a4 + 97e: a95e sh a5,20(a0) + 980: 0868 addi a0,sp,28 + 982: 35e9 jal 84c + 984: 400147b7 lui a5,0x40014 + 988: 80078793 addi a5,a5,-2048 # 40013800 <_eusrstack+0x2000e800> + 98c: 45b2 lw a1,12(sp) + 98e: 04f41a63 bne s0,a5,9e2 + 992: 57a2 lw a5,40(sp) + 994: 2456 lhu a3,12(s0) + 996: 4765 li a4,25 + 998: 02e787b3 mul a5,a5,a4 + 99c: 06c2 slli a3,a3,0x10 + 99e: 86c1 srai a3,a3,0x10 + 9a0: 4198 lw a4,0(a1) + 9a2: 0406d263 bgez a3,9e6 + 9a6: 0706 slli a4,a4,0x1 + 9a8: 2452 lhu a2,12(s0) + 9aa: 0642 slli a2,a2,0x10 + 9ac: 02e7d7b3 divu a5,a5,a4 + 9b0: 06400713 li a4,100 + 9b4: 8641 srai a2,a2,0x10 + 9b6: 02e7d6b3 divu a3,a5,a4 + 9ba: 02e7f7b3 remu a5,a5,a4 + 9be: 0692 slli a3,a3,0x4 + 9c0: 02065563 bgez a2,9ea + 9c4: 078e slli a5,a5,0x3 + 9c6: 03278793 addi a5,a5,50 + 9ca: 02e7d7b3 divu a5,a5,a4 + 9ce: 0077f713 andi a4,a5,7 + 9d2: 00d767b3 or a5,a4,a3 + 9d6: 07c2 slli a5,a5,0x10 + 9d8: 83c1 srli a5,a5,0x10 + 9da: a41e sh a5,8(s0) + 9dc: 6145 addi sp,sp,48 + 9de: fb6ff06f j 194 <__riscv_restore_0> + 9e2: 5792 lw a5,36(sp) + 9e4: bf45 j 994 + 9e6: 070a slli a4,a4,0x2 + 9e8: b7c1 j 9a8 + 9ea: 0792 slli a5,a5,0x4 + 9ec: 03278793 addi a5,a5,50 + 9f0: 02e7d7b3 divu a5,a5,a4 + 9f4: 8bbd andi a5,a5,15 + 9f6: 8fd5 or a5,a5,a3 + 9f8: bff9 j 9d6 + +000009fa : + 9fa: c591 beqz a1,a06 + 9fc: 255e lhu a5,12(a0) + 9fe: 6709 lui a4,0x2 + a00: 8fd9 or a5,a5,a4 + a02: a55e sh a5,12(a0) + a04: 8082 ret + a06: 255a lhu a4,12(a0) + a08: 77f9 lui a5,0xffffe + a0a: 17fd addi a5,a5,-1 + a0c: 8ff9 and a5,a5,a4 + a0e: bfd5 j a02 + +00000a10 : + a10: 1ff5f593 andi a1,a1,511 + a14: a14e sh a1,4(a0) + a16: 8082 ret + +00000a18 : + a18: 210a lhu a0,0(a0) + a1a: 8d6d and a0,a0,a1 + a1c: 00a03533 snez a0,a0 + a20: 8082 ret + +00000a22 : + a22: 200007b7 lui a5,0x20000 + a26: 0807a783 lw a5,128(a5) # 20000080 + a2a: 6709 lui a4,0x2 + a2c: f4070713 addi a4,a4,-192 # 1f40 <_data_lma+0x188> + a30: 02e7d7b3 divu a5,a5,a4 + a34: 07c2 slli a5,a5,0x10 + a36: 83c1 srli a5,a5,0x10 + a38: 82f19923 sh a5,-1998(gp) # 200000b2 + a3c: 82f19823 sh a5,-2000(gp) # 200000b0 + a40: 8082 ret + +00000a42 : + a42: e000f7b7 lui a5,0xe000f + a46: 43d8 lw a4,4(a5) + a48: 4681 li a3,0 + a4a: 9b79 andi a4,a4,-2 + a4c: c3d8 sw a4,4(a5) + a4e: 8301d703 lhu a4,-2000(gp) # 200000b0 + a52: 02a70633 mul a2,a4,a0 + a56: cb90 sw a2,16(a5) + a58: cbd4 sw a3,20(a5) + a5a: 4398 lw a4,0(a5) + a5c: 01076713 ori a4,a4,16 + a60: c398 sw a4,0(a5) + a62: 4398 lw a4,0(a5) + a64: 02176713 ori a4,a4,33 + a68: c398 sw a4,0(a5) + a6a: 43d8 lw a4,4(a5) + a6c: 8b05 andi a4,a4,1 + a6e: df75 beqz a4,a6a + a70: 4398 lw a4,0(a5) + a72: 9b79 andi a4,a4,-2 + a74: c398 sw a4,0(a5) + a76: 8082 ret + +00000a78 : + a78: ef8ff2ef jal t0,170 <__riscv_save_0> + a7c: 842a mv s0,a0 + a7e: 6511 lui a0,0x4 + a80: 1101 addi sp,sp,-32 + a82: 4585 li a1,1 + a84: 0511 addi a0,a0,4 + a86: 3d71 jal 922 + a88: 20000793 li a5,512 + a8c: 827c sh a5,4(sp) + a8e: 40011537 lui a0,0x40011 + a92: 478d li a5,3 + a94: c43e sw a5,8(sp) + a96: 004c addi a1,sp,4 + a98: 47e1 li a5,24 + a9a: 80050513 addi a0,a0,-2048 # 40010800 <_eusrstack+0x2000b800> + a9e: c63e sw a5,12(sp) + aa0: 3ae5 jal 498 + aa2: c822 sw s0,16(sp) + aa4: 40014437 lui s0,0x40014 + aa8: 000807b7 lui a5,0x80 + aac: 080c addi a1,sp,16 + aae: 80040513 addi a0,s0,-2048 # 40013800 <_eusrstack+0x2000e800> + ab2: cc3e sw a5,24(sp) + ab4: ca02 sw zero,20(sp) + ab6: 00011e23 sh zero,28(sp) + aba: 3559 jal 940 + abc: 4585 li a1,1 + abe: 80040513 addi a0,s0,-2048 + ac2: 3f25 jal 9fa + ac4: 6105 addi sp,sp,32 + ac6: eceff06f j 194 <__riscv_restore_0> + +00000aca <_write>: + aca: e8cff2ef jal t0,156 <__riscv_save_4> + ace: 400144b7 lui s1,0x40014 + ad2: 89ae mv s3,a1 + ad4: 8932 mv s2,a2 + ad6: 4401 li s0,0 + ad8: 80048493 addi s1,s1,-2048 # 40013800 <_eusrstack+0x2000e800> + adc: 01244563 blt s0,s2,ae6 <_write+0x1c> + ae0: 854a mv a0,s2 + ae2: ea8ff06f j 18a <__riscv_restore_4> + ae6: 04000593 li a1,64 + aea: 8526 mv a0,s1 + aec: 3735 jal a18 + aee: dd65 beqz a0,ae6 <_write+0x1c> + af0: 008987b3 add a5,s3,s0 + af4: 00078583 lb a1,0(a5) # 80000 <_data_lma+0x7e248> + af8: 8526 mv a0,s1 + afa: 0405 addi s0,s0,1 + afc: 05c2 slli a1,a1,0x10 + afe: 81c1 srli a1,a1,0x10 + b00: 3f01 jal a10 + b02: bfe9 j adc <_write+0x12> + +00000b04 <_sbrk>: + b04: 80818713 addi a4,gp,-2040 # 20000088 + b08: 431c lw a5,0(a4) + b0a: 84018693 addi a3,gp,-1984 # 200000c0 <_ebss> + b0e: 953e add a0,a0,a5 + b10: 00d56b63 bltu a0,a3,b26 <_sbrk+0x22> + b14: 200056b7 lui a3,0x20005 + b18: 80068693 addi a3,a3,-2048 # 20004800 <_heap_end> + b1c: 00a6e563 bltu a3,a0,b26 <_sbrk+0x22> + b20: c308 sw a0,0(a4) + b22: 853e mv a0,a5 + b24: 8082 ret + b26: 57fd li a5,-1 + b28: bfed j b22 <_sbrk+0x1e> + +00000b2a : + b2a: 7139 addi sp,sp,-64 + b2c: da3e sw a5,52(sp) + b2e: d22e sw a1,36(sp) + b30: d432 sw a2,40(sp) + b32: d636 sw a3,44(sp) + b34: d83a sw a4,48(sp) + b36: dc42 sw a6,56(sp) + b38: de46 sw a7,60(sp) + b3a: 80c18793 addi a5,gp,-2036 # 2000008c <_impure_ptr> + b3e: cc22 sw s0,24(sp) + b40: 4380 lw s0,0(a5) + b42: ca26 sw s1,20(sp) + b44: ce06 sw ra,28(sp) + b46: 84aa mv s1,a0 + b48: c409 beqz s0,b52 + b4a: 4c1c lw a5,24(s0) + b4c: e399 bnez a5,b52 + b4e: 8522 mv a0,s0 + b50: 29ed jal 104a <__sinit> + b52: 440c lw a1,8(s0) + b54: 1054 addi a3,sp,36 + b56: 8626 mv a2,s1 + b58: 8522 mv a0,s0 + b5a: c636 sw a3,12(sp) + b5c: 127000ef jal ra,1482 <_vfiprintf_r> + b60: 40f2 lw ra,28(sp) + b62: 4462 lw s0,24(sp) + b64: 44d2 lw s1,20(sp) + b66: 6121 addi sp,sp,64 + b68: 8082 ret + +00000b6a <_puts_r>: + b6a: 1101 addi sp,sp,-32 + b6c: ca26 sw s1,20(sp) + b6e: c84a sw s2,16(sp) + b70: ce06 sw ra,28(sp) + b72: cc22 sw s0,24(sp) + b74: c64e sw s3,12(sp) + b76: c452 sw s4,8(sp) + b78: 84aa mv s1,a0 + b7a: 892e mv s2,a1 + b7c: c501 beqz a0,b84 <_puts_r+0x1a> + b7e: 4d1c lw a5,24(a0) + b80: e391 bnez a5,b84 <_puts_r+0x1a> + b82: 21e1 jal 104a <__sinit> + b84: 4c9c lw a5,24(s1) + b86: 4480 lw s0,8(s1) + b88: e399 bnez a5,b8e <_puts_r+0x24> + b8a: 8526 mv a0,s1 + b8c: 297d jal 104a <__sinit> + b8e: 00001797 auipc a5,0x1 + b92: 1ae78793 addi a5,a5,430 # 1d3c <__sf_fake_stdin> + b96: 02f41b63 bne s0,a5,bcc <_puts_r+0x62> + b9a: 40c0 lw s0,4(s1) + b9c: 245e lhu a5,12(s0) + b9e: 8ba1 andi a5,a5,8 + ba0: c7b1 beqz a5,bec <_puts_r+0x82> + ba2: 481c lw a5,16(s0) + ba4: c7a1 beqz a5,bec <_puts_r+0x82> + ba6: 59fd li s3,-1 + ba8: 4a29 li s4,10 + baa: 441c lw a5,8(s0) + bac: 00094583 lbu a1,0(s2) + bb0: 17fd addi a5,a5,-1 + bb2: e9b1 bnez a1,c06 <_puts_r+0x9c> + bb4: c41c sw a5,8(s0) + bb6: 0607dd63 bgez a5,c30 <_puts_r+0xc6> + bba: 8622 mv a2,s0 + bbc: 45a9 li a1,10 + bbe: 8526 mv a0,s1 + bc0: 2061 jal c48 <__swbuf_r> + bc2: 57fd li a5,-1 + bc4: 02f50863 beq a0,a5,bf4 <_puts_r+0x8a> + bc8: 4529 li a0,10 + bca: a035 j bf6 <_puts_r+0x8c> + bcc: 00001797 auipc a5,0x1 + bd0: 19078793 addi a5,a5,400 # 1d5c <__sf_fake_stdout> + bd4: 00f41463 bne s0,a5,bdc <_puts_r+0x72> + bd8: 4480 lw s0,8(s1) + bda: b7c9 j b9c <_puts_r+0x32> + bdc: 00001797 auipc a5,0x1 + be0: 14078793 addi a5,a5,320 # 1d1c <__sf_fake_stderr> + be4: faf41ce3 bne s0,a5,b9c <_puts_r+0x32> + be8: 44c0 lw s0,12(s1) + bea: bf4d j b9c <_puts_r+0x32> + bec: 85a2 mv a1,s0 + bee: 8526 mv a0,s1 + bf0: 2a11 jal d04 <__swsetup_r> + bf2: d955 beqz a0,ba6 <_puts_r+0x3c> + bf4: 557d li a0,-1 + bf6: 40f2 lw ra,28(sp) + bf8: 4462 lw s0,24(sp) + bfa: 44d2 lw s1,20(sp) + bfc: 4942 lw s2,16(sp) + bfe: 49b2 lw s3,12(sp) + c00: 4a22 lw s4,8(sp) + c02: 6105 addi sp,sp,32 + c04: 8082 ret + c06: c41c sw a5,8(s0) + c08: 0905 addi s2,s2,1 + c0a: 0007d763 bgez a5,c18 <_puts_r+0xae> + c0e: 4c18 lw a4,24(s0) + c10: 00e7ca63 blt a5,a4,c24 <_puts_r+0xba> + c14: 01458863 beq a1,s4,c24 <_puts_r+0xba> + c18: 401c lw a5,0(s0) + c1a: 00178713 addi a4,a5,1 + c1e: c018 sw a4,0(s0) + c20: a38c sb a1,0(a5) + c22: b761 j baa <_puts_r+0x40> + c24: 8622 mv a2,s0 + c26: 8526 mv a0,s1 + c28: 2005 jal c48 <__swbuf_r> + c2a: f93510e3 bne a0,s3,baa <_puts_r+0x40> + c2e: b7d9 j bf4 <_puts_r+0x8a> + c30: 401c lw a5,0(s0) + c32: 00178713 addi a4,a5,1 + c36: c018 sw a4,0(s0) + c38: 4729 li a4,10 + c3a: a398 sb a4,0(a5) + c3c: b771 j bc8 <_puts_r+0x5e> + +00000c3e : + c3e: 80c18793 addi a5,gp,-2036 # 2000008c <_impure_ptr> + c42: 85aa mv a1,a0 + c44: 4388 lw a0,0(a5) + c46: b715 j b6a <_puts_r> + +00000c48 <__swbuf_r>: + c48: 1101 addi sp,sp,-32 + c4a: cc22 sw s0,24(sp) + c4c: ca26 sw s1,20(sp) + c4e: c84a sw s2,16(sp) + c50: ce06 sw ra,28(sp) + c52: c64e sw s3,12(sp) + c54: 84aa mv s1,a0 + c56: 892e mv s2,a1 + c58: 8432 mv s0,a2 + c5a: c501 beqz a0,c62 <__swbuf_r+0x1a> + c5c: 4d1c lw a5,24(a0) + c5e: e391 bnez a5,c62 <__swbuf_r+0x1a> + c60: 26ed jal 104a <__sinit> + c62: 00001797 auipc a5,0x1 + c66: 0da78793 addi a5,a5,218 # 1d3c <__sf_fake_stdin> + c6a: 06f41763 bne s0,a5,cd8 <__swbuf_r+0x90> + c6e: 40c0 lw s0,4(s1) + c70: 4c1c lw a5,24(s0) + c72: c41c sw a5,8(s0) + c74: 245e lhu a5,12(s0) + c76: 8ba1 andi a5,a5,8 + c78: c3c1 beqz a5,cf8 <__swbuf_r+0xb0> + c7a: 481c lw a5,16(s0) + c7c: cfb5 beqz a5,cf8 <__swbuf_r+0xb0> + c7e: 481c lw a5,16(s0) + c80: 4008 lw a0,0(s0) + c82: 0ff97993 andi s3,s2,255 + c86: 0ff97913 andi s2,s2,255 + c8a: 8d1d sub a0,a0,a5 + c8c: 485c lw a5,20(s0) + c8e: 00f54663 blt a0,a5,c9a <__swbuf_r+0x52> + c92: 85a2 mv a1,s0 + c94: 8526 mv a0,s1 + c96: 2c69 jal f30 <_fflush_r> + c98: e525 bnez a0,d00 <__swbuf_r+0xb8> + c9a: 441c lw a5,8(s0) + c9c: 0505 addi a0,a0,1 + c9e: 17fd addi a5,a5,-1 + ca0: c41c sw a5,8(s0) + ca2: 401c lw a5,0(s0) + ca4: 00178713 addi a4,a5,1 + ca8: c018 sw a4,0(s0) + caa: 01378023 sb s3,0(a5) + cae: 485c lw a5,20(s0) + cb0: 00a78863 beq a5,a0,cc0 <__swbuf_r+0x78> + cb4: 245e lhu a5,12(s0) + cb6: 8b85 andi a5,a5,1 + cb8: cb81 beqz a5,cc8 <__swbuf_r+0x80> + cba: 47a9 li a5,10 + cbc: 00f91663 bne s2,a5,cc8 <__swbuf_r+0x80> + cc0: 85a2 mv a1,s0 + cc2: 8526 mv a0,s1 + cc4: 24b5 jal f30 <_fflush_r> + cc6: ed0d bnez a0,d00 <__swbuf_r+0xb8> + cc8: 40f2 lw ra,28(sp) + cca: 4462 lw s0,24(sp) + ccc: 854a mv a0,s2 + cce: 44d2 lw s1,20(sp) + cd0: 4942 lw s2,16(sp) + cd2: 49b2 lw s3,12(sp) + cd4: 6105 addi sp,sp,32 + cd6: 8082 ret + cd8: 00001797 auipc a5,0x1 + cdc: 08478793 addi a5,a5,132 # 1d5c <__sf_fake_stdout> + ce0: 00f41463 bne s0,a5,ce8 <__swbuf_r+0xa0> + ce4: 4480 lw s0,8(s1) + ce6: b769 j c70 <__swbuf_r+0x28> + ce8: 00001797 auipc a5,0x1 + cec: 03478793 addi a5,a5,52 # 1d1c <__sf_fake_stderr> + cf0: f8f410e3 bne s0,a5,c70 <__swbuf_r+0x28> + cf4: 44c0 lw s0,12(s1) + cf6: bfad j c70 <__swbuf_r+0x28> + cf8: 85a2 mv a1,s0 + cfa: 8526 mv a0,s1 + cfc: 2021 jal d04 <__swsetup_r> + cfe: d141 beqz a0,c7e <__swbuf_r+0x36> + d00: 597d li s2,-1 + d02: b7d9 j cc8 <__swbuf_r+0x80> + +00000d04 <__swsetup_r>: + d04: 1141 addi sp,sp,-16 + d06: 80c18793 addi a5,gp,-2036 # 2000008c <_impure_ptr> + d0a: c226 sw s1,4(sp) + d0c: 4384 lw s1,0(a5) + d0e: c422 sw s0,8(sp) + d10: c04a sw s2,0(sp) + d12: c606 sw ra,12(sp) + d14: 892a mv s2,a0 + d16: 842e mv s0,a1 + d18: c489 beqz s1,d22 <__swsetup_r+0x1e> + d1a: 4c9c lw a5,24(s1) + d1c: e399 bnez a5,d22 <__swsetup_r+0x1e> + d1e: 8526 mv a0,s1 + d20: 262d jal 104a <__sinit> + d22: 00001797 auipc a5,0x1 + d26: 01a78793 addi a5,a5,26 # 1d3c <__sf_fake_stdin> + d2a: 02f41b63 bne s0,a5,d60 <__swsetup_r+0x5c> + d2e: 40c0 lw s0,4(s1) + d30: 00c41703 lh a4,12(s0) + d34: 01071793 slli a5,a4,0x10 + d38: 83c1 srli a5,a5,0x10 + d3a: 0087f693 andi a3,a5,8 + d3e: eaad bnez a3,db0 <__swsetup_r+0xac> + d40: 0107f693 andi a3,a5,16 + d44: ee95 bnez a3,d80 <__swsetup_r+0x7c> + d46: 47a5 li a5,9 + d48: 00f92023 sw a5,0(s2) + d4c: 04076713 ori a4,a4,64 + d50: a45a sh a4,12(s0) + d52: 557d li a0,-1 + d54: 40b2 lw ra,12(sp) + d56: 4422 lw s0,8(sp) + d58: 4492 lw s1,4(sp) + d5a: 4902 lw s2,0(sp) + d5c: 0141 addi sp,sp,16 + d5e: 8082 ret + d60: 00001797 auipc a5,0x1 + d64: ffc78793 addi a5,a5,-4 # 1d5c <__sf_fake_stdout> + d68: 00f41463 bne s0,a5,d70 <__swsetup_r+0x6c> + d6c: 4480 lw s0,8(s1) + d6e: b7c9 j d30 <__swsetup_r+0x2c> + d70: 00001797 auipc a5,0x1 + d74: fac78793 addi a5,a5,-84 # 1d1c <__sf_fake_stderr> + d78: faf41ce3 bne s0,a5,d30 <__swsetup_r+0x2c> + d7c: 44c0 lw s0,12(s1) + d7e: bf4d j d30 <__swsetup_r+0x2c> + d80: 8b91 andi a5,a5,4 + d82: c39d beqz a5,da8 <__swsetup_r+0xa4> + d84: 584c lw a1,52(s0) + d86: c989 beqz a1,d98 <__swsetup_r+0x94> + d88: 04440793 addi a5,s0,68 + d8c: 00f58463 beq a1,a5,d94 <__swsetup_r+0x90> + d90: 854a mv a0,s2 + d92: 2331 jal 129e <_free_r> + d94: 02042a23 sw zero,52(s0) + d98: 245e lhu a5,12(s0) + d9a: 00042223 sw zero,4(s0) + d9e: fdb7f793 andi a5,a5,-37 + da2: a45e sh a5,12(s0) + da4: 481c lw a5,16(s0) + da6: c01c sw a5,0(s0) + da8: 245e lhu a5,12(s0) + daa: 0087e793 ori a5,a5,8 + dae: a45e sh a5,12(s0) + db0: 481c lw a5,16(s0) + db2: eb99 bnez a5,dc8 <__swsetup_r+0xc4> + db4: 245e lhu a5,12(s0) + db6: 20000713 li a4,512 + dba: 2807f793 andi a5,a5,640 + dbe: 00e78563 beq a5,a4,dc8 <__swsetup_r+0xc4> + dc2: 85a2 mv a1,s0 + dc4: 854a mv a0,s2 + dc6: 21a1 jal 120e <__smakebuf_r> + dc8: 245e lhu a5,12(s0) + dca: 0017f713 andi a4,a5,1 + dce: c31d beqz a4,df4 <__swsetup_r+0xf0> + dd0: 485c lw a5,20(s0) + dd2: 00042423 sw zero,8(s0) + dd6: 40f007b3 neg a5,a5 + dda: cc1c sw a5,24(s0) + ddc: 481c lw a5,16(s0) + dde: 4501 li a0,0 + de0: fbb5 bnez a5,d54 <__swsetup_r+0x50> + de2: 00c41783 lh a5,12(s0) + de6: 0807f713 andi a4,a5,128 + dea: d72d beqz a4,d54 <__swsetup_r+0x50> + dec: 0407e793 ori a5,a5,64 + df0: a45e sh a5,12(s0) + df2: b785 j d52 <__swsetup_r+0x4e> + df4: 8b89 andi a5,a5,2 + df6: 4701 li a4,0 + df8: e391 bnez a5,dfc <__swsetup_r+0xf8> + dfa: 4858 lw a4,20(s0) + dfc: c418 sw a4,8(s0) + dfe: bff9 j ddc <__swsetup_r+0xd8> + +00000e00 <__sflush_r>: + e00: 25de lhu a5,12(a1) + e02: 1101 addi sp,sp,-32 + e04: cc22 sw s0,24(sp) + e06: ca26 sw s1,20(sp) + e08: ce06 sw ra,28(sp) + e0a: c84a sw s2,16(sp) + e0c: c64e sw s3,12(sp) + e0e: 0087f713 andi a4,a5,8 + e12: 84aa mv s1,a0 + e14: 842e mv s0,a1 + e16: eb79 bnez a4,eec <__sflush_r+0xec> + e18: 41d8 lw a4,4(a1) + e1a: 00e04d63 bgtz a4,e34 <__sflush_r+0x34> + e1e: 41b8 lw a4,64(a1) + e20: 00e04a63 bgtz a4,e34 <__sflush_r+0x34> + e24: 4501 li a0,0 + e26: 40f2 lw ra,28(sp) + e28: 4462 lw s0,24(sp) + e2a: 44d2 lw s1,20(sp) + e2c: 4942 lw s2,16(sp) + e2e: 49b2 lw s3,12(sp) + e30: 6105 addi sp,sp,32 + e32: 8082 ret + e34: 5458 lw a4,44(s0) + e36: d77d beqz a4,e24 <__sflush_r+0x24> + e38: 0004a903 lw s2,0(s1) + e3c: 01379693 slli a3,a5,0x13 + e40: 0004a023 sw zero,0(s1) + e44: 0606db63 bgez a3,eba <__sflush_r+0xba> + e48: 4870 lw a2,84(s0) + e4a: 245e lhu a5,12(s0) + e4c: 8b91 andi a5,a5,4 + e4e: c799 beqz a5,e5c <__sflush_r+0x5c> + e50: 405c lw a5,4(s0) + e52: 8e1d sub a2,a2,a5 + e54: 585c lw a5,52(s0) + e56: c399 beqz a5,e5c <__sflush_r+0x5c> + e58: 403c lw a5,64(s0) + e5a: 8e1d sub a2,a2,a5 + e5c: 545c lw a5,44(s0) + e5e: 500c lw a1,32(s0) + e60: 4681 li a3,0 + e62: 8526 mv a0,s1 + e64: 9782 jalr a5 + e66: 57fd li a5,-1 + e68: 245a lhu a4,12(s0) + e6a: 00f51d63 bne a0,a5,e84 <__sflush_r+0x84> + e6e: 4094 lw a3,0(s1) + e70: 47f5 li a5,29 + e72: 06d7e863 bltu a5,a3,ee2 <__sflush_r+0xe2> + e76: 204007b7 lui a5,0x20400 + e7a: 0785 addi a5,a5,1 + e7c: 00d7d7b3 srl a5,a5,a3 + e80: 8b85 andi a5,a5,1 + e82: c3a5 beqz a5,ee2 <__sflush_r+0xe2> + e84: 481c lw a5,16(s0) + e86: 00042223 sw zero,4(s0) + e8a: c01c sw a5,0(s0) + e8c: 01371793 slli a5,a4,0x13 + e90: 0007d863 bgez a5,ea0 <__sflush_r+0xa0> + e94: 57fd li a5,-1 + e96: 00f51463 bne a0,a5,e9e <__sflush_r+0x9e> + e9a: 409c lw a5,0(s1) + e9c: e391 bnez a5,ea0 <__sflush_r+0xa0> + e9e: c868 sw a0,84(s0) + ea0: 584c lw a1,52(s0) + ea2: 0124a023 sw s2,0(s1) + ea6: ddbd beqz a1,e24 <__sflush_r+0x24> + ea8: 04440793 addi a5,s0,68 + eac: 00f58463 beq a1,a5,eb4 <__sflush_r+0xb4> + eb0: 8526 mv a0,s1 + eb2: 26f5 jal 129e <_free_r> + eb4: 02042a23 sw zero,52(s0) + eb8: b7b5 j e24 <__sflush_r+0x24> + eba: 500c lw a1,32(s0) + ebc: 4601 li a2,0 + ebe: 4685 li a3,1 + ec0: 8526 mv a0,s1 + ec2: 9702 jalr a4 + ec4: 57fd li a5,-1 + ec6: 862a mv a2,a0 + ec8: f8f511e3 bne a0,a5,e4a <__sflush_r+0x4a> + ecc: 409c lw a5,0(s1) + ece: dfb5 beqz a5,e4a <__sflush_r+0x4a> + ed0: 4775 li a4,29 + ed2: 00e78563 beq a5,a4,edc <__sflush_r+0xdc> + ed6: 4759 li a4,22 + ed8: 04e79363 bne a5,a4,f1e <__sflush_r+0x11e> + edc: 0124a023 sw s2,0(s1) + ee0: b791 j e24 <__sflush_r+0x24> + ee2: 04076713 ori a4,a4,64 + ee6: a45a sh a4,12(s0) + ee8: 557d li a0,-1 + eea: bf35 j e26 <__sflush_r+0x26> + eec: 0105a983 lw s3,16(a1) + ef0: f2098ae3 beqz s3,e24 <__sflush_r+0x24> + ef4: 0005a903 lw s2,0(a1) + ef8: 8b8d andi a5,a5,3 + efa: 0135a023 sw s3,0(a1) + efe: 41390933 sub s2,s2,s3 + f02: 4701 li a4,0 + f04: e391 bnez a5,f08 <__sflush_r+0x108> + f06: 49d8 lw a4,20(a1) + f08: c418 sw a4,8(s0) + f0a: f1205de3 blez s2,e24 <__sflush_r+0x24> + f0e: 541c lw a5,40(s0) + f10: 500c lw a1,32(s0) + f12: 86ca mv a3,s2 + f14: 864e mv a2,s3 + f16: 8526 mv a0,s1 + f18: 9782 jalr a5 + f1a: 00a04763 bgtz a0,f28 <__sflush_r+0x128> + f1e: 245e lhu a5,12(s0) + f20: 0407e793 ori a5,a5,64 + f24: a45e sh a5,12(s0) + f26: b7c9 j ee8 <__sflush_r+0xe8> + f28: 99aa add s3,s3,a0 + f2a: 40a90933 sub s2,s2,a0 + f2e: bff1 j f0a <__sflush_r+0x10a> + +00000f30 <_fflush_r>: + f30: 499c lw a5,16(a1) + f32: cfb9 beqz a5,f90 <_fflush_r+0x60> + f34: 1101 addi sp,sp,-32 + f36: cc22 sw s0,24(sp) + f38: ce06 sw ra,28(sp) + f3a: 842a mv s0,a0 + f3c: c511 beqz a0,f48 <_fflush_r+0x18> + f3e: 4d1c lw a5,24(a0) + f40: e781 bnez a5,f48 <_fflush_r+0x18> + f42: c62e sw a1,12(sp) + f44: 2219 jal 104a <__sinit> + f46: 45b2 lw a1,12(sp) + f48: 00001797 auipc a5,0x1 + f4c: df478793 addi a5,a5,-524 # 1d3c <__sf_fake_stdin> + f50: 00f59b63 bne a1,a5,f66 <_fflush_r+0x36> + f54: 404c lw a1,4(s0) + f56: 00c59783 lh a5,12(a1) + f5a: c795 beqz a5,f86 <_fflush_r+0x56> + f5c: 8522 mv a0,s0 + f5e: 4462 lw s0,24(sp) + f60: 40f2 lw ra,28(sp) + f62: 6105 addi sp,sp,32 + f64: bd71 j e00 <__sflush_r> + f66: 00001797 auipc a5,0x1 + f6a: df678793 addi a5,a5,-522 # 1d5c <__sf_fake_stdout> + f6e: 00f59463 bne a1,a5,f76 <_fflush_r+0x46> + f72: 440c lw a1,8(s0) + f74: b7cd j f56 <_fflush_r+0x26> + f76: 00001797 auipc a5,0x1 + f7a: da678793 addi a5,a5,-602 # 1d1c <__sf_fake_stderr> + f7e: fcf59ce3 bne a1,a5,f56 <_fflush_r+0x26> + f82: 444c lw a1,12(s0) + f84: bfc9 j f56 <_fflush_r+0x26> + f86: 40f2 lw ra,28(sp) + f88: 4462 lw s0,24(sp) + f8a: 4501 li a0,0 + f8c: 6105 addi sp,sp,32 + f8e: 8082 ret + f90: 4501 li a0,0 + f92: 8082 ret + +00000f94 : + f94: 1141 addi sp,sp,-16 + f96: c422 sw s0,8(sp) + f98: c606 sw ra,12(sp) + f9a: 842a mv s0,a0 + f9c: a54e sh a1,12(a0) + f9e: a572 sh a2,14(a0) + fa0: 00052023 sw zero,0(a0) + fa4: 00052223 sw zero,4(a0) + fa8: 00052423 sw zero,8(a0) + fac: 06052223 sw zero,100(a0) + fb0: 00052823 sw zero,16(a0) + fb4: 00052a23 sw zero,20(a0) + fb8: 00052c23 sw zero,24(a0) + fbc: 4621 li a2,8 + fbe: 4581 li a1,0 + fc0: 05c50513 addi a0,a0,92 + fc4: 9dcff0ef jal ra,1a0 + fc8: 00001797 auipc a5,0x1 + fcc: b1478793 addi a5,a5,-1260 # 1adc <__sread> + fd0: d05c sw a5,36(s0) + fd2: 00001797 auipc a5,0x1 + fd6: b3678793 addi a5,a5,-1226 # 1b08 <__swrite> + fda: d41c sw a5,40(s0) + fdc: 00001797 auipc a5,0x1 + fe0: b7478793 addi a5,a5,-1164 # 1b50 <__sseek> + fe4: d45c sw a5,44(s0) + fe6: 00001797 auipc a5,0x1 + fea: b9a78793 addi a5,a5,-1126 # 1b80 <__sclose> + fee: d000 sw s0,32(s0) + ff0: d81c sw a5,48(s0) + ff2: 40b2 lw ra,12(sp) + ff4: 4422 lw s0,8(sp) + ff6: 0141 addi sp,sp,16 + ff8: 8082 ret + +00000ffa <_cleanup_r>: + ffa: 00000597 auipc a1,0x0 + ffe: f3658593 addi a1,a1,-202 # f30 <_fflush_r> + 1002: a2a9 j 114c <_fwalk_reent> + +00001004 <__sfmoreglue>: + 1004: 1141 addi sp,sp,-16 + 1006: c226 sw s1,4(sp) + 1008: 06800613 li a2,104 + 100c: fff58493 addi s1,a1,-1 + 1010: 02c484b3 mul s1,s1,a2 + 1014: c04a sw s2,0(sp) + 1016: 892e mv s2,a1 + 1018: c422 sw s0,8(sp) + 101a: c606 sw ra,12(sp) + 101c: 07448593 addi a1,s1,116 + 1020: 261d jal 1346 <_malloc_r> + 1022: 842a mv s0,a0 + 1024: cd01 beqz a0,103c <__sfmoreglue+0x38> + 1026: 00052023 sw zero,0(a0) + 102a: 01252223 sw s2,4(a0) + 102e: 0531 addi a0,a0,12 + 1030: c408 sw a0,8(s0) + 1032: 06848613 addi a2,s1,104 + 1036: 4581 li a1,0 + 1038: 968ff0ef jal ra,1a0 + 103c: 8522 mv a0,s0 + 103e: 40b2 lw ra,12(sp) + 1040: 4422 lw s0,8(sp) + 1042: 4492 lw s1,4(sp) + 1044: 4902 lw s2,0(sp) + 1046: 0141 addi sp,sp,16 + 1048: 8082 ret + +0000104a <__sinit>: + 104a: 4d1c lw a5,24(a0) + 104c: e3ad bnez a5,10ae <__sinit+0x64> + 104e: 1141 addi sp,sp,-16 + 1050: c606 sw ra,12(sp) + 1052: c422 sw s0,8(sp) + 1054: 00000797 auipc a5,0x0 + 1058: fa678793 addi a5,a5,-90 # ffa <_cleanup_r> + 105c: d51c sw a5,40(a0) + 105e: 81018793 addi a5,gp,-2032 # 20000090 <_global_impure_ptr> + 1062: 439c lw a5,0(a5) + 1064: 04052423 sw zero,72(a0) + 1068: 04052623 sw zero,76(a0) + 106c: 04052823 sw zero,80(a0) + 1070: 00f51463 bne a0,a5,1078 <__sinit+0x2e> + 1074: 4785 li a5,1 + 1076: cd1c sw a5,24(a0) + 1078: 842a mv s0,a0 + 107a: 281d jal 10b0 <__sfp> + 107c: c048 sw a0,4(s0) + 107e: 8522 mv a0,s0 + 1080: 2805 jal 10b0 <__sfp> + 1082: c408 sw a0,8(s0) + 1084: 8522 mv a0,s0 + 1086: 202d jal 10b0 <__sfp> + 1088: c448 sw a0,12(s0) + 108a: 4048 lw a0,4(s0) + 108c: 4601 li a2,0 + 108e: 4591 li a1,4 + 1090: 3711 jal f94 + 1092: 4408 lw a0,8(s0) + 1094: 4605 li a2,1 + 1096: 45a5 li a1,9 + 1098: 3df5 jal f94 + 109a: 4448 lw a0,12(s0) + 109c: 4609 li a2,2 + 109e: 45c9 li a1,18 + 10a0: 3dd5 jal f94 + 10a2: 4785 li a5,1 + 10a4: cc1c sw a5,24(s0) + 10a6: 40b2 lw ra,12(sp) + 10a8: 4422 lw s0,8(sp) + 10aa: 0141 addi sp,sp,16 + 10ac: 8082 ret + 10ae: 8082 ret + +000010b0 <__sfp>: + 10b0: 1141 addi sp,sp,-16 + 10b2: 81018793 addi a5,gp,-2032 # 20000090 <_global_impure_ptr> + 10b6: c226 sw s1,4(sp) + 10b8: 4384 lw s1,0(a5) + 10ba: c04a sw s2,0(sp) + 10bc: c606 sw ra,12(sp) + 10be: 4c9c lw a5,24(s1) + 10c0: c422 sw s0,8(sp) + 10c2: 892a mv s2,a0 + 10c4: e399 bnez a5,10ca <__sfp+0x1a> + 10c6: 8526 mv a0,s1 + 10c8: 3749 jal 104a <__sinit> + 10ca: 04848493 addi s1,s1,72 + 10ce: 4480 lw s0,8(s1) + 10d0: 40dc lw a5,4(s1) + 10d2: 17fd addi a5,a5,-1 + 10d4: 0007d663 bgez a5,10e0 <__sfp+0x30> + 10d8: 409c lw a5,0(s1) + 10da: cfb9 beqz a5,1138 <__sfp+0x88> + 10dc: 4084 lw s1,0(s1) + 10de: bfc5 j 10ce <__sfp+0x1e> + 10e0: 00c41703 lh a4,12(s0) + 10e4: e739 bnez a4,1132 <__sfp+0x82> + 10e6: 77c1 lui a5,0xffff0 + 10e8: 0785 addi a5,a5,1 + 10ea: 06042223 sw zero,100(s0) + 10ee: 00042023 sw zero,0(s0) + 10f2: 00042223 sw zero,4(s0) + 10f6: 00042423 sw zero,8(s0) + 10fa: c45c sw a5,12(s0) + 10fc: 00042823 sw zero,16(s0) + 1100: 00042a23 sw zero,20(s0) + 1104: 00042c23 sw zero,24(s0) + 1108: 4621 li a2,8 + 110a: 4581 li a1,0 + 110c: 05c40513 addi a0,s0,92 + 1110: 890ff0ef jal ra,1a0 + 1114: 02042a23 sw zero,52(s0) + 1118: 02042c23 sw zero,56(s0) + 111c: 04042423 sw zero,72(s0) + 1120: 04042623 sw zero,76(s0) + 1124: 8522 mv a0,s0 + 1126: 40b2 lw ra,12(sp) + 1128: 4422 lw s0,8(sp) + 112a: 4492 lw s1,4(sp) + 112c: 4902 lw s2,0(sp) + 112e: 0141 addi sp,sp,16 + 1130: 8082 ret + 1132: 06840413 addi s0,s0,104 + 1136: bf71 j 10d2 <__sfp+0x22> + 1138: 4591 li a1,4 + 113a: 854a mv a0,s2 + 113c: 35e1 jal 1004 <__sfmoreglue> + 113e: c088 sw a0,0(s1) + 1140: fd51 bnez a0,10dc <__sfp+0x2c> + 1142: 47b1 li a5,12 + 1144: 00f92023 sw a5,0(s2) + 1148: 4401 li s0,0 + 114a: bfe9 j 1124 <__sfp+0x74> + +0000114c <_fwalk_reent>: + 114c: 7179 addi sp,sp,-48 + 114e: d422 sw s0,40(sp) + 1150: d04a sw s2,32(sp) + 1152: cc52 sw s4,24(sp) + 1154: ca56 sw s5,20(sp) + 1156: c85a sw s6,16(sp) + 1158: c65e sw s7,12(sp) + 115a: d606 sw ra,44(sp) + 115c: d226 sw s1,36(sp) + 115e: ce4e sw s3,28(sp) + 1160: 8a2a mv s4,a0 + 1162: 8aae mv s5,a1 + 1164: 04850413 addi s0,a0,72 + 1168: 4901 li s2,0 + 116a: 4b05 li s6,1 + 116c: 5bfd li s7,-1 + 116e: ec09 bnez s0,1188 <_fwalk_reent+0x3c> + 1170: 50b2 lw ra,44(sp) + 1172: 5422 lw s0,40(sp) + 1174: 854a mv a0,s2 + 1176: 5492 lw s1,36(sp) + 1178: 5902 lw s2,32(sp) + 117a: 49f2 lw s3,28(sp) + 117c: 4a62 lw s4,24(sp) + 117e: 4ad2 lw s5,20(sp) + 1180: 4b42 lw s6,16(sp) + 1182: 4bb2 lw s7,12(sp) + 1184: 6145 addi sp,sp,48 + 1186: 8082 ret + 1188: 4404 lw s1,8(s0) + 118a: 00442983 lw s3,4(s0) + 118e: 19fd addi s3,s3,-1 + 1190: 0009d463 bgez s3,1198 <_fwalk_reent+0x4c> + 1194: 4000 lw s0,0(s0) + 1196: bfe1 j 116e <_fwalk_reent+0x22> + 1198: 24de lhu a5,12(s1) + 119a: 00fb7b63 bgeu s6,a5,11b0 <_fwalk_reent+0x64> + 119e: 00e49783 lh a5,14(s1) + 11a2: 01778763 beq a5,s7,11b0 <_fwalk_reent+0x64> + 11a6: 85a6 mv a1,s1 + 11a8: 8552 mv a0,s4 + 11aa: 9a82 jalr s5 + 11ac: 00a96933 or s2,s2,a0 + 11b0: 06848493 addi s1,s1,104 + 11b4: bfe9 j 118e <_fwalk_reent+0x42> + +000011b6 <__swhatbuf_r>: + 11b6: 7119 addi sp,sp,-128 + 11b8: daa6 sw s1,116(sp) + 11ba: 84ae mv s1,a1 + 11bc: 00e59583 lh a1,14(a1) + 11c0: dca2 sw s0,120(sp) + 11c2: de86 sw ra,124(sp) + 11c4: 8432 mv s0,a2 + 11c6: 0005db63 bgez a1,11dc <__swhatbuf_r+0x26> + 11ca: 24de lhu a5,12(s1) + 11cc: 0006a023 sw zero,0(a3) + 11d0: 0807f793 andi a5,a5,128 + 11d4: e785 bnez a5,11fc <__swhatbuf_r+0x46> + 11d6: 40000793 li a5,1024 + 11da: a01d j 1200 <__swhatbuf_r+0x4a> + 11dc: 0830 addi a2,sp,24 + 11de: c636 sw a3,12(sp) + 11e0: 1fd000ef jal ra,1bdc <_fstat_r> + 11e4: 46b2 lw a3,12(sp) + 11e6: fe0542e3 bltz a0,11ca <__swhatbuf_r+0x14> + 11ea: 4772 lw a4,28(sp) + 11ec: 67bd lui a5,0xf + 11ee: 8ff9 and a5,a5,a4 + 11f0: 7779 lui a4,0xffffe + 11f2: 97ba add a5,a5,a4 + 11f4: 0017b793 seqz a5,a5 + 11f8: c29c sw a5,0(a3) + 11fa: bff1 j 11d6 <__swhatbuf_r+0x20> + 11fc: 04000793 li a5,64 + 1200: c01c sw a5,0(s0) + 1202: 50f6 lw ra,124(sp) + 1204: 5466 lw s0,120(sp) + 1206: 54d6 lw s1,116(sp) + 1208: 4501 li a0,0 + 120a: 6109 addi sp,sp,128 + 120c: 8082 ret + +0000120e <__smakebuf_r>: + 120e: 25de lhu a5,12(a1) + 1210: 1101 addi sp,sp,-32 + 1212: cc22 sw s0,24(sp) + 1214: ce06 sw ra,28(sp) + 1216: ca26 sw s1,20(sp) + 1218: c84a sw s2,16(sp) + 121a: 8b89 andi a5,a5,2 + 121c: 842e mv s0,a1 + 121e: cf89 beqz a5,1238 <__smakebuf_r+0x2a> + 1220: 04740793 addi a5,s0,71 + 1224: c01c sw a5,0(s0) + 1226: c81c sw a5,16(s0) + 1228: 4785 li a5,1 + 122a: c85c sw a5,20(s0) + 122c: 40f2 lw ra,28(sp) + 122e: 4462 lw s0,24(sp) + 1230: 44d2 lw s1,20(sp) + 1232: 4942 lw s2,16(sp) + 1234: 6105 addi sp,sp,32 + 1236: 8082 ret + 1238: 0074 addi a3,sp,12 + 123a: 0030 addi a2,sp,8 + 123c: 84aa mv s1,a0 + 123e: 3fa5 jal 11b6 <__swhatbuf_r> + 1240: 45a2 lw a1,8(sp) + 1242: 892a mv s2,a0 + 1244: 8526 mv a0,s1 + 1246: 2201 jal 1346 <_malloc_r> + 1248: e919 bnez a0,125e <__smakebuf_r+0x50> + 124a: 00c41783 lh a5,12(s0) + 124e: 2007f713 andi a4,a5,512 + 1252: ff69 bnez a4,122c <__smakebuf_r+0x1e> + 1254: 9bf1 andi a5,a5,-4 + 1256: 0027e793 ori a5,a5,2 + 125a: a45e sh a5,12(s0) + 125c: b7d1 j 1220 <__smakebuf_r+0x12> + 125e: 00000797 auipc a5,0x0 + 1262: d9c78793 addi a5,a5,-612 # ffa <_cleanup_r> + 1266: d49c sw a5,40(s1) + 1268: 245e lhu a5,12(s0) + 126a: c008 sw a0,0(s0) + 126c: c808 sw a0,16(s0) + 126e: 0807e793 ori a5,a5,128 + 1272: a45e sh a5,12(s0) + 1274: 47a2 lw a5,8(sp) + 1276: c85c sw a5,20(s0) + 1278: 47b2 lw a5,12(sp) + 127a: cf81 beqz a5,1292 <__smakebuf_r+0x84> + 127c: 00e41583 lh a1,14(s0) + 1280: 8526 mv a0,s1 + 1282: 185000ef jal ra,1c06 <_isatty_r> + 1286: c511 beqz a0,1292 <__smakebuf_r+0x84> + 1288: 245e lhu a5,12(s0) + 128a: 9bf1 andi a5,a5,-4 + 128c: 0017e793 ori a5,a5,1 + 1290: a45e sh a5,12(s0) + 1292: 245e lhu a5,12(s0) + 1294: 00f96933 or s2,s2,a5 + 1298: 01241623 sh s2,12(s0) + 129c: bf41 j 122c <__smakebuf_r+0x1e> + +0000129e <_free_r>: + 129e: c1dd beqz a1,1344 <_free_r+0xa6> + 12a0: ffc5a783 lw a5,-4(a1) + 12a4: 1141 addi sp,sp,-16 + 12a6: c422 sw s0,8(sp) + 12a8: c606 sw ra,12(sp) + 12aa: c226 sw s1,4(sp) + 12ac: ffc58413 addi s0,a1,-4 + 12b0: 0007d363 bgez a5,12b6 <_free_r+0x18> + 12b4: 943e add s0,s0,a5 + 12b6: 84aa mv s1,a0 + 12b8: 1bb000ef jal ra,1c72 <__malloc_lock> + 12bc: 83418793 addi a5,gp,-1996 # 200000b4 <__malloc_free_list> + 12c0: 439c lw a5,0(a5) + 12c2: ef81 bnez a5,12da <_free_r+0x3c> + 12c4: 00042223 sw zero,4(s0) + 12c8: 8281aa23 sw s0,-1996(gp) # 200000b4 <__malloc_free_list> + 12cc: 4422 lw s0,8(sp) + 12ce: 40b2 lw ra,12(sp) + 12d0: 8526 mv a0,s1 + 12d2: 4492 lw s1,4(sp) + 12d4: 0141 addi sp,sp,16 + 12d6: 19f0006f j 1c74 <__malloc_unlock> + 12da: 00f47e63 bgeu s0,a5,12f6 <_free_r+0x58> + 12de: 4014 lw a3,0(s0) + 12e0: 00d40733 add a4,s0,a3 + 12e4: 00e79663 bne a5,a4,12f0 <_free_r+0x52> + 12e8: 4398 lw a4,0(a5) + 12ea: 43dc lw a5,4(a5) + 12ec: 9736 add a4,a4,a3 + 12ee: c018 sw a4,0(s0) + 12f0: c05c sw a5,4(s0) + 12f2: bfd9 j 12c8 <_free_r+0x2a> + 12f4: 87ba mv a5,a4 + 12f6: 43d8 lw a4,4(a5) + 12f8: c319 beqz a4,12fe <_free_r+0x60> + 12fa: fee47de3 bgeu s0,a4,12f4 <_free_r+0x56> + 12fe: 4394 lw a3,0(a5) + 1300: 00d78633 add a2,a5,a3 + 1304: 00861f63 bne a2,s0,1322 <_free_r+0x84> + 1308: 4010 lw a2,0(s0) + 130a: 96b2 add a3,a3,a2 + 130c: c394 sw a3,0(a5) + 130e: 00d78633 add a2,a5,a3 + 1312: fac71de3 bne a4,a2,12cc <_free_r+0x2e> + 1316: 4310 lw a2,0(a4) + 1318: 4358 lw a4,4(a4) + 131a: 96b2 add a3,a3,a2 + 131c: c394 sw a3,0(a5) + 131e: c3d8 sw a4,4(a5) + 1320: b775 j 12cc <_free_r+0x2e> + 1322: 00c47563 bgeu s0,a2,132c <_free_r+0x8e> + 1326: 47b1 li a5,12 + 1328: c09c sw a5,0(s1) + 132a: b74d j 12cc <_free_r+0x2e> + 132c: 4010 lw a2,0(s0) + 132e: 00c406b3 add a3,s0,a2 + 1332: 00d71663 bne a4,a3,133e <_free_r+0xa0> + 1336: 4314 lw a3,0(a4) + 1338: 4358 lw a4,4(a4) + 133a: 96b2 add a3,a3,a2 + 133c: c014 sw a3,0(s0) + 133e: c058 sw a4,4(s0) + 1340: c3c0 sw s0,4(a5) + 1342: b769 j 12cc <_free_r+0x2e> + 1344: 8082 ret + +00001346 <_malloc_r>: + 1346: 1101 addi sp,sp,-32 + 1348: ca26 sw s1,20(sp) + 134a: 00358493 addi s1,a1,3 + 134e: 98f1 andi s1,s1,-4 + 1350: ce06 sw ra,28(sp) + 1352: cc22 sw s0,24(sp) + 1354: c84a sw s2,16(sp) + 1356: c64e sw s3,12(sp) + 1358: 04a1 addi s1,s1,8 + 135a: 47b1 li a5,12 + 135c: 04f4f363 bgeu s1,a5,13a2 <_malloc_r+0x5c> + 1360: 44b1 li s1,12 + 1362: 04b4e263 bltu s1,a1,13a6 <_malloc_r+0x60> + 1366: 892a mv s2,a0 + 1368: 10b000ef jal ra,1c72 <__malloc_lock> + 136c: 83418793 addi a5,gp,-1996 # 200000b4 <__malloc_free_list> + 1370: 4398 lw a4,0(a5) + 1372: 843a mv s0,a4 + 1374: e039 bnez s0,13ba <_malloc_r+0x74> + 1376: 83818793 addi a5,gp,-1992 # 200000b8 <__malloc_sbrk_start> + 137a: 439c lw a5,0(a5) + 137c: e791 bnez a5,1388 <_malloc_r+0x42> + 137e: 4581 li a1,0 + 1380: 854a mv a0,s2 + 1382: 2f05 jal 1ab2 <_sbrk_r> + 1384: 82a1ac23 sw a0,-1992(gp) # 200000b8 <__malloc_sbrk_start> + 1388: 85a6 mv a1,s1 + 138a: 854a mv a0,s2 + 138c: 271d jal 1ab2 <_sbrk_r> + 138e: 59fd li s3,-1 + 1390: 07351963 bne a0,s3,1402 <_malloc_r+0xbc> + 1394: 47b1 li a5,12 + 1396: 00f92023 sw a5,0(s2) + 139a: 854a mv a0,s2 + 139c: 0d9000ef jal ra,1c74 <__malloc_unlock> + 13a0: a029 j 13aa <_malloc_r+0x64> + 13a2: fc04d0e3 bgez s1,1362 <_malloc_r+0x1c> + 13a6: 47b1 li a5,12 + 13a8: c11c sw a5,0(a0) + 13aa: 4501 li a0,0 + 13ac: 40f2 lw ra,28(sp) + 13ae: 4462 lw s0,24(sp) + 13b0: 44d2 lw s1,20(sp) + 13b2: 4942 lw s2,16(sp) + 13b4: 49b2 lw s3,12(sp) + 13b6: 6105 addi sp,sp,32 + 13b8: 8082 ret + 13ba: 401c lw a5,0(s0) + 13bc: 8f85 sub a5,a5,s1 + 13be: 0207cf63 bltz a5,13fc <_malloc_r+0xb6> + 13c2: 46ad li a3,11 + 13c4: 00f6f663 bgeu a3,a5,13d0 <_malloc_r+0x8a> + 13c8: c01c sw a5,0(s0) + 13ca: 943e add s0,s0,a5 + 13cc: c004 sw s1,0(s0) + 13ce: a031 j 13da <_malloc_r+0x94> + 13d0: 405c lw a5,4(s0) + 13d2: 02871363 bne a4,s0,13f8 <_malloc_r+0xb2> + 13d6: 82f1aa23 sw a5,-1996(gp) # 200000b4 <__malloc_free_list> + 13da: 854a mv a0,s2 + 13dc: 099000ef jal ra,1c74 <__malloc_unlock> + 13e0: 00b40513 addi a0,s0,11 + 13e4: 00440793 addi a5,s0,4 + 13e8: 9961 andi a0,a0,-8 + 13ea: 40f50733 sub a4,a0,a5 + 13ee: df5d beqz a4,13ac <_malloc_r+0x66> + 13f0: 943a add s0,s0,a4 + 13f2: 8f89 sub a5,a5,a0 + 13f4: c01c sw a5,0(s0) + 13f6: bf5d j 13ac <_malloc_r+0x66> + 13f8: c35c sw a5,4(a4) + 13fa: b7c5 j 13da <_malloc_r+0x94> + 13fc: 8722 mv a4,s0 + 13fe: 4040 lw s0,4(s0) + 1400: bf95 j 1374 <_malloc_r+0x2e> + 1402: 00350413 addi s0,a0,3 + 1406: 9871 andi s0,s0,-4 + 1408: fc8502e3 beq a0,s0,13cc <_malloc_r+0x86> + 140c: 40a405b3 sub a1,s0,a0 + 1410: 854a mv a0,s2 + 1412: 2545 jal 1ab2 <_sbrk_r> + 1414: fb351ce3 bne a0,s3,13cc <_malloc_r+0x86> + 1418: bfb5 j 1394 <_malloc_r+0x4e> + +0000141a <__sfputc_r>: + 141a: 461c lw a5,8(a2) + 141c: 17fd addi a5,a5,-1 + 141e: c61c sw a5,8(a2) + 1420: 0007da63 bgez a5,1434 <__sfputc_r+0x1a> + 1424: 4e18 lw a4,24(a2) + 1426: 00e7c563 blt a5,a4,1430 <__sfputc_r+0x16> + 142a: 47a9 li a5,10 + 142c: 00f59463 bne a1,a5,1434 <__sfputc_r+0x1a> + 1430: 819ff06f j c48 <__swbuf_r> + 1434: 421c lw a5,0(a2) + 1436: 852e mv a0,a1 + 1438: 00178713 addi a4,a5,1 + 143c: c218 sw a4,0(a2) + 143e: a38c sb a1,0(a5) + 1440: 8082 ret + +00001442 <__sfputs_r>: + 1442: 1101 addi sp,sp,-32 + 1444: cc22 sw s0,24(sp) + 1446: ca26 sw s1,20(sp) + 1448: c84a sw s2,16(sp) + 144a: c64e sw s3,12(sp) + 144c: c452 sw s4,8(sp) + 144e: ce06 sw ra,28(sp) + 1450: 892a mv s2,a0 + 1452: 89ae mv s3,a1 + 1454: 8432 mv s0,a2 + 1456: 00d604b3 add s1,a2,a3 + 145a: 5a7d li s4,-1 + 145c: 00941463 bne s0,s1,1464 <__sfputs_r+0x22> + 1460: 4501 li a0,0 + 1462: a801 j 1472 <__sfputs_r+0x30> + 1464: 200c lbu a1,0(s0) + 1466: 864e mv a2,s3 + 1468: 854a mv a0,s2 + 146a: 3f45 jal 141a <__sfputc_r> + 146c: 0405 addi s0,s0,1 + 146e: ff4517e3 bne a0,s4,145c <__sfputs_r+0x1a> + 1472: 40f2 lw ra,28(sp) + 1474: 4462 lw s0,24(sp) + 1476: 44d2 lw s1,20(sp) + 1478: 4942 lw s2,16(sp) + 147a: 49b2 lw s3,12(sp) + 147c: 4a22 lw s4,8(sp) + 147e: 6105 addi sp,sp,32 + 1480: 8082 ret + +00001482 <_vfiprintf_r>: + 1482: 7135 addi sp,sp,-160 + 1484: cd22 sw s0,152(sp) + 1486: cb26 sw s1,148(sp) + 1488: c94a sw s2,144(sp) + 148a: c74e sw s3,140(sp) + 148c: cf06 sw ra,156(sp) + 148e: c552 sw s4,136(sp) + 1490: c356 sw s5,132(sp) + 1492: c15a sw s6,128(sp) + 1494: dede sw s7,124(sp) + 1496: dce2 sw s8,120(sp) + 1498: dae6 sw s9,116(sp) + 149a: 89aa mv s3,a0 + 149c: 84ae mv s1,a1 + 149e: 8932 mv s2,a2 + 14a0: 8436 mv s0,a3 + 14a2: c501 beqz a0,14aa <_vfiprintf_r+0x28> + 14a4: 4d1c lw a5,24(a0) + 14a6: e391 bnez a5,14aa <_vfiprintf_r+0x28> + 14a8: 364d jal 104a <__sinit> + 14aa: 00001797 auipc a5,0x1 + 14ae: 89278793 addi a5,a5,-1902 # 1d3c <__sf_fake_stdin> + 14b2: 0cf49763 bne s1,a5,1580 <_vfiprintf_r+0xfe> + 14b6: 0049a483 lw s1,4(s3) + 14ba: 24de lhu a5,12(s1) + 14bc: 8ba1 andi a5,a5,8 + 14be: c3fd beqz a5,15a4 <_vfiprintf_r+0x122> + 14c0: 489c lw a5,16(s1) + 14c2: c3ed beqz a5,15a4 <_vfiprintf_r+0x122> + 14c4: 02000793 li a5,32 + 14c8: 02f104a3 sb a5,41(sp) + 14cc: 03000793 li a5,48 + 14d0: d202 sw zero,36(sp) + 14d2: 02f10523 sb a5,42(sp) + 14d6: c622 sw s0,12(sp) + 14d8: 02500b93 li s7,37 + 14dc: 00001a97 auipc s5,0x1 + 14e0: 8a0a8a93 addi s5,s5,-1888 # 1d7c <__sf_fake_stdout+0x20> + 14e4: 4c05 li s8,1 + 14e6: 4b29 li s6,10 + 14e8: 844a mv s0,s2 + 14ea: 201c lbu a5,0(s0) + 14ec: c399 beqz a5,14f2 <_vfiprintf_r+0x70> + 14ee: 0d779e63 bne a5,s7,15ca <_vfiprintf_r+0x148> + 14f2: 41240cb3 sub s9,s0,s2 + 14f6: 000c8d63 beqz s9,1510 <_vfiprintf_r+0x8e> + 14fa: 86e6 mv a3,s9 + 14fc: 864a mv a2,s2 + 14fe: 85a6 mv a1,s1 + 1500: 854e mv a0,s3 + 1502: 3781 jal 1442 <__sfputs_r> + 1504: 57fd li a5,-1 + 1506: 1cf50f63 beq a0,a5,16e4 <_vfiprintf_r+0x262> + 150a: 5692 lw a3,36(sp) + 150c: 96e6 add a3,a3,s9 + 150e: d236 sw a3,36(sp) + 1510: 201c lbu a5,0(s0) + 1512: 1c078963 beqz a5,16e4 <_vfiprintf_r+0x262> + 1516: 57fd li a5,-1 + 1518: 00140913 addi s2,s0,1 + 151c: c802 sw zero,16(sp) + 151e: ce02 sw zero,28(sp) + 1520: ca3e sw a5,20(sp) + 1522: cc02 sw zero,24(sp) + 1524: 040109a3 sb zero,83(sp) + 1528: d482 sw zero,104(sp) + 152a: 00094583 lbu a1,0(s2) + 152e: 4615 li a2,5 + 1530: 8556 mv a0,s5 + 1532: 2725 jal 1c5a + 1534: 00190413 addi s0,s2,1 + 1538: 47c2 lw a5,16(sp) + 153a: e951 bnez a0,15ce <_vfiprintf_r+0x14c> + 153c: 0107f713 andi a4,a5,16 + 1540: c709 beqz a4,154a <_vfiprintf_r+0xc8> + 1542: 02000713 li a4,32 + 1546: 04e109a3 sb a4,83(sp) + 154a: 0087f713 andi a4,a5,8 + 154e: c709 beqz a4,1558 <_vfiprintf_r+0xd6> + 1550: 02b00713 li a4,43 + 1554: 04e109a3 sb a4,83(sp) + 1558: 00094683 lbu a3,0(s2) + 155c: 02a00713 li a4,42 + 1560: 06e68f63 beq a3,a4,15de <_vfiprintf_r+0x15c> + 1564: 47f2 lw a5,28(sp) + 1566: 844a mv s0,s2 + 1568: 4681 li a3,0 + 156a: 4625 li a2,9 + 156c: 2018 lbu a4,0(s0) + 156e: 00140593 addi a1,s0,1 + 1572: fd070713 addi a4,a4,-48 # ffffdfd0 <_eusrstack+0xdfff8fd0> + 1576: 0ae67763 bgeu a2,a4,1624 <_vfiprintf_r+0x1a2> + 157a: cab5 beqz a3,15ee <_vfiprintf_r+0x16c> + 157c: ce3e sw a5,28(sp) + 157e: a885 j 15ee <_vfiprintf_r+0x16c> + 1580: 00000797 auipc a5,0x0 + 1584: 7dc78793 addi a5,a5,2012 # 1d5c <__sf_fake_stdout> + 1588: 00f49563 bne s1,a5,1592 <_vfiprintf_r+0x110> + 158c: 0089a483 lw s1,8(s3) + 1590: b72d j 14ba <_vfiprintf_r+0x38> + 1592: 00000797 auipc a5,0x0 + 1596: 78a78793 addi a5,a5,1930 # 1d1c <__sf_fake_stderr> + 159a: f2f490e3 bne s1,a5,14ba <_vfiprintf_r+0x38> + 159e: 00c9a483 lw s1,12(s3) + 15a2: bf21 j 14ba <_vfiprintf_r+0x38> + 15a4: 85a6 mv a1,s1 + 15a6: 854e mv a0,s3 + 15a8: f5cff0ef jal ra,d04 <__swsetup_r> + 15ac: dd01 beqz a0,14c4 <_vfiprintf_r+0x42> + 15ae: 557d li a0,-1 + 15b0: 40fa lw ra,156(sp) + 15b2: 446a lw s0,152(sp) + 15b4: 44da lw s1,148(sp) + 15b6: 494a lw s2,144(sp) + 15b8: 49ba lw s3,140(sp) + 15ba: 4a2a lw s4,136(sp) + 15bc: 4a9a lw s5,132(sp) + 15be: 4b0a lw s6,128(sp) + 15c0: 5bf6 lw s7,124(sp) + 15c2: 5c66 lw s8,120(sp) + 15c4: 5cd6 lw s9,116(sp) + 15c6: 610d addi sp,sp,160 + 15c8: 8082 ret + 15ca: 0405 addi s0,s0,1 + 15cc: bf39 j 14ea <_vfiprintf_r+0x68> + 15ce: 41550533 sub a0,a0,s5 + 15d2: 00ac1533 sll a0,s8,a0 + 15d6: 8fc9 or a5,a5,a0 + 15d8: c83e sw a5,16(sp) + 15da: 8922 mv s2,s0 + 15dc: b7b9 j 152a <_vfiprintf_r+0xa8> + 15de: 4732 lw a4,12(sp) + 15e0: 00470693 addi a3,a4,4 + 15e4: 4318 lw a4,0(a4) + 15e6: c636 sw a3,12(sp) + 15e8: 02074763 bltz a4,1616 <_vfiprintf_r+0x194> + 15ec: ce3a sw a4,28(sp) + 15ee: 2018 lbu a4,0(s0) + 15f0: 02e00793 li a5,46 + 15f4: 04f71d63 bne a4,a5,164e <_vfiprintf_r+0x1cc> + 15f8: 3018 lbu a4,1(s0) + 15fa: 02a00793 li a5,42 + 15fe: 02f71b63 bne a4,a5,1634 <_vfiprintf_r+0x1b2> + 1602: 47b2 lw a5,12(sp) + 1604: 0409 addi s0,s0,2 + 1606: 00478713 addi a4,a5,4 + 160a: 439c lw a5,0(a5) + 160c: c63a sw a4,12(sp) + 160e: 0207c163 bltz a5,1630 <_vfiprintf_r+0x1ae> + 1612: ca3e sw a5,20(sp) + 1614: a82d j 164e <_vfiprintf_r+0x1cc> + 1616: 40e00733 neg a4,a4 + 161a: 0027e793 ori a5,a5,2 + 161e: ce3a sw a4,28(sp) + 1620: c83e sw a5,16(sp) + 1622: b7f1 j 15ee <_vfiprintf_r+0x16c> + 1624: 036787b3 mul a5,a5,s6 + 1628: 4685 li a3,1 + 162a: 842e mv s0,a1 + 162c: 97ba add a5,a5,a4 + 162e: bf3d j 156c <_vfiprintf_r+0xea> + 1630: 57fd li a5,-1 + 1632: b7c5 j 1612 <_vfiprintf_r+0x190> + 1634: 0405 addi s0,s0,1 + 1636: ca02 sw zero,20(sp) + 1638: 4681 li a3,0 + 163a: 4781 li a5,0 + 163c: 4625 li a2,9 + 163e: 2018 lbu a4,0(s0) + 1640: 00140593 addi a1,s0,1 + 1644: fd070713 addi a4,a4,-48 + 1648: 06e67463 bgeu a2,a4,16b0 <_vfiprintf_r+0x22e> + 164c: f2f9 bnez a3,1612 <_vfiprintf_r+0x190> + 164e: 200c lbu a1,0(s0) + 1650: 460d li a2,3 + 1652: 00000517 auipc a0,0x0 + 1656: 73250513 addi a0,a0,1842 # 1d84 <__sf_fake_stdout+0x28> + 165a: 2501 jal 1c5a + 165c: cd11 beqz a0,1678 <_vfiprintf_r+0x1f6> + 165e: 00000797 auipc a5,0x0 + 1662: 72678793 addi a5,a5,1830 # 1d84 <__sf_fake_stdout+0x28> + 1666: 8d1d sub a0,a0,a5 + 1668: 04000793 li a5,64 + 166c: 00a797b3 sll a5,a5,a0 + 1670: 4542 lw a0,16(sp) + 1672: 0405 addi s0,s0,1 + 1674: 8d5d or a0,a0,a5 + 1676: c82a sw a0,16(sp) + 1678: 200c lbu a1,0(s0) + 167a: 4619 li a2,6 + 167c: 00000517 auipc a0,0x0 + 1680: 70c50513 addi a0,a0,1804 # 1d88 <__sf_fake_stdout+0x2c> + 1684: 00140913 addi s2,s0,1 + 1688: 02b10423 sb a1,40(sp) + 168c: 23f9 jal 1c5a + 168e: c135 beqz a0,16f2 <_vfiprintf_r+0x270> + 1690: fffff797 auipc a5,0xfffff + 1694: 97078793 addi a5,a5,-1680 # 0 <_sinit> + 1698: e795 bnez a5,16c4 <_vfiprintf_r+0x242> + 169a: 4742 lw a4,16(sp) + 169c: 47b2 lw a5,12(sp) + 169e: 10077713 andi a4,a4,256 + 16a2: cf09 beqz a4,16bc <_vfiprintf_r+0x23a> + 16a4: 0791 addi a5,a5,4 + 16a6: c63e sw a5,12(sp) + 16a8: 5792 lw a5,36(sp) + 16aa: 97d2 add a5,a5,s4 + 16ac: d23e sw a5,36(sp) + 16ae: bd2d j 14e8 <_vfiprintf_r+0x66> + 16b0: 036787b3 mul a5,a5,s6 + 16b4: 4685 li a3,1 + 16b6: 842e mv s0,a1 + 16b8: 97ba add a5,a5,a4 + 16ba: b751 j 163e <_vfiprintf_r+0x1bc> + 16bc: 079d addi a5,a5,7 + 16be: 9be1 andi a5,a5,-8 + 16c0: 07a1 addi a5,a5,8 + 16c2: b7d5 j 16a6 <_vfiprintf_r+0x224> + 16c4: 0078 addi a4,sp,12 + 16c6: 00000697 auipc a3,0x0 + 16ca: d7c68693 addi a3,a3,-644 # 1442 <__sfputs_r> + 16ce: 8626 mv a2,s1 + 16d0: 080c addi a1,sp,16 + 16d2: 854e mv a0,s3 + 16d4: 00000097 auipc ra,0x0 + 16d8: 000000e7 jalr zero # 0 <_sinit> + 16dc: 57fd li a5,-1 + 16de: 8a2a mv s4,a0 + 16e0: fcf514e3 bne a0,a5,16a8 <_vfiprintf_r+0x226> + 16e4: 24de lhu a5,12(s1) + 16e6: 0407f793 andi a5,a5,64 + 16ea: ec0792e3 bnez a5,15ae <_vfiprintf_r+0x12c> + 16ee: 5512 lw a0,36(sp) + 16f0: b5c1 j 15b0 <_vfiprintf_r+0x12e> + 16f2: 0078 addi a4,sp,12 + 16f4: 00000697 auipc a3,0x0 + 16f8: d4e68693 addi a3,a3,-690 # 1442 <__sfputs_r> + 16fc: 8626 mv a2,s1 + 16fe: 080c addi a1,sp,16 + 1700: 854e mv a0,s3 + 1702: 2a01 jal 1812 <_printf_i> + 1704: bfe1 j 16dc <_vfiprintf_r+0x25a> + +00001706 <_printf_common>: + 1706: 7179 addi sp,sp,-48 + 1708: ca56 sw s5,20(sp) + 170a: 499c lw a5,16(a1) + 170c: 8aba mv s5,a4 + 170e: 4598 lw a4,8(a1) + 1710: d422 sw s0,40(sp) + 1712: d226 sw s1,36(sp) + 1714: ce4e sw s3,28(sp) + 1716: cc52 sw s4,24(sp) + 1718: d606 sw ra,44(sp) + 171a: d04a sw s2,32(sp) + 171c: c85a sw s6,16(sp) + 171e: c65e sw s7,12(sp) + 1720: 89aa mv s3,a0 + 1722: 842e mv s0,a1 + 1724: 84b2 mv s1,a2 + 1726: 8a36 mv s4,a3 + 1728: 00e7d363 bge a5,a4,172e <_printf_common+0x28> + 172c: 87ba mv a5,a4 + 172e: c09c sw a5,0(s1) + 1730: 04344703 lbu a4,67(s0) + 1734: c319 beqz a4,173a <_printf_common+0x34> + 1736: 0785 addi a5,a5,1 + 1738: c09c sw a5,0(s1) + 173a: 401c lw a5,0(s0) + 173c: 0207f793 andi a5,a5,32 + 1740: c781 beqz a5,1748 <_printf_common+0x42> + 1742: 409c lw a5,0(s1) + 1744: 0789 addi a5,a5,2 + 1746: c09c sw a5,0(s1) + 1748: 00042903 lw s2,0(s0) + 174c: 00697913 andi s2,s2,6 + 1750: 00091a63 bnez s2,1764 <_printf_common+0x5e> + 1754: 01940b13 addi s6,s0,25 + 1758: 5bfd li s7,-1 + 175a: 445c lw a5,12(s0) + 175c: 4098 lw a4,0(s1) + 175e: 8f99 sub a5,a5,a4 + 1760: 04f94c63 blt s2,a5,17b8 <_printf_common+0xb2> + 1764: 401c lw a5,0(s0) + 1766: 04344683 lbu a3,67(s0) + 176a: 0207f793 andi a5,a5,32 + 176e: 00d036b3 snez a3,a3 + 1772: eba5 bnez a5,17e2 <_printf_common+0xdc> + 1774: 04340613 addi a2,s0,67 + 1778: 85d2 mv a1,s4 + 177a: 854e mv a0,s3 + 177c: 9a82 jalr s5 + 177e: 57fd li a5,-1 + 1780: 04f50363 beq a0,a5,17c6 <_printf_common+0xc0> + 1784: 401c lw a5,0(s0) + 1786: 4611 li a2,4 + 1788: 4098 lw a4,0(s1) + 178a: 8b99 andi a5,a5,6 + 178c: 4454 lw a3,12(s0) + 178e: 4481 li s1,0 + 1790: 00c79763 bne a5,a2,179e <_printf_common+0x98> + 1794: 40e684b3 sub s1,a3,a4 + 1798: 0004d363 bgez s1,179e <_printf_common+0x98> + 179c: 4481 li s1,0 + 179e: 441c lw a5,8(s0) + 17a0: 4818 lw a4,16(s0) + 17a2: 00f75463 bge a4,a5,17aa <_printf_common+0xa4> + 17a6: 8f99 sub a5,a5,a4 + 17a8: 94be add s1,s1,a5 + 17aa: 4901 li s2,0 + 17ac: 0469 addi s0,s0,26 + 17ae: 5b7d li s6,-1 + 17b0: 05249863 bne s1,s2,1800 <_printf_common+0xfa> + 17b4: 4501 li a0,0 + 17b6: a809 j 17c8 <_printf_common+0xc2> + 17b8: 4685 li a3,1 + 17ba: 865a mv a2,s6 + 17bc: 85d2 mv a1,s4 + 17be: 854e mv a0,s3 + 17c0: 9a82 jalr s5 + 17c2: 01751e63 bne a0,s7,17de <_printf_common+0xd8> + 17c6: 557d li a0,-1 + 17c8: 50b2 lw ra,44(sp) + 17ca: 5422 lw s0,40(sp) + 17cc: 5492 lw s1,36(sp) + 17ce: 5902 lw s2,32(sp) + 17d0: 49f2 lw s3,28(sp) + 17d2: 4a62 lw s4,24(sp) + 17d4: 4ad2 lw s5,20(sp) + 17d6: 4b42 lw s6,16(sp) + 17d8: 4bb2 lw s7,12(sp) + 17da: 6145 addi sp,sp,48 + 17dc: 8082 ret + 17de: 0905 addi s2,s2,1 + 17e0: bfad j 175a <_printf_common+0x54> + 17e2: 00d40733 add a4,s0,a3 + 17e6: 03000613 li a2,48 + 17ea: 04c701a3 sb a2,67(a4) + 17ee: 04544703 lbu a4,69(s0) + 17f2: 00168793 addi a5,a3,1 + 17f6: 97a2 add a5,a5,s0 + 17f8: 0689 addi a3,a3,2 + 17fa: 04e781a3 sb a4,67(a5) + 17fe: bf9d j 1774 <_printf_common+0x6e> + 1800: 4685 li a3,1 + 1802: 8622 mv a2,s0 + 1804: 85d2 mv a1,s4 + 1806: 854e mv a0,s3 + 1808: 9a82 jalr s5 + 180a: fb650ee3 beq a0,s6,17c6 <_printf_common+0xc0> + 180e: 0905 addi s2,s2,1 + 1810: b745 j 17b0 <_printf_common+0xaa> + +00001812 <_printf_i>: + 1812: 7179 addi sp,sp,-48 + 1814: d422 sw s0,40(sp) + 1816: d226 sw s1,36(sp) + 1818: d04a sw s2,32(sp) + 181a: ce4e sw s3,28(sp) + 181c: d606 sw ra,44(sp) + 181e: cc52 sw s4,24(sp) + 1820: ca56 sw s5,20(sp) + 1822: c85a sw s6,16(sp) + 1824: 89b6 mv s3,a3 + 1826: 2d94 lbu a3,24(a1) + 1828: 06900793 li a5,105 + 182c: 8932 mv s2,a2 + 182e: 84aa mv s1,a0 + 1830: 842e mv s0,a1 + 1832: 04358613 addi a2,a1,67 + 1836: 02f68d63 beq a3,a5,1870 <_printf_i+0x5e> + 183a: 06d7e263 bltu a5,a3,189e <_printf_i+0x8c> + 183e: 05800793 li a5,88 + 1842: 18f68563 beq a3,a5,19cc <_printf_i+0x1ba> + 1846: 00d7ed63 bltu a5,a3,1860 <_printf_i+0x4e> + 184a: 20068d63 beqz a3,1a64 <_printf_i+0x252> + 184e: 04300793 li a5,67 + 1852: 0af68e63 beq a3,a5,190e <_printf_i+0xfc> + 1856: 04240a93 addi s5,s0,66 + 185a: 04d40123 sb a3,66(s0) + 185e: a0c9 j 1920 <_printf_i+0x10e> + 1860: 06300793 li a5,99 + 1864: 0af68563 beq a3,a5,190e <_printf_i+0xfc> + 1868: 06400793 li a5,100 + 186c: fef695e3 bne a3,a5,1856 <_printf_i+0x44> + 1870: 401c lw a5,0(s0) + 1872: 4308 lw a0,0(a4) + 1874: 0807f693 andi a3,a5,128 + 1878: 00450593 addi a1,a0,4 + 187c: c6c5 beqz a3,1924 <_printf_i+0x112> + 187e: 411c lw a5,0(a0) + 1880: c30c sw a1,0(a4) + 1882: 0007d863 bgez a5,1892 <_printf_i+0x80> + 1886: 02d00713 li a4,45 + 188a: 40f007b3 neg a5,a5 + 188e: 04e401a3 sb a4,67(s0) + 1892: 00000697 auipc a3,0x0 + 1896: 4fe68693 addi a3,a3,1278 # 1d90 <__sf_fake_stdout+0x34> + 189a: 4729 li a4,10 + 189c: a865 j 1954 <_printf_i+0x142> + 189e: 07000793 li a5,112 + 18a2: 16f68163 beq a3,a5,1a04 <_printf_i+0x1f2> + 18a6: 02d7e563 bltu a5,a3,18d0 <_printf_i+0xbe> + 18aa: 06e00793 li a5,110 + 18ae: 18f68863 beq a3,a5,1a3e <_printf_i+0x22c> + 18b2: 06f00793 li a5,111 + 18b6: faf690e3 bne a3,a5,1856 <_printf_i+0x44> + 18ba: 400c lw a1,0(s0) + 18bc: 431c lw a5,0(a4) + 18be: 0805f813 andi a6,a1,128 + 18c2: 00478513 addi a0,a5,4 + 18c6: 06080763 beqz a6,1934 <_printf_i+0x122> + 18ca: c308 sw a0,0(a4) + 18cc: 439c lw a5,0(a5) + 18ce: a885 j 193e <_printf_i+0x12c> + 18d0: 07500793 li a5,117 + 18d4: fef683e3 beq a3,a5,18ba <_printf_i+0xa8> + 18d8: 07800793 li a5,120 + 18dc: 12f68863 beq a3,a5,1a0c <_printf_i+0x1fa> + 18e0: 07300793 li a5,115 + 18e4: f6f699e3 bne a3,a5,1856 <_printf_i+0x44> + 18e8: 431c lw a5,0(a4) + 18ea: 41d0 lw a2,4(a1) + 18ec: 4581 li a1,0 + 18ee: 00478693 addi a3,a5,4 + 18f2: c314 sw a3,0(a4) + 18f4: 0007aa83 lw s5,0(a5) + 18f8: 8556 mv a0,s5 + 18fa: 2685 jal 1c5a + 18fc: c501 beqz a0,1904 <_printf_i+0xf2> + 18fe: 41550533 sub a0,a0,s5 + 1902: c048 sw a0,4(s0) + 1904: 405c lw a5,4(s0) + 1906: c81c sw a5,16(s0) + 1908: 040401a3 sb zero,67(s0) + 190c: a861 j 19a4 <_printf_i+0x192> + 190e: 431c lw a5,0(a4) + 1910: 04240a93 addi s5,s0,66 + 1914: 00478693 addi a3,a5,4 + 1918: 439c lw a5,0(a5) + 191a: c314 sw a3,0(a4) + 191c: 04f40123 sb a5,66(s0) + 1920: 4785 li a5,1 + 1922: b7d5 j 1906 <_printf_i+0xf4> + 1924: 0407f693 andi a3,a5,64 + 1928: 411c lw a5,0(a0) + 192a: c30c sw a1,0(a4) + 192c: dab9 beqz a3,1882 <_printf_i+0x70> + 192e: 07c2 slli a5,a5,0x10 + 1930: 87c1 srai a5,a5,0x10 + 1932: bf81 j 1882 <_printf_i+0x70> + 1934: 0405f593 andi a1,a1,64 + 1938: c308 sw a0,0(a4) + 193a: d9c9 beqz a1,18cc <_printf_i+0xba> + 193c: 239e lhu a5,0(a5) + 193e: 06f00713 li a4,111 + 1942: 0ee68663 beq a3,a4,1a2e <_printf_i+0x21c> + 1946: 00000697 auipc a3,0x0 + 194a: 44a68693 addi a3,a3,1098 # 1d90 <__sf_fake_stdout+0x34> + 194e: 4729 li a4,10 + 1950: 040401a3 sb zero,67(s0) + 1954: 404c lw a1,4(s0) + 1956: c40c sw a1,8(s0) + 1958: 0005c563 bltz a1,1962 <_printf_i+0x150> + 195c: 4008 lw a0,0(s0) + 195e: 996d andi a0,a0,-5 + 1960: c008 sw a0,0(s0) + 1962: e399 bnez a5,1968 <_printf_i+0x156> + 1964: 8ab2 mv s5,a2 + 1966: cd89 beqz a1,1980 <_printf_i+0x16e> + 1968: 8ab2 mv s5,a2 + 196a: 02e7f5b3 remu a1,a5,a4 + 196e: 1afd addi s5,s5,-1 + 1970: 95b6 add a1,a1,a3 + 1972: 218c lbu a1,0(a1) + 1974: 00ba8023 sb a1,0(s5) + 1978: 02e7d5b3 divu a1,a5,a4 + 197c: 0ae7ff63 bgeu a5,a4,1a3a <_printf_i+0x228> + 1980: 47a1 li a5,8 + 1982: 00f71e63 bne a4,a5,199e <_printf_i+0x18c> + 1986: 401c lw a5,0(s0) + 1988: 8b85 andi a5,a5,1 + 198a: cb91 beqz a5,199e <_printf_i+0x18c> + 198c: 4058 lw a4,4(s0) + 198e: 481c lw a5,16(s0) + 1990: 00e7c763 blt a5,a4,199e <_printf_i+0x18c> + 1994: 03000793 li a5,48 + 1998: fefa8fa3 sb a5,-1(s5) + 199c: 1afd addi s5,s5,-1 + 199e: 41560633 sub a2,a2,s5 + 19a2: c810 sw a2,16(s0) + 19a4: 874e mv a4,s3 + 19a6: 86ca mv a3,s2 + 19a8: 0070 addi a2,sp,12 + 19aa: 85a2 mv a1,s0 + 19ac: 8526 mv a0,s1 + 19ae: 3ba1 jal 1706 <_printf_common> + 19b0: 5a7d li s4,-1 + 19b2: 0b451d63 bne a0,s4,1a6c <_printf_i+0x25a> + 19b6: 557d li a0,-1 + 19b8: 50b2 lw ra,44(sp) + 19ba: 5422 lw s0,40(sp) + 19bc: 5492 lw s1,36(sp) + 19be: 5902 lw s2,32(sp) + 19c0: 49f2 lw s3,28(sp) + 19c2: 4a62 lw s4,24(sp) + 19c4: 4ad2 lw s5,20(sp) + 19c6: 4b42 lw s6,16(sp) + 19c8: 6145 addi sp,sp,48 + 19ca: 8082 ret + 19cc: 04d582a3 sb a3,69(a1) + 19d0: 00000697 auipc a3,0x0 + 19d4: 3c068693 addi a3,a3,960 # 1d90 <__sf_fake_stdout+0x34> + 19d8: 400c lw a1,0(s0) + 19da: 4308 lw a0,0(a4) + 19dc: 0805f813 andi a6,a1,128 + 19e0: 411c lw a5,0(a0) + 19e2: 0511 addi a0,a0,4 + 19e4: 02080d63 beqz a6,1a1e <_printf_i+0x20c> + 19e8: c308 sw a0,0(a4) + 19ea: 0015f713 andi a4,a1,1 + 19ee: c701 beqz a4,19f6 <_printf_i+0x1e4> + 19f0: 0205e593 ori a1,a1,32 + 19f4: c00c sw a1,0(s0) + 19f6: 4741 li a4,16 + 19f8: ffa1 bnez a5,1950 <_printf_i+0x13e> + 19fa: 400c lw a1,0(s0) + 19fc: fdf5f593 andi a1,a1,-33 + 1a00: c00c sw a1,0(s0) + 1a02: b7b9 j 1950 <_printf_i+0x13e> + 1a04: 419c lw a5,0(a1) + 1a06: 0207e793 ori a5,a5,32 + 1a0a: c19c sw a5,0(a1) + 1a0c: 07800793 li a5,120 + 1a10: 04f402a3 sb a5,69(s0) + 1a14: 00000697 auipc a3,0x0 + 1a18: 39068693 addi a3,a3,912 # 1da4 <__sf_fake_stdout+0x48> + 1a1c: bf75 j 19d8 <_printf_i+0x1c6> + 1a1e: 0405f813 andi a6,a1,64 + 1a22: c308 sw a0,0(a4) + 1a24: fc0803e3 beqz a6,19ea <_printf_i+0x1d8> + 1a28: 07c2 slli a5,a5,0x10 + 1a2a: 83c1 srli a5,a5,0x10 + 1a2c: bf7d j 19ea <_printf_i+0x1d8> + 1a2e: 00000697 auipc a3,0x0 + 1a32: 36268693 addi a3,a3,866 # 1d90 <__sf_fake_stdout+0x34> + 1a36: 4721 li a4,8 + 1a38: bf21 j 1950 <_printf_i+0x13e> + 1a3a: 87ae mv a5,a1 + 1a3c: b73d j 196a <_printf_i+0x158> + 1a3e: 4194 lw a3,0(a1) + 1a40: 431c lw a5,0(a4) + 1a42: 49cc lw a1,20(a1) + 1a44: 0806f813 andi a6,a3,128 + 1a48: 00478513 addi a0,a5,4 + 1a4c: 00080663 beqz a6,1a58 <_printf_i+0x246> + 1a50: c308 sw a0,0(a4) + 1a52: 439c lw a5,0(a5) + 1a54: c38c sw a1,0(a5) + 1a56: a039 j 1a64 <_printf_i+0x252> + 1a58: c308 sw a0,0(a4) + 1a5a: 0406f693 andi a3,a3,64 + 1a5e: 439c lw a5,0(a5) + 1a60: daf5 beqz a3,1a54 <_printf_i+0x242> + 1a62: a38e sh a1,0(a5) + 1a64: 00042823 sw zero,16(s0) + 1a68: 8ab2 mv s5,a2 + 1a6a: bf2d j 19a4 <_printf_i+0x192> + 1a6c: 4814 lw a3,16(s0) + 1a6e: 8656 mv a2,s5 + 1a70: 85ca mv a1,s2 + 1a72: 8526 mv a0,s1 + 1a74: 9982 jalr s3 + 1a76: f54500e3 beq a0,s4,19b6 <_printf_i+0x1a4> + 1a7a: 401c lw a5,0(s0) + 1a7c: 8b89 andi a5,a5,2 + 1a7e: e78d bnez a5,1aa8 <_printf_i+0x296> + 1a80: 47b2 lw a5,12(sp) + 1a82: 4448 lw a0,12(s0) + 1a84: f2f55ae3 bge a0,a5,19b8 <_printf_i+0x1a6> + 1a88: 853e mv a0,a5 + 1a8a: b73d j 19b8 <_printf_i+0x1a6> + 1a8c: 4685 li a3,1 + 1a8e: 8656 mv a2,s5 + 1a90: 85ca mv a1,s2 + 1a92: 8526 mv a0,s1 + 1a94: 9982 jalr s3 + 1a96: f36500e3 beq a0,s6,19b6 <_printf_i+0x1a4> + 1a9a: 0a05 addi s4,s4,1 + 1a9c: 445c lw a5,12(s0) + 1a9e: 4732 lw a4,12(sp) + 1aa0: 8f99 sub a5,a5,a4 + 1aa2: fefa45e3 blt s4,a5,1a8c <_printf_i+0x27a> + 1aa6: bfe9 j 1a80 <_printf_i+0x26e> + 1aa8: 4a01 li s4,0 + 1aaa: 01940a93 addi s5,s0,25 + 1aae: 5b7d li s6,-1 + 1ab0: b7f5 j 1a9c <_printf_i+0x28a> + +00001ab2 <_sbrk_r>: + 1ab2: 1141 addi sp,sp,-16 + 1ab4: c422 sw s0,8(sp) + 1ab6: 842a mv s0,a0 + 1ab8: 852e mv a0,a1 + 1aba: 8201ae23 sw zero,-1988(gp) # 200000bc + 1abe: c606 sw ra,12(sp) + 1ac0: 844ff0ef jal ra,b04 <_sbrk> + 1ac4: 57fd li a5,-1 + 1ac6: 00f51763 bne a0,a5,1ad4 <_sbrk_r+0x22> + 1aca: 83c18793 addi a5,gp,-1988 # 200000bc + 1ace: 439c lw a5,0(a5) + 1ad0: c391 beqz a5,1ad4 <_sbrk_r+0x22> + 1ad2: c01c sw a5,0(s0) + 1ad4: 40b2 lw ra,12(sp) + 1ad6: 4422 lw s0,8(sp) + 1ad8: 0141 addi sp,sp,16 + 1ada: 8082 ret + +00001adc <__sread>: + 1adc: 1141 addi sp,sp,-16 + 1ade: c422 sw s0,8(sp) + 1ae0: 842e mv s0,a1 + 1ae2: 00e59583 lh a1,14(a1) + 1ae6: c606 sw ra,12(sp) + 1ae8: 2279 jal 1c76 <_read_r> + 1aea: 00054963 bltz a0,1afc <__sread+0x20> + 1aee: 487c lw a5,84(s0) + 1af0: 97aa add a5,a5,a0 + 1af2: c87c sw a5,84(s0) + 1af4: 40b2 lw ra,12(sp) + 1af6: 4422 lw s0,8(sp) + 1af8: 0141 addi sp,sp,16 + 1afa: 8082 ret + 1afc: 245e lhu a5,12(s0) + 1afe: 777d lui a4,0xfffff + 1b00: 177d addi a4,a4,-1 + 1b02: 8ff9 and a5,a5,a4 + 1b04: a45e sh a5,12(s0) + 1b06: b7fd j 1af4 <__sread+0x18> + +00001b08 <__swrite>: + 1b08: 25de lhu a5,12(a1) + 1b0a: 1101 addi sp,sp,-32 + 1b0c: cc22 sw s0,24(sp) + 1b0e: ca26 sw s1,20(sp) + 1b10: c84a sw s2,16(sp) + 1b12: c64e sw s3,12(sp) + 1b14: ce06 sw ra,28(sp) + 1b16: 1007f793 andi a5,a5,256 + 1b1a: 84aa mv s1,a0 + 1b1c: 842e mv s0,a1 + 1b1e: 8932 mv s2,a2 + 1b20: 89b6 mv s3,a3 + 1b22: c791 beqz a5,1b2e <__swrite+0x26> + 1b24: 00e59583 lh a1,14(a1) + 1b28: 4689 li a3,2 + 1b2a: 4601 li a2,0 + 1b2c: 2209 jal 1c2e <_lseek_r> + 1b2e: 245e lhu a5,12(s0) + 1b30: 777d lui a4,0xfffff + 1b32: 177d addi a4,a4,-1 + 1b34: 8ff9 and a5,a5,a4 + 1b36: a45e sh a5,12(s0) + 1b38: 00e41583 lh a1,14(s0) + 1b3c: 4462 lw s0,24(sp) + 1b3e: 40f2 lw ra,28(sp) + 1b40: 86ce mv a3,s3 + 1b42: 864a mv a2,s2 + 1b44: 49b2 lw s3,12(sp) + 1b46: 4942 lw s2,16(sp) + 1b48: 8526 mv a0,s1 + 1b4a: 44d2 lw s1,20(sp) + 1b4c: 6105 addi sp,sp,32 + 1b4e: a825 j 1b86 <_write_r> + +00001b50 <__sseek>: + 1b50: 1141 addi sp,sp,-16 + 1b52: c422 sw s0,8(sp) + 1b54: 842e mv s0,a1 + 1b56: 00e59583 lh a1,14(a1) + 1b5a: c606 sw ra,12(sp) + 1b5c: 28c9 jal 1c2e <_lseek_r> + 1b5e: 57fd li a5,-1 + 1b60: 245a lhu a4,12(s0) + 1b62: 00f51a63 bne a0,a5,1b76 <__sseek+0x26> + 1b66: 77fd lui a5,0xfffff + 1b68: 17fd addi a5,a5,-1 + 1b6a: 8ff9 and a5,a5,a4 + 1b6c: a45e sh a5,12(s0) + 1b6e: 40b2 lw ra,12(sp) + 1b70: 4422 lw s0,8(sp) + 1b72: 0141 addi sp,sp,16 + 1b74: 8082 ret + 1b76: 6785 lui a5,0x1 + 1b78: 8fd9 or a5,a5,a4 + 1b7a: a45e sh a5,12(s0) + 1b7c: c868 sw a0,84(s0) + 1b7e: bfc5 j 1b6e <__sseek+0x1e> + +00001b80 <__sclose>: + 1b80: 00e59583 lh a1,14(a1) + 1b84: a805 j 1bb4 <_close_r> + +00001b86 <_write_r>: + 1b86: 1141 addi sp,sp,-16 + 1b88: c422 sw s0,8(sp) + 1b8a: 842a mv s0,a0 + 1b8c: 852e mv a0,a1 + 1b8e: 85b2 mv a1,a2 + 1b90: 8636 mv a2,a3 + 1b92: 8201ae23 sw zero,-1988(gp) # 200000bc + 1b96: c606 sw ra,12(sp) + 1b98: f33fe0ef jal ra,aca <_write> + 1b9c: 57fd li a5,-1 + 1b9e: 00f51763 bne a0,a5,1bac <_write_r+0x26> + 1ba2: 83c18793 addi a5,gp,-1988 # 200000bc + 1ba6: 439c lw a5,0(a5) + 1ba8: c391 beqz a5,1bac <_write_r+0x26> + 1baa: c01c sw a5,0(s0) + 1bac: 40b2 lw ra,12(sp) + 1bae: 4422 lw s0,8(sp) + 1bb0: 0141 addi sp,sp,16 + 1bb2: 8082 ret + +00001bb4 <_close_r>: + 1bb4: 1141 addi sp,sp,-16 + 1bb6: c422 sw s0,8(sp) + 1bb8: 842a mv s0,a0 + 1bba: 852e mv a0,a1 + 1bbc: 8201ae23 sw zero,-1988(gp) # 200000bc + 1bc0: c606 sw ra,12(sp) + 1bc2: 20c5 jal 1ca2 <_close> + 1bc4: 57fd li a5,-1 + 1bc6: 00f51763 bne a0,a5,1bd4 <_close_r+0x20> + 1bca: 83c18793 addi a5,gp,-1988 # 200000bc + 1bce: 439c lw a5,0(a5) + 1bd0: c391 beqz a5,1bd4 <_close_r+0x20> + 1bd2: c01c sw a5,0(s0) + 1bd4: 40b2 lw ra,12(sp) + 1bd6: 4422 lw s0,8(sp) + 1bd8: 0141 addi sp,sp,16 + 1bda: 8082 ret + +00001bdc <_fstat_r>: + 1bdc: 1141 addi sp,sp,-16 + 1bde: c422 sw s0,8(sp) + 1be0: 842a mv s0,a0 + 1be2: 852e mv a0,a1 + 1be4: 85b2 mv a1,a2 + 1be6: 8201ae23 sw zero,-1988(gp) # 200000bc + 1bea: c606 sw ra,12(sp) + 1bec: 20c9 jal 1cae <_fstat> + 1bee: 57fd li a5,-1 + 1bf0: 00f51763 bne a0,a5,1bfe <_fstat_r+0x22> + 1bf4: 83c18793 addi a5,gp,-1988 # 200000bc + 1bf8: 439c lw a5,0(a5) + 1bfa: c391 beqz a5,1bfe <_fstat_r+0x22> + 1bfc: c01c sw a5,0(s0) + 1bfe: 40b2 lw ra,12(sp) + 1c00: 4422 lw s0,8(sp) + 1c02: 0141 addi sp,sp,16 + 1c04: 8082 ret + +00001c06 <_isatty_r>: + 1c06: 1141 addi sp,sp,-16 + 1c08: c422 sw s0,8(sp) + 1c0a: 842a mv s0,a0 + 1c0c: 852e mv a0,a1 + 1c0e: 8201ae23 sw zero,-1988(gp) # 200000bc + 1c12: c606 sw ra,12(sp) + 1c14: 205d jal 1cba <_isatty> + 1c16: 57fd li a5,-1 + 1c18: 00f51763 bne a0,a5,1c26 <_isatty_r+0x20> + 1c1c: 83c18793 addi a5,gp,-1988 # 200000bc + 1c20: 439c lw a5,0(a5) + 1c22: c391 beqz a5,1c26 <_isatty_r+0x20> + 1c24: c01c sw a5,0(s0) + 1c26: 40b2 lw ra,12(sp) + 1c28: 4422 lw s0,8(sp) + 1c2a: 0141 addi sp,sp,16 + 1c2c: 8082 ret + +00001c2e <_lseek_r>: + 1c2e: 1141 addi sp,sp,-16 + 1c30: c422 sw s0,8(sp) + 1c32: 842a mv s0,a0 + 1c34: 852e mv a0,a1 + 1c36: 85b2 mv a1,a2 + 1c38: 8636 mv a2,a3 + 1c3a: 8201ae23 sw zero,-1988(gp) # 200000bc + 1c3e: c606 sw ra,12(sp) + 1c40: 2059 jal 1cc6 <_lseek> + 1c42: 57fd li a5,-1 + 1c44: 00f51763 bne a0,a5,1c52 <_lseek_r+0x24> + 1c48: 83c18793 addi a5,gp,-1988 # 200000bc + 1c4c: 439c lw a5,0(a5) + 1c4e: c391 beqz a5,1c52 <_lseek_r+0x24> + 1c50: c01c sw a5,0(s0) + 1c52: 40b2 lw ra,12(sp) + 1c54: 4422 lw s0,8(sp) + 1c56: 0141 addi sp,sp,16 + 1c58: 8082 ret + +00001c5a : + 1c5a: 0ff5f593 andi a1,a1,255 + 1c5e: 962a add a2,a2,a0 + 1c60: 00c51463 bne a0,a2,1c68 + 1c64: 4501 li a0,0 + 1c66: 8082 ret + 1c68: 211c lbu a5,0(a0) + 1c6a: feb78ee3 beq a5,a1,1c66 + 1c6e: 0505 addi a0,a0,1 + 1c70: bfc5 j 1c60 + +00001c72 <__malloc_lock>: + 1c72: 8082 ret + +00001c74 <__malloc_unlock>: + 1c74: 8082 ret + +00001c76 <_read_r>: + 1c76: 1141 addi sp,sp,-16 + 1c78: c422 sw s0,8(sp) + 1c7a: 842a mv s0,a0 + 1c7c: 852e mv a0,a1 + 1c7e: 85b2 mv a1,a2 + 1c80: 8636 mv a2,a3 + 1c82: 8201ae23 sw zero,-1988(gp) # 200000bc + 1c86: c606 sw ra,12(sp) + 1c88: 20a9 jal 1cd2 <_read> + 1c8a: 57fd li a5,-1 + 1c8c: 00f51763 bne a0,a5,1c9a <_read_r+0x24> + 1c90: 83c18793 addi a5,gp,-1988 # 200000bc + 1c94: 439c lw a5,0(a5) + 1c96: c391 beqz a5,1c9a <_read_r+0x24> + 1c98: c01c sw a5,0(s0) + 1c9a: 40b2 lw ra,12(sp) + 1c9c: 4422 lw s0,8(sp) + 1c9e: 0141 addi sp,sp,16 + 1ca0: 8082 ret + +00001ca2 <_close>: + 1ca2: 05800793 li a5,88 + 1ca6: 82f1ae23 sw a5,-1988(gp) # 200000bc + 1caa: 557d li a0,-1 + 1cac: 8082 ret + +00001cae <_fstat>: + 1cae: 05800793 li a5,88 + 1cb2: 82f1ae23 sw a5,-1988(gp) # 200000bc + 1cb6: 557d li a0,-1 + 1cb8: 8082 ret + +00001cba <_isatty>: + 1cba: 05800793 li a5,88 + 1cbe: 82f1ae23 sw a5,-1988(gp) # 200000bc + 1cc2: 4501 li a0,0 + 1cc4: 8082 ret + +00001cc6 <_lseek>: + 1cc6: 05800793 li a5,88 + 1cca: 82f1ae23 sw a5,-1988(gp) # 200000bc + 1cce: 557d li a0,-1 + 1cd0: 8082 ret + +00001cd2 <_read>: + 1cd2: 05800793 li a5,88 + 1cd6: 82f1ae23 sw a5,-1988(gp) # 200000bc + 1cda: 557d li a0,-1 + 1cdc: 8082 ret + 1cde: 0000 unimp + 1ce0: 74737953 0x74737953 + 1ce4: 6d65 lui s10,0x19 + 1ce6: 3a6b6c43 fmadd.d fs8,fs6,ft6,ft7,unknown + 1cea: 6425 lui s0,0x9 + 1cec: 0a0d addi s4,s4,3 + 1cee: 0000 unimp + 1cf0: 70696843 fmadd.s fa6,fs2,ft6,fa4,unknown + 1cf4: 4449 li s0,18 + 1cf6: 253a lhu a4,10(a0) + 1cf8: 3830 lbu a2,19(s0) + 1cfa: 0d78 addi a4,sp,668 + 1cfc: 000a c.slli zero,0x2 + 1cfe: 0000 unimp + 1d00: 6854 flw fa3,20(s0) + 1d02: 7369 lui t1,0xffffa + 1d04: 6920 flw fs0,80(a0) + 1d06: 72702073 csrr zero,0x727 + 1d0a: 6e69 lui t3,0x1a + 1d0c: 6674 flw fa3,76(a2) + 1d0e: 6520 flw fs0,72(a0) + 1d10: 6178 flw fa4,68(a0) + 1d12: 706d c.lui zero,0xffffb + 1d14: 656c flw fa1,76(a0) + 1d16: 6320 flw fs0,64(a4) + 1d18: 00000d63 beqz zero,1d32 <__sf_fake_stderr+0x16> + +00001d1c <__sf_fake_stderr>: + ... + +00001d3c <__sf_fake_stdin>: + ... + +00001d5c <__sf_fake_stdout>: + ... + 1d7c: 2b302d23 00000020 004c6c68 45676665 #-0+ ...hlL.efgE + 1d8c: 00004746 33323130 37363534 42413938 FG..0123456789AB + 1d9c: 46454443 00000000 33323130 37363534 CDEF....01234567 + 1dac: 62613938 66656463 00000000 89abcdef.... diff --git a/ZDBMS/BMS_CC/obj/BMS_CC.map b/ZDBMS/BMS_CC/obj/BMS_CC.map new file mode 100644 index 0000000..5e080a7 --- /dev/null +++ b/ZDBMS/BMS_CC/obj/BMS_CC.map @@ -0,0 +1,2101 @@ +Archive member included to satisfy reference by file (symbol) + +d:/tool/code/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/rv32imacxw/ilp32\libgcc.a(save-restore.o) + ./Peripheral/src/ch32l103_flash.o (__riscv_save_7) +d:/tool/code/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib/rv32imacxw/ilp32\libg_nano.a(lib_a-printf.o) + ./User/main.o (printf) +d:/tool/code/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib/rv32imacxw/ilp32\libg_nano.a(lib_a-puts.o) + ./User/main.o (puts) +d:/tool/code/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib/rv32imacxw/ilp32\libg_nano.a(lib_a-wbuf.o) + d:/tool/code/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib/rv32imacxw/ilp32\libg_nano.a(lib_a-puts.o) (__swbuf_r) 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embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib/rv32imacxw/ilp32\libnosys.a(fstat.o) + .bss 0x0000000000000000 0x0 d:/tool/code/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib/rv32imacxw/ilp32\libnosys.a(fstat.o) + .text 0x0000000000000000 0x0 d:/tool/code/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib/rv32imacxw/ilp32\libnosys.a(isatty.o) + .data 0x0000000000000000 0x0 d:/tool/code/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib/rv32imacxw/ilp32\libnosys.a(isatty.o) + .bss 0x0000000000000000 0x0 d:/tool/code/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib/rv32imacxw/ilp32\libnosys.a(isatty.o) + .text 0x0000000000000000 0x0 d:/tool/code/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib/rv32imacxw/ilp32\libnosys.a(lseek.o) + .data 0x0000000000000000 0x0 d:/tool/code/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib/rv32imacxw/ilp32\libnosys.a(lseek.o) + .bss 0x0000000000000000 0x0 d:/tool/code/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib/rv32imacxw/ilp32\libnosys.a(lseek.o) + .text 0x0000000000000000 0x0 d:/tool/code/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib/rv32imacxw/ilp32\libnosys.a(read.o) + .data 0x0000000000000000 0x0 d:/tool/code/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib/rv32imacxw/ilp32\libnosys.a(read.o) + .bss 0x0000000000000000 0x0 d:/tool/code/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib/rv32imacxw/ilp32\libnosys.a(read.o) + +Memory Configuration + +Name Origin Length Attributes +FLASH 0x0000000000000000 0x0000000000010000 xr +RAM 0x0000000020000000 0x0000000000005000 xrw +*default* 0x0000000000000000 0xffffffffffffffff + +Linker script and memory map + +LOAD ./User/ch32l103_it.o +LOAD ./User/main.o +LOAD ./User/system_ch32l103.o +LOAD ./Startup/startup_ch32l103.o +LOAD ./Peripheral/src/ch32l103_adc.o +LOAD ./Peripheral/src/ch32l103_bkp.o +LOAD ./Peripheral/src/ch32l103_can.o +LOAD ./Peripheral/src/ch32l103_crc.o +LOAD ./Peripheral/src/ch32l103_dbgmcu.o +LOAD ./Peripheral/src/ch32l103_dma.o +LOAD ./Peripheral/src/ch32l103_exti.o +LOAD ./Peripheral/src/ch32l103_flash.o +LOAD ./Peripheral/src/ch32l103_gpio.o +LOAD ./Peripheral/src/ch32l103_i2c.o +LOAD ./Peripheral/src/ch32l103_iwdg.o +LOAD ./Peripheral/src/ch32l103_lptim.o +LOAD ./Peripheral/src/ch32l103_misc.o +LOAD ./Peripheral/src/ch32l103_opa.o +LOAD ./Peripheral/src/ch32l103_pwr.o +LOAD ./Peripheral/src/ch32l103_rcc.o +LOAD ./Peripheral/src/ch32l103_rtc.o +LOAD ./Peripheral/src/ch32l103_spi.o +LOAD ./Peripheral/src/ch32l103_tim.o +LOAD ./Peripheral/src/ch32l103_usart.o +LOAD ./Peripheral/src/ch32l103_wwdg.o +LOAD ./Debug/debug.o +LOAD ./Core/core_riscv.o +LOAD d:/tool/code/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/rv32imacxw/ilp32\libgcc.a +LOAD d:/tool/code/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib/rv32imacxw/ilp32\libg_nano.a +LOAD d:/tool/code/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib/rv32imacxw/ilp32\libc_nano.a +LOAD d:/tool/code/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/rv32imacxw/ilp32\libgcc.a +START GROUP +LOAD d:/tool/code/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/rv32imacxw/ilp32\libgcc.a +LOAD d:/tool/code/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib/rv32imacxw/ilp32\libc_nano.a +LOAD d:/tool/code/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib/rv32imacxw/ilp32\libnosys.a +END GROUP +START GROUP +LOAD d:/tool/code/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/rv32imacxw/ilp32\libgcc.a +LOAD d:/tool/code/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib/rv32imacxw/ilp32\libc_nano.a +LOAD d:/tool/code/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib/rv32imacxw/ilp32\libnosys.a +END GROUP + 0x0000000000000800 __stack_size = 0x800 + [!provide] PROVIDE (_stack_size = __stack_size) + +.init 0x0000000000000000 0x4 + 0x0000000000000000 _sinit = . + 0x0000000000000000 . = ALIGN (0x4) + *(SORT_NONE(.init)) + .init 0x0000000000000000 0x4 ./Startup/startup_ch32l103.o + 0x0000000000000000 _start + 0x0000000000000004 . = ALIGN (0x4) + 0x0000000000000004 _einit = . + +.vector 0x0000000000000004 0x13c + *(.vector) + .vector 0x0000000000000004 0x114 ./Startup/startup_ch32l103.o + 0x0000000000000140 . = ALIGN (0x40) + *fill* 0x0000000000000118 0x28 + +.text 0x0000000000000140 0x1c78 + 0x0000000000000140 . = ALIGN (0x4) + *(.text) + .text 0x0000000000000140 0x60 d:/tool/code/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/rv32imacxw/ilp32\libgcc.a(save-restore.o) + 0x0000000000000140 __riscv_save_12 + 0x0000000000000148 __riscv_save_9 + 0x0000000000000148 __riscv_save_11 + 0x0000000000000148 __riscv_save_10 + 0x0000000000000148 __riscv_save_8 + 0x0000000000000156 __riscv_save_4 + 0x0000000000000156 __riscv_save_6 + 0x0000000000000156 __riscv_save_5 + 0x0000000000000156 __riscv_save_7 + 0x0000000000000170 __riscv_save_3 + 0x0000000000000170 __riscv_save_2 + 0x0000000000000170 __riscv_save_1 + 0x0000000000000170 __riscv_save_0 + 0x000000000000017c __riscv_restore_12 + 0x0000000000000180 __riscv_restore_11 + 0x0000000000000180 __riscv_restore_9 + 0x0000000000000180 __riscv_restore_10 + 0x0000000000000180 __riscv_restore_8 + 0x000000000000018a __riscv_restore_5 + 0x000000000000018a __riscv_restore_7 + 0x000000000000018a __riscv_restore_6 + 0x000000000000018a __riscv_restore_4 + 0x0000000000000194 __riscv_restore_3 + 0x0000000000000194 __riscv_restore_0 + 0x0000000000000194 __riscv_restore_2 + 0x0000000000000194 __riscv_restore_1 + .text 0x00000000000001a0 0xa8 d:/tool/code/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib/rv32imacxw/ilp32\libg_nano.a(lib_a-memset.o) + 0x00000000000001a0 memset + *(.text.*) + .text.NMI_Handler + 0x0000000000000248 0x2 ./User/ch32l103_it.o + 0x0000000000000248 NMI_Handler + .text.HardFault_Handler + 0x000000000000024a 0x10 ./User/ch32l103_it.o + 0x000000000000024a HardFault_Handler + .text.startup.main + 0x000000000000025a 0x52 ./User/main.o + 0x000000000000025a main + .text.SystemInit + 0x00000000000002ac 0xba ./User/system_ch32l103.o + 0x00000000000002ac SystemInit + .text.SystemCoreClockUpdate + 0x0000000000000366 0xa4 ./User/system_ch32l103.o + 0x0000000000000366 SystemCoreClockUpdate + .text.vector_handler + 0x000000000000040a 0x2 ./Startup/startup_ch32l103.o + 0x000000000000040a EXTI2_IRQHandler + 0x000000000000040a TIM1_CC_IRQHandler + 0x000000000000040a USBPD_IRQHandler + 0x000000000000040a SysTick_Handler + 0x000000000000040a PVD_IRQHandler + 0x000000000000040a EXTI3_IRQHandler + 0x000000000000040a USBFS_IRQHandler + 0x000000000000040a EXTI0_IRQHandler + 0x000000000000040a I2C2_EV_IRQHandler + 0x000000000000040a LPTIM_IRQHandler + 0x000000000000040a Break_Point_Handler + 0x000000000000040a SPI1_IRQHandler + 0x000000000000040a TAMPER_IRQHandler + 0x000000000000040a Ecall_M_Mode_Handler + 0x000000000000040a DMA1_Channel4_IRQHandler + 0x000000000000040a USART3_IRQHandler + 0x000000000000040a RTC_IRQHandler + 0x000000000000040a DMA1_Channel7_IRQHandler + 0x000000000000040a CAN1_RX1_IRQHandler + 0x000000000000040a USBPDWakeUp_IRQHandler + 0x000000000000040a TIM4_IRQHandler + 0x000000000000040a I2C1_EV_IRQHandler + 0x000000000000040a USART4_IRQHandler + 0x000000000000040a DMA1_Channel6_IRQHandler + 0x000000000000040a TIM3_IRQHandler + 0x000000000000040a RCC_IRQHandler + 0x000000000000040a TIM1_TRG_COM_IRQHandler + 0x000000000000040a DMA1_Channel1_IRQHandler + 0x000000000000040a EXTI15_10_IRQHandler + 0x000000000000040a ADC_IRQHandler + 0x000000000000040a DMA1_Channel8_IRQHandler + 0x000000000000040a EXTI9_5_IRQHandler + 0x000000000000040a SPI2_IRQHandler + 0x000000000000040a DMA1_Channel5_IRQHandler + 0x000000000000040a EXTI4_IRQHandler + 0x000000000000040a USB_LP_CAN1_RX0_IRQHandler + 0x000000000000040a USB_HP_CAN1_TX_IRQHandler + 0x000000000000040a CMPWakeUp_IRQHandler + 0x000000000000040a DMA1_Channel3_IRQHandler + 0x000000000000040a TIM1_UP_IRQHandler + 0x000000000000040a LPTIMWakeUp_IRQHandler + 0x000000000000040a WWDG_IRQHandler + 0x000000000000040a Ecall_U_Mode_Handler + 0x000000000000040a TIM2_IRQHandler + 0x000000000000040a SW_Handler + 0x000000000000040a TIM1_BRK_IRQHandler + 0x000000000000040a OPA_IRQHandler + 0x000000000000040a EXTI1_IRQHandler + 0x000000000000040a RTCAlarm_IRQHandler + 0x000000000000040a USART2_IRQHandler + 0x000000000000040a I2C2_ER_IRQHandler + 0x000000000000040a DMA1_Channel2_IRQHandler + 0x000000000000040a CAN1_SCE_IRQHandler + 0x000000000000040a FLASH_IRQHandler + 0x000000000000040a USBFSWakeUp_IRQHandler + 0x000000000000040a USART1_IRQHandler + 0x000000000000040a I2C1_ER_IRQHandler + .text.handle_reset + 0x000000000000040c 0x86 ./Startup/startup_ch32l103.o + 0x000000000000040c handle_reset + .text.DBGMCU_GetCHIPID + 0x0000000000000492 0x6 ./Peripheral/src/ch32l103_dbgmcu.o + 0x0000000000000492 DBGMCU_GetCHIPID + .text.GPIO_Init + 0x0000000000000498 0xc0 ./Peripheral/src/ch32l103_gpio.o + 0x0000000000000498 GPIO_Init + .text.GPIO_PinRemapConfig + 0x0000000000000558 0x12c ./Peripheral/src/ch32l103_gpio.o + 0x0000000000000558 GPIO_PinRemapConfig + .text.GPIO_IPD_Unused + 0x0000000000000684 0x1c2 ./Peripheral/src/ch32l103_gpio.o + 0x0000000000000684 GPIO_IPD_Unused + .text.NVIC_PriorityGroupConfig + 0x0000000000000846 0x6 ./Peripheral/src/ch32l103_misc.o + 0x0000000000000846 NVIC_PriorityGroupConfig + .text.RCC_GetClocksFreq + 0x000000000000084c 0xd6 ./Peripheral/src/ch32l103_rcc.o + 0x000000000000084c RCC_GetClocksFreq + .text.RCC_PB2PeriphClockCmd + 0x0000000000000922 0x1e ./Peripheral/src/ch32l103_rcc.o + 0x0000000000000922 RCC_PB2PeriphClockCmd + .text.USART_Init + 0x0000000000000940 0xba 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0x00000000200000a4 0x4 ./Peripheral/src/ch32l103_gpio.o + 0x00000000200000a4 TS_Val + .sbss.USBPD_CFG + 0x00000000200000a8 0x2 ./Peripheral/src/ch32l103_gpio.o + 0x00000000200000a8 USBPD_CFG + *fill* 0x00000000200000aa 0x2 + .sbss.NVIC_Priority_Group + 0x00000000200000ac 0x4 ./Peripheral/src/ch32l103_misc.o + 0x00000000200000ac NVIC_Priority_Group + .sbss.p_ms 0x00000000200000b0 0x2 ./Debug/debug.o + .sbss.p_us 0x00000000200000b2 0x2 ./Debug/debug.o + .sbss.__malloc_free_list + 0x00000000200000b4 0x4 d:/tool/code/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib/rv32imacxw/ilp32\libg_nano.a(lib_a-nano-mallocr.o) + 0x00000000200000b4 __malloc_free_list + .sbss.__malloc_sbrk_start + 0x00000000200000b8 0x4 d:/tool/code/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib/rv32imacxw/ilp32\libg_nano.a(lib_a-nano-mallocr.o) + 0x00000000200000b8 __malloc_sbrk_start + *(.gnu.linkonce.sb.*) + *(.bss*) + *(.gnu.linkonce.b.*) + *(COMMON*) + COMMON 0x00000000200000bc 0x4 d:/tool/code/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib/rv32imacxw/ilp32\libg_nano.a(lib_a-reent.o) + 0x00000000200000bc errno + 0x00000000200000c0 . = ALIGN (0x4) + 0x00000000200000c0 PROVIDE (_ebss = .) + 0x00000000200000c0 PROVIDE (_end = _ebss) + [!provide] PROVIDE (end = .) + +.stack 0x0000000020004800 0x800 + 0x0000000020004800 PROVIDE (_heap_end = .) + 0x0000000020004800 . = ALIGN (0x4) + [!provide] PROVIDE (_susrstack = .) + 0x0000000020005000 . = (. + __stack_size) + *fill* 0x0000000020004800 0x800 + 0x0000000020005000 PROVIDE (_eusrstack = .) +OUTPUT(BMS_CC.elf elf32-littleriscv) + +.debug_info 0x0000000000000000 0x857c + .debug_info 0x0000000000000000 0xc14 ./User/ch32l103_it.o + .debug_info 0x0000000000000c14 0xaa6 ./User/main.o + .debug_info 0x00000000000016ba 0xc31 ./User/system_ch32l103.o + .debug_info 0x00000000000022eb 0x22 ./Startup/startup_ch32l103.o + .debug_info 0x000000000000230d 0xae8 ./Peripheral/src/ch32l103_dbgmcu.o + .debug_info 0x0000000000002df5 0x12e4 ./Peripheral/src/ch32l103_gpio.o + .debug_info 0x00000000000040d9 0xede ./Peripheral/src/ch32l103_misc.o + .debug_info 0x0000000000004fb7 0x12b1 ./Peripheral/src/ch32l103_rcc.o + .debug_info 0x0000000000006268 0x13f0 ./Peripheral/src/ch32l103_usart.o + .debug_info 0x0000000000007658 0xf24 ./Debug/debug.o + +.debug_abbrev 0x0000000000000000 0x197a + .debug_abbrev 0x0000000000000000 0x22c ./User/ch32l103_it.o + .debug_abbrev 0x000000000000022c 0x226 ./User/main.o + .debug_abbrev 0x0000000000000452 0x2b4 ./User/system_ch32l103.o + .debug_abbrev 0x0000000000000706 0x12 ./Startup/startup_ch32l103.o + .debug_abbrev 0x0000000000000718 0x2f7 ./Peripheral/src/ch32l103_dbgmcu.o + .debug_abbrev 0x0000000000000a0f 0x347 ./Peripheral/src/ch32l103_gpio.o + .debug_abbrev 0x0000000000000d56 0x2ea ./Peripheral/src/ch32l103_misc.o + .debug_abbrev 0x0000000000001040 0x351 ./Peripheral/src/ch32l103_rcc.o + .debug_abbrev 0x0000000000001391 0x312 ./Peripheral/src/ch32l103_usart.o + .debug_abbrev 0x00000000000016a3 0x2d7 ./Debug/debug.o + +.debug_aranges 0x0000000000000000 0x430 + .debug_aranges + 0x0000000000000000 0x28 ./User/ch32l103_it.o + .debug_aranges + 0x0000000000000028 0x20 ./User/main.o + .debug_aranges + 0x0000000000000048 0x28 ./User/system_ch32l103.o + .debug_aranges + 0x0000000000000070 0x30 ./Startup/startup_ch32l103.o + .debug_aranges + 0x00000000000000a0 0x48 ./Peripheral/src/ch32l103_dbgmcu.o + .debug_aranges + 0x00000000000000e8 0xa8 ./Peripheral/src/ch32l103_gpio.o + .debug_aranges + 0x0000000000000190 0x28 ./Peripheral/src/ch32l103_misc.o + .debug_aranges + 0x00000000000001b8 0x130 ./Peripheral/src/ch32l103_rcc.o + .debug_aranges + 0x00000000000002e8 0x100 ./Peripheral/src/ch32l103_usart.o + .debug_aranges + 0x00000000000003e8 0x48 ./Debug/debug.o + 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E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_exti.h \ + E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_flash.h \ + E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_gpio.h \ + E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_i2c.h \ + E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_iwdg.h \ + E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_pwr.h \ + E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_rcc.h \ + E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_rtc.h \ + E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_spi.h \ + E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_tim.h \ + E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_usart.h \ + E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_wwdg.h \ + E:\Y\MounRiver\ZDBMS\BMS_CC\User/ch32l103_it.h \ + E:\Y\MounRiver\ZDBMS\BMS_CC\Debug/debug.h \ + E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103.h \ + E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_misc.h \ + E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_lptim.h \ + E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_opa.h + +E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_dbgmcu.h: + +E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103.h: + +E:\Y\MounRiver\ZDBMS\BMS_CC\Core/core_riscv.h: + +E:\Y\MounRiver\ZDBMS\BMS_CC\User/system_ch32l103.h: + +E:\Y\MounRiver\ZDBMS\BMS_CC\User/ch32l103_conf.h: + +E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_adc.h: + +E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_bkp.h: + +E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_can.h: + +E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_crc.h: + +E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_dma.h: + +E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_exti.h: + +E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_flash.h: + +E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_gpio.h: + +E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_i2c.h: + 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E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_dma.h \ + E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103.h \ + E:\Y\MounRiver\ZDBMS\BMS_CC\Core/core_riscv.h \ + E:\Y\MounRiver\ZDBMS\BMS_CC\User/system_ch32l103.h \ + E:\Y\MounRiver\ZDBMS\BMS_CC\User/ch32l103_conf.h \ + E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_adc.h \ + E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_bkp.h \ + E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_can.h \ + E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_crc.h \ + E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_dbgmcu.h \ + E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_exti.h \ + E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_flash.h \ + E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_gpio.h \ + E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_i2c.h \ + E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_iwdg.h \ + E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_pwr.h \ + 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E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_flash.h \ + E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_gpio.h \ + E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_i2c.h \ + E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_iwdg.h \ + E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_pwr.h \ + E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_rcc.h \ + E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_rtc.h \ + E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_spi.h \ + E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_tim.h \ + E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_usart.h \ + E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_wwdg.h \ + E:\Y\MounRiver\ZDBMS\BMS_CC\User/ch32l103_it.h \ + E:\Y\MounRiver\ZDBMS\BMS_CC\Debug/debug.h \ + E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103.h \ + E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_misc.h \ + E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_lptim.h \ + E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_opa.h + +E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_exti.h: + +E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103.h: + +E:\Y\MounRiver\ZDBMS\BMS_CC\Core/core_riscv.h: + +E:\Y\MounRiver\ZDBMS\BMS_CC\User/system_ch32l103.h: + +E:\Y\MounRiver\ZDBMS\BMS_CC\User/ch32l103_conf.h: + +E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_adc.h: + +E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_bkp.h: + +E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_can.h: + +E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_crc.h: + +E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_dbgmcu.h: + +E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_dma.h: + +E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_flash.h: + +E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_gpio.h: + +E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_i2c.h: + +E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_iwdg.h: + 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E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_bkp.h \ + E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_can.h \ + E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_crc.h \ + E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_dbgmcu.h \ + E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_dma.h \ + E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_exti.h \ + E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_flash.h \ + E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_gpio.h \ + E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_i2c.h \ + E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_pwr.h \ + E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_rcc.h \ + E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_rtc.h \ + E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_spi.h \ + E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_tim.h \ + E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_usart.h \ + E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_wwdg.h \ + E:\Y\MounRiver\ZDBMS\BMS_CC\User/ch32l103_it.h \ + E:\Y\MounRiver\ZDBMS\BMS_CC\Debug/debug.h \ + E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103.h \ + E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_misc.h \ + E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_lptim.h \ + E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_opa.h + +E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_iwdg.h: + +E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103.h: + +E:\Y\MounRiver\ZDBMS\BMS_CC\Core/core_riscv.h: + +E:\Y\MounRiver\ZDBMS\BMS_CC\User/system_ch32l103.h: + +E:\Y\MounRiver\ZDBMS\BMS_CC\User/ch32l103_conf.h: + +E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_adc.h: + +E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_bkp.h: + +E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_can.h: + +E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_crc.h: + +E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_dbgmcu.h: + +E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_dma.h: + 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E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_exti.h \ + E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_flash.h \ + E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_gpio.h \ + E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_i2c.h \ + E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_iwdg.h \ + E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_pwr.h \ + E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_rcc.h \ + E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_rtc.h \ + E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_spi.h \ + E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_tim.h \ + E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_usart.h \ + E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_wwdg.h \ + E:\Y\MounRiver\ZDBMS\BMS_CC\User/ch32l103_it.h \ + E:\Y\MounRiver\ZDBMS\BMS_CC\Debug/debug.h \ + E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103.h \ + E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_lptim.h \ + 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b/ZDBMS/BMS_CC/obj/Peripheral/src/ch32l103_opa.d new file mode 100644 index 0000000..a67ef62 --- /dev/null +++ b/ZDBMS/BMS_CC/obj/Peripheral/src/ch32l103_opa.d @@ -0,0 +1,85 @@ +Peripheral/src/ch32l103_opa.o: ../Peripheral/src/ch32l103_opa.c \ + E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_opa.h \ + E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103.h \ + E:\Y\MounRiver\ZDBMS\BMS_CC\Core/core_riscv.h \ + E:\Y\MounRiver\ZDBMS\BMS_CC\User/system_ch32l103.h \ + E:\Y\MounRiver\ZDBMS\BMS_CC\User/ch32l103_conf.h \ + E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_adc.h \ + E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_bkp.h \ + E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_can.h \ + E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_crc.h \ + E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_dbgmcu.h \ + E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_dma.h \ + E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_exti.h \ + E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_flash.h \ + E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_gpio.h \ + E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_i2c.h \ + E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_iwdg.h \ + E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_pwr.h \ + E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_rcc.h \ + E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_rtc.h \ + E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_spi.h \ + E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_tim.h \ + E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_usart.h \ + E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_wwdg.h \ + E:\Y\MounRiver\ZDBMS\BMS_CC\User/ch32l103_it.h \ + E:\Y\MounRiver\ZDBMS\BMS_CC\Debug/debug.h \ + E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103.h \ + E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_misc.h \ + E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_lptim.h + +E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_opa.h: + +E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103.h: + +E:\Y\MounRiver\ZDBMS\BMS_CC\Core/core_riscv.h: + +E:\Y\MounRiver\ZDBMS\BMS_CC\User/system_ch32l103.h: + +E:\Y\MounRiver\ZDBMS\BMS_CC\User/ch32l103_conf.h: + +E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_adc.h: + +E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_bkp.h: + +E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_can.h: + +E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_crc.h: + +E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_dbgmcu.h: + +E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_dma.h: + +E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_exti.h: + +E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_flash.h: + +E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_gpio.h: + +E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_i2c.h: + +E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_iwdg.h: + +E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_pwr.h: + +E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_rcc.h: + +E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_rtc.h: + +E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_spi.h: + +E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_tim.h: + +E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_usart.h: + +E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_wwdg.h: + +E:\Y\MounRiver\ZDBMS\BMS_CC\User/ch32l103_it.h: + +E:\Y\MounRiver\ZDBMS\BMS_CC\Debug/debug.h: + +E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103.h: + +E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_misc.h: + +E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_lptim.h: diff --git a/ZDBMS/BMS_CC/obj/Peripheral/src/ch32l103_opa.o b/ZDBMS/BMS_CC/obj/Peripheral/src/ch32l103_opa.o new file mode 100644 index 0000000000000000000000000000000000000000..26129de395b305b2504125de4e4b4f5d52453d43 GIT binary patch literal 41552 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E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_dma.h \ + E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_exti.h \ + E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_flash.h \ + E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_gpio.h \ + E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_i2c.h \ + E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_iwdg.h \ + E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_rcc.h \ + E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_rtc.h \ + E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_spi.h \ + E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_tim.h \ + E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_usart.h \ + E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_wwdg.h \ + E:\Y\MounRiver\ZDBMS\BMS_CC\User/ch32l103_it.h \ + E:\Y\MounRiver\ZDBMS\BMS_CC\Debug/debug.h \ + E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103.h \ + E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_misc.h \ + E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_lptim.h \ + E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_opa.h + +E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_pwr.h: + +E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103.h: + +E:\Y\MounRiver\ZDBMS\BMS_CC\Core/core_riscv.h: + +E:\Y\MounRiver\ZDBMS\BMS_CC\User/system_ch32l103.h: + +E:\Y\MounRiver\ZDBMS\BMS_CC\User/ch32l103_conf.h: + +E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_adc.h: + +E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_bkp.h: + +E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_can.h: + +E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_crc.h: + +E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_dbgmcu.h: + +E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_dma.h: + +E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_exti.h: + +E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_flash.h: + +E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_gpio.h: + +E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_i2c.h: + +E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_iwdg.h: + +E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_rcc.h: + +E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_rtc.h: + +E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_spi.h: + +E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_tim.h: + +E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_usart.h: + +E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_wwdg.h: + +E:\Y\MounRiver\ZDBMS\BMS_CC\User/ch32l103_it.h: + +E:\Y\MounRiver\ZDBMS\BMS_CC\Debug/debug.h: + +E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103.h: + +E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_misc.h: + +E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_lptim.h: + +E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_opa.h: diff --git a/ZDBMS/BMS_CC/obj/Peripheral/src/ch32l103_pwr.o b/ZDBMS/BMS_CC/obj/Peripheral/src/ch32l103_pwr.o new file mode 100644 index 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E:\Y\MounRiver\ZDBMS\BMS_CC\Core/core_riscv.h \ + E:\Y\MounRiver\ZDBMS\BMS_CC\User/system_ch32l103.h \ + E:\Y\MounRiver\ZDBMS\BMS_CC\User/ch32l103_conf.h \ + E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_adc.h \ + E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_bkp.h \ + E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_can.h \ + E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_crc.h \ + E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_dbgmcu.h \ + E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_dma.h \ + E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_exti.h \ + E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_flash.h \ + E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_gpio.h \ + E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_i2c.h \ + E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_iwdg.h \ + E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_pwr.h \ + E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_rcc.h \ + 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E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_adc.h \ + E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_bkp.h \ + E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_can.h \ + E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_crc.h \ + E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_dbgmcu.h \ + E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_dma.h \ + E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_exti.h \ + E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_flash.h \ + E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_gpio.h \ + E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_i2c.h \ + E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_iwdg.h \ + E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_pwr.h \ + E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_rcc.h \ + E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_rtc.h \ + E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_tim.h \ + E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_usart.h \ + E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_wwdg.h \ + E:\Y\MounRiver\ZDBMS\BMS_CC\User/ch32l103_it.h \ + E:\Y\MounRiver\ZDBMS\BMS_CC\Debug/debug.h \ + E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103.h \ + E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_misc.h \ + E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_lptim.h \ + E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_opa.h + +E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_spi.h: + +E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103.h: + +E:\Y\MounRiver\ZDBMS\BMS_CC\Core/core_riscv.h: + +E:\Y\MounRiver\ZDBMS\BMS_CC\User/system_ch32l103.h: + +E:\Y\MounRiver\ZDBMS\BMS_CC\User/ch32l103_conf.h: + +E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_adc.h: + +E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_bkp.h: + +E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_can.h: + +E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_crc.h: + +E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_dbgmcu.h: + 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E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103.h \ + E:\Y\MounRiver\ZDBMS\BMS_CC\Core/core_riscv.h \ + E:\Y\MounRiver\ZDBMS\BMS_CC\User/system_ch32l103.h \ + E:\Y\MounRiver\ZDBMS\BMS_CC\User/ch32l103_conf.h \ + E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_adc.h \ + E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_bkp.h \ + E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_can.h \ + E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_crc.h \ + E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_dbgmcu.h \ + E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_dma.h \ + E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_exti.h \ + E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_flash.h \ + E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_gpio.h \ + E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_i2c.h \ + E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_iwdg.h \ + E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_pwr.h \ + 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E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_wwdg.h \ + E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103.h \ + E:\Y\MounRiver\ZDBMS\BMS_CC\Core/core_riscv.h \ + E:\Y\MounRiver\ZDBMS\BMS_CC\User/system_ch32l103.h \ + E:\Y\MounRiver\ZDBMS\BMS_CC\User/ch32l103_conf.h \ + E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_adc.h \ + E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_bkp.h \ + E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_can.h \ + E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_crc.h \ + E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_dbgmcu.h \ + E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_dma.h \ + E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_exti.h \ + E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_flash.h \ + E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_gpio.h \ + E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_i2c.h \ + E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_iwdg.h \ + E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_pwr.h \ + E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_rcc.h \ + E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_rtc.h \ + E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_spi.h \ + E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_tim.h \ + E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_usart.h \ + E:\Y\MounRiver\ZDBMS\BMS_CC\User/ch32l103_it.h \ + E:\Y\MounRiver\ZDBMS\BMS_CC\Debug/debug.h \ + E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103.h \ + E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_misc.h \ + E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_lptim.h \ + E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_opa.h + +E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_wwdg.h: + +E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103.h: + +E:\Y\MounRiver\ZDBMS\BMS_CC\Core/core_riscv.h: + +E:\Y\MounRiver\ZDBMS\BMS_CC\User/system_ch32l103.h: + +E:\Y\MounRiver\ZDBMS\BMS_CC\User/ch32l103_conf.h: + +E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_adc.h: + +E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_bkp.h: + +E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_can.h: + +E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_crc.h: + +E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_dbgmcu.h: + +E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_dma.h: + +E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_exti.h: + +E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_flash.h: + +E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_gpio.h: + +E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_i2c.h: + +E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_iwdg.h: + +E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_pwr.h: + +E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_rcc.h: + +E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_rtc.h: + +E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_spi.h: + +E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_tim.h: + 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zyvq=jMx%`e@LO+UI1tgtuW>nGsZ!A6%My&kiUX^ L4nD(o#limsfdP}B literal 0 HcmV?d00001 diff --git a/ZDBMS/BMS_CC/obj/Peripheral/src/subdir.mk b/ZDBMS/BMS_CC/obj/Peripheral/src/subdir.mk new file mode 100644 index 0000000..9a28b00 --- /dev/null +++ b/ZDBMS/BMS_CC/obj/Peripheral/src/subdir.mk @@ -0,0 +1,81 @@ +################################################################################ +# MRS Version: 1.9.2 +# 自动生成的文件。不要编辑！ +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +C_SRCS += \ +../Peripheral/src/ch32l103_adc.c \ +../Peripheral/src/ch32l103_bkp.c \ +../Peripheral/src/ch32l103_can.c \ +../Peripheral/src/ch32l103_crc.c \ +../Peripheral/src/ch32l103_dbgmcu.c \ +../Peripheral/src/ch32l103_dma.c \ +../Peripheral/src/ch32l103_exti.c \ +../Peripheral/src/ch32l103_flash.c \ +../Peripheral/src/ch32l103_gpio.c \ +../Peripheral/src/ch32l103_i2c.c \ +../Peripheral/src/ch32l103_iwdg.c \ +../Peripheral/src/ch32l103_lptim.c \ +../Peripheral/src/ch32l103_misc.c \ +../Peripheral/src/ch32l103_opa.c \ +../Peripheral/src/ch32l103_pwr.c \ +../Peripheral/src/ch32l103_rcc.c \ +../Peripheral/src/ch32l103_rtc.c \ +../Peripheral/src/ch32l103_spi.c \ +../Peripheral/src/ch32l103_tim.c \ +../Peripheral/src/ch32l103_usart.c \ +../Peripheral/src/ch32l103_wwdg.c + +OBJS += \ +./Peripheral/src/ch32l103_adc.o \ +./Peripheral/src/ch32l103_bkp.o \ +./Peripheral/src/ch32l103_can.o \ +./Peripheral/src/ch32l103_crc.o \ +./Peripheral/src/ch32l103_dbgmcu.o \ +./Peripheral/src/ch32l103_dma.o \ +./Peripheral/src/ch32l103_exti.o \ +./Peripheral/src/ch32l103_flash.o \ +./Peripheral/src/ch32l103_gpio.o \ +./Peripheral/src/ch32l103_i2c.o \ +./Peripheral/src/ch32l103_iwdg.o \ +./Peripheral/src/ch32l103_lptim.o \ +./Peripheral/src/ch32l103_misc.o \ +./Peripheral/src/ch32l103_opa.o \ +./Peripheral/src/ch32l103_pwr.o \ +./Peripheral/src/ch32l103_rcc.o \ +./Peripheral/src/ch32l103_rtc.o \ +./Peripheral/src/ch32l103_spi.o \ +./Peripheral/src/ch32l103_tim.o \ +./Peripheral/src/ch32l103_usart.o \ +./Peripheral/src/ch32l103_wwdg.o + +C_DEPS += \ +./Peripheral/src/ch32l103_adc.d \ +./Peripheral/src/ch32l103_bkp.d \ +./Peripheral/src/ch32l103_can.d \ +./Peripheral/src/ch32l103_crc.d \ +./Peripheral/src/ch32l103_dbgmcu.d \ +./Peripheral/src/ch32l103_dma.d \ +./Peripheral/src/ch32l103_exti.d \ +./Peripheral/src/ch32l103_flash.d \ +./Peripheral/src/ch32l103_gpio.d \ +./Peripheral/src/ch32l103_i2c.d \ +./Peripheral/src/ch32l103_iwdg.d \ +./Peripheral/src/ch32l103_lptim.d \ +./Peripheral/src/ch32l103_misc.d \ +./Peripheral/src/ch32l103_opa.d \ +./Peripheral/src/ch32l103_pwr.d \ +./Peripheral/src/ch32l103_rcc.d \ +./Peripheral/src/ch32l103_rtc.d \ +./Peripheral/src/ch32l103_spi.d \ +./Peripheral/src/ch32l103_tim.d \ +./Peripheral/src/ch32l103_usart.d \ +./Peripheral/src/ch32l103_wwdg.d + + +# Each subdirectory must supply rules for building sources it contributes +Peripheral/src/%.o: ../Peripheral/src/%.c + @ @ riscv-none-embed-gcc -march=rv32imacxw -mabi=ilp32 -msmall-data-limit=8 -msave-restore -Os -fmessage-length=0 -fsigned-char -ffunction-sections -fdata-sections -fno-common -Wunused -Wuninitialized -g -I"E:\Y\MounRiver\ZDBMS\BMS_CC\Debug" -I"E:\Y\MounRiver\ZDBMS\BMS_CC\Core" -I"E:\Y\MounRiver\ZDBMS\BMS_CC\User" -I"E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc" -std=gnu99 -MMD -MP -MF"$(@:%.o=%.d)" -MT"$(@)" -c -o "$@" "$<" + @ @ + diff --git a/ZDBMS/BMS_CC/obj/Startup/startup_ch32l103.d b/ZDBMS/BMS_CC/obj/Startup/startup_ch32l103.d new file mode 100644 index 0000000..5643714 --- /dev/null +++ b/ZDBMS/BMS_CC/obj/Startup/startup_ch32l103.d @@ -0,0 +1 @@ +Startup/startup_ch32l103.o: ../Startup/startup_ch32l103.S diff --git a/ZDBMS/BMS_CC/obj/Startup/startup_ch32l103.o b/ZDBMS/BMS_CC/obj/Startup/startup_ch32l103.o new file mode 100644 index 0000000000000000000000000000000000000000..b74a9d3a13e2666cb83022d75788184c73209e6e GIT binary patch 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+../User/main.c \ +../User/system_ch32l103.c + +OBJS += \ +./User/ch32l103_it.o \ +./User/main.o \ +./User/system_ch32l103.o + +C_DEPS += \ +./User/ch32l103_it.d \ +./User/main.d \ +./User/system_ch32l103.d + + +# Each subdirectory must supply rules for building sources it contributes +User/%.o: ../User/%.c + @ @ riscv-none-embed-gcc -march=rv32imacxw -mabi=ilp32 -msmall-data-limit=8 -msave-restore -Os -fmessage-length=0 -fsigned-char -ffunction-sections -fdata-sections -fno-common -Wunused -Wuninitialized -g -I"E:\Y\MounRiver\ZDBMS\BMS_CC\Debug" -I"E:\Y\MounRiver\ZDBMS\BMS_CC\Core" -I"E:\Y\MounRiver\ZDBMS\BMS_CC\User" -I"E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc" -std=gnu99 -MMD -MP -MF"$(@:%.o=%.d)" -MT"$(@)" -c -o "$@" "$<" + @ @ + diff --git a/ZDBMS/BMS_CC/obj/User/system_ch32l103.d b/ZDBMS/BMS_CC/obj/User/system_ch32l103.d new file mode 100644 index 0000000..6a91109 --- /dev/null +++ b/ZDBMS/BMS_CC/obj/User/system_ch32l103.d @@ -0,0 +1,85 @@ +User/system_ch32l103.o: ../User/system_ch32l103.c \ + E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103.h \ + E:\Y\MounRiver\ZDBMS\BMS_CC\Core/core_riscv.h \ + E:\Y\MounRiver\ZDBMS\BMS_CC\User/system_ch32l103.h \ + E:\Y\MounRiver\ZDBMS\BMS_CC\User/ch32l103_conf.h \ + E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_adc.h \ + E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103.h \ + E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_bkp.h \ + E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_can.h \ + E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_crc.h \ + E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_dbgmcu.h \ + E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_dma.h \ + E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_exti.h \ + E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_flash.h \ + E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_gpio.h \ + E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_i2c.h \ + E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_iwdg.h \ + E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_pwr.h \ + E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_rcc.h \ + E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_rtc.h \ + E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_spi.h \ + E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_tim.h \ + E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_usart.h \ + E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_wwdg.h \ + E:\Y\MounRiver\ZDBMS\BMS_CC\User/ch32l103_it.h \ + E:\Y\MounRiver\ZDBMS\BMS_CC\Debug/debug.h \ + E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_misc.h \ + E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_lptim.h \ + E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_opa.h + +E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103.h: + +E:\Y\MounRiver\ZDBMS\BMS_CC\Core/core_riscv.h: + +E:\Y\MounRiver\ZDBMS\BMS_CC\User/system_ch32l103.h: + +E:\Y\MounRiver\ZDBMS\BMS_CC\User/ch32l103_conf.h: + +E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_adc.h: + +E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103.h: + +E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_bkp.h: + +E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_can.h: + +E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_crc.h: + +E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_dbgmcu.h: + +E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_dma.h: + +E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_exti.h: + +E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_flash.h: + +E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_gpio.h: + +E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_i2c.h: + +E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_iwdg.h: + +E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_pwr.h: + +E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_rcc.h: + +E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_rtc.h: + +E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_spi.h: + +E:\Y\MounRiver\ZDBMS\BMS_CC\Peripheral\inc/ch32l103_tim.h: + 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+-include sources.mk +-include User/subdir.mk +-include Startup/subdir.mk +-include Peripheral/src/subdir.mk +-include Debug/subdir.mk +-include Core/subdir.mk +-include subdir.mk +-include objects.mk + +ifneq ($(MAKECMDGOALS),clean) +ifneq ($(strip $(ASM_UPPER_DEPS)),) +-include $(ASM_UPPER_DEPS) +endif +ifneq ($(strip $(ASM_DEPS)),) +-include $(ASM_DEPS) +endif +ifneq ($(strip $(S_DEPS)),) +-include $(S_DEPS) +endif +ifneq ($(strip $(S_UPPER_DEPS)),) +-include $(S_UPPER_DEPS) +endif +ifneq ($(strip $(C_DEPS)),) +-include $(C_DEPS) +endif +endif + +-include ../makefile.defs + +# Add inputs and outputs from these tool invocations to the build variables +SECONDARY_FLASH += \ +BMS_CC.hex \ + +SECONDARY_LIST += \ +BMS_CC.lst \ + +SECONDARY_SIZE += \ +BMS_CC.siz \ + + +# 所有目标 +all: BMS_CC.elf secondary-outputs + +# 工具调用 +BMS_CC.elf: $(OBJS) $(USER_OBJS) + @ @ riscv-none-embed-gcc -march=rv32imacxw -mabi=ilp32 -msmall-data-limit=8 -msave-restore -Os -fmessage-length=0 -fsigned-char -ffunction-sections -fdata-sections -fno-common -Wunused -Wuninitialized -g -T "E:\Y\MounRiver\ZDBMS\BMS_CC\Ld\Link.ld" -nostartfiles -Xlinker --gc-sections -Wl,-Map,"BMS_CC.map" --specs=nano.specs --specs=nosys.specs -o "BMS_CC.elf" $(OBJS) $(USER_OBJS) $(LIBS) + @ @ +BMS_CC.hex: BMS_CC.elf + @ riscv-none-embed-objcopy -O ihex "BMS_CC.elf" "BMS_CC.hex" + @ @ +BMS_CC.lst: BMS_CC.elf + @ riscv-none-embed-objdump --all-headers --demangle --disassemble -M xw "BMS_CC.elf" > "BMS_CC.lst" + @ @ +BMS_CC.siz: BMS_CC.elf + @ riscv-none-embed-size --format=berkeley "BMS_CC.elf" + @ @ +# 其他目标 +clean: + -$(RM) $(ASM_UPPER_DEPS)$(OBJS)$(SECONDARY_FLASH)$(SECONDARY_LIST)$(SECONDARY_SIZE)$(ASM_DEPS)$(S_DEPS)$(S_UPPER_DEPS)$(C_DEPS) BMS_CC.elf + -@ +secondary-outputs: $(SECONDARY_FLASH) $(SECONDARY_LIST) $(SECONDARY_SIZE) + +.PHONY: all clean dependents + +-include ../makefile.targets diff --git a/ZDBMS/BMS_CC/obj/objects.mk b/ZDBMS/BMS_CC/obj/objects.mk new file mode 100644 index 0000000..cccee33 --- /dev/null +++ b/ZDBMS/BMS_CC/obj/objects.mk @@ -0,0 +1,9 @@ +################################################################################ +# MRS Version: 1.9.2 +# 自动生成的文件。不要编辑！ +################################################################################ + +USER_OBJS := + +LIBS := + diff --git a/ZDBMS/BMS_CC/obj/sources.mk b/ZDBMS/BMS_CC/obj/sources.mk new file mode 100644 index 0000000..81b4ecc --- /dev/null +++ b/ZDBMS/BMS_CC/obj/sources.mk @@ -0,0 +1,31 @@ +################################################################################ +# MRS Version: 1.9.2 +# 自动生成的文件。不要编辑！ +################################################################################ + +ELF_SRCS := +OBJ_SRCS := +S_SRCS := +ASM_UPPER_SRCS := +ASM_SRCS := +C_SRCS := +S_UPPER_SRCS := +O_SRCS := +ASM_UPPER_DEPS := +OBJS := +SECONDARY_FLASH := +SECONDARY_LIST := +SECONDARY_SIZE := +ASM_DEPS := +S_DEPS := +S_UPPER_DEPS := +C_DEPS := + +# Every subdirectory with source files must be described here +SUBDIRS := \ +Core \ +Debug \ +Peripheral/src \ +Startup \ +User \ + diff --git a/ZDBMS/BMS_MC/.cproject b/ZDBMS/BMS_MC/.cproject new file mode 100644 index 0000000..f6bc68e --- /dev/null +++ b/ZDBMS/BMS_MC/.cproject @@ -0,0 +1,144 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/ZDBMS/BMS_MC/.project b/ZDBMS/BMS_MC/.project new file mode 100644 index 0000000..1d50014 --- /dev/null +++ b/ZDBMS/BMS_MC/.project @@ -0,0 +1,34 @@ + + + BMS_MC + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + 1595986042669 + + 22 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-*.wvproj + + + + diff --git a/ZDBMS/BMS_MC/.settings/language.settings.xml b/ZDBMS/BMS_MC/.settings/language.settings.xml new file mode 100644 index 0000000..76e1fd6 --- /dev/null +++ b/ZDBMS/BMS_MC/.settings/language.settings.xml @@ -0,0 +1,14 @@ + + + + + + + + + + + + + + diff --git a/ZDBMS/BMS_MC/.template b/ZDBMS/BMS_MC/.template new file mode 100644 index 0000000..64214f9 --- /dev/null +++ b/ZDBMS/BMS_MC/.template @@ -0,0 +1,17 @@ +Mcu Type=CH32L10x +Address=0x08000000 +Target Path=obj/BMS_MC.hex +Erase All=true +Program=true +Verify=true +Reset=true + +Vendor=WCH +Link=WCH-Link +Toolchain=RISC-V +Series=CH32L103 +MCU=CH32L103C8T6 +Description=Website: https://www.wch.cn/products/CH32L103.html?\nROM(byte): 64K, SRAM(byte): 20K, CHIP PINS: 48, GPIO PORTS: 37.\nCH32L103 is an industrial-grade low-power general purpose microcontroller based on Highland Barley RISC-V core design. The CH32L103 has built-in USB and PD PHY, support PDUSB, including USB Host host and USB Device device function, USB PD and type C fast charge function, built-in low power timer, It provides a set of OPA operation amplifier, 3 sets of CMP voltage comparators, 4 sets of USART serial ports, 2 I2C interfaces, 2 SPI interfaces, 1 set of CAN interfaces, multiple sets of timers, 12-bit ADC, 10 Touchkeys and other peripheral resources. + +PeripheralVersion=1.4 + diff --git a/ZDBMS/BMS_MC/BMS_MC.launch b/ZDBMS/BMS_MC/BMS_MC.launch new file mode 100644 index 0000000..f490287 --- /dev/null +++ b/ZDBMS/BMS_MC/BMS_MC.launch @@ -0,0 +1,61 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/ZDBMS/BMS_MC/BMS_MC.wvproj b/ZDBMS/BMS_MC/BMS_MC.wvproj new file mode 100644 index 0000000..8f41dac --- /dev/null +++ b/ZDBMS/BMS_MC/BMS_MC.wvproj @@ -0,0 +1 @@ +叿竁1]Op0 /坣:眿{瓰%axP腝]浗d7-潟痭嫊焳l;#7莬2#絜p\┑t京Md|#G魔b枔?|嚦枪sR暦﹏mO:W8 \'/媯n[<7-&恅r吂AqKbEVZ娋;纍媐艶B=倵;楶睼舶i4%[悑嚀K5e WH磼*;u^LyW膒mw箍oY \ No newline at end of file diff --git a/ZDBMS/BMS_MC/Core/core_riscv.c b/ZDBMS/BMS_MC/Core/core_riscv.c new file mode 100644 index 0000000..d7d416d --- /dev/null +++ b/ZDBMS/BMS_MC/Core/core_riscv.c @@ -0,0 +1,306 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : core_riscv.c + * Author : WCH + * Version : V1.0.0 + * Date : 2023/11/11 + * Description : RISC-V V4 Core Peripheral Access Layer Source File for CH32L103 + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#include + +/* define compiler specific symbols */ +#if defined ( __CC_ARM ) + #define __ASM __asm /* asm keyword for ARM Compiler */ + #define __INLINE __inline /* inline keyword for ARM Compiler */ + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /* asm keyword for IAR Compiler */ + #define __INLINE inline /* inline keyword for IAR Compiler. Only avaiable in High optimization mode */ + +#elif defined ( __GNUC__ ) + #define __ASM __asm /* asm keyword for GNU Compiler */ + #define __INLINE inline /* inline keyword for GNU Compiler */ + +#elif defined ( __TASKING__ ) + #define __ASM __asm /* asm keyword for TASKING Compiler */ + #define __INLINE inline /* inline keyword for TASKING Compiler */ + +#endif + + + +/********************************************************************* + * @fn __get_MSTATUS + * + * @brief Return the Machine Status Register + * + * @return mstatus value + */ +uint32_t __get_MSTATUS(void) +{ + uint32_t result; + + __ASM volatile ( "csrr %0," "mstatus" : "=r" (result) ); + return (result); +} + +/********************************************************************* + * @fn __set_MSTATUS + * + * @brief Set the Machine Status Register + * + * @param value - set mstatus value + * + * @return none + */ +void __set_MSTATUS(uint32_t value) +{ + __ASM volatile ("csrw mstatus, %0" : : "r" (value) ); +} + +/********************************************************************* + * @fn __get_MISA + * + * @brief Return the Machine ISA Register + * + * @return misa value + */ +uint32_t __get_MISA(void) +{ + uint32_t result; + + __ASM volatile ( "csrr %0," "misa" : "=r" (result) ); + return (result); +} + +/********************************************************************* + * @fn __set_MISA + * + * @brief Set the Machine ISA Register + * + * @param value - set misa value + * + * @return none + */ +void __set_MISA(uint32_t value) +{ + __ASM volatile ("csrw misa, %0" : : "r" (value) ); +} + +/********************************************************************* + * @fn __get_MTVEC + * + * @brief Return the Machine Trap-Vector Base-Address Register + * + * @return mtvec value + */ +uint32_t __get_MTVEC(void) +{ + uint32_t result; + + __ASM volatile ( "csrr %0," "mtvec" : "=r" (result) ); + return (result); +} + +/********************************************************************* + * @fn __set_MTVEC + * + * @brief Set the Machine Trap-Vector Base-Address Register + * + * @param value - set mtvec value + * + * @return none + */ +void __set_MTVEC(uint32_t value) +{ + __ASM volatile ("csrw mtvec, %0" : : "r" (value) ); +} + +/********************************************************************* + * @fn __get_MSCRATCH + * + * @brief Return the Machine Seratch Register + * + * @return mscratch value + */ +uint32_t __get_MSCRATCH(void) +{ + uint32_t result; + + __ASM volatile ( "csrr %0," "mscratch" : "=r" (result) ); + return (result); +} + +/********************************************************************* + * @fn __set_MSCRATCH + * + * @brief Set the Machine Seratch Register + * + * @param value - set mscratch value + * + * @return none + */ +void __set_MSCRATCH(uint32_t value) +{ + __ASM volatile ("csrw mscratch, %0" : : "r" (value) ); +} + +/********************************************************************* + * @fn __get_MEPC + * + * @brief Return the Machine Exception Program Register + * + * @return mepc value + */ +uint32_t __get_MEPC(void) +{ + uint32_t result; + + __ASM volatile ( "csrr %0," "mepc" : "=r" (result) ); + return (result); +} + +/********************************************************************* + * @fn __set_MEPC + * + * @brief Set the Machine Exception Program Register + * + * @return mepc value + */ +void __set_MEPC(uint32_t value) +{ + __ASM volatile ("csrw mepc, %0" : : "r" (value) ); +} + +/********************************************************************* + * @fn __get_MCAUSE + * + * @brief Return the Machine Cause Register + * + * @return mcause value + */ +uint32_t __get_MCAUSE(void) +{ + uint32_t result; + + __ASM volatile ( "csrr %0," "mcause" : "=r" (result) ); + return (result); +} + +/********************************************************************* + * @fn __set_MEPC + * + * @brief Set the Machine Cause Register + * + * @return mcause value + */ +void __set_MCAUSE(uint32_t value) +{ + __ASM volatile ("csrw mcause, %0" : : "r" (value) ); +} + +/********************************************************************* + * @fn __get_MTVAL + * + * @brief Return the Machine Trap Value Register + * + * @return mtval value + */ +uint32_t __get_MTVAL(void) +{ + uint32_t result; + + __ASM volatile ( "csrr %0," "mtval" : "=r" (result) ); + return (result); +} + +/********************************************************************* + * @fn __set_MTVAL + * + * @brief Set the Machine Trap Value Register + * + * @return mtval value + */ +void __set_MTVAL(uint32_t value) +{ + __ASM volatile ("csrw mtval, %0" : : "r" (value) ); +} + +/********************************************************************* + * @fn __get_MVENDORID + * + * @brief Return Vendor ID Register + * + * @return mvendorid value + */ +uint32_t __get_MVENDORID(void) +{ + uint32_t result; + + __ASM volatile ( "csrr %0," "mvendorid" : "=r" (result) ); + return (result); +} + +/********************************************************************* + * @fn __get_MARCHID + * + * @brief Return Machine Architecture ID Register + * + * @return marchid value + */ +uint32_t __get_MARCHID(void) +{ + uint32_t result; + + __ASM volatile ( "csrr %0," "marchid" : "=r" (result) ); + return (result); +} + +/********************************************************************* + * @fn __get_MIMPID + * + * @brief Return Machine Implementation ID Register + * + * @return mimpid value + */ +uint32_t __get_MIMPID(void) +{ + uint32_t result; + + __ASM volatile ( "csrr %0," "mimpid" : "=r" (result) ); + return (result); +} + +/********************************************************************* + * @fn __get_MHARTID + * + * @brief Return Hart ID Register + * + * @return mhartid value + */ +uint32_t __get_MHARTID(void) +{ + uint32_t result; + + __ASM volatile ( "csrr %0," "mhartid" : "=r" (result) ); + return (result); +} + +/********************************************************************* + * @fn __get_SP + * + * @brief Return SP Register + * + * @return SP value + */ +uint32_t __get_SP(void) +{ + uint32_t result; + + __ASM volatile ( "mv %0," "sp" : "=r"(result) : ); + return (result); +} + diff --git a/ZDBMS/BMS_MC/Core/core_riscv.h b/ZDBMS/BMS_MC/Core/core_riscv.h new file mode 100644 index 0000000..46c433c --- /dev/null +++ b/ZDBMS/BMS_MC/Core/core_riscv.h @@ -0,0 +1,585 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : core_riscv.h + * Author : WCH + * Version : V1.0.0 + * Date : 2023/12/26 + * Description : RISC-V V4 Core Peripheral Access Layer Header File for CH32L103 + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#ifndef __CORE_RISCV_H__ +#define __CORE_RISCV_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/* IO definitions */ +#ifdef __cplusplus + #define __I volatile /* defines 'read only' permissions */ +#else + #define __I volatile const /* defines 'read only' permissions */ +#endif +#define __O volatile /* defines 'write only' permissions */ +#define __IO volatile /* defines 'read / write' permissions */ + + +typedef __I uint64_t vuc64; /* Read Only */ +typedef __I uint32_t vuc32; /* Read Only */ +typedef __I uint16_t vuc16; /* Read Only */ +typedef __I uint8_t vuc8; /* Read Only */ + +typedef const uint64_t uc64; /* Read Only */ +typedef const uint32_t uc32; /* Read Only */ +typedef const uint16_t uc16; /* Read Only */ +typedef const uint8_t uc8; /* Read Only */ + +typedef __I int64_t vsc64; /* Read Only */ +typedef __I int32_t vsc32; /* Read Only */ +typedef __I int16_t vsc16; /* Read Only */ +typedef __I int8_t vsc8; /* Read Only */ + +typedef const int64_t sc64; /* Read Only */ +typedef const int32_t sc32; /* Read Only */ +typedef const int16_t sc16; /* Read Only */ +typedef const int8_t sc8; /* Read Only */ + +typedef __IO uint64_t vu64; +typedef __IO uint32_t vu32; +typedef __IO uint16_t vu16; +typedef __IO uint8_t vu8; + +typedef uint64_t u64; +typedef uint32_t u32; +typedef uint16_t u16; +typedef uint8_t u8; + +typedef __IO int64_t vs64; +typedef __IO int32_t vs32; +typedef __IO int16_t vs16; +typedef __IO int8_t vs8; + +typedef int64_t s64; +typedef int32_t s32; +typedef int16_t s16; +typedef int8_t s8; + +typedef enum {NoREADY = 0, READY = !NoREADY} ErrorStatus; + +typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState; + +typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus; + +#define RV_STATIC_INLINE static inline + +/* memory mapped structure for Program Fast Interrupt Controller (PFIC) */ +typedef struct{ + __I uint32_t ISR[8]; + __I uint32_t IPR[8]; + __IO uint32_t ITHRESDR; + __IO uint32_t RESERVED; + __IO uint32_t CFGR; + __I uint32_t GISR; + __IO uint8_t VTFIDR[4]; + uint8_t RESERVED0[12]; + __IO uint32_t VTFADDR[4]; + uint8_t RESERVED1[0x90]; + __O uint32_t IENR[8]; + uint8_t RESERVED2[0x60]; + __O uint32_t IRER[8]; + uint8_t RESERVED3[0x60]; + __O uint32_t IPSR[8]; + uint8_t RESERVED4[0x60]; + __O uint32_t IPRR[8]; + uint8_t RESERVED5[0x60]; + __IO uint32_t IACTR[8]; + uint8_t RESERVED6[0xE0]; + __IO uint8_t IPRIOR[256]; + uint8_t RESERVED7[0x810]; + __IO uint32_t SCTLR; +}PFIC_Type; + +/* memory mapped structure for SysTick */ +typedef struct +{ + __IO uint32_t CTLR; + __IO uint32_t SR; + __IO uint64_t CNT; + __IO uint64_t CMP; +}SysTick_Type; + + +#define PFIC ((PFIC_Type *) 0xE000E000) +#define NVIC PFIC +#define NVIC_KEY1 ((uint32_t)0xFA050000) +#define NVIC_KEY2 ((uint32_t)0xBCAF0000) +#define NVIC_KEY3 ((uint32_t)0xBEEF0000) +#define SysTick ((SysTick_Type *) 0xE000F000) + + +/********************************************************************* + * @fn __enable_irq + * + * @brief Enable Global Interrupt + * + * @return none + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE void __enable_irq() +{ + __asm volatile ("csrs 0x800, %0" : : "r" (0x88) ); +} + +/********************************************************************* + * @fn __disable_irq + * + * @brief Disable Global Interrupt + * + * @return none + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE void __disable_irq() +{ + __asm volatile ("csrc 0x800, %0" : : "r" (0x88) ); +} + +/********************************************************************* + * @fn __NOP + * + * @brief nop + * + * @return none + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE void __NOP() +{ + __asm volatile ("nop"); +} + +/********************************************************************* + * @fn NVIC_EnableIRQ + * + * @brief Disable Interrupt + * + * @param IRQn - Interrupt Numbers + * + * @return none + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ + NVIC->IENR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); +} + +/********************************************************************* + * @fn NVIC_DisableIRQ + * + * @brief Disable Interrupt + * + * @param IRQn - Interrupt Numbers + * + * @return none + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->IRER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); +} + +/********************************************************************* + * @fn NVIC_GetStatusIRQ + * + * @brief Get Interrupt Enable State + * + * @param IRQn - Interrupt Numbers + * + * @return 1 - Interrupt Pending Enable + * 0 - Interrupt Pending Disable + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE uint32_t NVIC_GetStatusIRQ(IRQn_Type IRQn) +{ + return((uint32_t) ((NVIC->ISR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); +} + +/********************************************************************* + * @fn NVIC_GetPendingIRQ + * + * @brief Get Interrupt Pending State + * + * @param IRQn - Interrupt Numbers + * + * @return 1 - Interrupt Pending Enable + * 0 - Interrupt Pending Disable + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t) ((NVIC->IPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); +} + +/********************************************************************* + * @fn NVIC_SetPendingIRQ + * + * @brief Set Interrupt Pending + * + * @param IRQn - Interrupt Numbers + * + * @return none + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->IPSR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); +} + +/********************************************************************* + * @fn NVIC_ClearPendingIRQ + * + * @brief Clear Interrupt Pending + * + * @param IRQn - Interrupt Numbers + * + * @return none + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->IPRR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); +} + +/********************************************************************* + * @fn NVIC_GetActive + * + * @brief Get Interrupt Active State + * + * @param IRQn - Interrupt Numbers + * + * @return 1 - Interrupt Active + * 0 - Interrupt No Active + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) +{ + return((uint32_t)((NVIC->IACTR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); +} + +/********************************************************************* + * @fn NVIC_SetPriority + * + * @brief Set Interrupt Priority + * + * @param IRQn - Interrupt Numbers + * interrupt nesting enable(CSR-0x804 bit1 = 1) + * priority - bit[7] - Preemption Priority + * bit[6:5] - Sub priority + * bit[4:0] - Reserve + * interrupt nesting disable(CSR-0x804 bit1 = 0) + * priority - bit[7:5] - Sub priority + * bit[4:0] - Reserve + * + * @return none + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint8_t priority) +{ + NVIC->IPRIOR[(uint32_t)(IRQn)] = priority; +} + +/********************************************************************* + * @fn __WFI + * + * @brief Wait for Interrupt + * + * @return none + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE void __WFI(void) +{ + NVIC->SCTLR &= ~(1<<3); // wfi + asm volatile ("wfi"); +} + +/********************************************************************* + * @fn _SEV + * + * @brief Set Event + * + * @return none + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE void _SEV(void) +{ + uint32_t t; + + t = NVIC->SCTLR; + NVIC->SCTLR |= (1<<3)|(1<<5); + NVIC->SCTLR = (NVIC->SCTLR & ~(1<<5)) | ( t & (1<<5)); +} + +/********************************************************************* + * @fn _WFE + * + * @brief Wait for Events + * + * @return none + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE void _WFE(void) +{ + NVIC->SCTLR |= (1<<3); + asm volatile ("wfi"); +} + +/********************************************************************* + * @fn __WFE + * + * @brief Wait for Events + * + * @return none + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE void __WFE(void) +{ + _SEV(); + _WFE(); + _WFE(); +} + +/********************************************************************* + * @fn SetVTFIRQ + * + * @brief Set VTF Interrupt + * + * @param addr - VTF interrupt service function base address. + * IRQn - Interrupt Numbers + * num - VTF Interrupt Numbers + * NewState - DISABLE or ENABLE + * + * @return none + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE void SetVTFIRQ(uint32_t addr, IRQn_Type IRQn, uint8_t num, FunctionalState NewState) +{ + if(num > 3) return ; + + if (NewState != DISABLE) + { + NVIC->VTFIDR[num] = IRQn; + NVIC->VTFADDR[num] = ((addr&0xFFFFFFFE)|0x1); + } + else + { + NVIC->VTFIDR[num] = IRQn; + NVIC->VTFADDR[num] = ((addr&0xFFFFFFFE)&(~0x1)); + } +} + +/********************************************************************* + * @fn NVIC_SystemReset + * + * @brief Initiate a system reset request + * + * @return none + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE void NVIC_SystemReset(void) +{ + NVIC->CFGR = NVIC_KEY3|(1<<7); +} + +/********************************************************************* + * @fn __AMOADD_W + * + * @brief Atomic Add with 32bit value + * Atomically ADD 32bit value with value in memory using amoadd.d. + * + * @param addr - Address pointer to data, address need to be 4byte aligned + * value - value to be ADDed + * + * @return return memory value + add value + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE int32_t __AMOADD_W(volatile int32_t *addr, int32_t value) +{ + int32_t result; + + __asm volatile ("amoadd.w %0, %2, %1" : \ + "=r"(result), "+A"(*addr) : "r"(value) : "memory"); + return *addr; +} + +/********************************************************************* + * @fn __AMOAND_W + * + * @brief Atomic And with 32bit value + * Atomically AND 32bit value with value in memory using amoand.d. + * + * @param addr - Address pointer to data, address need to be 4byte aligned + * value - value to be ANDed + * + * @return return memory value & and value + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE int32_t __AMOAND_W(volatile int32_t *addr, int32_t value) +{ + int32_t result; + + __asm volatile ("amoand.w %0, %2, %1" : \ + "=r"(result), "+A"(*addr) : "r"(value) : "memory"); + return *addr; +} + +/********************************************************************* + * @fn __AMOMAX_W + * + * @brief Atomic signed MAX with 32bit value + * Atomically signed max compare 32bit value with value in memory using amomax.d. + * + * @param addr - Address pointer to data, address need to be 4byte aligned + * value - value to be compared + * + * @return the bigger value + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE int32_t __AMOMAX_W(volatile int32_t *addr, int32_t value) +{ + int32_t result; + + __asm volatile ("amomax.w %0, %2, %1" : \ + "=r"(result), "+A"(*addr) : "r"(value) : "memory"); + return *addr; +} + +/********************************************************************* + * @fn __AMOMAXU_W + * + * @brief Atomic unsigned MAX with 32bit value + * Atomically unsigned max compare 32bit value with value in memory using amomaxu.d. + * + * @param addr - Address pointer to data, address need to be 4byte aligned + * value - value to be compared + * + * @return return the bigger value + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE uint32_t __AMOMAXU_W(volatile uint32_t *addr, uint32_t value) +{ + uint32_t result; + + __asm volatile ("amomaxu.w %0, %2, %1" : \ + "=r"(result), "+A"(*addr) : "r"(value) : "memory"); + return *addr; +} + +/********************************************************************* + * @fn __AMOMIN_W + * + * @brief Atomic signed MIN with 32bit value + * Atomically signed min compare 32bit value with value in memory using amomin.d. + * + * @param addr - Address pointer to data, address need to be 4byte aligned + * value - value to be compared + * + * @return the smaller value + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE int32_t __AMOMIN_W(volatile int32_t *addr, int32_t value) +{ + int32_t result; + + __asm volatile ("amomin.w %0, %2, %1" : \ + "=r"(result), "+A"(*addr) : "r"(value) : "memory"); + return *addr; +} + +/********************************************************************* + * @fn __AMOMINU_W + * + * @brief Atomic unsigned MIN with 32bit value + * Atomically unsigned min compare 32bit value with value in memory using amominu.d. + * + * @param addr - Address pointer to data, address need to be 4byte aligned + * value - value to be compared + * + * @return the smaller value + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE uint32_t __AMOMINU_W(volatile uint32_t *addr, uint32_t value) +{ + uint32_t result; + + __asm volatile ("amominu.w %0, %2, %1" : \ + "=r"(result), "+A"(*addr) : "r"(value) : "memory"); + return *addr; +} + +/********************************************************************* + * @fn __AMOOR_W + * + * @brief Atomic OR with 32bit value + * Atomically OR 32bit value with value in memory using amoor.d. + * + * @param addr - Address pointer to data, address need to be 4byte aligned + * value - value to be ORed + * + * @return return memory value | and value + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE int32_t __AMOOR_W(volatile int32_t *addr, int32_t value) +{ + int32_t result; + + __asm volatile ("amoor.w %0, %2, %1" : \ + "=r"(result), "+A"(*addr) : "r"(value) : "memory"); + return *addr; +} + +/********************************************************************* + * @fn __AMOSWAP_W + * + * @brief Atomically swap new 32bit value into memory using amoswap.d. + * + * @param addr - Address pointer to data, address need to be 4byte aligned + * newval - New value to be stored into the address + * + * @return return the original value in memory + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE uint32_t __AMOSWAP_W(volatile uint32_t *addr, uint32_t newval) +{ + uint32_t result; + + __asm volatile ("amoswap.w %0, %2, %1" : \ + "=r"(result), "+A"(*addr) : "r"(newval) : "memory"); + return result; +} + +/********************************************************************* + * @fn __AMOXOR_W + * + * @brief Atomic XOR with 32bit value + * Atomically XOR 32bit value with value in memory using amoxor.d. + * + * @param addr - Address pointer to data, address need to be 4byte aligned + * value - value to be XORed + * + * @return return memory value ^ and value + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE int32_t __AMOXOR_W(volatile int32_t *addr, int32_t value) +{ + int32_t result; + + __asm volatile ("amoxor.w %0, %2, %1" : \ + "=r"(result), "+A"(*addr) : "r"(value) : "memory"); + return *addr; +} + +/* Core_Exported_Functions */ +extern uint32_t __get_MSTATUS(void); +extern void __set_MSTATUS(uint32_t value); +extern uint32_t __get_MISA(void); +extern void __set_MISA(uint32_t value); +extern uint32_t __get_MTVEC(void); +extern void __set_MTVEC(uint32_t value); +extern uint32_t __get_MSCRATCH(void); +extern void __set_MSCRATCH(uint32_t value); +extern uint32_t __get_MEPC(void); +extern void __set_MEPC(uint32_t value); +extern uint32_t __get_MCAUSE(void); +extern void __set_MCAUSE(uint32_t value); +extern uint32_t __get_MTVAL(void); +extern void __set_MTVAL(uint32_t value); +extern uint32_t __get_MVENDORID(void); +extern uint32_t __get_MARCHID(void); +extern uint32_t __get_MIMPID(void); +extern uint32_t __get_MHARTID(void); +extern uint32_t __get_SP(void); + +#ifdef __cplusplus +} +#endif + +#endif + + + + + diff --git a/ZDBMS/BMS_MC/Debug/debug.c b/ZDBMS/BMS_MC/Debug/debug.c new file mode 100644 index 0000000..7643334 --- /dev/null +++ b/ZDBMS/BMS_MC/Debug/debug.c @@ -0,0 +1,192 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : debug.c + * Author : WCH + * Version : V1.0.0 + * Date : 2023/07/08 + * Description : This file contains all the functions prototypes for UART + * Printf , Delay functions. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#include "debug.h" + +static uint16_t p_us = 0; +static uint16_t p_ms = 0; +/********************************************************************* + * @fn Delay_Init + * + * @brief Initializes Delay Funcation. + * + * @return none + */ +void Delay_Init(void) +{ + p_us = SystemCoreClock / 8000; + p_ms = (uint16_t)p_us * 1; +} + +/********************************************************************* + * @fn Delay_Us + * + * @brief Microsecond Delay Time. + * + * @param n - Microsecond number. + * + * @return None + */ +void Delay_Us(uint32_t n) +{ + uint32_t i; + + SysTick->SR &= ~(1 << 0); + i = (uint32_t)(n * p_us)/1000; + + SysTick->CMP = i; + SysTick->CTLR |= (1 << 4); + SysTick->CTLR |= (1 << 5) | (1 << 0); + + while((SysTick->SR & (1 << 0)) != (1 << 0)); + SysTick->CTLR &= ~(1 << 0); +} + +/********************************************************************* + * @fn Delay_Ms + * + * @brief Millisecond Delay Time. + * + * @param n - Millisecond number. + * + * @return None + */ +void Delay_Ms(uint32_t n) +{ + uint32_t i; + + SysTick->SR &= ~(1 << 0); + i = (uint32_t)n * p_ms; + + SysTick->CMP = i; + SysTick->CTLR |= (1 << 4); + SysTick->CTLR |= (1 << 5) | (1 << 0); + + while((SysTick->SR & (1 << 0)) != (1 << 0)); + SysTick->CTLR &= ~(1 << 0); +} + +/********************************************************************* + * @fn USART_Printf_Init + * + * @brief Initializes the USARTx peripheral. + * + * @param baudrate - USART communication baud rate. + * + * @return None + */ +void USART_Printf_Init(uint32_t baudrate) +{ + GPIO_InitTypeDef GPIO_InitStructure; + USART_InitTypeDef USART_InitStructure; + +#if(DEBUG == DEBUG_UART1) + RCC_PB2PeriphClockCmd(RCC_PB2Periph_USART1 | RCC_PB2Periph_GPIOA, ENABLE); + + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_9; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP; + GPIO_Init(GPIOA, &GPIO_InitStructure); + +#elif(DEBUG == DEBUG_UART2) + RCC_PB1PeriphClockCmd(RCC_PB1Periph_USART2, ENABLE); + RCC_PB2PeriphClockCmd(RCC_PB2Periph_GPIOA, ENABLE); + + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP; + GPIO_Init(GPIOA, &GPIO_InitStructure); + +#elif(DEBUG == DEBUG_UART3) + RCC_PB1PeriphClockCmd(RCC_PB1Periph_USART3, ENABLE); + RCC_PB2PeriphClockCmd(RCC_PB2Periph_GPIOB, ENABLE); + + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_10; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP; + GPIO_Init(GPIOB, &GPIO_InitStructure); + +#endif + + USART_InitStructure.USART_BaudRate = baudrate; + USART_InitStructure.USART_WordLength = USART_WordLength_8b; + USART_InitStructure.USART_StopBits = USART_StopBits_1; + USART_InitStructure.USART_Parity = USART_Parity_No; + USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None; + USART_InitStructure.USART_Mode = USART_Mode_Tx; + +#if(DEBUG == DEBUG_UART1) + USART_Init(USART1, &USART_InitStructure); + USART_Cmd(USART1, ENABLE); + +#elif(DEBUG == DEBUG_UART2) + USART_Init(USART2, &USART_InitStructure); + USART_Cmd(USART2, ENABLE); + +#elif(DEBUG == DEBUG_UART3) + USART_Init(USART3, &USART_InitStructure); + USART_Cmd(USART3, ENABLE); + +#endif +} + +/********************************************************************* + * @fn _write + * + * @brief Support Printf Function + * + * @param *buf - UART send Data. + * size - Data length + * + * @return size: Data length + */ +__attribute__((used)) +int _write(int fd, char *buf, int size) +{ + int i; + + for(i = 0; i < size; i++){ +#if(DEBUG == DEBUG_UART1) + while(USART_GetFlagStatus(USART1, USART_FLAG_TC) == RESET); + USART_SendData(USART1, *buf++); +#elif(DEBUG == DEBUG_UART2) + while(USART_GetFlagStatus(USART2, USART_FLAG_TC) == RESET); + USART_SendData(USART2, *buf++); +#elif(DEBUG == DEBUG_UART3) + while(USART_GetFlagStatus(USART3, USART_FLAG_TC) == RESET); + USART_SendData(USART3, *buf++); +#endif + } + + return size; +} + +/********************************************************************* + * @fn _sbrk + * + * @brief Change the spatial position of data segment. + * + * @return size: Data length + */ +__attribute__((used)) +void *_sbrk(ptrdiff_t incr) +{ + extern char _end[]; + extern char _heap_end[]; + static char *curbrk = _end; + + if ((curbrk + incr < _end) || (curbrk + incr > _heap_end)) + return NULL - 1; + + curbrk += incr; + return curbrk - incr; +} diff --git a/ZDBMS/BMS_MC/Debug/debug.h b/ZDBMS/BMS_MC/Debug/debug.h new file mode 100644 index 0000000..db1175d --- /dev/null +++ b/ZDBMS/BMS_MC/Debug/debug.h @@ -0,0 +1,54 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : debug.h + * Author : WCH + * Version : V1.0.0 + * Date : 2023/11/06 + * Description : This file contains all the functions prototypes for UART + * Printf , Delay functions. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#ifndef __DEBUG_H +#define __DEBUG_H + +#include "stdio.h" +#include "ch32l103.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* UART Printf Definition */ +#define DEBUG_UART1 1 +#define DEBUG_UART2 2 +#define DEBUG_UART3 3 + +/* DEBUG UATR Definition */ +#ifndef DEBUG +#define DEBUG DEBUG_UART1 +#endif + +extern uint32_t OPA_Trim; +extern uint16_t ADC_Trim; +extern uint32_t TS_Val; +extern uint32_t CHIPID; +extern uint16_t USBPD_CFG; + +void Delay_Init(void); +void Delay_Us(uint32_t n); +void Delay_Ms(uint32_t n); +void USART_Printf_Init(uint32_t baudrate); + +#if(DEBUG) + #define PRINT(format, ...) printf(format, ##__VA_ARGS__) +#else + #define PRINT(X...) +#endif + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/ZDBMS/BMS_MC/Ld/Link.ld b/ZDBMS/BMS_MC/Ld/Link.ld new file mode 100644 index 0000000..8825ecf --- /dev/null +++ b/ZDBMS/BMS_MC/Ld/Link.ld @@ -0,0 +1 @@ +ENTRY( _start ) __stack_size = 2048; PROVIDE( _stack_size = __stack_size ); MEMORY { FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 64K RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 20K } SECTIONS { .init : { _sinit = .; . = ALIGN(4); KEEP(*(SORT_NONE(.init))) . = ALIGN(4); _einit = .; } >FLASH AT>FLASH .vector : { *(.vector); . = ALIGN(64); } >FLASH AT>FLASH .text : { . = ALIGN(4); *(.text) *(.text.*) *(.rodata) *(.rodata*) *(.gnu.linkonce.t.*) . = ALIGN(4); } >FLASH AT>FLASH .fini : { KEEP(*(SORT_NONE(.fini))) . = ALIGN(4); } >FLASH AT>FLASH PROVIDE( _etext = . ); PROVIDE( _eitcm = . ); .preinit_array : { PROVIDE_HIDDEN (__preinit_array_start = .); KEEP (*(.preinit_array)) PROVIDE_HIDDEN (__preinit_array_end = .); } >FLASH AT>FLASH .init_array : { PROVIDE_HIDDEN (__init_array_start = .); KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors)) PROVIDE_HIDDEN (__init_array_end = .); } >FLASH AT>FLASH .fini_array : { PROVIDE_HIDDEN (__fini_array_start = .); KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*))) KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors)) PROVIDE_HIDDEN (__fini_array_end = .); } >FLASH AT>FLASH .ctors : { /* gcc uses crtbegin.o to find the start of the constructors, so we make sure it is first. Because this is a wildcard, it doesn't matter if the user does not actually link against crtbegin.o; the linker won't look for a file to match a wildcard. The wildcard also means that it doesn't matter which directory crtbegin.o is in. */ KEEP (*crtbegin.o(.ctors)) KEEP (*crtbegin?.o(.ctors)) /* We don't want to include the .ctor section from the crtend.o file until after the sorted ctors. The .ctor section from the crtend file contains the end of ctors marker and it must be last */ KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors)) KEEP (*(SORT(.ctors.*))) KEEP (*(.ctors)) } >FLASH AT>FLASH .dtors : { KEEP (*crtbegin.o(.dtors)) KEEP (*crtbegin?.o(.dtors)) KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors)) KEEP (*(SORT(.dtors.*))) KEEP (*(.dtors)) } >FLASH AT>FLASH .dalign : { . = ALIGN(4); PROVIDE(_data_vma = .); } >RAM AT>FLASH .dlalign : { . = ALIGN(4); PROVIDE(_data_lma = .); } >FLASH AT>FLASH .data : { *(.gnu.linkonce.r.*) *(.data .data.*) *(.gnu.linkonce.d.*) . = ALIGN(8); PROVIDE( __global_pointer$ = . + 0x800 ); *(.sdata .sdata.*) *(.sdata2.*) *(.gnu.linkonce.s.*) . = ALIGN(8); *(.srodata.cst16) *(.srodata.cst8) *(.srodata.cst4) *(.srodata.cst2) *(.srodata .srodata.*) . = ALIGN(4); PROVIDE( _edata = .); } >RAM AT>FLASH .bss : { . = ALIGN(4); PROVIDE( _sbss = .); *(.sbss*) *(.gnu.linkonce.sb.*) *(.bss*) *(.gnu.linkonce.b.*) *(COMMON*) . = ALIGN(4); PROVIDE( _ebss = .); } >RAM AT>FLASH PROVIDE( _end = _ebss); PROVIDE( end = . ); .stack ORIGIN(RAM) + LENGTH(RAM) - __stack_size : { PROVIDE( _heap_end = . ); . = ALIGN(4); PROVIDE(_susrstack = . ); . = . + __stack_size; PROVIDE( _eusrstack = .); } >RAM } \ No newline at end of file diff --git a/ZDBMS/BMS_MC/Peripheral/inc/ch32l103.h b/ZDBMS/BMS_MC/Peripheral/inc/ch32l103.h new file mode 100644 index 0000000..11e21fc --- /dev/null +++ b/ZDBMS/BMS_MC/Peripheral/inc/ch32l103.h @@ -0,0 +1,4759 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32l103.h + * Author : WCH + * Version : V1.0.1 + * Date : 2025/01/08 + * Description : CH32L103 Device Peripheral Access Layer Header File. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#ifndef __CH32L103_H +#define __CH32L103_H + +#ifdef __cplusplus +extern "C" { +#endif + +#ifndef HSE_VALUE +#define HSE_VALUE ((uint32_t)8000000) /* Value of the External oscillator in Hz */ +#endif + +/* In the following line adjust the External High Speed oscillator (HSE) Startup Timeout value */ +#define HSE_STARTUP_TIMEOUT ((uint16_t)0x1000) /* Time out for HSE start up */ + +#define HSI_VALUE ((uint32_t)8000000) /* Value of the Internal oscillator in Hz */ + +#define HSI_LP_VALUE ((uint32_t)1000000) /* Value of the Internal oscillator in Hz for low power mode */ + +/* Standard Peripheral Library version number */ +#define __CH32L103_STDPERIPH_VERSION_MAIN (0x01) /* [15:8] main version */ +#define __CH32L103_STDPERIPH_VERSION_SUB (0x04) /* [7:0] sub version */ +#define __CH32L103_STDPERIPH_VERSION ((__CH32L103_STDPERIPH_VERSION_MAIN << 8)\ + |(__CH32L103_STDPERIPH_VERSION_SUB << 0)) + +/* Interrupt Number Definition, according to the selected device */ +typedef enum IRQn +{ + /****** RISC-V Processor Exceptions Numbers *******************************************************/ + NonMaskableInt_IRQn = 2, /* Non Maskable Interrupt */ + EXC_IRQn = 3, /* Exception Interrupt */ + Ecall_M_Mode_IRQn = 5, /* Ecall M Mode Interrupt */ + Ecall_U_Mode_IRQn = 8, /* Ecall U Mode Interrupt */ + Break_Point_IRQn = 9, /* Break Point Interrupt */ + SysTick_IRQn = 12, /* System timer Interrupt */ + Software_IRQn = 14, /* Software Interrupt */ + + /****** RISC-V specific Interrupt Numbers *********************************************************/ + WWDG_IRQn = 16, /* Window WatchDog Interrupt */ + PVD_IRQn = 17, /* PVD through EXTI Line detection Interrupt */ + TAMPER_IRQn = 18, /* Tamper Interrupt */ + RTC_IRQn = 19, /* RTC global Interrupt */ + FLASH_IRQn = 20, /* FLASH global Interrupt */ + RCC_IRQn = 21, /* RCC global Interrupt */ + EXTI0_IRQn = 22, /* EXTI Line0 Interrupt */ + EXTI1_IRQn = 23, /* EXTI Line1 Interrupt */ + EXTI2_IRQn = 24, /* EXTI Line2 Interrupt */ + EXTI3_IRQn = 25, /* EXTI Line3 Interrupt */ + EXTI4_IRQn = 26, /* EXTI Line4 Interrupt */ + DMA1_Channel1_IRQn = 27, /* DMA1 Channel 1 global Interrupt */ + DMA1_Channel2_IRQn = 28, /* DMA1 Channel 2 global Interrupt */ + DMA1_Channel3_IRQn = 29, /* DMA1 Channel 3 global Interrupt */ + DMA1_Channel4_IRQn = 30, /* DMA1 Channel 4 global Interrupt */ + DMA1_Channel5_IRQn = 31, /* DMA1 Channel 5 global Interrupt */ + DMA1_Channel6_IRQn = 32, /* DMA1 Channel 6 global Interrupt */ + DMA1_Channel7_IRQn = 33, /* DMA1 Channel 7 global Interrupt */ + ADC_IRQn = 34, /* ADC1 global Interrupt */ + USB_HP_CAN1_TX_IRQn = 35, /* USB Device High Priority or CAN1 TX Interrupts */ + USB_LP_CAN1_RX0_IRQn = 36, /* USB Device Low Priority or CAN1 RX0 Interrupts */ + CAN1_RX1_IRQn = 37, /* CAN1 RX1 Interrupt */ + CAN1_SCE_IRQn = 38, /* CAN1 SCE Interrupt */ + EXTI9_5_IRQn = 39, /* External Line[9:5] Interrupts */ + TIM1_BRK_IRQn = 40, /* TIM1 Break Interrupt */ + TIM1_UP_IRQn = 41, /* TIM1 Update Interrupt */ + TIM1_TRG_COM_IRQn = 42, /* TIM1 Trigger and Commutation Interrupt */ + TIM1_CC_IRQn = 43, /* TIM1 Capture Compare Interrupt */ + TIM2_IRQn = 44, /* TIM2 global Interrupt */ + TIM3_IRQn = 45, /* TIM3 global Interrupt */ + TIM4_IRQn = 46, /* TIM4 global Interrupt */ + I2C1_EV_IRQn = 47, /* I2C1 Event Interrupt */ + I2C1_ER_IRQn = 48, /* I2C1 Error Interrupt */ + I2C2_EV_IRQn = 49, /* I2C2 Event Interrupt */ + I2C2_ER_IRQn = 50, /* I2C2 Error Interrupt */ + SPI1_IRQn = 51, /* SPI1 global Interrupt */ + SPI2_IRQn = 52, /* SPI2 global Interrupt */ + USART1_IRQn = 53, /* USART1 global Interrupt */ + USART2_IRQn = 54, /* USART2 global Interrupt */ + USART3_IRQn = 55, /* USART3 global Interrupt */ + EXTI15_10_IRQn = 56, /* External Line[15:10] Interrupts */ + RTCAlarm_IRQn = 57, /* RTC Alarm through EXTI Line Interrupt */ + LPTIMWakeUp_IRQn = 58, /* LPTIM WakeUp Interrupt */ + USBFS_IRQn = 59, /* USBFS global Interrupt */ + USBFSWakeUp_IRQn = 60, /* USBFS WakeUp Interrupt */ + USART4_IRQn = 61, /* USART4 global Interrupt */ + DMA1_Channel8_IRQn = 62, /* DMA1 Channel 8 global Interrupt */ + LPTIM_IRQn = 63, /* LPTIM global Interrupt */ + OPA_IRQn = 64, /* OPA global Interrupt */ + USBPD_IRQn = 65, /* USBPD global Interrupt */ + + USBPDWakeUp_IRQn = 67, /* USBPD WakeUp Interrupt */ + CMPWakeUp_IRQn = 68, /* CMP WakeUp Interrupt */ + +} IRQn_Type; + +#define HardFault_IRQn EXC_IRQn +#define ADC1_2_IRQn ADC_IRQn +#define SysTicK_IRQn SysTick_IRQn + +#include +#include "core_riscv.h" +#include "system_ch32l103.h" + +#define HSI_Value HSI_VALUE +#define HSE_Value HSE_VALUE +#define HSEStartUp_TimeOut HSE_STARTUP_TIMEOUT + +/* Analog to Digital Converter */ +typedef struct +{ + __IO uint32_t STATR; + __IO uint32_t CTLR1; + __IO uint32_t CTLR2; + __IO uint32_t SAMPTR1; + __IO uint32_t SAMPTR2; + __IO uint32_t IOFR1; + __IO uint32_t IOFR2; + __IO uint32_t IOFR3; + __IO uint32_t IOFR4; + __IO uint32_t WDHTR; + __IO uint32_t WDLTR; + __IO uint32_t RSQR1; + __IO uint32_t RSQR2; + __IO uint32_t RSQR3; + __IO uint32_t ISQR; + __IO uint32_t IDATAR1; + __IO uint32_t IDATAR2; + __IO uint32_t IDATAR3; + __IO uint32_t IDATAR4; + __IO uint32_t RDATAR; + __IO uint32_t CFG; +} ADC_TypeDef; + +/* Backup Registers */ +typedef struct +{ + uint32_t RESERVED0; + __IO uint16_t DATAR1; + uint16_t RESERVED1; + __IO uint16_t DATAR2; + uint16_t RESERVED2; + __IO uint16_t DATAR3; + uint16_t RESERVED3; + __IO uint16_t DATAR4; + uint16_t RESERVED4; + __IO uint16_t DATAR5; + uint16_t RESERVED5; + __IO uint16_t DATAR6; + uint16_t RESERVED6; + __IO uint16_t DATAR7; + uint16_t RESERVED7; + __IO uint16_t DATAR8; + uint16_t RESERVED8; + __IO uint16_t DATAR9; + uint16_t RESERVED9; + __IO uint16_t DATAR10; + uint16_t RESERVED10; + __IO uint16_t OCTLR; + uint16_t RESERVED11; + __IO uint16_t TPCTLR; + uint16_t RESERVED12; + __IO uint16_t TPCSR; + uint16_t RESERVED13; +} BKP_TypeDef; + +/* Controller Area Network TxMailBox */ +typedef struct +{ + __IO uint32_t TXMIR; + __IO uint32_t TXMDTR; + __IO uint32_t TXMDLR; + __IO uint32_t TXMDHR; +} CAN_TxMailBox_TypeDef; + +/* Controller Area Network FIFOMailBox */ +typedef struct +{ + __IO uint32_t RXMIR; + __IO uint32_t RXMDTR; + __IO uint32_t RXMDLR; + __IO uint32_t RXMDHR; +} CAN_FIFOMailBox_TypeDef; + +/* Controller Area Network FilterRegister */ +typedef struct +{ + __IO uint32_t FR1; + __IO uint32_t FR2; +} CAN_FilterRegister_TypeDef; + +/* Controller Area Network */ +typedef struct +{ + __IO uint32_t CTLR; + __IO uint32_t STATR; + __IO uint32_t TSTATR; + __IO uint32_t RFIFO0; + __IO uint32_t RFIFO1; + __IO uint32_t INTENR; + __IO uint32_t ERRSR; + __IO uint32_t BTIMR; + __IO uint32_t TTCTLR; + __IO uint32_t TTCNT; + __IO uint32_t TERR_CNT; + __IO uint32_t CANFD_CR; + __IO uint32_t CANFD_BTR; + __IO uint32_t CANFD_TDCT; + __IO uint32_t CANFD_PSR; + __IO uint32_t CANFD_DMA_T[3]; + __IO uint32_t CANFD_DMA_R[2]; + uint32_t RESERVED0[76]; + CAN_TxMailBox_TypeDef sTxMailBox[3]; + CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; + uint32_t RESERVED1[12]; + __IO uint32_t FCTLR; + __IO uint32_t FMCFGR; + uint32_t RESERVED2; + __IO uint32_t FSCFGR; + uint32_t RESERVED3; + __IO uint32_t FAFIFOR; + uint32_t RESERVED4; + __IO uint32_t FWR; + uint32_t RESERVED5[8]; + CAN_FilterRegister_TypeDef sFilterRegister[14]; +} CAN_TypeDef; + +/* CRC Calculation Unit */ +typedef struct +{ + __IO uint32_t DATAR; + __IO uint8_t IDATAR; + uint8_t RESERVED0; + uint16_t RESERVED1; + __IO uint32_t CTLR; +} CRC_TypeDef; + +/* DMA Channel Controller */ +typedef struct +{ + __IO uint32_t CFGR; + __IO uint32_t CNTR; + __IO uint32_t PADDR; + __IO uint32_t MADDR; +} DMA_Channel_TypeDef; + +/* DMA Controller */ +typedef struct +{ + __IO uint32_t INTFR; + __IO uint32_t INTFCR; +} DMA_TypeDef; + +/* External Interrupt/Event Controller */ +typedef struct +{ + __IO uint32_t INTENR; + __IO uint32_t EVENR; + __IO uint32_t RTENR; + __IO uint32_t FTENR; + __IO uint32_t SWIEVR; + __IO uint32_t INTFR; +} EXTI_TypeDef; + +/* FLASH Registers */ +typedef struct +{ + __IO uint32_t ACTLR; + __IO uint32_t KEYR; + __IO uint32_t OBKEYR; + __IO uint32_t STATR; + __IO uint32_t CTLR; + __IO uint32_t ADDR; + __IO uint32_t RESERVED; + __IO uint32_t OBR; + __IO uint32_t WPR; + __IO uint32_t MODEKEYR; +} FLASH_TypeDef; + +/* Option Bytes Registers */ +typedef struct +{ + __IO uint16_t RDPR; + __IO uint16_t USER; + __IO uint16_t Data0; + __IO uint16_t Data1; + __IO uint16_t WRPR0; + __IO uint16_t WRPR1; + __IO uint16_t WRPR2; + __IO uint16_t WRPR3; +} OB_TypeDef; + +/* General Purpose I/O */ +typedef struct +{ + __IO uint32_t CFGLR; + __IO uint32_t CFGHR; + __IO uint32_t INDR; + __IO uint32_t OUTDR; + __IO uint32_t BSHR; + __IO uint32_t BCR; + __IO uint32_t LCKR; +} GPIO_TypeDef; + +/* Alternate Function I/O */ +typedef struct +{ + __IO uint32_t ECR; + __IO uint32_t PCFR1; + __IO uint32_t EXTICR[4]; + __IO uint32_t CR; + __IO uint32_t PCFR2; +} AFIO_TypeDef; + +/* Inter Integrated Circuit Interface */ +typedef struct +{ + __IO uint16_t CTLR1; + uint16_t RESERVED0; + __IO uint16_t CTLR2; + uint16_t RESERVED1; + __IO uint16_t OADDR1; + uint16_t RESERVED2; + __IO uint16_t OADDR2; + uint16_t RESERVED3; + __IO uint16_t DATAR; + uint16_t RESERVED4; + __IO uint16_t STAR1; + uint16_t RESERVED5; + __IO uint16_t STAR2; + uint16_t RESERVED6; + __IO uint16_t CKCFGR; + uint16_t RESERVED7; + __IO uint16_t RTR; + uint16_t RESERVED8; +} I2C_TypeDef; + +/* Independent WatchDog */ +typedef struct +{ + __IO uint32_t CTLR; + __IO uint32_t PSCR; + __IO uint32_t RLDR; + __IO uint32_t STATR; +} IWDG_TypeDef; + +/* Power Control */ +typedef struct +{ + __IO uint32_t CTLR; + __IO uint32_t CSR; +} PWR_TypeDef; + +/* Reset and Clock Control */ +typedef struct +{ + __IO uint32_t CTLR; + __IO uint32_t CFGR0; + __IO uint32_t INTR; + __IO uint32_t PB2PRSTR; + __IO uint32_t PB1PRSTR; + __IO uint32_t HBPCENR; + __IO uint32_t PB2PCENR; + __IO uint32_t PB1PCENR; + __IO uint32_t BDCTLR; + __IO uint32_t RSTSCKR; + __IO uint32_t HBRSTR; +} RCC_TypeDef; + +/* Real-Time Clock */ +typedef struct +{ + __IO uint16_t CTLRH; + uint16_t RESERVED0; + __IO uint16_t CTLRL; + uint16_t RESERVED1; + __IO uint16_t PSCRH; + uint16_t RESERVED2; + __IO uint16_t PSCRL; + uint16_t RESERVED3; + __IO uint16_t DIVH; + uint16_t RESERVED4; + __IO uint16_t DIVL; + uint16_t RESERVED5; + __IO uint16_t CNTH; + uint16_t RESERVED6; + __IO uint16_t CNTL; + uint16_t RESERVED7; + __IO uint16_t ALRMH; + uint16_t RESERVED8; + __IO uint16_t ALRML; + uint16_t RESERVED9; +} RTC_TypeDef; + +/* Serial Peripheral Interface */ +typedef struct +{ + __IO uint16_t CTLR1; + uint16_t RESERVED0; + __IO uint16_t CTLR2; + uint16_t RESERVED1; + __IO uint16_t STATR; + uint16_t RESERVED2; + __IO uint16_t DATAR; + uint16_t RESERVED3; + __IO uint16_t CRCR; + uint16_t RESERVED4; + __IO uint16_t RCRCR; + uint16_t RESERVED5; + __IO uint16_t TCRCR; + uint16_t RESERVED6; + uint32_t RESERVED7; + uint32_t RESERVED8; + __IO uint16_t HSCR; + uint16_t RESERVED9; +} SPI_TypeDef; + +/* TIM */ +typedef struct +{ + __IO uint16_t CTLR1; + uint16_t RESERVED0; + __IO uint16_t CTLR2; + uint16_t RESERVED1; + __IO uint16_t SMCFGR; + uint16_t RESERVED2; + __IO uint16_t DMAINTENR; + uint16_t RESERVED3; + __IO uint16_t INTFR; + uint16_t RESERVED4; + __IO uint16_t SWEVGR; + uint16_t RESERVED5; + __IO uint16_t CHCTLR1; + uint16_t RESERVED6; + __IO uint16_t CHCTLR2; + uint16_t RESERVED7; + __IO uint16_t CCER; + uint16_t RESERVED8; + union + { + __IO uint32_t CNT_TIM4; + struct + { + __IO uint16_t CNT; + uint16_t RESERVED9; + }; + }; + __IO uint16_t PSC; + uint16_t RESERVED10; + union + { + __IO uint32_t ATRLR_TIM4; + struct + { + __IO uint16_t ATRLR; + uint16_t RESERVED11; + }; + }; + __IO uint16_t RPTCR; + uint16_t RESERVED12; + union + { + __IO uint32_t CH1CVR_TIM4; + + __IO uint32_t CH1CVR; + }; + union + { + __IO uint32_t CH2CVR_TIM4; + + __IO uint32_t CH2CVR; + }; + union + { + __IO uint32_t CH3CVR_TIM4; + + __IO uint32_t CH3CVR; + }; + union + { + __IO uint32_t CH4CVR_TIM4; + + __IO uint32_t CH4CVR; + }; + __IO uint16_t BDTR; + uint16_t RESERVED13; + __IO uint16_t DMACFGR; + uint16_t RESERVED14; + __IO uint32_t DMAADR; +} TIM_TypeDef; + +/* Universal Synchronous Asynchronous Receiver Transmitter */ +typedef struct +{ + __IO uint16_t STATR; + uint16_t RESERVED0; + __IO uint16_t DATAR; + uint16_t RESERVED1; + __IO uint16_t BRR; + uint16_t RESERVED2; + __IO uint16_t CTLR1; + uint16_t RESERVED3; + __IO uint16_t CTLR2; + uint16_t RESERVED4; + __IO uint16_t CTLR3; + uint16_t RESERVED5; + __IO uint16_t GPR; + uint16_t RESERVED6; +} USART_TypeDef; + +/* Window WatchDog */ +typedef struct +{ + __IO uint32_t CTLR; + __IO uint32_t CFGR; + __IO uint32_t STATR; +} WWDG_TypeDef; + +/* Enhanced Registers */ +typedef struct +{ + __IO uint32_t EXTEN_CTR; +} EXTEN_TypeDef; + +/* OPA Registers */ +typedef struct +{ + __IO uint16_t CFGR1; + __IO uint16_t CFGR2; + __IO uint32_t CTLR1; + __IO uint32_t CTLR2; + __IO uint32_t RESERVED0; + __IO uint32_t RESERVED1; + __IO uint32_t OPCMKEY; +} OPA_TypeDef; + +/* LPTIM Registers */ +typedef struct +{ + __IO uint32_t ISR; + __IO uint32_t ICR; + __IO uint32_t IER; + __IO uint32_t CFGR; + __IO uint32_t CR; + __IO uint16_t CMP; + uint16_t RESERVED0; + __IO uint16_t ARR; + uint16_t RESERVED1; + __IO uint16_t CNT; + uint16_t RESERVED2; +} LPTIM_TypeDef; + +/* PD Registers */ +typedef struct +{ + union + { + __IO uint32_t USBPD_CONFIG; + struct + { + __IO uint16_t CONFIG; + __IO uint16_t BMC_CLK_CNT; + }; + }; + union + { + __IO uint32_t USBPD_CONTROL; + struct + { + union + { + __IO uint16_t R16_CONTROL; + struct + { + __IO uint8_t CONTROL; + __IO uint8_t TX_SEL; + }; + }; + __IO uint16_t BMC_TX_SZ; + }; + }; + union + { + __IO uint32_t USBPD_STATUS; + struct + { + union + { + __IO uint16_t R16_STATUS; + struct + { + __IO uint8_t DATA_BUF; + __IO uint8_t STATUS; + }; + }; + __IO uint16_t BMC_BYTE_CNT; + }; + }; + union + { + __IO uint32_t USBPD_PORT; + struct + { + __IO uint16_t PORT_CC1; + __IO uint16_t PORT_CC2; + }; + }; + union + { + __IO uint32_t USBPD_DMA; + struct + { + __IO uint16_t DMA; + __IO uint16_t RESERVED; + }; + }; +} USBPD_TypeDef; + +/* USBFS Registers */ +typedef struct +{ + __IO uint8_t BASE_CTRL; + __IO uint8_t UDEV_CTRL; + __IO uint8_t INT_EN; + __IO uint8_t DEV_ADDR; + __IO uint8_t Reserve0; + __IO uint8_t MIS_ST; + __IO uint8_t INT_FG; + __IO uint8_t INT_ST; + __IO uint32_t RX_LEN; + __IO uint8_t UEP4_1_MOD; + __IO uint8_t UEP2_3_MOD; + __IO uint8_t UEP5_6_MOD; + __IO uint8_t UEP7_MOD; + __IO uint32_t UEP0_DMA; + __IO uint32_t UEP1_DMA; + __IO uint32_t UEP2_DMA; + __IO uint32_t UEP3_DMA; + __IO uint32_t UEP4_DMA; + __IO uint32_t UEP5_DMA; + __IO uint32_t UEP6_DMA; + __IO uint32_t UEP7_DMA; + __IO uint16_t UEP0_TX_LEN; + union{ + __IO uint16_t UEP0_CTRL; + struct{ + __IO uint8_t UEP0_TX_CTRL; + __IO uint8_t UEP0_RX_CTRL; + }; + }; + __IO uint16_t UEP1_TX_LEN; + union{ + __IO uint16_t UEP1_CTRL; + struct{ + __IO uint8_t UEP1_TX_CTRL; + __IO uint8_t UEP1_RX_CTRL; + }; + }; + __IO uint16_t UEP2_TX_LEN; + union{ + __IO uint16_t UEP2_CTRL; + struct{ + __IO uint8_t UEP2_TX_CTRL; + __IO uint8_t UEP2_RX_CTRL; + }; + }; + __IO uint16_t UEP3_TX_LEN; + union{ + __IO uint16_t UEP3_CTRL; + struct{ + __IO uint8_t UEP3_TX_CTRL; + __IO uint8_t UEP3_RX_CTRL; + }; + }; + __IO uint16_t UEP4_TX_LEN; + union{ + __IO uint16_t UEP4_CTRL; + struct{ + __IO uint8_t UEP4_TX_CTRL; + __IO uint8_t UEP4_RX_CTRL; + }; + }; + __IO uint16_t UEP5_TX_LEN; + union{ + __IO uint16_t UEP5_CTRL; + struct{ + __IO uint8_t UEP5_TX_CTRL; + __IO uint8_t UEP5_RX_CTRL; + }; + }; + __IO uint16_t UEP6_TX_LEN; + union{ + __IO uint16_t UEP6_CTRL; + struct{ + __IO uint8_t UEP6_TX_CTRL; + __IO uint8_t UEP6_RX_CTRL; + }; + }; + __IO uint16_t UEP7_TX_LEN; + union{ + __IO uint16_t UEP7_CTRL; + struct{ + __IO uint8_t UEP7_TX_CTRL; + __IO uint8_t UEP7_RX_CTRL; + }; + }; + __IO uint32_t Reserve1; + __IO uint32_t OTG_CR; + __IO uint32_t OTG_SR; +} USBFSD_TypeDef; + +typedef struct +{ + __IO uint8_t BASE_CTRL; + __IO uint8_t HOST_CTRL; + __IO uint8_t INT_EN; + __IO uint8_t DEV_ADDR; + __IO uint8_t Reserve0; + __IO uint8_t MIS_ST; + __IO uint8_t INT_FG; + __IO uint8_t INT_ST; + __IO uint16_t RX_LEN; + __IO uint16_t Reserve1; + __IO uint8_t Reserve2; + __IO uint8_t HOST_EP_MOD; + __IO uint16_t Reserve3; + __IO uint32_t Reserve4; + __IO uint32_t Reserve5; + __IO uint32_t HOST_RX_DMA; + __IO uint32_t HOST_TX_DMA; + __IO uint32_t Reserve6; + __IO uint32_t Reserve7; + __IO uint32_t Reserve8; + __IO uint32_t Reserve9; + __IO uint32_t Reserve10; + __IO uint16_t Reserve11; + __IO uint16_t HOST_SETUP; + __IO uint8_t HOST_EP_PID; + __IO uint8_t Reserve12; + __IO uint8_t Reserve13; + __IO uint8_t HOST_RX_CTRL; + __IO uint16_t HOST_TX_LEN; + __IO uint8_t HOST_TX_CTRL; + __IO uint8_t Reserve14; + __IO uint32_t Reserve15; + __IO uint32_t Reserve16; + __IO uint32_t Reserve17; + __IO uint32_t Reserve18; + __IO uint32_t Reserve19; + __IO uint32_t OTG_CR; + __IO uint32_t OTG_SR; +} USBFSH_TypeDef; + +/* Peripheral memory map */ +#define FLASH_BASE ((uint32_t)0x08000000) /* FLASH base address in the alias region */ +#define SRAM_BASE ((uint32_t)0x20000000) /* SRAM base address in the alias region */ +#define PERIPH_BASE ((uint32_t)0x40000000) /* Peripheral base address in the alias region */ + +#define PB1PERIPH_BASE (PERIPH_BASE) +#define PB2PERIPH_BASE (PERIPH_BASE + 0x10000) +#define HBPERIPH_BASE (PERIPH_BASE + 0x20000) + +#define TIM2_BASE (PB1PERIPH_BASE + 0x0000) +#define TIM3_BASE (PB1PERIPH_BASE + 0x0400) +#define TIM4_BASE (PB1PERIPH_BASE + 0x0800) +#define RTC_BASE (PB1PERIPH_BASE + 0x2800) +#define WWDG_BASE (PB1PERIPH_BASE + 0x2C00) +#define IWDG_BASE (PB1PERIPH_BASE + 0x3000) +#define SPI2_BASE (PB1PERIPH_BASE + 0x3800) +#define USART2_BASE (PB1PERIPH_BASE + 0x4400) +#define USART3_BASE (PB1PERIPH_BASE + 0x4800) +#define USART4_BASE (PB1PERIPH_BASE + 0x4C00) +#define I2C1_BASE (PB1PERIPH_BASE + 0x5400) +#define I2C2_BASE (PB1PERIPH_BASE + 0x5800) +#define CAN1_BASE (PB1PERIPH_BASE + 0x6400) +#define BKP_BASE (PB1PERIPH_BASE + 0x6C00) +#define PWR_BASE (PB1PERIPH_BASE + 0x7000) +#define LPTIM_BASE (PB1PERIPH_BASE + 0x7C00) + +#define AFIO_BASE (PB2PERIPH_BASE + 0x0000) +#define EXTI_BASE (PB2PERIPH_BASE + 0x0400) +#define GPIOA_BASE (PB2PERIPH_BASE + 0x0800) +#define GPIOB_BASE (PB2PERIPH_BASE + 0x0C00) +#define GPIOC_BASE (PB2PERIPH_BASE + 0x1000) +#define GPIOD_BASE (PB2PERIPH_BASE + 0x1400) +#define ADC1_BASE (PB2PERIPH_BASE + 0x2400) +#define TIM1_BASE (PB2PERIPH_BASE + 0x2C00) +#define SPI1_BASE (PB2PERIPH_BASE + 0x3000) +#define USART1_BASE (PB2PERIPH_BASE + 0x3800) + +#define DMA1_BASE (HBPERIPH_BASE + 0x0000) +#define DMA1_Channel1_BASE (HBPERIPH_BASE + 0x0008) +#define DMA1_Channel2_BASE (HBPERIPH_BASE + 0x001C) +#define DMA1_Channel3_BASE (HBPERIPH_BASE + 0x0030) +#define DMA1_Channel4_BASE (HBPERIPH_BASE + 0x0044) +#define DMA1_Channel5_BASE (HBPERIPH_BASE + 0x0058) +#define DMA1_Channel6_BASE (HBPERIPH_BASE + 0x006C) +#define DMA1_Channel7_BASE (HBPERIPH_BASE + 0x0080) +#define DMA1_Channel8_BASE (HBPERIPH_BASE + 0x0094) +#define RCC_BASE (HBPERIPH_BASE + 0x1000) +#define FLASH_R_BASE (HBPERIPH_BASE + 0x2000) +#define CRC_BASE (HBPERIPH_BASE + 0x3000) +#define EXTEN_BASE (HBPERIPH_BASE + 0x3800) +#define OPA_BASE (HBPERIPH_BASE + 0x6000) +#define USBPD_BASE (HBPERIPH_BASE + 0x7000) + +#define USBFS_BASE ((uint32_t)0x50000000) + +#define OB_BASE ((uint32_t)0x1FFFF800) + +#define TS_BASE ((uint32_t)0x1FFFF720) +#define OPA_TRIM_BASE ((uint32_t)0x1FFFF724) +#define ADC_TRIM_BASE ((uint32_t)0x1FFFF728) +#define HSI_LP_TRIM_BASE ((uint32_t)0x1FFFF72A) +#define CHIPID_BASE ((uint32_t)0x1FFFF704) +#define USBPD_CFG_BASE ((uint32_t)0x1FFFF730) + +/* Peripheral declaration */ +#define TIM2 ((TIM_TypeDef *)TIM2_BASE) +#define TIM3 ((TIM_TypeDef *)TIM3_BASE) +#define TIM4 ((TIM_TypeDef *)TIM4_BASE) +#define RTC ((RTC_TypeDef *)RTC_BASE) +#define WWDG ((WWDG_TypeDef *)WWDG_BASE) +#define IWDG ((IWDG_TypeDef *)IWDG_BASE) +#define SPI2 ((SPI_TypeDef *)SPI2_BASE) +#define USART2 ((USART_TypeDef *)USART2_BASE) +#define USART3 ((USART_TypeDef *)USART3_BASE) +#define USART4 ((USART_TypeDef *)USART4_BASE) +#define I2C1 ((I2C_TypeDef *)I2C1_BASE) +#define I2C2 ((I2C_TypeDef *)I2C2_BASE) +#define CAN1 ((CAN_TypeDef *)CAN1_BASE) +#define BKP ((BKP_TypeDef *)BKP_BASE) +#define PWR ((PWR_TypeDef *)PWR_BASE) +#define LPTIM ((LPTIM_TypeDef *)LPTIM_BASE) + +#define AFIO ((AFIO_TypeDef *)AFIO_BASE) +#define EXTI ((EXTI_TypeDef *)EXTI_BASE) +#define GPIOA ((GPIO_TypeDef *)GPIOA_BASE) +#define GPIOB ((GPIO_TypeDef *)GPIOB_BASE) +#define GPIOC ((GPIO_TypeDef *)GPIOC_BASE) +#define GPIOD ((GPIO_TypeDef *)GPIOD_BASE) +#define ADC1 ((ADC_TypeDef *)ADC1_BASE) +#define TKey1 ((ADC_TypeDef *)ADC1_BASE) +#define TIM1 ((TIM_TypeDef *)TIM1_BASE) +#define SPI1 ((SPI_TypeDef *)SPI1_BASE) +#define USART1 ((USART_TypeDef *)USART1_BASE) + +#define DMA1 ((DMA_TypeDef *)DMA1_BASE) +#define DMA1_Channel1 ((DMA_Channel_TypeDef *)DMA1_Channel1_BASE) +#define DMA1_Channel2 ((DMA_Channel_TypeDef *)DMA1_Channel2_BASE) +#define DMA1_Channel3 ((DMA_Channel_TypeDef *)DMA1_Channel3_BASE) +#define DMA1_Channel4 ((DMA_Channel_TypeDef *)DMA1_Channel4_BASE) +#define DMA1_Channel5 ((DMA_Channel_TypeDef *)DMA1_Channel5_BASE) +#define DMA1_Channel6 ((DMA_Channel_TypeDef *)DMA1_Channel6_BASE) +#define DMA1_Channel7 ((DMA_Channel_TypeDef *)DMA1_Channel7_BASE) +#define DMA1_Channel8 ((DMA_Channel_TypeDef *)DMA1_Channel8_BASE) +#define RCC ((RCC_TypeDef *)RCC_BASE) +#define FLASH ((FLASH_TypeDef *)FLASH_R_BASE) +#define CRC ((CRC_TypeDef *)CRC_BASE) +#define USBFSD ((USBFSD_TypeDef *)USBFS_BASE) +#define USBFSH ((USBFSH_TypeDef *)USBFS_BASE) +#define EXTEN ((EXTEN_TypeDef *)EXTEN_BASE) +#define OPA ((OPA_TypeDef *)OPA_BASE) +#define USBPD ((USBPD_TypeDef *)USBPD_BASE) + +#define OB ((OB_TypeDef *)OB_BASE) + + +/******************************************************************************/ +/* Peripheral Registers Bits Definition */ +/******************************************************************************/ + +/******************************************************************************/ +/* Analog to Digital Converter */ +/******************************************************************************/ + +/******************** Bit definition for ADC_STATR register ********************/ +#define ADC_AWD ((uint8_t)0x01) /* Analog watchdog flag */ +#define ADC_EOC ((uint8_t)0x02) /* End of conversion */ +#define ADC_JEOC ((uint8_t)0x04) /* Injected channel end of conversion */ +#define ADC_JSTRT ((uint8_t)0x08) /* Injected channel Start flag */ +#define ADC_STRT ((uint8_t)0x10) /* Regular channel Start flag */ + +/******************* Bit definition for ADC_CTLR1 register ********************/ +#define ADC_AWDCH ((uint32_t)0x0000001F) /* AWDCH[4:0] bits (Analog watchdog channel select bits) */ +#define ADC_AWDCH_0 ((uint32_t)0x00000001) /* Bit 0 */ +#define ADC_AWDCH_1 ((uint32_t)0x00000002) /* Bit 1 */ +#define ADC_AWDCH_2 ((uint32_t)0x00000004) /* Bit 2 */ +#define ADC_AWDCH_3 ((uint32_t)0x00000008) /* Bit 3 */ +#define ADC_AWDCH_4 ((uint32_t)0x00000010) /* Bit 4 */ + +#define ADC_EOCIE ((uint32_t)0x00000020) /* Interrupt enable for EOC */ +#define ADC_AWDIE ((uint32_t)0x00000040) /* Analog Watchdog interrupt enable */ +#define ADC_JEOCIE ((uint32_t)0x00000080) /* Interrupt enable for injected channels */ +#define ADC_SCAN ((uint32_t)0x00000100) /* Scan mode */ +#define ADC_AWDSGL ((uint32_t)0x00000200) /* Enable the watchdog on a single channel in scan mode */ +#define ADC_JAUTO ((uint32_t)0x00000400) /* Automatic injected group conversion */ +#define ADC_DISCEN ((uint32_t)0x00000800) /* Discontinuous mode on regular channels */ +#define ADC_JDISCEN ((uint32_t)0x00001000) /* Discontinuous mode on injected channels */ +#define ADC_RDISCEN ADC_DISCEN + +#define ADC_DISCNUM ((uint32_t)0x0000E000) /* DISCNUM[2:0] bits (Discontinuous mode channel count) */ +#define ADC_DISCNUM_0 ((uint32_t)0x00002000) /* Bit 0 */ +#define ADC_DISCNUM_1 ((uint32_t)0x00004000) /* Bit 1 */ +#define ADC_DISCNUM_2 ((uint32_t)0x00008000) /* Bit 2 */ + +#define ADC_JAWDEN ((uint32_t)0x00400000) /* Analog watchdog enable on injected channels */ +#define ADC_AWDEN ((uint32_t)0x00800000) /* Analog watchdog enable on regular channels */ + +#define ADC_TKENABLE ((uint32_t)0x01000000) +#define ADC_TK1TUNE ((uint32_t)0x02000000) +#define ADC_BUFEN ((uint32_t)0x04000000) + +#define ADC_PGA ((uint32_t)0x18000000) /* PGA[1:0] bits */ +#define ADC_PGA_0 ((uint32_t)0x08000000) +#define ADC_PGA_1 ((uint32_t)0x10000000) + +/******************* Bit definition for ADC_CTLR2 register ********************/ +#define ADC_ADON ((uint32_t)0x00000001) /* A/D Converter ON / OFF */ +#define ADC_CONT ((uint32_t)0x00000002) /* Continuous Conversion */ +#define ADC_CAL ((uint32_t)0x00000004) /* A/D Calibration */ +#define ADC_RSTCAL ((uint32_t)0x00000008) /* Reset Calibration */ +#define ADC_DMA ((uint32_t)0x00000100) /* Direct Memory access mode */ +#define ADC_ALIGN ((uint32_t)0x00000800) /* Data Alignment */ + +#define ADC_JEXTSEL ((uint32_t)0x00007000) /* JEXTSEL[2:0] bits (External event select for injected group) */ +#define ADC_JEXTSEL_0 ((uint32_t)0x00001000) /* Bit 0 */ +#define ADC_JEXTSEL_1 ((uint32_t)0x00002000) /* Bit 1 */ +#define ADC_JEXTSEL_2 ((uint32_t)0x00004000) /* Bit 2 */ + +#define ADC_JEXTTRIG ((uint32_t)0x00008000) /* External Trigger Conversion mode for injected channels */ + +#define ADC_EXTSEL ((uint32_t)0x000E0000) /* EXTSEL[2:0] bits (External Event Select for regular group) */ +#define ADC_EXTSEL_0 ((uint32_t)0x00020000) /* Bit 0 */ +#define ADC_EXTSEL_1 ((uint32_t)0x00040000) /* Bit 1 */ +#define ADC_EXTSEL_2 ((uint32_t)0x00080000) /* Bit 2 */ + +#define ADC_EXTTRIG ((uint32_t)0x00100000) /* External Trigger Conversion mode for regular channels */ +#define ADC_JSWSTART ((uint32_t)0x00200000) /* Start Conversion of injected channels */ +#define ADC_RSWSTART ((uint32_t)0x00400000) /* Start Conversion of regular channels */ +#define ADC_TSVREFE ((uint32_t)0x00800000) /* Temperature Sensor and VREFINT Enable */ + +/****************** Bit definition for ADC_SAMPTR1 register *******************/ +#define ADC_SMP16 ((uint32_t)0x001C0000) /* SMP16[2:0] bits (Channel 16 Sample time selection) */ +#define ADC_SMP16_0 ((uint32_t)0x00040000) /* Bit 0 */ +#define ADC_SMP16_1 ((uint32_t)0x00080000) /* Bit 1 */ +#define ADC_SMP16_2 ((uint32_t)0x00100000) /* Bit 2 */ + +#define ADC_SMP17 ((uint32_t)0x00E00000) /* SMP17[2:0] bits (Channel 17 Sample time selection) */ +#define ADC_SMP17_0 ((uint32_t)0x00200000) /* Bit 0 */ +#define ADC_SMP17_1 ((uint32_t)0x00400000) /* Bit 1 */ +#define ADC_SMP17_2 ((uint32_t)0x00800000) /* Bit 2 */ + +#define ADC_SMP18 ((uint32_t)0x07000000) /* SMP18[2:0] bits (Channel 18 Sample time selection) */ +#define ADC_SMP18_0 ((uint32_t)0x01000000) /* Bit 0 */ +#define ADC_SMP18_1 ((uint32_t)0x02000000) /* Bit 1 */ +#define ADC_SMP18_2 ((uint32_t)0x04000000) /* Bit 2 */ + +/****************** Bit definition for ADC_SAMPTR2 register *******************/ +#define ADC_SMP0 ((uint32_t)0x00000007) /* SMP0[2:0] bits (Channel 0 Sample time selection) */ +#define ADC_SMP0_0 ((uint32_t)0x00000001) /* Bit 0 */ +#define ADC_SMP0_1 ((uint32_t)0x00000002) /* Bit 1 */ +#define ADC_SMP0_2 ((uint32_t)0x00000004) /* Bit 2 */ + +#define ADC_SMP1 ((uint32_t)0x00000038) /* SMP1[2:0] bits (Channel 1 Sample time selection) */ +#define ADC_SMP1_0 ((uint32_t)0x00000008) /* Bit 0 */ +#define ADC_SMP1_1 ((uint32_t)0x00000010) /* Bit 1 */ +#define ADC_SMP1_2 ((uint32_t)0x00000020) /* Bit 2 */ + +#define ADC_SMP2 ((uint32_t)0x000001C0) /* SMP2[2:0] bits (Channel 2 Sample time selection) */ +#define ADC_SMP2_0 ((uint32_t)0x00000040) /* Bit 0 */ +#define ADC_SMP2_1 ((uint32_t)0x00000080) /* Bit 1 */ +#define ADC_SMP2_2 ((uint32_t)0x00000100) /* Bit 2 */ + +#define ADC_SMP3 ((uint32_t)0x00000E00) /* SMP3[2:0] bits (Channel 3 Sample time selection) */ +#define ADC_SMP3_0 ((uint32_t)0x00000200) /* Bit 0 */ +#define ADC_SMP3_1 ((uint32_t)0x00000400) /* Bit 1 */ +#define ADC_SMP3_2 ((uint32_t)0x00000800) /* Bit 2 */ + +#define ADC_SMP4 ((uint32_t)0x00007000) /* SMP4[2:0] bits (Channel 4 Sample time selection) */ +#define ADC_SMP4_0 ((uint32_t)0x00001000) /* Bit 0 */ +#define ADC_SMP4_1 ((uint32_t)0x00002000) /* Bit 1 */ +#define ADC_SMP4_2 ((uint32_t)0x00004000) /* Bit 2 */ + +#define ADC_SMP5 ((uint32_t)0x00038000) /* SMP5[2:0] bits (Channel 5 Sample time selection) */ +#define ADC_SMP5_0 ((uint32_t)0x00008000) /* Bit 0 */ +#define ADC_SMP5_1 ((uint32_t)0x00010000) /* Bit 1 */ +#define ADC_SMP5_2 ((uint32_t)0x00020000) /* Bit 2 */ + +#define ADC_SMP6 ((uint32_t)0x001C0000) /* SMP6[2:0] bits (Channel 6 Sample time selection) */ +#define ADC_SMP6_0 ((uint32_t)0x00040000) /* Bit 0 */ +#define ADC_SMP6_1 ((uint32_t)0x00080000) /* Bit 1 */ +#define ADC_SMP6_2 ((uint32_t)0x00100000) /* Bit 2 */ + +#define ADC_SMP7 ((uint32_t)0x00E00000) /* SMP7[2:0] bits (Channel 7 Sample time selection) */ +#define ADC_SMP7_0 ((uint32_t)0x00200000) /* Bit 0 */ +#define ADC_SMP7_1 ((uint32_t)0x00400000) /* Bit 1 */ +#define ADC_SMP7_2 ((uint32_t)0x00800000) /* Bit 2 */ + +#define ADC_SMP8 ((uint32_t)0x07000000) /* SMP8[2:0] bits (Channel 8 Sample time selection) */ +#define ADC_SMP8_0 ((uint32_t)0x01000000) /* Bit 0 */ +#define ADC_SMP8_1 ((uint32_t)0x02000000) /* Bit 1 */ +#define ADC_SMP8_2 ((uint32_t)0x04000000) /* Bit 2 */ + +#define ADC_SMP9 ((uint32_t)0x38000000) /* SMP9[2:0] bits (Channel 9 Sample time selection) */ +#define ADC_SMP9_0 ((uint32_t)0x08000000) /* Bit 0 */ +#define ADC_SMP9_1 ((uint32_t)0x10000000) /* Bit 1 */ +#define ADC_SMP9_2 ((uint32_t)0x20000000) /* Bit 2 */ + +/****************** Bit definition for ADC_IOFR1 register *******************/ +#define ADC_JOFFSET1 ((uint16_t)0x0FFF) /* Data offset for injected channel 1 */ + +/****************** Bit definition for ADC_IOFR2 register *******************/ +#define ADC_JOFFSET2 ((uint16_t)0x0FFF) /* Data offset for injected channel 2 */ + +/****************** Bit definition for ADC_IOFR3 register *******************/ +#define ADC_JOFFSET3 ((uint16_t)0x0FFF) /* Data offset for injected channel 3 */ + +/****************** Bit definition for ADC_IOFR4 register *******************/ +#define ADC_JOFFSET4 ((uint16_t)0x0FFF) /* Data offset for injected channel 4 */ + +/******************* Bit definition for ADC_WDHTR register ********************/ +#define ADC_HT ((uint16_t)0x0FFF) /* Analog watchdog high threshold */ + +/******************* Bit definition for ADC_WDLTR register ********************/ +#define ADC_LT ((uint16_t)0x0FFF) /* Analog watchdog low threshold */ + +/******************* Bit definition for ADC_RSQR1 register *******************/ +#define ADC_SQ13 ((uint32_t)0x0000001F) /* SQ13[4:0] bits (13th conversion in regular sequence) */ +#define ADC_SQ13_0 ((uint32_t)0x00000001) /* Bit 0 */ +#define ADC_SQ13_1 ((uint32_t)0x00000002) /* Bit 1 */ +#define ADC_SQ13_2 ((uint32_t)0x00000004) /* Bit 2 */ +#define ADC_SQ13_3 ((uint32_t)0x00000008) /* Bit 3 */ +#define ADC_SQ13_4 ((uint32_t)0x00000010) /* Bit 4 */ + +#define ADC_SQ14 ((uint32_t)0x000003E0) /* SQ14[4:0] bits (14th conversion in regular sequence) */ +#define ADC_SQ14_0 ((uint32_t)0x00000020) /* Bit 0 */ +#define ADC_SQ14_1 ((uint32_t)0x00000040) /* Bit 1 */ +#define ADC_SQ14_2 ((uint32_t)0x00000080) /* Bit 2 */ +#define ADC_SQ14_3 ((uint32_t)0x00000100) /* Bit 3 */ +#define ADC_SQ14_4 ((uint32_t)0x00000200) /* Bit 4 */ + +#define ADC_SQ15 ((uint32_t)0x00007C00) /* SQ15[4:0] bits (15th conversion in regular sequence) */ +#define ADC_SQ15_0 ((uint32_t)0x00000400) /* Bit 0 */ +#define ADC_SQ15_1 ((uint32_t)0x00000800) /* Bit 1 */ +#define ADC_SQ15_2 ((uint32_t)0x00001000) /* Bit 2 */ +#define ADC_SQ15_3 ((uint32_t)0x00002000) /* Bit 3 */ +#define ADC_SQ15_4 ((uint32_t)0x00004000) /* Bit 4 */ + +#define ADC_SQ16 ((uint32_t)0x000F8000) /* SQ16[4:0] bits (16th conversion in regular sequence) */ +#define ADC_SQ16_0 ((uint32_t)0x00008000) /* Bit 0 */ +#define ADC_SQ16_1 ((uint32_t)0x00010000) /* Bit 1 */ +#define ADC_SQ16_2 ((uint32_t)0x00020000) /* Bit 2 */ +#define ADC_SQ16_3 ((uint32_t)0x00040000) /* Bit 3 */ +#define ADC_SQ16_4 ((uint32_t)0x00080000) /* Bit 4 */ + +#define ADC_L ((uint32_t)0x00F00000) /* L[3:0] bits (Regular channel sequence length) */ +#define ADC_L_0 ((uint32_t)0x00100000) /* Bit 0 */ +#define ADC_L_1 ((uint32_t)0x00200000) /* Bit 1 */ +#define ADC_L_2 ((uint32_t)0x00400000) /* Bit 2 */ +#define ADC_L_3 ((uint32_t)0x00800000) /* Bit 3 */ + +/******************* Bit definition for ADC_RSQR2 register *******************/ +#define ADC_SQ7 ((uint32_t)0x0000001F) /* SQ7[4:0] bits (7th conversion in regular sequence) */ +#define ADC_SQ7_0 ((uint32_t)0x00000001) /* Bit 0 */ +#define ADC_SQ7_1 ((uint32_t)0x00000002) /* Bit 1 */ +#define ADC_SQ7_2 ((uint32_t)0x00000004) /* Bit 2 */ +#define ADC_SQ7_3 ((uint32_t)0x00000008) /* Bit 3 */ +#define ADC_SQ7_4 ((uint32_t)0x00000010) /* Bit 4 */ + +#define ADC_SQ8 ((uint32_t)0x000003E0) /* SQ8[4:0] bits (8th conversion in regular sequence) */ +#define ADC_SQ8_0 ((uint32_t)0x00000020) /* Bit 0 */ +#define ADC_SQ8_1 ((uint32_t)0x00000040) /* Bit 1 */ +#define ADC_SQ8_2 ((uint32_t)0x00000080) /* Bit 2 */ +#define ADC_SQ8_3 ((uint32_t)0x00000100) /* Bit 3 */ +#define ADC_SQ8_4 ((uint32_t)0x00000200) /* Bit 4 */ + +#define ADC_SQ9 ((uint32_t)0x00007C00) /* SQ9[4:0] bits (9th conversion in regular sequence) */ +#define ADC_SQ9_0 ((uint32_t)0x00000400) /* Bit 0 */ +#define ADC_SQ9_1 ((uint32_t)0x00000800) /* Bit 1 */ +#define ADC_SQ9_2 ((uint32_t)0x00001000) /* Bit 2 */ +#define ADC_SQ9_3 ((uint32_t)0x00002000) /* Bit 3 */ +#define ADC_SQ9_4 ((uint32_t)0x00004000) /* Bit 4 */ + +#define ADC_SQ10 ((uint32_t)0x000F8000) /* SQ10[4:0] bits (10th conversion in regular sequence) */ +#define ADC_SQ10_0 ((uint32_t)0x00008000) /* Bit 0 */ +#define ADC_SQ10_1 ((uint32_t)0x00010000) /* Bit 1 */ +#define ADC_SQ10_2 ((uint32_t)0x00020000) /* Bit 2 */ +#define ADC_SQ10_3 ((uint32_t)0x00040000) /* Bit 3 */ +#define ADC_SQ10_4 ((uint32_t)0x00080000) /* Bit 4 */ + +#define ADC_SQ11 ((uint32_t)0x01F00000) /* SQ11[4:0] bits (11th conversion in regular sequence) */ +#define ADC_SQ11_0 ((uint32_t)0x00100000) /* Bit 0 */ +#define ADC_SQ11_1 ((uint32_t)0x00200000) /* Bit 1 */ +#define ADC_SQ11_2 ((uint32_t)0x00400000) /* Bit 2 */ +#define ADC_SQ11_3 ((uint32_t)0x00800000) /* Bit 3 */ +#define ADC_SQ11_4 ((uint32_t)0x01000000) /* Bit 4 */ + +#define ADC_SQ12 ((uint32_t)0x3E000000) /* SQ12[4:0] bits (12th conversion in regular sequence) */ +#define ADC_SQ12_0 ((uint32_t)0x02000000) /* Bit 0 */ +#define ADC_SQ12_1 ((uint32_t)0x04000000) /* Bit 1 */ +#define ADC_SQ12_2 ((uint32_t)0x08000000) /* Bit 2 */ +#define ADC_SQ12_3 ((uint32_t)0x10000000) /* Bit 3 */ +#define ADC_SQ12_4 ((uint32_t)0x20000000) /* Bit 4 */ + +/******************* Bit definition for ADC_RSQR3 register *******************/ +#define ADC_SQ1 ((uint32_t)0x0000001F) /* SQ1[4:0] bits (1st conversion in regular sequence) */ +#define ADC_SQ1_0 ((uint32_t)0x00000001) /* Bit 0 */ +#define ADC_SQ1_1 ((uint32_t)0x00000002) /* Bit 1 */ +#define ADC_SQ1_2 ((uint32_t)0x00000004) /* Bit 2 */ +#define ADC_SQ1_3 ((uint32_t)0x00000008) /* Bit 3 */ +#define ADC_SQ1_4 ((uint32_t)0x00000010) /* Bit 4 */ + +#define ADC_SQ2 ((uint32_t)0x000003E0) /* SQ2[4:0] bits (2nd conversion in regular sequence) */ +#define ADC_SQ2_0 ((uint32_t)0x00000020) /* Bit 0 */ +#define ADC_SQ2_1 ((uint32_t)0x00000040) /* Bit 1 */ +#define ADC_SQ2_2 ((uint32_t)0x00000080) /* Bit 2 */ +#define ADC_SQ2_3 ((uint32_t)0x00000100) /* Bit 3 */ +#define ADC_SQ2_4 ((uint32_t)0x00000200) /* Bit 4 */ + +#define ADC_SQ3 ((uint32_t)0x00007C00) /* SQ3[4:0] bits (3rd conversion in regular sequence) */ +#define ADC_SQ3_0 ((uint32_t)0x00000400) /* Bit 0 */ +#define ADC_SQ3_1 ((uint32_t)0x00000800) /* Bit 1 */ +#define ADC_SQ3_2 ((uint32_t)0x00001000) /* Bit 2 */ +#define ADC_SQ3_3 ((uint32_t)0x00002000) /* Bit 3 */ +#define ADC_SQ3_4 ((uint32_t)0x00004000) /* Bit 4 */ + +#define ADC_SQ4 ((uint32_t)0x000F8000) /* SQ4[4:0] bits (4th conversion in regular sequence) */ +#define ADC_SQ4_0 ((uint32_t)0x00008000) /* Bit 0 */ +#define ADC_SQ4_1 ((uint32_t)0x00010000) /* Bit 1 */ +#define ADC_SQ4_2 ((uint32_t)0x00020000) /* Bit 2 */ +#define ADC_SQ4_3 ((uint32_t)0x00040000) /* Bit 3 */ +#define ADC_SQ4_4 ((uint32_t)0x00080000) /* Bit 4 */ + +#define ADC_SQ5 ((uint32_t)0x01F00000) /* SQ5[4:0] bits (5th conversion in regular sequence) */ +#define ADC_SQ5_0 ((uint32_t)0x00100000) /* Bit 0 */ +#define ADC_SQ5_1 ((uint32_t)0x00200000) /* Bit 1 */ +#define ADC_SQ5_2 ((uint32_t)0x00400000) /* Bit 2 */ +#define ADC_SQ5_3 ((uint32_t)0x00800000) /* Bit 3 */ +#define ADC_SQ5_4 ((uint32_t)0x01000000) /* Bit 4 */ + +#define ADC_SQ6 ((uint32_t)0x3E000000) /* SQ6[4:0] bits (6th conversion in regular sequence) */ +#define ADC_SQ6_0 ((uint32_t)0x02000000) /* Bit 0 */ +#define ADC_SQ6_1 ((uint32_t)0x04000000) /* Bit 1 */ +#define ADC_SQ6_2 ((uint32_t)0x08000000) /* Bit 2 */ +#define ADC_SQ6_3 ((uint32_t)0x10000000) /* Bit 3 */ +#define ADC_SQ6_4 ((uint32_t)0x20000000) /* Bit 4 */ + +/******************* Bit definition for ADC_ISQR register *******************/ +#define ADC_JSQ1 ((uint32_t)0x0000001F) /* JSQ1[4:0] bits (1st conversion in injected sequence) */ +#define ADC_JSQ1_0 ((uint32_t)0x00000001) /* Bit 0 */ +#define ADC_JSQ1_1 ((uint32_t)0x00000002) /* Bit 1 */ +#define ADC_JSQ1_2 ((uint32_t)0x00000004) /* Bit 2 */ +#define ADC_JSQ1_3 ((uint32_t)0x00000008) /* Bit 3 */ +#define ADC_JSQ1_4 ((uint32_t)0x00000010) /* Bit 4 */ + +#define ADC_JSQ2 ((uint32_t)0x000003E0) /* JSQ2[4:0] bits (2nd conversion in injected sequence) */ +#define ADC_JSQ2_0 ((uint32_t)0x00000020) /* Bit 0 */ +#define ADC_JSQ2_1 ((uint32_t)0x00000040) /* Bit 1 */ +#define ADC_JSQ2_2 ((uint32_t)0x00000080) /* Bit 2 */ +#define ADC_JSQ2_3 ((uint32_t)0x00000100) /* Bit 3 */ +#define ADC_JSQ2_4 ((uint32_t)0x00000200) /* Bit 4 */ + +#define ADC_JSQ3 ((uint32_t)0x00007C00) /* JSQ3[4:0] bits (3rd conversion in injected sequence) */ +#define ADC_JSQ3_0 ((uint32_t)0x00000400) /* Bit 0 */ +#define ADC_JSQ3_1 ((uint32_t)0x00000800) /* Bit 1 */ +#define ADC_JSQ3_2 ((uint32_t)0x00001000) /* Bit 2 */ +#define ADC_JSQ3_3 ((uint32_t)0x00002000) /* Bit 3 */ +#define ADC_JSQ3_4 ((uint32_t)0x00004000) /* Bit 4 */ + +#define ADC_JSQ4 ((uint32_t)0x000F8000) /* JSQ4[4:0] bits (4th conversion in injected sequence) */ +#define ADC_JSQ4_0 ((uint32_t)0x00008000) /* Bit 0 */ +#define ADC_JSQ4_1 ((uint32_t)0x00010000) /* Bit 1 */ +#define ADC_JSQ4_2 ((uint32_t)0x00020000) /* Bit 2 */ +#define ADC_JSQ4_3 ((uint32_t)0x00040000) /* Bit 3 */ +#define ADC_JSQ4_4 ((uint32_t)0x00080000) /* Bit 4 */ + +#define ADC_JL ((uint32_t)0x00300000) /* JL[1:0] bits (Injected Sequence length) */ +#define ADC_JL_0 ((uint32_t)0x00100000) /* Bit 0 */ +#define ADC_JL_1 ((uint32_t)0x00200000) /* Bit 1 */ + +/******************* Bit definition for ADC_IDATAR1 register *******************/ +#define ADC_IDATAR1_JDATA ((uint16_t)0xFFFF) /* Injected data */ + +/******************* Bit definition for ADC_IDATAR2 register *******************/ +#define ADC_IDATAR2_JDATA ((uint16_t)0xFFFF) /* Injected data */ + +/******************* Bit definition for ADC_IDATAR3 register *******************/ +#define ADC_IDATAR3_JDATA ((uint16_t)0xFFFF) /* Injected data */ + +/******************* Bit definition for ADC_IDATAR4 register *******************/ +#define ADC_IDATAR4_JDATA ((uint16_t)0xFFFF) /* Injected data */ + +/******************** Bit definition for ADC_RDATAR register ********************/ +#define ADC_RDATAR_DATA ((uint32_t)0x0000FFFF) /* Regular data */ +/******************** Bit definition for ADC_CFG register ********************/ +#define ADC_BUFTRIM ((uint32_t)0x0000000F) /* BUFTRIM[3:0] bits */ +#define ADC_BUFTRIM_0 ((uint32_t)0x00000001) +#define ADC_BUFTRIM_1 ((uint32_t)0x00000002) +#define ADC_BUFTRIM_2 ((uint32_t)0x00000004) +#define ADC_BUFTRIM_3 ((uint32_t)0x00000008) + +#define ADC_AWDRST_EN ((uint32_t)0x00000010) +#define ADC_LP ((uint32_t)0x00000020) +#define ADC_FIFO_EN ((uint32_t)0x00000040) +#define ADC_DUTY_EN ((uint32_t)0x00000080) +#define ADC_TKEY_DRV_EN ((uint32_t)0x00000100) + +#define ADC_TKEY_DRV_OUTEN ((uint32_t)0x0007FE00) /* TKEY_DRV_OUTEN[9:0] bits */ +#define ADC_TKEY_DRV_OUTEN_0 ((uint32_t)0x00000200) +#define ADC_TKEY_DRV_OUTEN_1 ((uint32_t)0x00000400) +#define ADC_TKEY_DRV_OUTEN_2 ((uint32_t)0x00000800) +#define ADC_TKEY_DRV_OUTEN_3 ((uint32_t)0x00001000) +#define ADC_TKEY_DRV_OUTEN_4 ((uint32_t)0x00002000) +#define ADC_TKEY_DRV_OUTEN_5 ((uint32_t)0x00004000) +#define ADC_TKEY_DRV_OUTEN_6 ((uint32_t)0x00008000) +#define ADC_TKEY_DRV_OUTEN_7 ((uint32_t)0x00010000) +#define ADC_TKEY_DRV_OUTEN_8 ((uint32_t)0x00020000) +#define ADC_TKEY_DRV_OUTEN_9 ((uint32_t)0x00040000) + +#define ADC_TKEY_SEL ((uint32_t)0x00180000) /* TKEY_SEL[1:0] bits */ +#define ADC_TKEY_SEL_0 ((uint32_t)0x00080000) +#define ADC_TKEY_SEL_1 ((uint32_t)0x00080000) + +#define ADC_TKEY_WAKE_EN ((uint32_t)0x8FE00000) /* TKEY_WAKE_EN[9:0] bits */ +#define ADC_TKEY_WAKE_EN_0 ((uint32_t)0x00200000) +#define ADC_TKEY_WAKE_EN_1 ((uint32_t)0x00400000) +#define ADC_TKEY_WAKE_EN_2 ((uint32_t)0x00800000) +#define ADC_TKEY_WAKE_EN_3 ((uint32_t)0x01000000) +#define ADC_TKEY_WAKE_EN_4 ((uint32_t)0x02000000) +#define ADC_TKEY_WAKE_EN_5 ((uint32_t)0x04000000) +#define ADC_TKEY_WAKE_EN_6 ((uint32_t)0x08000000) +#define ADC_TKEY_WAKE_EN_7 ((uint32_t)0x10000000) +#define ADC_TKEY_WAKE_EN_8 ((uint32_t)0x20000000) +#define ADC_TKEY_WAKE_EN_9 ((uint32_t)0x40000000) + +/******************************************************************************/ +/* Backup registers */ +/******************************************************************************/ + +/******************* Bit definition for BKP_DATAR1 register ********************/ +#define BKP_DATAR1_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR2 register ********************/ +#define BKP_DATAR2_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR3 register ********************/ +#define BKP_DATAR3_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR4 register ********************/ +#define BKP_DATAR4_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR5 register ********************/ +#define BKP_DATAR5_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR6 register ********************/ +#define BKP_DATAR6_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR7 register ********************/ +#define BKP_DATAR7_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR8 register ********************/ +#define BKP_DATAR8_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR9 register ********************/ +#define BKP_DATAR9_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR10 register *******************/ +#define BKP_DATAR10_D ((uint16_t)0xFFFF) /* Backup data */ + +/****************** Bit definition for BKP_OCTLR register *******************/ +#define BKP_CAL ((uint16_t)0x007F) /* Calibration value */ +#define BKP_CCO ((uint16_t)0x0080) /* Calibration Clock Output */ +#define BKP_ASOE ((uint16_t)0x0100) /* Alarm or Second Output Enable */ +#define BKP_ASOS ((uint16_t)0x0200) /* Alarm or Second Output Selection */ + +/******************** Bit definition for BKP_TPCTLR register ********************/ +#define BKP_TPE ((uint8_t)0x01) /* TAMPER pin enable */ +#define BKP_TPAL ((uint8_t)0x02) /* TAMPER pin active level */ + +/******************* Bit definition for BKP_TPCSR register ********************/ +#define BKP_CTE ((uint16_t)0x0001) /* Clear Tamper event */ +#define BKP_CTI ((uint16_t)0x0002) /* Clear Tamper Interrupt */ +#define BKP_TPIE ((uint16_t)0x0004) /* TAMPER Pin interrupt enable */ +#define BKP_TEF ((uint16_t)0x0100) /* Tamper Event Flag */ +#define BKP_TIF ((uint16_t)0x0200) /* Tamper Interrupt Flag */ + +/******************************************************************************/ +/* Controller Area Network */ +/******************************************************************************/ + +/******************* Bit definition for CAN_CTLR register ********************/ +#define CAN_CTLR_INRQ ((uint32_t)0x00000001) /* Initialization Request */ +#define CAN_CTLR_SLEEP ((uint32_t)0x00000002) /* Sleep Mode Request */ +#define CAN_CTLR_TXFP ((uint32_t)0x00000004) /* Transmit FIFO Priority */ +#define CAN_CTLR_RFLM ((uint32_t)0x00000008) /* Receive FIFO Locked Mode */ +#define CAN_CTLR_NART ((uint32_t)0x00000010) /* No Automatic Retransmission */ +#define CAN_CTLR_AWUM ((uint32_t)0x00000020) /* Automatic Wakeup Mode */ +#define CAN_CTLR_ABOM ((uint32_t)0x00000040) /* Automatic Bus-Off Management */ +#define CAN_CTLR_TTCM ((uint32_t)0x00000080) /* Time Triggered Communication Mode */ +#define CAN_CTLR_RESET ((uint32_t)0x00008000) /* CAN software master reset */ +#define CAN_CTLR_DBF ((uint32_t)0x00010000) /* CAN controller operating state selection during debugging */ + +/******************* Bit definition for CAN_STATR register ********************/ +#define CAN_STATR_INAK ((uint16_t)0x0001) /* Initialization Acknowledge */ +#define CAN_STATR_SLAK ((uint16_t)0x0002) /* Sleep Acknowledge */ +#define CAN_STATR_ERRI ((uint16_t)0x0004) /* Error Interrupt */ +#define CAN_STATR_WKUI ((uint16_t)0x0008) /* Wakeup Interrupt */ +#define CAN_STATR_SLAKI ((uint16_t)0x0010) /* Sleep Acknowledge Interrupt */ +#define CAN_STATR_TXM ((uint16_t)0x0100) /* Transmit Mode */ +#define CAN_STATR_RXM ((uint16_t)0x0200) /* Receive Mode */ +#define CAN_STATR_SAMP ((uint16_t)0x0400) /* Last Sample Point */ +#define CAN_STATR_RX ((uint16_t)0x0800) /* CAN Rx Signal */ + +/******************* Bit definition for CAN_TSTATR register ********************/ +#define CAN_TSTATR_RQCP0 ((uint32_t)0x00000001) /* Request Completed Mailbox0 */ +#define CAN_TSTATR_TXOK0 ((uint32_t)0x00000002) /* Transmission OK of Mailbox0 */ +#define CAN_TSTATR_ALST0 ((uint32_t)0x00000004) /* Arbitration Lost for Mailbox0 */ +#define CAN_TSTATR_TERR0 ((uint32_t)0x00000008) /* Transmission Error of Mailbox0 */ +#define CAN_TSTATR_ABRQ0 ((uint32_t)0x00000080) /* Abort Request for Mailbox0 */ +#define CAN_TSTATR_RQCP1 ((uint32_t)0x00000100) /* Request Completed Mailbox1 */ +#define CAN_TSTATR_TXOK1 ((uint32_t)0x00000200) /* Transmission OK of Mailbox1 */ +#define CAN_TSTATR_ALST1 ((uint32_t)0x00000400) /* Arbitration Lost for Mailbox1 */ +#define CAN_TSTATR_TERR1 ((uint32_t)0x00000800) /* Transmission Error of Mailbox1 */ +#define CAN_TSTATR_ABRQ1 ((uint32_t)0x00008000) /* Abort Request for Mailbox 1 */ +#define CAN_TSTATR_RQCP2 ((uint32_t)0x00010000) /* Request Completed Mailbox2 */ +#define CAN_TSTATR_TXOK2 ((uint32_t)0x00020000) /* Transmission OK of Mailbox 2 */ +#define CAN_TSTATR_ALST2 ((uint32_t)0x00040000) /* Arbitration Lost for mailbox 2 */ +#define CAN_TSTATR_TERR2 ((uint32_t)0x00080000) /* Transmission Error of Mailbox 2 */ +#define CAN_TSTATR_ABRQ2 ((uint32_t)0x00800000) /* Abort Request for Mailbox 2 */ +#define CAN_TSTATR_CODE ((uint32_t)0x03000000) /* Mailbox Code */ + +#define CAN_TSTATR_TME ((uint32_t)0x1C000000) /* TME[2:0] bits */ +#define CAN_TSTATR_TME0 ((uint32_t)0x04000000) /* Transmit Mailbox 0 Empty */ +#define CAN_TSTATR_TME1 ((uint32_t)0x08000000) /* Transmit Mailbox 1 Empty */ +#define CAN_TSTATR_TME2 ((uint32_t)0x10000000) /* Transmit Mailbox 2 Empty */ + +#define CAN_TSTATR_LOW ((uint32_t)0xE0000000) /* LOW[2:0] bits */ +#define CAN_TSTATR_LOW0 ((uint32_t)0x20000000) /* Lowest Priority Flag for Mailbox 0 */ +#define CAN_TSTATR_LOW1 ((uint32_t)0x40000000) /* Lowest Priority Flag for Mailbox 1 */ +#define CAN_TSTATR_LOW2 ((uint32_t)0x80000000) /* Lowest Priority Flag for Mailbox 2 */ + +/******************* Bit definition for CAN_RFIFO0 register *******************/ +#define CAN_RFIFO0_FMP0 ((uint8_t)0x03) /* FIFO 0 Message Pending */ +#define CAN_RFIFO0_FULL0 ((uint8_t)0x08) /* FIFO 0 Full */ +#define CAN_RFIFO0_FOVR0 ((uint8_t)0x10) /* FIFO 0 Overrun */ +#define CAN_RFIFO0_RFOM0 ((uint8_t)0x20) /* Release FIFO 0 Output Mailbox */ + +/******************* Bit definition for CAN_RFIFO1 register *******************/ +#define CAN_RFIFO1_FMP1 ((uint8_t)0x03) /* FIFO 1 Message Pending */ +#define CAN_RFIFO1_FULL1 ((uint8_t)0x08) /* FIFO 1 Full */ +#define CAN_RFIFO1_FOVR1 ((uint8_t)0x10) /* FIFO 1 Overrun */ +#define CAN_RFIFO1_RFOM1 ((uint8_t)0x20) /* Release FIFO 1 Output Mailbox */ + +/******************** Bit definition for CAN_INTENR register *******************/ +#define CAN_INTENR_TMEIE ((uint32_t)0x00000001) /* Transmit Mailbox Empty Interrupt Enable */ +#define CAN_INTENR_FMPIE0 ((uint32_t)0x00000002) /* FIFO Message Pending Interrupt Enable */ +#define CAN_INTENR_FFIE0 ((uint32_t)0x00000004) /* FIFO Full Interrupt Enable */ +#define CAN_INTENR_FOVIE0 ((uint32_t)0x00000008) /* FIFO Overrun Interrupt Enable */ +#define CAN_INTENR_FMPIE1 ((uint32_t)0x00000010) /* FIFO Message Pending Interrupt Enable */ +#define CAN_INTENR_FFIE1 ((uint32_t)0x00000020) /* FIFO Full Interrupt Enable */ +#define CAN_INTENR_FOVIE1 ((uint32_t)0x00000040) /* FIFO Overrun Interrupt Enable */ +#define CAN_INTENR_EWGIE ((uint32_t)0x00000100) /* Error Warning Interrupt Enable */ +#define CAN_INTENR_EPVIE ((uint32_t)0x00000200) /* Error Passive Interrupt Enable */ +#define CAN_INTENR_BOFIE ((uint32_t)0x00000400) /* Bus-Off Interrupt Enable */ +#define CAN_INTENR_LECIE ((uint32_t)0x00000800) /* Last Error Code Interrupt Enable */ +#define CAN_INTENR_ERRIE ((uint32_t)0x00008000) /* Error Interrupt Enable */ +#define CAN_INTENR_WKUIE ((uint32_t)0x00010000) /* Wakeup Interrupt Enable */ +#define CAN_INTENR_SLKIE ((uint32_t)0x00020000) /* Sleep Interrupt Enable */ + +/******************** Bit definition for CAN_ERRSR register *******************/ +#define CAN_ERRSR_EWGF ((uint32_t)0x00000001) /* Error Warning Flag */ +#define CAN_ERRSR_EPVF ((uint32_t)0x00000002) /* Error Passive Flag */ +#define CAN_ERRSR_BOFF ((uint32_t)0x00000004) /* Bus-Off Flag */ + +#define CAN_ERRSR_LEC ((uint32_t)0x00000070) /* LEC[2:0] bits (Last Error Code) */ +#define CAN_ERRSR_LEC_0 ((uint32_t)0x00000010) /* Bit 0 */ +#define CAN_ERRSR_LEC_1 ((uint32_t)0x00000020) /* Bit 1 */ +#define CAN_ERRSR_LEC_2 ((uint32_t)0x00000040) /* Bit 2 */ + +#define CAN_ERRSR_TEC ((uint32_t)0x00FF0000) /* Least significant byte of the 9-bit Transmit Error Counter */ +#define CAN_ERRSR_REC ((uint32_t)0xFF000000) /* Receive Error Counter */ + +/******************* Bit definition for CAN_BTIMR register ********************/ +#define CAN_BTIMR_BRP ((uint32_t)0x000003FF) /* Baud Rate Prescaler */ +#define CAN_BTIMR_TS1 ((uint32_t)0x000F0000) /* Time Segment 1 */ +#define CAN_BTIMR_TS2 ((uint32_t)0x00700000) /* Time Segment 2 */ +#define CAN_BTIMR_SJW ((uint32_t)0x03000000) /* Resynchronization Jump Width */ +#define CAN_BTIMR_LBKM ((uint32_t)0x40000000) /* Loop Back Mode (Debug) */ +#define CAN_BTIMR_SILM ((uint32_t)0x80000000) /* Silent Mode */ + +/******************** Bit definition for CAN_TTCTLR register *******************/ +#define CAN_TTCTLR_TIMCMV ((uint32_t)0x0000FFFF) +#define CAN_TTCTLR_TIMRST ((uint32_t)0x00010000) +#define CAN_TTCTLR_MODE ((uint32_t)0x00020000) + +/******************** Bit definition for CAN_TTCNT register *******************/ +#define CAN_TTCNT ((uint32_t)0x0000FFFF) + +/******************** Bit definition for CAN_TERR_CNT register *******************/ +#define CAN_TERR_CNT ((uint32_t)0x000001FF) + +/******************** Bit definition for CANFD_CR register *******************/ +#define CANFD_CR_TX_FD ((uint32_t)0x00000001) +#define CANFD_CR_TX_BRS_B ((uint32_t)0x0000000E) +#define CANFD_CR_USER_ESI_B ((uint32_t)0x00000070) +#define CANFD_CR_RES_EXCEPT ((uint32_t)0x00000080) +#define CANFD_CR_CLAS_LONG_TS1 ((uint32_t)0x00000100) +#define CANFD_CR_RESTRICT_MODE ((uint32_t)0x00000200) + +/******************** Bit definition for CANFD_BTR register *******************/ +#define CANFD_BTR_BTR_SJW_FD ((uint32_t)0x0000000F) +#define CANFD_BTR_BTR_TS2_FD ((uint32_t)0x000000F0) +#define CANFD_BTR_BTR_TS1_FD ((uint32_t)0x00001F00) +#define CANFD_BTR_BTR_BRP_FD ((uint32_t)0x001F0000) +#define CANFD_BTR_BTR_TDCE ((uint32_t)0x00800000) + +/******************** Bit definition for CANFD_TDCT register *******************/ +#define CANFD_TDCT_TDCO ((uint32_t)0x0000003F) +#define CANFD_TDCT_TDC_FILTER ((uint32_t)0x00003F00) + +/******************** Bit definition for CANFD_PSR register *******************/ +#define CANFD_PSR_TDCV ((uint32_t)0x00FF0000) + +/******************** Bit definition for CAN_DMA_T0 register *******************/ +#define CANFD_DMA_T0 ((uint32_t)0x00007FFF) + +/******************** Bit definition for CAN_DMA_T1 register *******************/ +#define CANFD_DMA_T1 ((uint32_t)0x00007FFF) + +/******************** Bit definition for CAN_DMA_T2 register *******************/ +#define CANFD_DMA_T2 ((uint32_t)0x00007FFF) + +/******************** Bit definition for CAN_DMA_R0 register *******************/ +#define CANFD_DMA_R0 ((uint32_t)0x00007FFF) + +/******************** Bit definition for CAN_DMA_R1 register *******************/ +#define CANFD_DMA_R1 ((uint32_t)0x00007FFF) + +/****************** Bit definition for CAN_TXMI0R register ********************/ +#define CAN_TXMI0R_TXRQ ((uint32_t)0x00000001) /* Transmit Mailbox Request */ +#define CAN_TXMI0R_RTR ((uint32_t)0x00000002) /* Remote Transmission Request */ +#define CAN_TXMI0R_IDE ((uint32_t)0x00000004) /* Identifier Extension */ +#define CAN_TXMI0R_EXID ((uint32_t)0x001FFFF8) /* Extended Identifier */ +#define CAN_TXMI0R_STID ((uint32_t)0xFFE00000) /* Standard Identifier or Extended Identifier */ + +/****************** Bit definition for CAN_TXMDT0R register *******************/ +#define CAN_TXMDT0R_DLC ((uint32_t)0x0000000F) /* Data Length Code */ +#define CAN_TXMDT0R_TGT ((uint32_t)0x00000100) /* Transmit Global Time */ +#define CAN_TXMDT0R_TIME ((uint32_t)0xFFFF0000) /* Message Time Stamp */ + +/****************** Bit definition for CAN_TXMDL0R register *******************/ +#define CAN_TXMDL0R_DATA0 ((uint32_t)0x000000FF) /* Data byte 0 */ +#define CAN_TXMDL0R_DATA1 ((uint32_t)0x0000FF00) /* Data byte 1 */ +#define CAN_TXMDL0R_DATA2 ((uint32_t)0x00FF0000) /* Data byte 2 */ +#define CAN_TXMDL0R_DATA3 ((uint32_t)0xFF000000) /* Data byte 3 */ + +/****************** Bit definition for CAN_TXMDH0R register *******************/ +#define CAN_TXMDH0R_DATA4 ((uint32_t)0x000000FF) /* Data byte 4 */ +#define CAN_TXMDH0R_DATA5 ((uint32_t)0x0000FF00) /* Data byte 5 */ +#define CAN_TXMDH0R_DATA6 ((uint32_t)0x00FF0000) /* Data byte 6 */ +#define CAN_TXMDH0R_DATA7 ((uint32_t)0xFF000000) /* Data byte 7 */ + +/******************* Bit definition for CAN_TXMI1R register *******************/ +#define CAN_TXMI1R_TXRQ ((uint32_t)0x00000001) /* Transmit Mailbox Request */ +#define CAN_TXMI1R_RTR ((uint32_t)0x00000002) /* Remote Transmission Request */ +#define CAN_TXMI1R_IDE ((uint32_t)0x00000004) /* Identifier Extension */ +#define CAN_TXMI1R_EXID ((uint32_t)0x001FFFF8) /* Extended Identifier */ +#define CAN_TXMI1R_STID ((uint32_t)0xFFE00000) /* Standard Identifier or Extended Identifier */ + +/******************* Bit definition for CAN_TXMDT1R register ******************/ +#define CAN_TXMDT1R_DLC ((uint32_t)0x0000000F) /* Data Length Code */ +#define CAN_TXMDT1R_TGT ((uint32_t)0x00000100) /* Transmit Global Time */ +#define CAN_TXMDT1R_TIME ((uint32_t)0xFFFF0000) /* Message Time Stamp */ + +/******************* Bit definition for CAN_TXMDL1R register ******************/ +#define CAN_TXMDL1R_DATA0 ((uint32_t)0x000000FF) /* Data byte 0 */ +#define CAN_TXMDL1R_DATA1 ((uint32_t)0x0000FF00) /* Data byte 1 */ +#define CAN_TXMDL1R_DATA2 ((uint32_t)0x00FF0000) /* Data byte 2 */ +#define CAN_TXMDL1R_DATA3 ((uint32_t)0xFF000000) /* Data byte 3 */ + +/******************* Bit definition for CAN_TXMDH1R register ******************/ +#define CAN_TXMDH1R_DATA4 ((uint32_t)0x000000FF) /* Data byte 4 */ +#define CAN_TXMDH1R_DATA5 ((uint32_t)0x0000FF00) /* Data byte 5 */ +#define CAN_TXMDH1R_DATA6 ((uint32_t)0x00FF0000) /* Data byte 6 */ +#define CAN_TXMDH1R_DATA7 ((uint32_t)0xFF000000) /* Data byte 7 */ + +/******************* Bit definition for CAN_TXMI2R register *******************/ +#define CAN_TXMI2R_TXRQ ((uint32_t)0x00000001) /* Transmit Mailbox Request */ +#define CAN_TXMI2R_RTR ((uint32_t)0x00000002) /* Remote Transmission Request */ +#define CAN_TXMI2R_IDE ((uint32_t)0x00000004) /* Identifier Extension */ +#define CAN_TXMI2R_EXID ((uint32_t)0x001FFFF8) /* Extended identifier */ +#define CAN_TXMI2R_STID ((uint32_t)0xFFE00000) /* Standard Identifier or Extended Identifier */ + +/******************* Bit definition for CAN_TXMDT2R register ******************/ +#define CAN_TXMDT2R_DLC ((uint32_t)0x0000000F) /* Data Length Code */ +#define CAN_TXMDT2R_TGT ((uint32_t)0x00000100) /* Transmit Global Time */ +#define CAN_TXMDT2R_TIME ((uint32_t)0xFFFF0000) /* Message Time Stamp */ + +/******************* Bit definition for CAN_TXMDL2R register ******************/ +#define CAN_TXMDL2R_DATA0 ((uint32_t)0x000000FF) /* Data byte 0 */ +#define CAN_TXMDL2R_DATA1 ((uint32_t)0x0000FF00) /* Data byte 1 */ +#define CAN_TXMDL2R_DATA2 ((uint32_t)0x00FF0000) /* Data byte 2 */ +#define CAN_TXMDL2R_DATA3 ((uint32_t)0xFF000000) /* Data byte 3 */ + +/******************* Bit definition for CAN_TXMDH2R register ******************/ +#define CAN_TXMDH2R_DATA4 ((uint32_t)0x000000FF) /* Data byte 4 */ +#define CAN_TXMDH2R_DATA5 ((uint32_t)0x0000FF00) /* Data byte 5 */ +#define CAN_TXMDH2R_DATA6 ((uint32_t)0x00FF0000) /* Data byte 6 */ +#define CAN_TXMDH2R_DATA7 ((uint32_t)0xFF000000) /* Data byte 7 */ + +/******************* Bit definition for CAN_RXMI0R register *******************/ +#define CAN_RXMIOR_FDF ((uint32_t)0x00000001) +#define CAN_RXMI0R_RTR ((uint32_t)0x00000002) /* Remote Transmission Request */ +#define CAN_RXMI0R_IDE ((uint32_t)0x00000004) /* Identifier Extension */ +#define CAN_RXMI0R_EXID ((uint32_t)0x001FFFF8) /* Extended Identifier */ +#define CAN_RXMI0R_STID ((uint32_t)0xFFE00000) /* Standard Identifier or Extended Identifier */ + +/******************* Bit definition for CAN_RXMDT0R register ******************/ +#define CAN_RXMDT0R_DLC ((uint32_t)0x0000000F) /* Data Length Code */ +#define CAN_RXMDT0R_BRS ((uint32_t)0x00000010) +#define CAN_RXMDT0R_ESI ((uint32_t)0x00000020) +#define CAN_RXMDH0R_RES ((uint32_t)0x00000100) +#define CAN_RXMDT0R_FMI ((uint32_t)0x0000FF00) /* Filter Match Index */ +#define CAN_RXMDT0R_TIME ((uint32_t)0xFFFF0000) /* Message Time Stamp */ + +/******************* Bit definition for CAN_RXMDL0R register ******************/ +#define CAN_RXMDL0R_DATA0 ((uint32_t)0x000000FF) /* Data byte 0 */ +#define CAN_RXMDL0R_DATA1 ((uint32_t)0x0000FF00) /* Data byte 1 */ +#define CAN_RXMDL0R_DATA2 ((uint32_t)0x00FF0000) /* Data byte 2 */ +#define CAN_RXMDL0R_DATA3 ((uint32_t)0xFF000000) /* Data byte 3 */ + +/******************* Bit definition for CAN_RXMDH0R register ******************/ +#define CAN_RXMDH0R_DATA4 ((uint32_t)0x000000FF) /* Data byte 4 */ +#define CAN_RXMDH0R_DATA5 ((uint32_t)0x0000FF00) /* Data byte 5 */ +#define CAN_RXMDH0R_DATA6 ((uint32_t)0x00FF0000) /* Data byte 6 */ +#define CAN_RXMDH0R_DATA7 ((uint32_t)0xFF000000) /* Data byte 7 */ + +/******************* Bit definition for CAN_RXMI1R register *******************/ +#define CAN_RXMI1R_FDF ((uint32_t)0x00000001) +#define CAN_RXMI1R_RTR ((uint32_t)0x00000002) /* Remote Transmission Request */ +#define CAN_RXMI1R_IDE ((uint32_t)0x00000004) /* Identifier Extension */ +#define CAN_RXMI1R_EXID ((uint32_t)0x001FFFF8) /* Extended identifier */ +#define CAN_RXMI1R_STID ((uint32_t)0xFFE00000) /* Standard Identifier or Extended Identifier */ + +/******************* Bit definition for CAN_RXMDT1R register ******************/ +#define CAN_RXMDT1R_DLC ((uint32_t)0x0000000F) /* Data Length Code */ +#define CAN_RXMDT1R_BRS ((uint32_t)0x00000010) +#define CAN_RXMDT1R_ESI ((uint32_t)0x00000020) +#define CAN_RXMDH1R_RES ((uint32_t)0x00000100) +#define CAN_RXMDT1R_FMI ((uint32_t)0x0000FF00) /* Filter Match Index */ +#define CAN_RXMDT1R_TIME ((uint32_t)0xFFFF0000) /* Message Time Stamp */ + +/******************* Bit definition for CAN_RXMDL1R register ******************/ +#define CAN_RXMDL1R_DATA0 ((uint32_t)0x000000FF) /* Data byte 0 */ +#define CAN_RXMDL1R_DATA1 ((uint32_t)0x0000FF00) /* Data byte 1 */ +#define CAN_RXMDL1R_DATA2 ((uint32_t)0x00FF0000) /* Data byte 2 */ +#define CAN_RXMDL1R_DATA3 ((uint32_t)0xFF000000) /* Data byte 3 */ + +/******************* Bit definition for CAN_RXMDH1R register ******************/ +#define CAN_RXMDH1R_DATA4 ((uint32_t)0x000000FF) /* Data byte 4 */ +#define CAN_RXMDH1R_DATA5 ((uint32_t)0x0000FF00) /* Data byte 5 */ +#define CAN_RXMDH1R_DATA6 ((uint32_t)0x00FF0000) /* Data byte 6 */ +#define CAN_RXMDH1R_DATA7 ((uint32_t)0xFF000000) /* Data byte 7 */ + +/******************* Bit definition for CAN_FCTLR register ********************/ +#define CAN_FCTLR_FINIT ((uint8_t)0x01) /* Filter Init Mode */ + +/******************* Bit definition for CAN_FMCFGR register *******************/ +#define CAN_FMCFGR_FBM ((uint32_t)0x00003FFF) /* Filter Mode */ +#define CAN_FMCFGR_FBM0 ((uint32_t)0x00000001) /* Filter Init Mode bit 0 */ +#define CAN_FMCFGR_FBM1 ((uint32_t)0x00000002) /* Filter Init Mode bit 1 */ +#define CAN_FMCFGR_FBM2 ((uint32_t)0x00000004) /* Filter Init Mode bit 2 */ +#define CAN_FMCFGR_FBM3 ((uint32_t)0x00000008) /* Filter Init Mode bit 3 */ +#define CAN_FMCFGR_FBM4 ((uint32_t)0x00000010) /* Filter Init Mode bit 4 */ +#define CAN_FMCFGR_FBM5 ((uint32_t)0x00000020) /* Filter Init Mode bit 5 */ +#define CAN_FMCFGR_FBM6 ((uint32_t)0x00000040) /* Filter Init Mode bit 6 */ +#define CAN_FMCFGR_FBM7 ((uint32_t)0x00000080) /* Filter Init Mode bit 7 */ +#define CAN_FMCFGR_FBM8 ((uint32_t)0x00000100) /* Filter Init Mode bit 8 */ +#define CAN_FMCFGR_FBM9 ((uint32_t)0x00000200) /* Filter Init Mode bit 9 */ +#define CAN_FMCFGR_FBM10 ((uint32_t)0x00000400) /* Filter Init Mode bit 10 */ +#define CAN_FMCFGR_FBM11 ((uint32_t)0x00000800) /* Filter Init Mode bit 11 */ +#define CAN_FMCFGR_FBM12 ((uint32_t)0x00001000) /* Filter Init Mode bit 12 */ +#define CAN_FMCFGR_FBM13 ((uint32_t)0x00002000) /* Filter Init Mode bit 13 */ +#define CAN_FMCFGR_FBM14 ((uint32_t)0x00004000) /* Filter Init Mode bit 14 */ +#define CAN_FMCFGR_FBM15 ((uint32_t)0x00008000) /* Filter Init Mode bit 15 */ +#define CAN_FMCFGR_FBM16 ((uint32_t)0x00010000) /* Filter Init Mode bit 16 */ +#define CAN_FMCFGR_FBM17 ((uint32_t)0x00020000) /* Filter Init Mode bit 17 */ +#define CAN_FMCFGR_FBM18 ((uint32_t)0x00040000) /* Filter Init Mode bit 18 */ +#define CAN_FMCFGR_FBM19 ((uint32_t)0x00080000) /* Filter Init Mode bit 19 */ +#define CAN_FMCFGR_FBM20 ((uint32_t)0x00100000) /* Filter Init Mode bit 20 */ +#define CAN_FMCFGR_FBM21 ((uint32_t)0x00200000) /* Filter Init Mode bit 21 */ +#define CAN_FMCFGR_FBM22 ((uint32_t)0x00400000) /* Filter Init Mode bit 22 */ +#define CAN_FMCFGR_FBM23 ((uint32_t)0x00800000) /* Filter Init Mode bit 23 */ +#define CAN_FMCFGR_FBM24 ((uint32_t)0x01000000) /* Filter Init Mode bit 24 */ +#define CAN_FMCFGR_FBM25 ((uint32_t)0x02000000) /* Filter Init Mode bit 25 */ +#define CAN_FMCFGR_FBM26 ((uint32_t)0x04000000) /* Filter Init Mode bit 26 */ +#define CAN_FMCFGR_FBM27 ((uint32_t)0x08000000) /* Filter Init Mode bit 27 */ + +/******************* Bit definition for CAN_FSCFGR register *******************/ +#define CAN_FSCFGR_FSC ((uint32_t)0x00003FFF) /* Filter Scale Configuration */ +#define CAN_FSCFGR_FSC0 ((uint32_t)0x00000001) /* Filter Scale Configuration bit 0 */ +#define CAN_FSCFGR_FSC1 ((uint32_t)0x00000002) /* Filter Scale Configuration bit 1 */ +#define CAN_FSCFGR_FSC2 ((uint32_t)0x00000004) /* Filter Scale Configuration bit 2 */ +#define CAN_FSCFGR_FSC3 ((uint32_t)0x00000008) /* Filter Scale Configuration bit 3 */ +#define CAN_FSCFGR_FSC4 ((uint32_t)0x00000010) /* Filter Scale Configuration bit 4 */ +#define CAN_FSCFGR_FSC5 ((uint32_t)0x00000020) /* Filter Scale Configuration bit 5 */ +#define CAN_FSCFGR_FSC6 ((uint32_t)0x00000040) /* Filter Scale Configuration bit 6 */ +#define CAN_FSCFGR_FSC7 ((uint32_t)0x00000080) /* Filter Scale Configuration bit 7 */ +#define CAN_FSCFGR_FSC8 ((uint32_t)0x00000100) /* Filter Scale Configuration bit 8 */ +#define CAN_FSCFGR_FSC9 ((uint32_t)0x00000200) /* Filter Scale Configuration bit 9 */ +#define CAN_FSCFGR_FSC10 ((uint32_t)0x00000400) /* Filter Scale Configuration bit 10 */ +#define CAN_FSCFGR_FSC11 ((uint32_t)0x00000800) /* Filter Scale Configuration bit 11 */ +#define CAN_FSCFGR_FSC12 ((uint32_t)0x00001000) /* Filter Scale Configuration bit 12 */ +#define CAN_FSCFGR_FSC13 ((uint32_t)0x00002000) /* Filter Scale Configuration bit 13 */ +#define CAN_FSCFGR_FSC14 ((uint32_t)0x00004000) /* Filter Scale Configuration bit 14 */ +#define CAN_FSCFGR_FSC15 ((uint32_t)0x00008000) /* Filter Scale Configuration bit 15 */ +#define CAN_FSCFGR_FSC16 ((uint32_t)0x00010000) /* Filter Scale Configuration bit 16 */ +#define CAN_FSCFGR_FSC17 ((uint32_t)0x00020000) /* Filter Scale Configuration bit 17 */ +#define CAN_FSCFGR_FSC18 ((uint32_t)0x00040000) /* Filter Scale Configuration bit 18 */ +#define CAN_FSCFGR_FSC19 ((uint32_t)0x00080000) /* Filter Scale Configuration bit 19 */ +#define CAN_FSCFGR_FSC20 ((uint32_t)0x00100000) /* Filter Scale Configuration bit 20 */ +#define CAN_FSCFGR_FSC21 ((uint32_t)0x00200000) /* Filter Scale Configuration bit 21 */ +#define CAN_FSCFGR_FSC22 ((uint32_t)0x00400000) /* Filter Scale Configuration bit 22 */ +#define CAN_FSCFGR_FSC23 ((uint32_t)0x00800000) /* Filter Scale Configuration bit 23 */ +#define CAN_FSCFGR_FSC24 ((uint32_t)0x01000000) /* Filter Scale Configuration bit 24 */ +#define CAN_FSCFGR_FSC25 ((uint32_t)0x02000000) /* Filter Scale Configuration bit 25 */ +#define CAN_FSCFGR_FSC26 ((uint32_t)0x04000000) /* Filter Scale Configuration bit 26 */ +#define CAN_FSCFGR_FSC27 ((uint32_t)0x08000000) /* Filter Scale Configuration bit 27 */ + +/****************** Bit definition for CAN_FAFIFOR register *******************/ +#define CAN_FAFIFOR_FFA ((uint32_t)0x00003FFF) /* Filter FIFO Assignment */ +#define CAN_FAFIFOR_FFA0 ((uint32_t)0x00000001) /* Filter FIFO Assignment for Filter 0 */ +#define CAN_FAFIFOR_FFA1 ((uint32_t)0x00000002) /* Filter FIFO Assignment for Filter 1 */ +#define CAN_FAFIFOR_FFA2 ((uint32_t)0x00000004) /* Filter FIFO Assignment for Filter 2 */ +#define CAN_FAFIFOR_FFA3 ((uint32_t)0x00000008) /* Filter FIFO Assignment for Filter 3 */ +#define CAN_FAFIFOR_FFA4 ((uint32_t)0x00000010) /* Filter FIFO Assignment for Filter 4 */ +#define CAN_FAFIFOR_FFA5 ((uint32_t)0x00000020) /* Filter FIFO Assignment for Filter 5 */ +#define CAN_FAFIFOR_FFA6 ((uint32_t)0x00000040) /* Filter FIFO Assignment for Filter 6 */ +#define CAN_FAFIFOR_FFA7 ((uint32_t)0x00000080) /* Filter FIFO Assignment for Filter 7 */ +#define CAN_FAFIFOR_FFA8 ((uint32_t)0x00000100) /* Filter FIFO Assignment for Filter 8 */ +#define CAN_FAFIFOR_FFA9 ((uint32_t)0x00000200) /* Filter FIFO Assignment for Filter 9 */ +#define CAN_FAFIFOR_FFA10 ((uint32_t)0x00000400) /* Filter FIFO Assignment for Filter 10 */ +#define CAN_FAFIFOR_FFA11 ((uint32_t)0x00000800) /* Filter FIFO Assignment for Filter 11 */ +#define CAN_FAFIFOR_FFA12 ((uint32_t)0x00001000) /* Filter FIFO Assignment for Filter 12 */ +#define CAN_FAFIFOR_FFA13 ((uint32_t)0x00002000) /* Filter FIFO Assignment for Filter 13 */ +#define CAN_FAFIFOR_FFA14 ((uint32_t)0x00004000) /* Filter FIFO Assignment for Filter 14 */ +#define CAN_FAFIFOR_FFA15 ((uint32_t)0x00008000) /* Filter FIFO Assignment for Filter 15 */ +#define CAN_FAFIFOR_FFA16 ((uint32_t)0x00010000) /* Filter FIFO Assignment for Filter 16 */ +#define CAN_FAFIFOR_FFA17 ((uint32_t)0x00020000) /* Filter FIFO Assignment for Filter 17 */ +#define CAN_FAFIFOR_FFA18 ((uint32_t)0x00040000) /* Filter FIFO Assignment for Filter 18 */ +#define CAN_FAFIFOR_FFA19 ((uint32_t)0x00080000) /* Filter FIFO Assignment for Filter 19 */ +#define CAN_FAFIFOR_FFA20 ((uint32_t)0x00100000) /* Filter FIFO Assignment for Filter 20 */ +#define CAN_FAFIFOR_FFA21 ((uint32_t)0x00200000) /* Filter FIFO Assignment for Filter 21 */ +#define CAN_FAFIFOR_FFA22 ((uint32_t)0x00400000) /* Filter FIFO Assignment for Filter 22 */ +#define CAN_FAFIFOR_FFA23 ((uint32_t)0x00800000) /* Filter FIFO Assignment for Filter 23 */ +#define CAN_FAFIFOR_FFA24 ((uint32_t)0x01000000) /* Filter FIFO Assignment for Filter 24 */ +#define CAN_FAFIFOR_FFA25 ((uint32_t)0x02000000) /* Filter FIFO Assignment for Filter 25 */ +#define CAN_FAFIFOR_FFA26 ((uint32_t)0x04000000) /* Filter FIFO Assignment for Filter 26 */ +#define CAN_FAFIFOR_FFA27 ((uint32_t)0x08000000) /* Filter FIFO Assignment for Filter 27 */ + +/******************* Bit definition for CAN_FWR register *******************/ +#define CAN_FWR_FACT ((uint32_t)0x00003FFF) /* Filter Active */ +#define CAN_FWR_FACT0 ((uint32_t)0x00000001) /* Filter 0 Active */ +#define CAN_FWR_FACT1 ((uint32_t)0x00000002) /* Filter 1 Active */ +#define CAN_FWR_FACT2 ((uint32_t)0x00000004) /* Filter 2 Active */ +#define CAN_FWR_FACT3 ((uint32_t)0x00000008) /* Filter 3 Active */ +#define CAN_FWR_FACT4 ((uint32_t)0x00000010) /* Filter 4 Active */ +#define CAN_FWR_FACT5 ((uint32_t)0x00000020) /* Filter 5 Active */ +#define CAN_FWR_FACT6 ((uint32_t)0x00000040) /* Filter 6 Active */ +#define CAN_FWR_FACT7 ((uint32_t)0x00000080) /* Filter 7 Active */ +#define CAN_FWR_FACT8 ((uint32_t)0x00000100) /* Filter 8 Active */ +#define CAN_FWR_FACT9 ((uint32_t)0x00000200) /* Filter 9 Active */ +#define CAN_FWR_FACT10 ((uint32_t)0x00000400) /* Filter 10 Active */ +#define CAN_FWR_FACT11 ((uint32_t)0x00000800) /* Filter 11 Active */ +#define CAN_FWR_FACT12 ((uint32_t)0x00001000) /* Filter 12 Active */ +#define CAN_FWR_FACT13 ((uint32_t)0x00002000) /* Filter 13 Active */ +#define CAN_FWR_FACT14 ((uint32_t)0x00004000) /* Filter 14 Active */ +#define CAN_FWR_FACT15 ((uint32_t)0x00008000) /* Filter 15 Active */ +#define CAN_FWR_FACT16 ((uint32_t)0x00010000) /* Filter 16 Active */ +#define CAN_FWR_FACT17 ((uint32_t)0x00020000) /* Filter 17 Active */ +#define CAN_FWR_FACT18 ((uint32_t)0x00040000) /* Filter 18 Active */ +#define CAN_FWR_FACT19 ((uint32_t)0x00080000) /* Filter 19 Active */ +#define CAN_FWR_FACT20 ((uint32_t)0x00100000) /* Filter 20 Active */ +#define CAN_FWR_FACT21 ((uint32_t)0x00200000) /* Filter 21 Active */ +#define CAN_FWR_FACT22 ((uint32_t)0x00400000) /* Filter 22 Active */ +#define CAN_FWR_FACT23 ((uint32_t)0x00800000) /* Filter 23 Active */ +#define CAN_FWR_FACT24 ((uint32_t)0x01000000) /* Filter 24 Active */ +#define CAN_FWR_FACT25 ((uint32_t)0x02000000) /* Filter 25 Active */ +#define CAN_FWR_FACT26 ((uint32_t)0x04000000) /* Filter 26 Active */ +#define CAN_FWR_FACT27 ((uint32_t)0x08000000) /* Filter 27 Active */ + +/******************* Bit definition for CAN_F0R1 register *******************/ +#define CAN_F0R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F0R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F0R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F0R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F0R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F0R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F0R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F0R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F0R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F0R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F0R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F0R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F0R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F0R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F0R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F0R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F0R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F0R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F0R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F0R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F0R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F0R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F0R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F0R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F0R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F0R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F0R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F0R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F0R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F0R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F0R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F0R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F1R1 register *******************/ +#define CAN_F1R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F1R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F1R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F1R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F1R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F1R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F1R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F1R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F1R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F1R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F1R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F1R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F1R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F1R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F1R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F1R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F1R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F1R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F1R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F1R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F1R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F1R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F1R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F1R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F1R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F1R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F1R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F1R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F1R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F1R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F1R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F1R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F2R1 register *******************/ +#define CAN_F2R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F2R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F2R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F2R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F2R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F2R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F2R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F2R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F2R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F2R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F2R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F2R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F2R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F2R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F2R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F2R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F2R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F2R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F2R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F2R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F2R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F2R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F2R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F2R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F2R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F2R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F2R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F2R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F2R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F2R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F2R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F2R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F3R1 register *******************/ +#define CAN_F3R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F3R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F3R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F3R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F3R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F3R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F3R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F3R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F3R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F3R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F3R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F3R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F3R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F3R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F3R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F3R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F3R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F3R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F3R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F3R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F3R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F3R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F3R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F3R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F3R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F3R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F3R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F3R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F3R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F3R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F3R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F3R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F4R1 register *******************/ +#define CAN_F4R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F4R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F4R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F4R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F4R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F4R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F4R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F4R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F4R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F4R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F4R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F4R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F4R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F4R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F4R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F4R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F4R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F4R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F4R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F4R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F4R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F4R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F4R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F4R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F4R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F4R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F4R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F4R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F4R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F4R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F4R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F4R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F5R1 register *******************/ +#define CAN_F5R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F5R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F5R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F5R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F5R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F5R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F5R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F5R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F5R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F5R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F5R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F5R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F5R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F5R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F5R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F5R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F5R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F5R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F5R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F5R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F5R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F5R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F5R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F5R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F5R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F5R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F5R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F5R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F5R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F5R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F5R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F5R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F6R1 register *******************/ +#define CAN_F6R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F6R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F6R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F6R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F6R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F6R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F6R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F6R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F6R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F6R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F6R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F6R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F6R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F6R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F6R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F6R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F6R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F6R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F6R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F6R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F6R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F6R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F6R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F6R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F6R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F6R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F6R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F6R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F6R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F6R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F6R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F6R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F7R1 register *******************/ +#define CAN_F7R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F7R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F7R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F7R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F7R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F7R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F7R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F7R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F7R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F7R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F7R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F7R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F7R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F7R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F7R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F7R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F7R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F7R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F7R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F7R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F7R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F7R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F7R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F7R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F7R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F7R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F7R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F7R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F7R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F7R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F7R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F7R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F8R1 register *******************/ +#define CAN_F8R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F8R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F8R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F8R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F8R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F8R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F8R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F8R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F8R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F8R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F8R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F8R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F8R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F8R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F8R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F8R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F8R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F8R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F8R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F8R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F8R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F8R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F8R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F8R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F8R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F8R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F8R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F8R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F8R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F8R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F8R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F8R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F9R1 register *******************/ +#define CAN_F9R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F9R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F9R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F9R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F9R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F9R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F9R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F9R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F9R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F9R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F9R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F9R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F9R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F9R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F9R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F9R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F9R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F9R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F9R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F9R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F9R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F9R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F9R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F9R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F9R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F9R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F9R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F9R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F9R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F9R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F9R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F9R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F10R1 register ******************/ +#define CAN_F10R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F10R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F10R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F10R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F10R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F10R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F10R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F10R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F10R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F10R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F10R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F10R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F10R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F10R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F10R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F10R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F10R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F10R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F10R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F10R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F10R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F10R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F10R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F10R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F10R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F10R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F10R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F10R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F10R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F10R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F10R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F10R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F11R1 register ******************/ +#define CAN_F11R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F11R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F11R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F11R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F11R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F11R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F11R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F11R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F11R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F11R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F11R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F11R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F11R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F11R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F11R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F11R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F11R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F11R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F11R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F11R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F11R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F11R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F11R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F11R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F11R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F11R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F11R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F11R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F11R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F11R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F11R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F11R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F12R1 register ******************/ +#define CAN_F12R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F12R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F12R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F12R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F12R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F12R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F12R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F12R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F12R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F12R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F12R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F12R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F12R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F12R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F12R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F12R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F12R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F12R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F12R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F12R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F12R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F12R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F12R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F12R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F12R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F12R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F12R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F12R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F12R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F12R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F12R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F12R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F13R1 register ******************/ +#define CAN_F13R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F13R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F13R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F13R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F13R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F13R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F13R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F13R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F13R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F13R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F13R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F13R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F13R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F13R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F13R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F13R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F13R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F13R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F13R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F13R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F13R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F13R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F13R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F13R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F13R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F13R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F13R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F13R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F13R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F13R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F13R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F13R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F0R2 register *******************/ +#define CAN_F0R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F0R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F0R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F0R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F0R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F0R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F0R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F0R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F0R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F0R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F0R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F0R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F0R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F0R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F0R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F0R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F0R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F0R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F0R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F0R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F0R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F0R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F0R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F0R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F0R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F0R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F0R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F0R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F0R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F0R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F0R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F0R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F1R2 register *******************/ +#define CAN_F1R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F1R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F1R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F1R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F1R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F1R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F1R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F1R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F1R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F1R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F1R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F1R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F1R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F1R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F1R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F1R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F1R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F1R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F1R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F1R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F1R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F1R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F1R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F1R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F1R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F1R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F1R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F1R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F1R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F1R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F1R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F1R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F2R2 register *******************/ +#define CAN_F2R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F2R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F2R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F2R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F2R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F2R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F2R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F2R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F2R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F2R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F2R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F2R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F2R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F2R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F2R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F2R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F2R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F2R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F2R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F2R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F2R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F2R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F2R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F2R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F2R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F2R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F2R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F2R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F2R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F2R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F2R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F2R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F3R2 register *******************/ +#define CAN_F3R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F3R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F3R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F3R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F3R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F3R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F3R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F3R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F3R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F3R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F3R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F3R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F3R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F3R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F3R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F3R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F3R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F3R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F3R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F3R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F3R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F3R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F3R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F3R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F3R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F3R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F3R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F3R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F3R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F3R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F3R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F3R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F4R2 register *******************/ +#define CAN_F4R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F4R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F4R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F4R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F4R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F4R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F4R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F4R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F4R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F4R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F4R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F4R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F4R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F4R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F4R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F4R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F4R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F4R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F4R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F4R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F4R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F4R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F4R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F4R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F4R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F4R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F4R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F4R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F4R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F4R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F4R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F4R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F5R2 register *******************/ +#define CAN_F5R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F5R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F5R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F5R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F5R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F5R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F5R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F5R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F5R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F5R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F5R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F5R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F5R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F5R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F5R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F5R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F5R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F5R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F5R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F5R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F5R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F5R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F5R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F5R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F5R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F5R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F5R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F5R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F5R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F5R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F5R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F5R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F6R2 register *******************/ +#define CAN_F6R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F6R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F6R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F6R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F6R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F6R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F6R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F6R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F6R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F6R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F6R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F6R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F6R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F6R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F6R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F6R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F6R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F6R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F6R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F6R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F6R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F6R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F6R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F6R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F6R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F6R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F6R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F6R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F6R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F6R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F6R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F6R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F7R2 register *******************/ +#define CAN_F7R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F7R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F7R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F7R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F7R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F7R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F7R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F7R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F7R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F7R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F7R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F7R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F7R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F7R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F7R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F7R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F7R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F7R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F7R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F7R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F7R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F7R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F7R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F7R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F7R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F7R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F7R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F7R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F7R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F7R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F7R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F7R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F8R2 register *******************/ +#define CAN_F8R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F8R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F8R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F8R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F8R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F8R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F8R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F8R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F8R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F8R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F8R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F8R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F8R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F8R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F8R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F8R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F8R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F8R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F8R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F8R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F8R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F8R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F8R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F8R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F8R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F8R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F8R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F8R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F8R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F8R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F8R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F8R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F9R2 register *******************/ +#define CAN_F9R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F9R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F9R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F9R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F9R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F9R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F9R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F9R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F9R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F9R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F9R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F9R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F9R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F9R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F9R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F9R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F9R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F9R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F9R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F9R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F9R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F9R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F9R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F9R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F9R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F9R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F9R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F9R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F9R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F9R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F9R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F9R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F10R2 register ******************/ +#define CAN_F10R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F10R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F10R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F10R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F10R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F10R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F10R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F10R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F10R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F10R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F10R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F10R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F10R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F10R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F10R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F10R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F10R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F10R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F10R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F10R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F10R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F10R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F10R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F10R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F10R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F10R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F10R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F10R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F10R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F10R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F10R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F10R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F11R2 register ******************/ +#define CAN_F11R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F11R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F11R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F11R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F11R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F11R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F11R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F11R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F11R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F11R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F11R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F11R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F11R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F11R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F11R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F11R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F11R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F11R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F11R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F11R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F11R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F11R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F11R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F11R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F11R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F11R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F11R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F11R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F11R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F11R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F11R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F11R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F12R2 register ******************/ +#define CAN_F12R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F12R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F12R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F12R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F12R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F12R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F12R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F12R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F12R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F12R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F12R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F12R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F12R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F12R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F12R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F12R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F12R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F12R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F12R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F12R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F12R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F12R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F12R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F12R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F12R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F12R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F12R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F12R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F12R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F12R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F12R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F12R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F13R2 register ******************/ +#define CAN_F13R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F13R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F13R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F13R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F13R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F13R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F13R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F13R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F13R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F13R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F13R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F13R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F13R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F13R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F13R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F13R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F13R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F13R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F13R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F13R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F13R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F13R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F13R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F13R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F13R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F13R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F13R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F13R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F13R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F13R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F13R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F13R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************************************************************************/ +/* CRC Calculation Unit */ +/******************************************************************************/ + +/******************* Bit definition for CRC_DATAR register *********************/ +#define CRC_DATAR_DR ((uint32_t)0xFFFFFFFF) /* Data register bits */ + +/******************* Bit definition for CRC_IDATAR register ********************/ +#define CRC_IDR_IDATAR ((uint8_t)0xFF) /* General-purpose 8-bit data register bits */ + +/******************** Bit definition for CRC_CTLR register ********************/ +#define CRC_CTLR_RESET ((uint8_t)0x01) /* RESET bit */ + +/******************************************************************************/ +/* DMA Controller */ +/******************************************************************************/ + +/******************* Bit definition for DMA_INTFR register ********************/ +#define DMA_GIF1 ((uint32_t)0x00000001) /* Channel 1 Global interrupt flag */ +#define DMA_TCIF1 ((uint32_t)0x00000002) /* Channel 1 Transfer Complete flag */ +#define DMA_HTIF1 ((uint32_t)0x00000004) /* Channel 1 Half Transfer flag */ +#define DMA_TEIF1 ((uint32_t)0x00000008) /* Channel 1 Transfer Error flag */ +#define DMA_GIF2 ((uint32_t)0x00000010) /* Channel 2 Global interrupt flag */ +#define DMA_TCIF2 ((uint32_t)0x00000020) /* Channel 2 Transfer Complete flag */ +#define DMA_HTIF2 ((uint32_t)0x00000040) /* Channel 2 Half Transfer flag */ +#define DMA_TEIF2 ((uint32_t)0x00000080) /* Channel 2 Transfer Error flag */ +#define DMA_GIF3 ((uint32_t)0x00000100) /* Channel 3 Global interrupt flag */ +#define DMA_TCIF3 ((uint32_t)0x00000200) /* Channel 3 Transfer Complete flag */ +#define DMA_HTIF3 ((uint32_t)0x00000400) /* Channel 3 Half Transfer flag */ +#define DMA_TEIF3 ((uint32_t)0x00000800) /* Channel 3 Transfer Error flag */ +#define DMA_GIF4 ((uint32_t)0x00001000) /* Channel 4 Global interrupt flag */ +#define DMA_TCIF4 ((uint32_t)0x00002000) /* Channel 4 Transfer Complete flag */ +#define DMA_HTIF4 ((uint32_t)0x00004000) /* Channel 4 Half Transfer flag */ +#define DMA_TEIF4 ((uint32_t)0x00008000) /* Channel 4 Transfer Error flag */ +#define DMA_GIF5 ((uint32_t)0x00010000) /* Channel 5 Global interrupt flag */ +#define DMA_TCIF5 ((uint32_t)0x00020000) /* Channel 5 Transfer Complete flag */ +#define DMA_HTIF5 ((uint32_t)0x00040000) /* Channel 5 Half Transfer flag */ +#define DMA_TEIF5 ((uint32_t)0x00080000) /* Channel 5 Transfer Error flag */ +#define DMA_GIF6 ((uint32_t)0x00100000) /* Channel 6 Global interrupt flag */ +#define DMA_TCIF6 ((uint32_t)0x00200000) /* Channel 6 Transfer Complete flag */ +#define DMA_HTIF6 ((uint32_t)0x00400000) /* Channel 6 Half Transfer flag */ +#define DMA_TEIF6 ((uint32_t)0x00800000) /* Channel 6 Transfer Error flag */ +#define DMA_GIF7 ((uint32_t)0x01000000) /* Channel 7 Global interrupt flag */ +#define DMA_TCIF7 ((uint32_t)0x02000000) /* Channel 7 Transfer Complete flag */ +#define DMA_HTIF7 ((uint32_t)0x04000000) /* Channel 7 Half Transfer flag */ +#define DMA_TEIF7 ((uint32_t)0x08000000) /* Channel 7 Transfer Error flag */ +#define DMA_GIF8 ((uint32_t)0x10000000) /* Channel 8 Global interrupt flag */ +#define DMA_TCIF8 ((uint32_t)0x20000000) /* Channel 8 Transfer Complete flag */ +#define DMA_HTIF8 ((uint32_t)0x40000000) /* Channel 8 Half Transfer flag */ +#define DMA_TEIF8 ((uint32_t)0x80000000) /* Channel 8 Transfer Error flag */ + +/******************* Bit definition for DMA_INTFCR register *******************/ +#define DMA_CGIF1 ((uint32_t)0x00000001) /* Channel 1 Global interrupt clear */ +#define DMA_CTCIF1 ((uint32_t)0x00000002) /* Channel 1 Transfer Complete clear */ +#define DMA_CHTIF1 ((uint32_t)0x00000004) /* Channel 1 Half Transfer clear */ +#define DMA_CTEIF1 ((uint32_t)0x00000008) /* Channel 1 Transfer Error clear */ +#define DMA_CGIF2 ((uint32_t)0x00000010) /* Channel 2 Global interrupt clear */ +#define DMA_CTCIF2 ((uint32_t)0x00000020) /* Channel 2 Transfer Complete clear */ +#define DMA_CHTIF2 ((uint32_t)0x00000040) /* Channel 2 Half Transfer clear */ +#define DMA_CTEIF2 ((uint32_t)0x00000080) /* Channel 2 Transfer Error clear */ +#define DMA_CGIF3 ((uint32_t)0x00000100) /* Channel 3 Global interrupt clear */ +#define DMA_CTCIF3 ((uint32_t)0x00000200) /* Channel 3 Transfer Complete clear */ +#define DMA_CHTIF3 ((uint32_t)0x00000400) /* Channel 3 Half Transfer clear */ +#define DMA_CTEIF3 ((uint32_t)0x00000800) /* Channel 3 Transfer Error clear */ +#define DMA_CGIF4 ((uint32_t)0x00001000) /* Channel 4 Global interrupt clear */ +#define DMA_CTCIF4 ((uint32_t)0x00002000) /* Channel 4 Transfer Complete clear */ +#define DMA_CHTIF4 ((uint32_t)0x00004000) /* Channel 4 Half Transfer clear */ +#define DMA_CTEIF4 ((uint32_t)0x00008000) /* Channel 4 Transfer Error clear */ +#define DMA_CGIF5 ((uint32_t)0x00010000) /* Channel 5 Global interrupt clear */ +#define DMA_CTCIF5 ((uint32_t)0x00020000) /* Channel 5 Transfer Complete clear */ +#define DMA_CHTIF5 ((uint32_t)0x00040000) /* Channel 5 Half Transfer clear */ +#define DMA_CTEIF5 ((uint32_t)0x00080000) /* Channel 5 Transfer Error clear */ +#define DMA_CGIF6 ((uint32_t)0x00100000) /* Channel 6 Global interrupt clear */ +#define DMA_CTCIF6 ((uint32_t)0x00200000) /* Channel 6 Transfer Complete clear */ +#define DMA_CHTIF6 ((uint32_t)0x00400000) /* Channel 6 Half Transfer clear */ +#define DMA_CTEIF6 ((uint32_t)0x00800000) /* Channel 6 Transfer Error clear */ +#define DMA_CGIF7 ((uint32_t)0x01000000) /* Channel 7 Global interrupt clear */ +#define DMA_CTCIF7 ((uint32_t)0x02000000) /* Channel 7 Transfer Complete clear */ +#define DMA_CHTIF7 ((uint32_t)0x04000000) /* Channel 7 Half Transfer clear */ +#define DMA_CTEIF7 ((uint32_t)0x08000000) /* Channel 7 Transfer Error clear */ +#define DMA_CGIF8 ((uint32_t)0x10000000) /* Channel 8 Global interrupt clear */ +#define DMA_CTCIF8 ((uint32_t)0x20000000) /* Channel 8 Transfer Complete clear */ +#define DMA_CHTIF8 ((uint32_t)0x40000000) /* Channel 8 Half Transfer clear */ +#define DMA_CTEIF8 ((uint32_t)0x80000000) /* Channel 8 Transfer Error clear */ + +/******************* Bit definition for DMA_CFGR1 register *******************/ +#define DMA_CFGR1_EN ((uint16_t)0x0001) /* Channel enable*/ +#define DMA_CFGR1_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */ +#define DMA_CFGR1_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */ +#define DMA_CFGR1_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */ +#define DMA_CFGR1_DIR ((uint16_t)0x0010) /* Data transfer direction */ +#define DMA_CFGR1_CIRC ((uint16_t)0x0020) /* Circular mode */ +#define DMA_CFGR1_PINC ((uint16_t)0x0040) /* Peripheral increment mode */ +#define DMA_CFGR1_MINC ((uint16_t)0x0080) /* Memory increment mode */ + +#define DMA_CFGR1_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CFGR1_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */ +#define DMA_CFGR1_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */ + +#define DMA_CFGR1_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */ +#define DMA_CFGR1_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */ +#define DMA_CFGR1_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */ + +#define DMA_CFGR1_PL ((uint16_t)0x3000) /* PL[1:0] bits(Channel Priority level) */ +#define DMA_CFGR1_PL_0 ((uint16_t)0x1000) /* Bit 0 */ +#define DMA_CFGR1_PL_1 ((uint16_t)0x2000) /* Bit 1 */ + +#define DMA_CFGR1_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode */ + +/******************* Bit definition for DMA_CFGR2 register *******************/ +#define DMA_CFGR2_EN ((uint16_t)0x0001) /* Channel enable */ +#define DMA_CFGR2_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */ +#define DMA_CFGR2_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */ +#define DMA_CFGR2_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */ +#define DMA_CFGR2_DIR ((uint16_t)0x0010) /* Data transfer direction */ +#define DMA_CFGR2_CIRC ((uint16_t)0x0020) /* Circular mode */ +#define DMA_CFGR2_PINC ((uint16_t)0x0040) /* Peripheral increment mode */ +#define DMA_CFGR2_MINC ((uint16_t)0x0080) /* Memory increment mode */ + +#define DMA_CFGR2_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CFGR2_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */ +#define DMA_CFGR2_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */ + +#define DMA_CFGR2_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */ +#define DMA_CFGR2_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */ +#define DMA_CFGR2_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */ + +#define DMA_CFGR2_PL ((uint16_t)0x3000) /* PL[1:0] bits (Channel Priority level) */ +#define DMA_CFGR2_PL_0 ((uint16_t)0x1000) /* Bit 0 */ +#define DMA_CFGR2_PL_1 ((uint16_t)0x2000) /* Bit 1 */ + +#define DMA_CFGR2_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode */ + +/******************* Bit definition for DMA_CFGR3 register *******************/ +#define DMA_CFGR3_EN ((uint16_t)0x0001) /* Channel enable */ +#define DMA_CFGR3_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */ +#define DMA_CFGR3_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */ +#define DMA_CFGR3_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */ +#define DMA_CFGR3_DIR ((uint16_t)0x0010) /* Data transfer direction */ +#define DMA_CFGR3_CIRC ((uint16_t)0x0020) /* Circular mode */ +#define DMA_CFGR3_PINC ((uint16_t)0x0040) /* Peripheral increment mode */ +#define DMA_CFGR3_MINC ((uint16_t)0x0080) /* Memory increment mode */ + +#define DMA_CFGR3_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CFGR3_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */ +#define DMA_CFGR3_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */ + +#define DMA_CFGR3_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */ +#define DMA_CFGR3_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */ +#define DMA_CFGR3_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */ + +#define DMA_CFGR3_PL ((uint16_t)0x3000) /* PL[1:0] bits (Channel Priority level) */ +#define DMA_CFGR3_PL_0 ((uint16_t)0x1000) /* Bit 0 */ +#define DMA_CFGR3_PL_1 ((uint16_t)0x2000) /* Bit 1 */ + +#define DMA_CFGR3_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode */ + +/******************* Bit definition for DMA_CFG4 register *******************/ +#define DMA_CFG4_EN ((uint16_t)0x0001) /* Channel enable */ +#define DMA_CFG4_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */ +#define DMA_CFG4_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */ +#define DMA_CFG4_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */ +#define DMA_CFG4_DIR ((uint16_t)0x0010) /* Data transfer direction */ +#define DMA_CFG4_CIRC ((uint16_t)0x0020) /* Circular mode */ +#define DMA_CFG4_PINC ((uint16_t)0x0040) /* Peripheral increment mode */ +#define DMA_CFG4_MINC ((uint16_t)0x0080) /* Memory increment mode */ + +#define DMA_CFG4_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CFG4_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */ +#define DMA_CFG4_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */ + +#define DMA_CFG4_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */ +#define DMA_CFG4_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */ +#define DMA_CFG4_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */ + +#define DMA_CFG4_PL ((uint16_t)0x3000) /* PL[1:0] bits (Channel Priority level) */ +#define DMA_CFG4_PL_0 ((uint16_t)0x1000) /* Bit 0 */ +#define DMA_CFG4_PL_1 ((uint16_t)0x2000) /* Bit 1 */ + +#define DMA_CFG4_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode */ + +/****************** Bit definition for DMA_CFG5 register *******************/ +#define DMA_CFG5_EN ((uint16_t)0x0001) /* Channel enable */ +#define DMA_CFG5_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */ +#define DMA_CFG5_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */ +#define DMA_CFG5_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */ +#define DMA_CFG5_DIR ((uint16_t)0x0010) /* Data transfer direction */ +#define DMA_CFG5_CIRC ((uint16_t)0x0020) /* Circular mode */ +#define DMA_CFG5_PINC ((uint16_t)0x0040) /* Peripheral increment mode */ +#define DMA_CFG5_MINC ((uint16_t)0x0080) /* Memory increment mode */ + +#define DMA_CFG5_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CFG5_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */ +#define DMA_CFG5_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */ + +#define DMA_CFG5_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */ +#define DMA_CFG5_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */ +#define DMA_CFG5_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */ + +#define DMA_CFG5_PL ((uint16_t)0x3000) /* PL[1:0] bits (Channel Priority level) */ +#define DMA_CFG5_PL_0 ((uint16_t)0x1000) /* Bit 0 */ +#define DMA_CFG5_PL_1 ((uint16_t)0x2000) /* Bit 1 */ + +#define DMA_CFG5_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode enable */ + +/******************* Bit definition for DMA_CFG6 register *******************/ +#define DMA_CFG6_EN ((uint16_t)0x0001) /* Channel enable */ +#define DMA_CFG6_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */ +#define DMA_CFG6_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */ +#define DMA_CFG6_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */ +#define DMA_CFG6_DIR ((uint16_t)0x0010) /* Data transfer direction */ +#define DMA_CFG6_CIRC ((uint16_t)0x0020) /* Circular mode */ +#define DMA_CFG6_PINC ((uint16_t)0x0040) /* Peripheral increment mode */ +#define DMA_CFG6_MINC ((uint16_t)0x0080) /* Memory increment mode */ + +#define DMA_CFG6_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CFG6_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */ +#define DMA_CFG6_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */ + +#define DMA_CFG6_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */ +#define DMA_CFG6_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */ +#define DMA_CFG6_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */ + +#define DMA_CFG6_PL ((uint16_t)0x3000) /* PL[1:0] bits (Channel Priority level) */ +#define DMA_CFG6_PL_0 ((uint16_t)0x1000) /* Bit 0 */ +#define DMA_CFG6_PL_1 ((uint16_t)0x2000) /* Bit 1 */ + +#define DMA_CFG6_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode */ + +/******************* Bit definition for DMA_CFG7 register *******************/ +#define DMA_CFG7_EN ((uint16_t)0x0001) /* Channel enable */ +#define DMA_CFG7_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */ +#define DMA_CFG7_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */ +#define DMA_CFG7_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */ +#define DMA_CFG7_DIR ((uint16_t)0x0010) /* Data transfer direction */ +#define DMA_CFG7_CIRC ((uint16_t)0x0020) /* Circular mode */ +#define DMA_CFG7_PINC ((uint16_t)0x0040) /* Peripheral increment mode */ +#define DMA_CFG7_MINC ((uint16_t)0x0080) /* Memory increment mode */ + +#define DMA_CFG7_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CFG7_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */ +#define DMA_CFG7_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */ + +#define DMA_CFG7_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */ +#define DMA_CFG7_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */ +#define DMA_CFG7_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */ + +#define DMA_CFG7_PL ((uint16_t)0x3000) /* PL[1:0] bits (Channel Priority level) */ +#define DMA_CFG7_PL_0 ((uint16_t)0x1000) /* Bit 0 */ +#define DMA_CFG7_PL_1 ((uint16_t)0x2000) /* Bit 1 */ + +#define DMA_CFG7_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode enable */ + +/****************** Bit definition for DMA_CNTR1 register ******************/ +#define DMA_CNTR1_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */ + +/****************** Bit definition for DMA_CNTR2 register ******************/ +#define DMA_CNTR2_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */ + +/****************** Bit definition for DMA_CNTR3 register ******************/ +#define DMA_CNTR3_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */ + +/****************** Bit definition for DMA_CNTR4 register ******************/ +#define DMA_CNTR4_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */ + +/****************** Bit definition for DMA_CNTR5 register ******************/ +#define DMA_CNTR5_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */ + +/****************** Bit definition for DMA_CNTR6 register ******************/ +#define DMA_CNTR6_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */ + +/****************** Bit definition for DMA_CNTR7 register ******************/ +#define DMA_CNTR7_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */ + +/****************** Bit definition for DMA_CNTR8 register ******************/ +#define DMA_CNTR8_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */ + +/****************** Bit definition for DMA_PADDR1 register *******************/ +#define DMA_PADDR1_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */ + +/****************** Bit definition for DMA_PADDR2 register *******************/ +#define DMA_PADDR2_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */ + +/****************** Bit definition for DMA_PADDR3 register *******************/ +#define DMA_PADDR3_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */ + +/****************** Bit definition for DMA_PADDR4 register *******************/ +#define DMA_PADDR4_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */ + +/****************** Bit definition for DMA_PADDR5 register *******************/ +#define DMA_PADDR5_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */ + +/****************** Bit definition for DMA_PADDR6 register *******************/ +#define DMA_PADDR6_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */ + +/****************** Bit definition for DMA_PADDR7 register *******************/ +#define DMA_PADDR7_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */ + +/****************** Bit definition for DMA_PADDR8 register *******************/ +#define DMA_PADDR8_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */ + +/****************** Bit definition for DMA_MADDR1 register *******************/ +#define DMA_MADDR1_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */ + +/****************** Bit definition for DMA_MADDR2 register *******************/ +#define DMA_MADDR2_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */ + +/****************** Bit definition for DMA_MADDR3 register *******************/ +#define DMA_MADDR3_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */ + +/****************** Bit definition for DMA_MADDR4 register *******************/ +#define DMA_MADDR4_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */ + +/****************** Bit definition for DMA_MADDR5 register *******************/ +#define DMA_MADDR5_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */ + +/****************** Bit definition for DMA_MADDR6 register *******************/ +#define DMA_MADDR6_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */ + +/****************** Bit definition for DMA_MADDR7 register *******************/ +#define DMA_MADDR7_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */ + +/****************** Bit definition for DMA_MADDR8 register *******************/ +#define DMA_MADDR8_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */ + +/******************************************************************************/ +/* External Interrupt/Event Controller */ +/******************************************************************************/ + +/******************* Bit definition for EXTI_INTENR register *******************/ +#define EXTI_INTENR_MR0 ((uint32_t)0x00000001) /* Interrupt Mask on line 0 */ +#define EXTI_INTENR_MR1 ((uint32_t)0x00000002) /* Interrupt Mask on line 1 */ +#define EXTI_INTENR_MR2 ((uint32_t)0x00000004) /* Interrupt Mask on line 2 */ +#define EXTI_INTENR_MR3 ((uint32_t)0x00000008) /* Interrupt Mask on line 3 */ +#define EXTI_INTENR_MR4 ((uint32_t)0x00000010) /* Interrupt Mask on line 4 */ +#define EXTI_INTENR_MR5 ((uint32_t)0x00000020) /* Interrupt Mask on line 5 */ +#define EXTI_INTENR_MR6 ((uint32_t)0x00000040) /* Interrupt Mask on line 6 */ +#define EXTI_INTENR_MR7 ((uint32_t)0x00000080) /* Interrupt Mask on line 7 */ +#define EXTI_INTENR_MR8 ((uint32_t)0x00000100) /* Interrupt Mask on line 8 */ +#define EXTI_INTENR_MR9 ((uint32_t)0x00000200) /* Interrupt Mask on line 9 */ +#define EXTI_INTENR_MR10 ((uint32_t)0x00000400) /* Interrupt Mask on line 10 */ +#define EXTI_INTENR_MR11 ((uint32_t)0x00000800) /* Interrupt Mask on line 11 */ +#define EXTI_INTENR_MR12 ((uint32_t)0x00001000) /* Interrupt Mask on line 12 */ +#define EXTI_INTENR_MR13 ((uint32_t)0x00002000) /* Interrupt Mask on line 13 */ +#define EXTI_INTENR_MR14 ((uint32_t)0x00004000) /* Interrupt Mask on line 14 */ +#define EXTI_INTENR_MR15 ((uint32_t)0x00008000) /* Interrupt Mask on line 15 */ +#define EXTI_INTENR_MR16 ((uint32_t)0x00010000) /* Interrupt Mask on line 16 */ +#define EXTI_INTENR_MR17 ((uint32_t)0x00020000) /* Interrupt Mask on line 17 */ +#define EXTI_INTENR_MR18 ((uint32_t)0x00040000) /* Interrupt Mask on line 18 */ +#define EXTI_INTENR_MR19 ((uint32_t)0x00080000) /* Interrupt Mask on line 19 */ +#define EXTI_INTENR_MR20 ((uint32_t)0x00100000) /* Interrupt Mask on line 20 */ +#define EXTI_INTENR_MR21 ((uint32_t)0x00200000) /* Interrupt Mask on line 21 */ +#define EXTI_INTENR_MR22 ((uint32_t)0x00400000) /* Interrupt Mask on line 22 */ + +/******************* Bit definition for EXTI_EVENR register *******************/ +#define EXTI_EVENR_MR0 ((uint32_t)0x00000001) /* Event Mask on line 0 */ +#define EXTI_EVENR_MR1 ((uint32_t)0x00000002) /* Event Mask on line 1 */ +#define EXTI_EVENR_MR2 ((uint32_t)0x00000004) /* Event Mask on line 2 */ +#define EXTI_EVENR_MR3 ((uint32_t)0x00000008) /* Event Mask on line 3 */ +#define EXTI_EVENR_MR4 ((uint32_t)0x00000010) /* Event Mask on line 4 */ +#define EXTI_EVENR_MR5 ((uint32_t)0x00000020) /* Event Mask on line 5 */ +#define EXTI_EVENR_MR6 ((uint32_t)0x00000040) /* Event Mask on line 6 */ +#define EXTI_EVENR_MR7 ((uint32_t)0x00000080) /* Event Mask on line 7 */ +#define EXTI_EVENR_MR8 ((uint32_t)0x00000100) /* Event Mask on line 8 */ +#define EXTI_EVENR_MR9 ((uint32_t)0x00000200) /* Event Mask on line 9 */ +#define EXTI_EVENR_MR10 ((uint32_t)0x00000400) /* Event Mask on line 10 */ +#define EXTI_EVENR_MR11 ((uint32_t)0x00000800) /* Event Mask on line 11 */ +#define EXTI_EVENR_MR12 ((uint32_t)0x00001000) /* Event Mask on line 12 */ +#define EXTI_EVENR_MR13 ((uint32_t)0x00002000) /* Event Mask on line 13 */ +#define EXTI_EVENR_MR14 ((uint32_t)0x00004000) /* Event Mask on line 14 */ +#define EXTI_EVENR_MR15 ((uint32_t)0x00008000) /* Event Mask on line 15 */ +#define EXTI_EVENR_MR16 ((uint32_t)0x00010000) /* Event Mask on line 16 */ +#define EXTI_EVENR_MR17 ((uint32_t)0x00020000) /* Event Mask on line 17 */ +#define EXTI_EVENR_MR18 ((uint32_t)0x00040000) /* Event Mask on line 18 */ +#define EXTI_EVENR_MR19 ((uint32_t)0x00080000) /* Event Mask on line 19 */ +#define EXTI_EVENR_MR20 ((uint32_t)0x00100000) /* Event Mask on line 20 */ +#define EXTI_EVENR_MR21 ((uint32_t)0x00200000) /* Event Mask on line 21 */ +#define EXTI_EVENR_MR22 ((uint32_t)0x00400000) /* Event Mask on line 22 */ + +/****************** Bit definition for EXTI_RTENR register *******************/ +#define EXTI_RTENR_TR0 ((uint32_t)0x00000001) /* Rising trigger event configuration bit of line 0 */ +#define EXTI_RTENR_TR1 ((uint32_t)0x00000002) /* Rising trigger event configuration bit of line 1 */ +#define EXTI_RTENR_TR2 ((uint32_t)0x00000004) /* Rising trigger event configuration bit of line 2 */ +#define EXTI_RTENR_TR3 ((uint32_t)0x00000008) /* Rising trigger event configuration bit of line 3 */ +#define EXTI_RTENR_TR4 ((uint32_t)0x00000010) /* Rising trigger event configuration bit of line 4 */ +#define EXTI_RTENR_TR5 ((uint32_t)0x00000020) /* Rising trigger event configuration bit of line 5 */ +#define EXTI_RTENR_TR6 ((uint32_t)0x00000040) /* Rising trigger event configuration bit of line 6 */ +#define EXTI_RTENR_TR7 ((uint32_t)0x00000080) /* Rising trigger event configuration bit of line 7 */ +#define EXTI_RTENR_TR8 ((uint32_t)0x00000100) /* Rising trigger event configuration bit of line 8 */ +#define EXTI_RTENR_TR9 ((uint32_t)0x00000200) /* Rising trigger event configuration bit of line 9 */ +#define EXTI_RTENR_TR10 ((uint32_t)0x00000400) /* Rising trigger event configuration bit of line 10 */ +#define EXTI_RTENR_TR11 ((uint32_t)0x00000800) /* Rising trigger event configuration bit of line 11 */ +#define EXTI_RTENR_TR12 ((uint32_t)0x00001000) /* Rising trigger event configuration bit of line 12 */ +#define EXTI_RTENR_TR13 ((uint32_t)0x00002000) /* Rising trigger event configuration bit of line 13 */ +#define EXTI_RTENR_TR14 ((uint32_t)0x00004000) /* Rising trigger event configuration bit of line 14 */ +#define EXTI_RTENR_TR15 ((uint32_t)0x00008000) /* Rising trigger event configuration bit of line 15 */ +#define EXTI_RTENR_TR16 ((uint32_t)0x00010000) /* Rising trigger event configuration bit of line 16 */ +#define EXTI_RTENR_TR17 ((uint32_t)0x00020000) /* Rising trigger event configuration bit of line 17 */ +#define EXTI_RTENR_TR18 ((uint32_t)0x00040000) /* Rising trigger event configuration bit of line 18 */ +#define EXTI_RTENR_TR19 ((uint32_t)0x00080000) /* Rising trigger event configuration bit of line 19 */ +#define EXTI_RTENR_TR20 ((uint32_t)0x00100000) /* Rising trigger event configuration bit of line 20 */ +#define EXTI_RTENR_TR21 ((uint32_t)0x00200000) /* Rising trigger event configuration bit of line 21 */ +#define EXTI_RTENR_TR22 ((uint32_t)0x00400000) /* Rising trigger event configuration bit of line 22 */ + +/****************** Bit definition for EXTI_FTENR register *******************/ +#define EXTI_FTENR_TR0 ((uint32_t)0x00000001) /* Falling trigger event configuration bit of line 0 */ +#define EXTI_FTENR_TR1 ((uint32_t)0x00000002) /* Falling trigger event configuration bit of line 1 */ +#define EXTI_FTENR_TR2 ((uint32_t)0x00000004) /* Falling trigger event configuration bit of line 2 */ +#define EXTI_FTENR_TR3 ((uint32_t)0x00000008) /* Falling trigger event configuration bit of line 3 */ +#define EXTI_FTENR_TR4 ((uint32_t)0x00000010) /* Falling trigger event configuration bit of line 4 */ +#define EXTI_FTENR_TR5 ((uint32_t)0x00000020) /* Falling trigger event configuration bit of line 5 */ +#define EXTI_FTENR_TR6 ((uint32_t)0x00000040) /* Falling trigger event configuration bit of line 6 */ +#define EXTI_FTENR_TR7 ((uint32_t)0x00000080) /* Falling trigger event configuration bit of line 7 */ +#define EXTI_FTENR_TR8 ((uint32_t)0x00000100) /* Falling trigger event configuration bit of line 8 */ +#define EXTI_FTENR_TR9 ((uint32_t)0x00000200) /* Falling trigger event configuration bit of line 9 */ +#define EXTI_FTENR_TR10 ((uint32_t)0x00000400) /* Falling trigger event configuration bit of line 10 */ +#define EXTI_FTENR_TR11 ((uint32_t)0x00000800) /* Falling trigger event configuration bit of line 11 */ +#define EXTI_FTENR_TR12 ((uint32_t)0x00001000) /* Falling trigger event configuration bit of line 12 */ +#define EXTI_FTENR_TR13 ((uint32_t)0x00002000) /* Falling trigger event configuration bit of line 13 */ +#define EXTI_FTENR_TR14 ((uint32_t)0x00004000) /* Falling trigger event configuration bit of line 14 */ +#define EXTI_FTENR_TR15 ((uint32_t)0x00008000) /* Falling trigger event configuration bit of line 15 */ +#define EXTI_FTENR_TR16 ((uint32_t)0x00010000) /* Falling trigger event configuration bit of line 16 */ +#define EXTI_FTENR_TR17 ((uint32_t)0x00020000) /* Falling trigger event configuration bit of line 17 */ +#define EXTI_FTENR_TR18 ((uint32_t)0x00040000) /* Falling trigger event configuration bit of line 18 */ +#define EXTI_FTENR_TR19 ((uint32_t)0x00080000) /* Falling trigger event configuration bit of line 19 */ +#define EXTI_FTENR_TR20 ((uint32_t)0x00100000) /* Falling trigger event configuration bit of line 20 */ +#define EXTI_FTENR_TR21 ((uint32_t)0x00200000) /* Falling trigger event configuration bit of line 21 */ +#define EXTI_FTENR_TR22 ((uint32_t)0x00400000) /* Falling trigger event configuration bit of line 22 */ + +/****************** Bit definition for EXTI_SWIEVR register ******************/ +#define EXTI_SWIEVR_SWIEVR0 ((uint32_t)0x00000001) /* Software Interrupt on line 0 */ +#define EXTI_SWIEVR_SWIEVR1 ((uint32_t)0x00000002) /* Software Interrupt on line 1 */ +#define EXTI_SWIEVR_SWIEVR2 ((uint32_t)0x00000004) /* Software Interrupt on line 2 */ +#define EXTI_SWIEVR_SWIEVR3 ((uint32_t)0x00000008) /* Software Interrupt on line 3 */ +#define EXTI_SWIEVR_SWIEVR4 ((uint32_t)0x00000010) /* Software Interrupt on line 4 */ +#define EXTI_SWIEVR_SWIEVR5 ((uint32_t)0x00000020) /* Software Interrupt on line 5 */ +#define EXTI_SWIEVR_SWIEVR6 ((uint32_t)0x00000040) /* Software Interrupt on line 6 */ +#define EXTI_SWIEVR_SWIEVR7 ((uint32_t)0x00000080) /* Software Interrupt on line 7 */ +#define EXTI_SWIEVR_SWIEVR8 ((uint32_t)0x00000100) /* Software Interrupt on line 8 */ +#define EXTI_SWIEVR_SWIEVR9 ((uint32_t)0x00000200) /* Software Interrupt on line 9 */ +#define EXTI_SWIEVR_SWIEVR10 ((uint32_t)0x00000400) /* Software Interrupt on line 10 */ +#define EXTI_SWIEVR_SWIEVR11 ((uint32_t)0x00000800) /* Software Interrupt on line 11 */ +#define EXTI_SWIEVR_SWIEVR12 ((uint32_t)0x00001000) /* Software Interrupt on line 12 */ +#define EXTI_SWIEVR_SWIEVR13 ((uint32_t)0x00002000) /* Software Interrupt on line 13 */ +#define EXTI_SWIEVR_SWIEVR14 ((uint32_t)0x00004000) /* Software Interrupt on line 14 */ +#define EXTI_SWIEVR_SWIEVR15 ((uint32_t)0x00008000) /* Software Interrupt on line 15 */ +#define EXTI_SWIEVR_SWIEVR16 ((uint32_t)0x00010000) /* Software Interrupt on line 16 */ +#define EXTI_SWIEVR_SWIEVR17 ((uint32_t)0x00020000) /* Software Interrupt on line 17 */ +#define EXTI_SWIEVR_SWIEVR18 ((uint32_t)0x00040000) /* Software Interrupt on line 18 */ +#define EXTI_SWIEVR_SWIEVR19 ((uint32_t)0x00080000) /* Software Interrupt on line 19 */ +#define EXTI_SWIEVR_SWIEVR20 ((uint32_t)0x00100000) /* Software Interrupt on line 20 */ +#define EXTI_SWIEVR_SWIEVR21 ((uint32_t)0x00200000) /* Software Interrupt on line 21 */ +#define EXTI_SWIEVR_SWIEVR22 ((uint32_t)0x00400000) /* Software Interrupt on line 22 */ + +/******************* Bit definition for EXTI_INTFR register ********************/ +#define EXTI_INTF_INTF0 ((uint32_t)0x00000001) /* Pending bit for line 0 */ +#define EXTI_INTF_INTF1 ((uint32_t)0x00000002) /* Pending bit for line 1 */ +#define EXTI_INTF_INTF2 ((uint32_t)0x00000004) /* Pending bit for line 2 */ +#define EXTI_INTF_INTF3 ((uint32_t)0x00000008) /* Pending bit for line 3 */ +#define EXTI_INTF_INTF4 ((uint32_t)0x00000010) /* Pending bit for line 4 */ +#define EXTI_INTF_INTF5 ((uint32_t)0x00000020) /* Pending bit for line 5 */ +#define EXTI_INTF_INTF6 ((uint32_t)0x00000040) /* Pending bit for line 6 */ +#define EXTI_INTF_INTF7 ((uint32_t)0x00000080) /* Pending bit for line 7 */ +#define EXTI_INTF_INTF8 ((uint32_t)0x00000100) /* Pending bit for line 8 */ +#define EXTI_INTF_INTF9 ((uint32_t)0x00000200) /* Pending bit for line 9 */ +#define EXTI_INTF_INTF10 ((uint32_t)0x00000400) /* Pending bit for line 10 */ +#define EXTI_INTF_INTF11 ((uint32_t)0x00000800) /* Pending bit for line 11 */ +#define EXTI_INTF_INTF12 ((uint32_t)0x00001000) /* Pending bit for line 12 */ +#define EXTI_INTF_INTF13 ((uint32_t)0x00002000) /* Pending bit for line 13 */ +#define EXTI_INTF_INTF14 ((uint32_t)0x00004000) /* Pending bit for line 14 */ +#define EXTI_INTF_INTF15 ((uint32_t)0x00008000) /* Pending bit for line 15 */ +#define EXTI_INTF_INTF16 ((uint32_t)0x00010000) /* Pending bit for line 16 */ +#define EXTI_INTF_INTF17 ((uint32_t)0x00020000) /* Pending bit for line 17 */ +#define EXTI_INTF_INTF18 ((uint32_t)0x00040000) /* Pending bit for line 18 */ +#define EXTI_INTF_INTF19 ((uint32_t)0x00080000) /* Pending bit for line 19 */ +#define EXTI_INTF_INTF20 ((uint32_t)0x00100000) /* Pending bit for line 20 */ +#define EXTI_INTF_INTF21 ((uint32_t)0x00200000) /* Pending bit for line 21 */ +#define EXTI_INTF_INTF22 ((uint32_t)0x00400000) /* Pending bit for line 22 */ + +/******************************************************************************/ +/* FLASH and Option Bytes Registers */ +/******************************************************************************/ + +/******************* Bit definition for FLASH_ACTLR register ******************/ +#define FLASH_ACTLR_LATENCY ((uint8_t)0x03) /* LATENCY[1:0] bits (Latency) */ +#define FLASH_ACTLR_LATENCY_0 ((uint8_t)0x00) /* Bit 0 */ +#define FLASH_ACTLR_LATENCY_1 ((uint8_t)0x01) /* Bit 0 */ +#define FLASH_ACTLR_LATENCY_2 ((uint8_t)0x02) /* Bit 1 */ + +/****************** Bit definition for FLASH_KEYR register ******************/ +#define FLASH_KEYR_FKEYR ((uint32_t)0xFFFFFFFF) /* FPEC Key */ + +/***************** Bit definition for FLASH_OBKEYR register ****************/ +#define FLASH_OBKEYR_OBKEYR ((uint32_t)0xFFFFFFFF) /* Option Byte Key */ + +/****************** Bit definition for FLASH_STATR register *******************/ +#define FLASH_STATR_BSY ((uint8_t)0x01) /* Busy */ +#define FLASH_STATR_WRPRTERR ((uint8_t)0x10) /* Write Protection Error */ +#define FLASH_STATR_EOP ((uint8_t)0x20) /* End of operation */ +#define FLASH_STATR_FWAKE_FLAG ((uint8_t)0x40) +#define FLASH_STATR_TURBO ((uint8_t)0x80) + +/******************* Bit definition for FLASH_CTLR register *******************/ +#define FLASH_CTLR_PER ((uint32_t)0x00000002) /* Sector Erase 1K */ +#define FLASH_CTLR_MER ((uint32_t)0x00000004) /* Mass Erase */ +#define FLASH_CTLR_OBER ((uint32_t)0x00000020) /* Option Byte Erase */ +#define FLASH_CTLR_STRT ((uint32_t)0x00000040) /* Start */ +#define FLASH_CTLR_LOCK ((uint32_t)0x00000080) /* Lock */ +#define FLASH_CTLR_OBWRE ((uint32_t)0x00000200) /* Option Bytes Write Enable */ +#define FLASH_CTLR_ERRIE ((uint32_t)0x00000400) /* Error Interrupt Enable */ +#define FLASH_CTLR_EOPIE ((uint32_t)0x00001000) /* End of operation interrupt enable */ +#define FLASH_CTLR_FWAKEIE ((uint32_t)0x00002000) +#define FLASH_CTLR_FLOCK ((uint32_t)0x00008000) /* Fast Lock */ +#define FLASH_CTLR_FTPG ((uint32_t)0x00010000) /* Page Programming 256Byte */ +#define FLASH_CTLR_FTER ((uint32_t)0x00020000) /* Page Erase 256Byte */ +#define FLASH_CTLR_BUFLOAD ((uint32_t)0x00040000) +#define FLASH_CTLR_BUFRST ((uint32_t)0x00080000) +#define FLASH_CTLR_BER32 ((uint32_t)0x00800000) /* Block Erase 32K */ + +/******************* Bit definition for FLASH_ADDR register *******************/ +#define FLASH_ADDR_FAR ((uint32_t)0xFFFFFFFF) /* Flash Address */ + +/****************** Bit definition for FLASH_OBR register *******************/ +#define FLASH_OBR_OBERR ((uint32_t)0x00000001) /* Option Byte Error */ +#define FLASH_OBR_RDPRT ((uint32_t)0x00000002) /* Read protection */ + +#define FLASH_OBR_USER ((uint32_t)0x000000FC) /* User Option Bytes */ +#define FLASH_OBR_iWDG_SW ((uint32_t)0x00000004) /* WDG_SW */ +#define FLASH_OBR_STOP_nRST ((uint32_t)0x00000008) /* nRST_STOP */ +#define FLASH_OBR_STANDY_nRST ((uint32_t)0x00000010) /* nRST_STDBY */ +#define FLASH_OBR_CFGCANM ((uint32_t)0x00000080) + +#define FLASH_OBR_DATA0 ((uint32_t)0x0003FC00) /* DATA0 */ +#define FLASH_OBR_DATA1 ((uint32_t)0x03FC0000) /* DATA1 */ + +/****************** Bit definition for FLASH_WPR register ******************/ +#define FLASH_WPR_WRP ((uint32_t)0xFFFFFFFF) /* Write Protect */ + +/****************** Bit definition for FLASH_OBR_MODEKEYR register ******************/ +#define FLASH_OBR_MODEKEYR ((uint32_t)0xFFFFFFFF) + +/****************** Bit definition for FLASH_RDPR register *******************/ +#define FLASH_RDPR_RDPR ((uint32_t)0x000000FF) /* Read protection option byte */ +#define FLASH_RDPR_nRDPR ((uint32_t)0x0000FF00) /* Read protection complemented option byte */ + +/****************** Bit definition for FLASH_USER register ******************/ +#define FLASH_USER_USER ((uint32_t)0x00FF0000) /* User option byte */ +#define FLASH_USER_nUSER ((uint32_t)0xFF000000) /* User complemented option byte */ + +/****************** Bit definition for FLASH_Data0 register *****************/ +#define FLASH_Data0_Data0 ((uint32_t)0x000000FF) /* User data storage option byte */ +#define FLASH_Data0_nData0 ((uint32_t)0x0000FF00) /* User data storage complemented option byte */ + +/****************** Bit definition for FLASH_Data1 register *****************/ +#define FLASH_Data1_Data1 ((uint32_t)0x00FF0000) /* User data storage option byte */ +#define FLASH_Data1_nData1 ((uint32_t)0xFF000000) /* User data storage complemented option byte */ + +/****************** Bit definition for FLASH_WRPR0 register ******************/ +#define FLASH_WRPR0_WRPR0 ((uint32_t)0x000000FF) /* Flash memory write protection option bytes */ +#define FLASH_WRPR0_nWRPR0 ((uint32_t)0x0000FF00) /* Flash memory write protection complemented option bytes */ + +/****************** Bit definition for FLASH_WRPR1 register ******************/ +#define FLASH_WRPR1_WRPR1 ((uint32_t)0x00FF0000) /* Flash memory write protection option bytes */ +#define FLASH_WRPR1_nWRPR1 ((uint32_t)0xFF000000) /* Flash memory write protection complemented option bytes */ + +/****************** Bit definition for FLASH_WRPR2 register ******************/ +#define FLASH_WRPR2_WRPR2 ((uint32_t)0x000000FF) /* Flash memory write protection option bytes */ +#define FLASH_WRPR2_nWRPR2 ((uint32_t)0x0000FF00) /* Flash memory write protection complemented option bytes */ + +/****************** Bit definition for FLASH_WRPR3 register ******************/ +#define FLASH_WRPR3_WRPR3 ((uint32_t)0x00FF0000) /* Flash memory write protection option bytes */ +#define FLASH_WRPR3_nWRPR3 ((uint32_t)0xFF000000) /* Flash memory write protection complemented option bytes */ + +/******************************************************************************/ +/* General Purpose and Alternate Function I/O */ +/******************************************************************************/ + +/******************* Bit definition for GPIO_CFGLR register *******************/ +#define GPIO_CFGLR_MODE ((uint32_t)0x33333333) /* Port x mode bits */ + +#define GPIO_CFGLR_MODE0 ((uint32_t)0x00000003) /* MODE0[1:0] bits (Port x mode bits, pin 0) */ +#define GPIO_CFGLR_MODE0_0 ((uint32_t)0x00000001) /* Bit 0 */ +#define GPIO_CFGLR_MODE0_1 ((uint32_t)0x00000002) /* Bit 1 */ + +#define GPIO_CFGLR_MODE1 ((uint32_t)0x00000030) /* MODE1[1:0] bits (Port x mode bits, pin 1) */ +#define GPIO_CFGLR_MODE1_0 ((uint32_t)0x00000010) /* Bit 0 */ +#define GPIO_CFGLR_MODE1_1 ((uint32_t)0x00000020) /* Bit 1 */ + +#define GPIO_CFGLR_MODE2 ((uint32_t)0x00000300) /* MODE2[1:0] bits (Port x mode bits, pin 2) */ +#define GPIO_CFGLR_MODE2_0 ((uint32_t)0x00000100) /* Bit 0 */ +#define GPIO_CFGLR_MODE2_1 ((uint32_t)0x00000200) /* Bit 1 */ + +#define GPIO_CFGLR_MODE3 ((uint32_t)0x00003000) /* MODE3[1:0] bits (Port x mode bits, pin 3) */ +#define GPIO_CFGLR_MODE3_0 ((uint32_t)0x00001000) /* Bit 0 */ +#define GPIO_CFGLR_MODE3_1 ((uint32_t)0x00002000) /* Bit 1 */ + +#define GPIO_CFGLR_MODE4 ((uint32_t)0x00030000) /* MODE4[1:0] bits (Port x mode bits, pin 4) */ +#define GPIO_CFGLR_MODE4_0 ((uint32_t)0x00010000) /* Bit 0 */ +#define GPIO_CFGLR_MODE4_1 ((uint32_t)0x00020000) /* Bit 1 */ + +#define GPIO_CFGLR_MODE5 ((uint32_t)0x00300000) /* MODE5[1:0] bits (Port x mode bits, pin 5) */ +#define GPIO_CFGLR_MODE5_0 ((uint32_t)0x00100000) /* Bit 0 */ +#define GPIO_CFGLR_MODE5_1 ((uint32_t)0x00200000) /* Bit 1 */ + +#define GPIO_CFGLR_MODE6 ((uint32_t)0x03000000) /* MODE6[1:0] bits (Port x mode bits, pin 6) */ +#define GPIO_CFGLR_MODE6_0 ((uint32_t)0x01000000) /* Bit 0 */ +#define GPIO_CFGLR_MODE6_1 ((uint32_t)0x02000000) /* Bit 1 */ + +#define GPIO_CFGLR_MODE7 ((uint32_t)0x30000000) /* MODE7[1:0] bits (Port x mode bits, pin 7) */ +#define GPIO_CFGLR_MODE7_0 ((uint32_t)0x10000000) /* Bit 0 */ +#define GPIO_CFGLR_MODE7_1 ((uint32_t)0x20000000) /* Bit 1 */ + +#define GPIO_CFGLR_CNF ((uint32_t)0xCCCCCCCC) /* Port x configuration bits */ + +#define GPIO_CFGLR_CNF0 ((uint32_t)0x0000000C) /* CNF0[1:0] bits (Port x configuration bits, pin 0) */ +#define GPIO_CFGLR_CNF0_0 ((uint32_t)0x00000004) /* Bit 0 */ +#define GPIO_CFGLR_CNF0_1 ((uint32_t)0x00000008) /* Bit 1 */ + +#define GPIO_CFGLR_CNF1 ((uint32_t)0x000000C0) /* CNF1[1:0] bits (Port x configuration bits, pin 1) */ +#define GPIO_CFGLR_CNF1_0 ((uint32_t)0x00000040) /* Bit 0 */ +#define GPIO_CFGLR_CNF1_1 ((uint32_t)0x00000080) /* Bit 1 */ + +#define GPIO_CFGLR_CNF2 ((uint32_t)0x00000C00) /* CNF2[1:0] bits (Port x configuration bits, pin 2) */ +#define GPIO_CFGLR_CNF2_0 ((uint32_t)0x00000400) /* Bit 0 */ +#define GPIO_CFGLR_CNF2_1 ((uint32_t)0x00000800) /* Bit 1 */ + +#define GPIO_CFGLR_CNF3 ((uint32_t)0x0000C000) /* CNF3[1:0] bits (Port x configuration bits, pin 3) */ +#define GPIO_CFGLR_CNF3_0 ((uint32_t)0x00004000) /* Bit 0 */ +#define GPIO_CFGLR_CNF3_1 ((uint32_t)0x00008000) /* Bit 1 */ + +#define GPIO_CFGLR_CNF4 ((uint32_t)0x000C0000) /* CNF4[1:0] bits (Port x configuration bits, pin 4) */ +#define GPIO_CFGLR_CNF4_0 ((uint32_t)0x00040000) /* Bit 0 */ +#define GPIO_CFGLR_CNF4_1 ((uint32_t)0x00080000) /* Bit 1 */ + +#define GPIO_CFGLR_CNF5 ((uint32_t)0x00C00000) /* CNF5[1:0] bits (Port x configuration bits, pin 5) */ +#define GPIO_CFGLR_CNF5_0 ((uint32_t)0x00400000) /* Bit 0 */ +#define GPIO_CFGLR_CNF5_1 ((uint32_t)0x00800000) /* Bit 1 */ + +#define GPIO_CFGLR_CNF6 ((uint32_t)0x0C000000) /* CNF6[1:0] bits (Port x configuration bits, pin 6) */ +#define GPIO_CFGLR_CNF6_0 ((uint32_t)0x04000000) /* Bit 0 */ +#define GPIO_CFGLR_CNF6_1 ((uint32_t)0x08000000) /* Bit 1 */ + +#define GPIO_CFGLR_CNF7 ((uint32_t)0xC0000000) /* CNF7[1:0] bits (Port x configuration bits, pin 7) */ +#define GPIO_CFGLR_CNF7_0 ((uint32_t)0x40000000) /* Bit 0 */ +#define GPIO_CFGLR_CNF7_1 ((uint32_t)0x80000000) /* Bit 1 */ + +/******************* Bit definition for GPIO_CFGHR register *******************/ +#define GPIO_CFGHR_MODE ((uint32_t)0x33333333) /* Port x mode bits */ + +#define GPIO_CFGHR_MODE8 ((uint32_t)0x00000003) /* MODE8[1:0] bits (Port x mode bits, pin 8) */ +#define GPIO_CFGHR_MODE8_0 ((uint32_t)0x00000001) /* Bit 0 */ +#define GPIO_CFGHR_MODE8_1 ((uint32_t)0x00000002) /* Bit 1 */ + +#define GPIO_CFGHR_MODE9 ((uint32_t)0x00000030) /* MODE9[1:0] bits (Port x mode bits, pin 9) */ +#define GPIO_CFGHR_MODE9_0 ((uint32_t)0x00000010) /* Bit 0 */ +#define GPIO_CFGHR_MODE9_1 ((uint32_t)0x00000020) /* Bit 1 */ + +#define GPIO_CFGHR_MODE10 ((uint32_t)0x00000300) /* MODE10[1:0] bits (Port x mode bits, pin 10) */ +#define GPIO_CFGHR_MODE10_0 ((uint32_t)0x00000100) /* Bit 0 */ +#define GPIO_CFGHR_MODE10_1 ((uint32_t)0x00000200) /* Bit 1 */ + +#define GPIO_CFGHR_MODE11 ((uint32_t)0x00003000) /* MODE11[1:0] bits (Port x mode bits, pin 11) */ +#define GPIO_CFGHR_MODE11_0 ((uint32_t)0x00001000) /* Bit 0 */ +#define GPIO_CFGHR_MODE11_1 ((uint32_t)0x00002000) /* Bit 1 */ + +#define GPIO_CFGHR_MODE12 ((uint32_t)0x00030000) /* MODE12[1:0] bits (Port x mode bits, pin 12) */ +#define GPIO_CFGHR_MODE12_0 ((uint32_t)0x00010000) /* Bit 0 */ +#define GPIO_CFGHR_MODE12_1 ((uint32_t)0x00020000) /* Bit 1 */ + +#define GPIO_CFGHR_MODE13 ((uint32_t)0x00300000) /* MODE13[1:0] bits (Port x mode bits, pin 13) */ +#define GPIO_CFGHR_MODE13_0 ((uint32_t)0x00100000) /* Bit 0 */ +#define GPIO_CFGHR_MODE13_1 ((uint32_t)0x00200000) /* Bit 1 */ + +#define GPIO_CFGHR_MODE14 ((uint32_t)0x03000000) /* MODE14[1:0] bits (Port x mode bits, pin 14) */ +#define GPIO_CFGHR_MODE14_0 ((uint32_t)0x01000000) /* Bit 0 */ +#define GPIO_CFGHR_MODE14_1 ((uint32_t)0x02000000) /* Bit 1 */ + +#define GPIO_CFGHR_MODE15 ((uint32_t)0x30000000) /* MODE15[1:0] bits (Port x mode bits, pin 15) */ +#define GPIO_CFGHR_MODE15_0 ((uint32_t)0x10000000) /* Bit 0 */ +#define GPIO_CFGHR_MODE15_1 ((uint32_t)0x20000000) /* Bit 1 */ + +#define GPIO_CFGHR_CNF ((uint32_t)0xCCCCCCCC) /* Port x configuration bits */ + +#define GPIO_CFGHR_CNF8 ((uint32_t)0x0000000C) /* CNF8[1:0] bits (Port x configuration bits, pin 8) */ +#define GPIO_CFGHR_CNF8_0 ((uint32_t)0x00000004) /* Bit 0 */ +#define GPIO_CFGHR_CNF8_1 ((uint32_t)0x00000008) /* Bit 1 */ + +#define GPIO_CFGHR_CNF9 ((uint32_t)0x000000C0) /* CNF9[1:0] bits (Port x configuration bits, pin 9) */ +#define GPIO_CFGHR_CNF9_0 ((uint32_t)0x00000040) /* Bit 0 */ +#define GPIO_CFGHR_CNF9_1 ((uint32_t)0x00000080) /* Bit 1 */ + +#define GPIO_CFGHR_CNF10 ((uint32_t)0x00000C00) /* CNF10[1:0] bits (Port x configuration bits, pin 10) */ +#define GPIO_CFGHR_CNF10_0 ((uint32_t)0x00000400) /* Bit 0 */ +#define GPIO_CFGHR_CNF10_1 ((uint32_t)0x00000800) /* Bit 1 */ + +#define GPIO_CFGHR_CNF11 ((uint32_t)0x0000C000) /* CNF11[1:0] bits (Port x configuration bits, pin 11) */ +#define GPIO_CFGHR_CNF11_0 ((uint32_t)0x00004000) /* Bit 0 */ +#define GPIO_CFGHR_CNF11_1 ((uint32_t)0x00008000) /* Bit 1 */ + +#define GPIO_CFGHR_CNF12 ((uint32_t)0x000C0000) /* CNF12[1:0] bits (Port x configuration bits, pin 12) */ +#define GPIO_CFGHR_CNF12_0 ((uint32_t)0x00040000) /* Bit 0 */ +#define GPIO_CFGHR_CNF12_1 ((uint32_t)0x00080000) /* Bit 1 */ + +#define GPIO_CFGHR_CNF13 ((uint32_t)0x00C00000) /* CNF13[1:0] bits (Port x configuration bits, pin 13) */ +#define GPIO_CFGHR_CNF13_0 ((uint32_t)0x00400000) /* Bit 0 */ +#define GPIO_CFGHR_CNF13_1 ((uint32_t)0x00800000) /* Bit 1 */ + +#define GPIO_CFGHR_CNF14 ((uint32_t)0x0C000000) /* CNF14[1:0] bits (Port x configuration bits, pin 14) */ +#define GPIO_CFGHR_CNF14_0 ((uint32_t)0x04000000) /* Bit 0 */ +#define GPIO_CFGHR_CNF14_1 ((uint32_t)0x08000000) /* Bit 1 */ + +#define GPIO_CFGHR_CNF15 ((uint32_t)0xC0000000) /* CNF15[1:0] bits (Port x configuration bits, pin 15) */ +#define GPIO_CFGHR_CNF15_0 ((uint32_t)0x40000000) /* Bit 0 */ +#define GPIO_CFGHR_CNF15_1 ((uint32_t)0x80000000) /* Bit 1 */ + +/******************* Bit definition for GPIO_INDR register *******************/ +#define GPIO_INDR_IDR0 ((uint16_t)0x0001) /* Port input data, bit 0 */ +#define GPIO_INDR_IDR1 ((uint16_t)0x0002) /* Port input data, bit 1 */ +#define GPIO_INDR_IDR2 ((uint16_t)0x0004) /* Port input data, bit 2 */ +#define GPIO_INDR_IDR3 ((uint16_t)0x0008) /* Port input data, bit 3 */ +#define GPIO_INDR_IDR4 ((uint16_t)0x0010) /* Port input data, bit 4 */ +#define GPIO_INDR_IDR5 ((uint16_t)0x0020) /* Port input data, bit 5 */ +#define GPIO_INDR_IDR6 ((uint16_t)0x0040) /* Port input data, bit 6 */ +#define GPIO_INDR_IDR7 ((uint16_t)0x0080) /* Port input data, bit 7 */ +#define GPIO_INDR_IDR8 ((uint16_t)0x0100) /* Port input data, bit 8 */ +#define GPIO_INDR_IDR9 ((uint16_t)0x0200) /* Port input data, bit 9 */ +#define GPIO_INDR_IDR10 ((uint16_t)0x0400) /* Port input data, bit 10 */ +#define GPIO_INDR_IDR11 ((uint16_t)0x0800) /* Port input data, bit 11 */ +#define GPIO_INDR_IDR12 ((uint16_t)0x1000) /* Port input data, bit 12 */ +#define GPIO_INDR_IDR13 ((uint16_t)0x2000) /* Port input data, bit 13 */ +#define GPIO_INDR_IDR14 ((uint16_t)0x4000) /* Port input data, bit 14 */ +#define GPIO_INDR_IDR15 ((uint16_t)0x8000) /* Port input data, bit 15 */ + +/******************* Bit definition for GPIO_OUTDR register *******************/ +#define GPIO_OUTDR_ODR0 ((uint16_t)0x0001) /* Port output data, bit 0 */ +#define GPIO_OUTDR_ODR1 ((uint16_t)0x0002) /* Port output data, bit 1 */ +#define GPIO_OUTDR_ODR2 ((uint16_t)0x0004) /* Port output data, bit 2 */ +#define GPIO_OUTDR_ODR3 ((uint16_t)0x0008) /* Port output data, bit 3 */ +#define GPIO_OUTDR_ODR4 ((uint16_t)0x0010) /* Port output data, bit 4 */ +#define GPIO_OUTDR_ODR5 ((uint16_t)0x0020) /* Port output data, bit 5 */ +#define GPIO_OUTDR_ODR6 ((uint16_t)0x0040) /* Port output data, bit 6 */ +#define GPIO_OUTDR_ODR7 ((uint16_t)0x0080) /* Port output data, bit 7 */ +#define GPIO_OUTDR_ODR8 ((uint16_t)0x0100) /* Port output data, bit 8 */ +#define GPIO_OUTDR_ODR9 ((uint16_t)0x0200) /* Port output data, bit 9 */ +#define GPIO_OUTDR_ODR10 ((uint16_t)0x0400) /* Port output data, bit 10 */ +#define GPIO_OUTDR_ODR11 ((uint16_t)0x0800) /* Port output data, bit 11 */ +#define GPIO_OUTDR_ODR12 ((uint16_t)0x1000) /* Port output data, bit 12 */ +#define GPIO_OUTDR_ODR13 ((uint16_t)0x2000) /* Port output data, bit 13 */ +#define GPIO_OUTDR_ODR14 ((uint16_t)0x4000) /* Port output data, bit 14 */ +#define GPIO_OUTDR_ODR15 ((uint16_t)0x8000) /* Port output data, bit 15 */ + +/****************** Bit definition for GPIO_BSHR register *******************/ +#define GPIO_BSHR_BS0 ((uint32_t)0x00000001) /* Port x Set bit 0 */ +#define GPIO_BSHR_BS1 ((uint32_t)0x00000002) /* Port x Set bit 1 */ +#define GPIO_BSHR_BS2 ((uint32_t)0x00000004) /* Port x Set bit 2 */ +#define GPIO_BSHR_BS3 ((uint32_t)0x00000008) /* Port x Set bit 3 */ +#define GPIO_BSHR_BS4 ((uint32_t)0x00000010) /* Port x Set bit 4 */ +#define GPIO_BSHR_BS5 ((uint32_t)0x00000020) /* Port x Set bit 5 */ +#define GPIO_BSHR_BS6 ((uint32_t)0x00000040) /* Port x Set bit 6 */ +#define GPIO_BSHR_BS7 ((uint32_t)0x00000080) /* Port x Set bit 7 */ +#define GPIO_BSHR_BS8 ((uint32_t)0x00000100) /* Port x Set bit 8 */ +#define GPIO_BSHR_BS9 ((uint32_t)0x00000200) /* Port x Set bit 9 */ +#define GPIO_BSHR_BS10 ((uint32_t)0x00000400) /* Port x Set bit 10 */ +#define GPIO_BSHR_BS11 ((uint32_t)0x00000800) /* Port x Set bit 11 */ +#define GPIO_BSHR_BS12 ((uint32_t)0x00001000) /* Port x Set bit 12 */ +#define GPIO_BSHR_BS13 ((uint32_t)0x00002000) /* Port x Set bit 13 */ +#define GPIO_BSHR_BS14 ((uint32_t)0x00004000) /* Port x Set bit 14 */ +#define GPIO_BSHR_BS15 ((uint32_t)0x00008000) /* Port x Set bit 15 */ + +#define GPIO_BSHR_BR0 ((uint32_t)0x00010000) /* Port x Reset bit 0 */ +#define GPIO_BSHR_BR1 ((uint32_t)0x00020000) /* Port x Reset bit 1 */ +#define GPIO_BSHR_BR2 ((uint32_t)0x00040000) /* Port x Reset bit 2 */ +#define GPIO_BSHR_BR3 ((uint32_t)0x00080000) /* Port x Reset bit 3 */ +#define GPIO_BSHR_BR4 ((uint32_t)0x00100000) /* Port x Reset bit 4 */ +#define GPIO_BSHR_BR5 ((uint32_t)0x00200000) /* Port x Reset bit 5 */ +#define GPIO_BSHR_BR6 ((uint32_t)0x00400000) /* Port x Reset bit 6 */ +#define GPIO_BSHR_BR7 ((uint32_t)0x00800000) /* Port x Reset bit 7 */ +#define GPIO_BSHR_BR8 ((uint32_t)0x01000000) /* Port x Reset bit 8 */ +#define GPIO_BSHR_BR9 ((uint32_t)0x02000000) /* Port x Reset bit 9 */ +#define GPIO_BSHR_BR10 ((uint32_t)0x04000000) /* Port x Reset bit 10 */ +#define GPIO_BSHR_BR11 ((uint32_t)0x08000000) /* Port x Reset bit 11 */ +#define GPIO_BSHR_BR12 ((uint32_t)0x10000000) /* Port x Reset bit 12 */ +#define GPIO_BSHR_BR13 ((uint32_t)0x20000000) /* Port x Reset bit 13 */ +#define GPIO_BSHR_BR14 ((uint32_t)0x40000000) /* Port x Reset bit 14 */ +#define GPIO_BSHR_BR15 ((uint32_t)0x80000000) /* Port x Reset bit 15 */ + +/******************* Bit definition for GPIO_BCR register *******************/ +#define GPIO_BCR_BR0 ((uint16_t)0x0001) /* Port x Reset bit 0 */ +#define GPIO_BCR_BR1 ((uint16_t)0x0002) /* Port x Reset bit 1 */ +#define GPIO_BCR_BR2 ((uint16_t)0x0004) /* Port x Reset bit 2 */ +#define GPIO_BCR_BR3 ((uint16_t)0x0008) /* Port x Reset bit 3 */ +#define GPIO_BCR_BR4 ((uint16_t)0x0010) /* Port x Reset bit 4 */ +#define GPIO_BCR_BR5 ((uint16_t)0x0020) /* Port x Reset bit 5 */ +#define GPIO_BCR_BR6 ((uint16_t)0x0040) /* Port x Reset bit 6 */ +#define GPIO_BCR_BR7 ((uint16_t)0x0080) /* Port x Reset bit 7 */ +#define GPIO_BCR_BR8 ((uint16_t)0x0100) /* Port x Reset bit 8 */ +#define GPIO_BCR_BR9 ((uint16_t)0x0200) /* Port x Reset bit 9 */ +#define GPIO_BCR_BR10 ((uint16_t)0x0400) /* Port x Reset bit 10 */ +#define GPIO_BCR_BR11 ((uint16_t)0x0800) /* Port x Reset bit 11 */ +#define GPIO_BCR_BR12 ((uint16_t)0x1000) /* Port x Reset bit 12 */ +#define GPIO_BCR_BR13 ((uint16_t)0x2000) /* Port x Reset bit 13 */ +#define GPIO_BCR_BR14 ((uint16_t)0x4000) /* Port x Reset bit 14 */ +#define GPIO_BCR_BR15 ((uint16_t)0x8000) /* Port x Reset bit 15 */ + +/****************** Bit definition for GPIO_LCKR register *******************/ +#define GPIO_LCK0 ((uint32_t)0x00000001) /* Port x Lock bit 0 */ +#define GPIO_LCK1 ((uint32_t)0x00000002) /* Port x Lock bit 1 */ +#define GPIO_LCK2 ((uint32_t)0x00000004) /* Port x Lock bit 2 */ +#define GPIO_LCK3 ((uint32_t)0x00000008) /* Port x Lock bit 3 */ +#define GPIO_LCK4 ((uint32_t)0x00000010) /* Port x Lock bit 4 */ +#define GPIO_LCK5 ((uint32_t)0x00000020) /* Port x Lock bit 5 */ +#define GPIO_LCK6 ((uint32_t)0x00000040) /* Port x Lock bit 6 */ +#define GPIO_LCK7 ((uint32_t)0x00000080) /* Port x Lock bit 7 */ +#define GPIO_LCK8 ((uint32_t)0x00000100) /* Port x Lock bit 8 */ +#define GPIO_LCK9 ((uint32_t)0x00000200) /* Port x Lock bit 9 */ +#define GPIO_LCK10 ((uint32_t)0x00000400) /* Port x Lock bit 10 */ +#define GPIO_LCK11 ((uint32_t)0x00000800) /* Port x Lock bit 11 */ +#define GPIO_LCK12 ((uint32_t)0x00001000) /* Port x Lock bit 12 */ +#define GPIO_LCK13 ((uint32_t)0x00002000) /* Port x Lock bit 13 */ +#define GPIO_LCK14 ((uint32_t)0x00004000) /* Port x Lock bit 14 */ +#define GPIO_LCK15 ((uint32_t)0x00008000) /* Port x Lock bit 15 */ +#define GPIO_LCKK ((uint32_t)0x00010000) /* Lock key */ + +/****************** Bit definition for AFIO_ECR register *******************/ +#define AFIO_ECR_PIN ((uint8_t)0x0F) /* PIN[3:0] bits (Pin selection) */ +#define AFIO_ECR_PIN_0 ((uint8_t)0x01) /* Bit 0 */ +#define AFIO_ECR_PIN_1 ((uint8_t)0x02) /* Bit 1 */ +#define AFIO_ECR_PIN_2 ((uint8_t)0x04) /* Bit 2 */ +#define AFIO_ECR_PIN_3 ((uint8_t)0x08) /* Bit 3 */ + +#define AFIO_ECR_PIN_PX0 ((uint8_t)0x00) /* Pin 0 selected */ +#define AFIO_ECR_PIN_PX1 ((uint8_t)0x01) /* Pin 1 selected */ +#define AFIO_ECR_PIN_PX2 ((uint8_t)0x02) /* Pin 2 selected */ +#define AFIO_ECR_PIN_PX3 ((uint8_t)0x03) /* Pin 3 selected */ +#define AFIO_ECR_PIN_PX4 ((uint8_t)0x04) /* Pin 4 selected */ +#define AFIO_ECR_PIN_PX5 ((uint8_t)0x05) /* Pin 5 selected */ +#define AFIO_ECR_PIN_PX6 ((uint8_t)0x06) /* Pin 6 selected */ +#define AFIO_ECR_PIN_PX7 ((uint8_t)0x07) /* Pin 7 selected */ +#define AFIO_ECR_PIN_PX8 ((uint8_t)0x08) /* Pin 8 selected */ +#define AFIO_ECR_PIN_PX9 ((uint8_t)0x09) /* Pin 9 selected */ +#define AFIO_ECR_PIN_PX10 ((uint8_t)0x0A) /* Pin 10 selected */ +#define AFIO_ECR_PIN_PX11 ((uint8_t)0x0B) /* Pin 11 selected */ +#define AFIO_ECR_PIN_PX12 ((uint8_t)0x0C) /* Pin 12 selected */ +#define AFIO_ECR_PIN_PX13 ((uint8_t)0x0D) /* Pin 13 selected */ +#define AFIO_ECR_PIN_PX14 ((uint8_t)0x0E) /* Pin 14 selected */ +#define AFIO_ECR_PIN_PX15 ((uint8_t)0x0F) /* Pin 15 selected */ + +#define AFIO_ECR_PORT ((uint8_t)0x70) /* PORT[2:0] bits (Port selection) */ +#define AFIO_ECR_PORT_0 ((uint8_t)0x10) /* Bit 0 */ +#define AFIO_ECR_PORT_1 ((uint8_t)0x20) /* Bit 1 */ +#define AFIO_ECR_PORT_2 ((uint8_t)0x40) /* Bit 2 */ + +#define AFIO_ECR_PORT_PA ((uint8_t)0x00) /* Port A selected */ +#define AFIO_ECR_PORT_PB ((uint8_t)0x10) /* Port B selected */ +#define AFIO_ECR_PORT_PC ((uint8_t)0x20) /* Port C selected */ +#define AFIO_ECR_PORT_PD ((uint8_t)0x30) /* Port D selected */ + +#define AFIO_ECR_EVOE ((uint8_t)0x80) /* Event Output Enable */ + +/****************** Bit definition for AFIO_PCFR1register *******************/ +#define AFIO_PCFR1_SPI1_RM ((uint32_t)0x00000001) /* SPI1 remapping */ +#define AFIO_PCFR1_I2C1_RM ((uint32_t)0x00000002) /* I2C1 remapping */ +#define AFIO_PCFR1_USART1_RM ((uint32_t)0x00000004) /* USART1 remapping */ +#define AFIO_PCFR1_USART2_RM ((uint32_t)0x00000008) /* USART2 remapping */ + +#define AFIO_PCFR1_USART3_RM ((uint32_t)0x00000030) /* USART3_RM[1:0] bits (USART3 remapping) */ +#define AFIO_PCFR1_USART3_RM_0 ((uint32_t)0x00000010) /* Bit 0 */ +#define AFIO_PCFR1_USART3_RM_1 ((uint32_t)0x00000020) /* Bit 1 */ + +#define AFIO_PCFR1_TIM1_RM ((uint32_t)0x000000C0) /* TIM1_RM[1:0] bits (TIM1 remapping) */ +#define AFIO_PCFR1_TIM1_RM_0 ((uint32_t)0x00000040) /* Bit 0 */ +#define AFIO_PCFR1_TIM1_RM_1 ((uint32_t)0x00000080) /* Bit 1 */ + +#define AFIO_PCFR1_TIM2_RM ((uint32_t)0x00000300) /* TIM2_RM[1:0] bits (TIM2 remapping) */ +#define AFIO_PCFR1_TIM2_RM_0 ((uint32_t)0x00000100) /* Bit 0 */ +#define AFIO_PCFR1_TIM2_RM_1 ((uint32_t)0x00000200) /* Bit 1 */ + +#define AFIO_PCFR1_TIM3_RM ((uint32_t)0x00000400) /* TIM3_RM bits (TIM3 remapping) */ + +#define AFIO_PCFR1_TIM4_RM ((uint32_t)0x00001000) /* TIM4_RM bit (TIM4 remapping) */ + +#define AFIO_PCFR1_CAN_RM ((uint32_t)0x00006000) /* CAN_RM[1:0] bits (CAN Alternate function remapping) */ +#define AFIO_PCFR1_CAN_RM_0 ((uint32_t)0x00002000) /* Bit 0 */ +#define AFIO_PCFR1_CAN_RM_1 ((uint32_t)0x00004000) /* Bit 1 */ + +#define AFIO_PCFR1_PD0PD1_RM ((uint32_t)0x00008000) /* Port D0/Port D1 mapping on OSC_IN/OSC_OUT */ +#define AFIO_PCFR1_PD01_RM AFIO_PCFR1_PD0PD1_RM + +#define AFIO_PCFR1_SW_CFG ((uint32_t)0x07000000) /* SW_CFG[2:0] bits (SDI configuration) */ +#define AFIO_PCFR1_SW_CFG_0 ((uint32_t)0x01000000) /* Bit 0 */ +#define AFIO_PCFR1_SW_CFG_1 ((uint32_t)0x02000000) /* Bit 1 */ +#define AFIO_PCFR1_SW_CFG_2 ((uint32_t)0x04000000) /* Bit 2 */ + +/***************** Bit definition for AFIO_EXTICR1 register *****************/ +#define AFIO_EXTICR1_EXTI0 ((uint16_t)0x000F) /* EXTI 0 configuration */ +#define AFIO_EXTICR1_EXTI1 ((uint16_t)0x00F0) /* EXTI 1 configuration */ +#define AFIO_EXTICR1_EXTI2 ((uint16_t)0x0F00) /* EXTI 2 configuration */ +#define AFIO_EXTICR1_EXTI3 ((uint16_t)0xF000) /* EXTI 3 configuration */ + +#define AFIO_EXTICR1_EXTI0_PA ((uint16_t)0x0000) /* PA[0] pin */ +#define AFIO_EXTICR1_EXTI0_PB ((uint16_t)0x0001) /* PB[0] pin */ +#define AFIO_EXTICR1_EXTI0_PC ((uint16_t)0x0002) /* PC[0] pin */ +#define AFIO_EXTICR1_EXTI0_PD ((uint16_t)0x0003) /* PD[0] pin */ + +#define AFIO_EXTICR1_EXTI1_PA ((uint16_t)0x0000) /* PA[1] pin */ +#define AFIO_EXTICR1_EXTI1_PB ((uint16_t)0x0010) /* PB[1] pin */ +#define AFIO_EXTICR1_EXTI1_PC ((uint16_t)0x0020) /* PC[1] pin */ +#define AFIO_EXTICR1_EXTI1_PD ((uint16_t)0x0030) /* PD[1] pin */ + +#define AFIO_EXTICR1_EXTI2_PA ((uint16_t)0x0000) /* PA[2] pin */ +#define AFIO_EXTICR1_EXTI2_PB ((uint16_t)0x0100) /* PB[2] pin */ +#define AFIO_EXTICR1_EXTI2_PC ((uint16_t)0x0200) /* PC[2] pin */ +#define AFIO_EXTICR1_EXTI2_PD ((uint16_t)0x0300) /* PD[2] pin */ + +#define AFIO_EXTICR1_EXTI3_PA ((uint16_t)0x0000) /* PA[3] pin */ +#define AFIO_EXTICR1_EXTI3_PB ((uint16_t)0x1000) /* PB[3] pin */ +#define AFIO_EXTICR1_EXTI3_PC ((uint16_t)0x2000) /* PC[3] pin */ +#define AFIO_EXTICR1_EXTI3_PD ((uint16_t)0x3000) /* PD[3] pin */ + +/***************** Bit definition for AFIO_EXTICR2 register *****************/ +#define AFIO_EXTICR2_EXTI4 ((uint16_t)0x000F) /* EXTI 4 configuration */ +#define AFIO_EXTICR2_EXTI5 ((uint16_t)0x00F0) /* EXTI 5 configuration */ +#define AFIO_EXTICR2_EXTI6 ((uint16_t)0x0F00) /* EXTI 6 configuration */ +#define AFIO_EXTICR2_EXTI7 ((uint16_t)0xF000) /* EXTI 7 configuration */ + +#define AFIO_EXTICR2_EXTI4_PA ((uint16_t)0x0000) /* PA[4] pin */ +#define AFIO_EXTICR2_EXTI4_PB ((uint16_t)0x0001) /* PB[4] pin */ +#define AFIO_EXTICR2_EXTI4_PC ((uint16_t)0x0002) /* PC[4] pin */ +#define AFIO_EXTICR2_EXTI4_PD ((uint16_t)0x0003) /* PD[4] pin */ + +#define AFIO_EXTICR2_EXTI5_PA ((uint16_t)0x0000) /* PA[5] pin */ +#define AFIO_EXTICR2_EXTI5_PB ((uint16_t)0x0010) /* PB[5] pin */ +#define AFIO_EXTICR2_EXTI5_PC ((uint16_t)0x0020) /* PC[5] pin */ +#define AFIO_EXTICR2_EXTI5_PD ((uint16_t)0x0030) /* PD[5] pin */ + +#define AFIO_EXTICR2_EXTI6_PA ((uint16_t)0x0000) /* PA[6] pin */ +#define AFIO_EXTICR2_EXTI6_PB ((uint16_t)0x0100) /* PB[6] pin */ +#define AFIO_EXTICR2_EXTI6_PC ((uint16_t)0x0200) /* PC[6] pin */ +#define AFIO_EXTICR2_EXTI6_PD ((uint16_t)0x0300) /* PD[6] pin */ + +#define AFIO_EXTICR2_EXTI7_PA ((uint16_t)0x0000) /* PA[7] pin */ +#define AFIO_EXTICR2_EXTI7_PB ((uint16_t)0x1000) /* PB[7] pin */ +#define AFIO_EXTICR2_EXTI7_PC ((uint16_t)0x2000) /* PC[7] pin */ +#define AFIO_EXTICR2_EXTI7_PD ((uint16_t)0x3000) /* PD[7] pin */ + +/***************** Bit definition for AFIO_EXTICR3 register *****************/ +#define AFIO_EXTICR3_EXTI8 ((uint16_t)0x000F) /* EXTI 8 configuration */ +#define AFIO_EXTICR3_EXTI9 ((uint16_t)0x00F0) /* EXTI 9 configuration */ +#define AFIO_EXTICR3_EXTI10 ((uint16_t)0x0F00) /* EXTI 10 configuration */ +#define AFIO_EXTICR3_EXTI11 ((uint16_t)0xF000) /* EXTI 11 configuration */ + +#define AFIO_EXTICR3_EXTI8_PA ((uint16_t)0x0000) /* PA[8] pin */ +#define AFIO_EXTICR3_EXTI8_PB ((uint16_t)0x0001) /* PB[8] pin */ +#define AFIO_EXTICR3_EXTI8_PC ((uint16_t)0x0002) /* PC[8] pin */ +#define AFIO_EXTICR3_EXTI8_PD ((uint16_t)0x0003) /* PD[8] pin */ + +#define AFIO_EXTICR3_EXTI9_PA ((uint16_t)0x0000) /* PA[9] pin */ +#define AFIO_EXTICR3_EXTI9_PB ((uint16_t)0x0010) /* PB[9] pin */ +#define AFIO_EXTICR3_EXTI9_PC ((uint16_t)0x0020) /* PC[9] pin */ +#define AFIO_EXTICR3_EXTI9_PD ((uint16_t)0x0030) /* PD[9] pin */ + +#define AFIO_EXTICR3_EXTI10_PA ((uint16_t)0x0000) /* PA[10] pin */ +#define AFIO_EXTICR3_EXTI10_PB ((uint16_t)0x0100) /* PB[10] pin */ +#define AFIO_EXTICR3_EXTI10_PC ((uint16_t)0x0200) /* PC[10] pin */ +#define AFIO_EXTICR3_EXTI10_PD ((uint16_t)0x0300) /* PD[10] pin */ + +#define AFIO_EXTICR3_EXTI11_PA ((uint16_t)0x0000) /* PA[11] pin */ +#define AFIO_EXTICR3_EXTI11_PB ((uint16_t)0x1000) /* PB[11] pin */ +#define AFIO_EXTICR3_EXTI11_PC ((uint16_t)0x2000) /* PC[11] pin */ +#define AFIO_EXTICR3_EXTI11_PD ((uint16_t)0x3000) /* PD[11] pin */ + +/***************** Bit definition for AFIO_EXTICR4 register *****************/ +#define AFIO_EXTICR4_EXTI12 ((uint16_t)0x000F) /* EXTI 12 configuration */ +#define AFIO_EXTICR4_EXTI13 ((uint16_t)0x00F0) /* EXTI 13 configuration */ +#define AFIO_EXTICR4_EXTI14 ((uint16_t)0x0F00) /* EXTI 14 configuration */ +#define AFIO_EXTICR4_EXTI15 ((uint16_t)0xF000) /* EXTI 15 configuration */ + +#define AFIO_EXTICR4_EXTI12_PA ((uint16_t)0x0000) /* PA[12] pin */ +#define AFIO_EXTICR4_EXTI12_PB ((uint16_t)0x0001) /* PB[12] pin */ +#define AFIO_EXTICR4_EXTI12_PC ((uint16_t)0x0002) /* PC[12] pin */ +#define AFIO_EXTICR4_EXTI12_PD ((uint16_t)0x0003) /* PD[12] pin */ + +#define AFIO_EXTICR4_EXTI13_PA ((uint16_t)0x0000) /* PA[13] pin */ +#define AFIO_EXTICR4_EXTI13_PB ((uint16_t)0x0010) /* PB[13] pin */ +#define AFIO_EXTICR4_EXTI13_PC ((uint16_t)0x0020) /* PC[13] pin */ +#define AFIO_EXTICR4_EXTI13_PD ((uint16_t)0x0030) /* PD[13] pin */ + +#define AFIO_EXTICR4_EXTI14_PA ((uint16_t)0x0000) /* PA[14] pin */ +#define AFIO_EXTICR4_EXTI14_PB ((uint16_t)0x0100) /* PB[14] pin */ +#define AFIO_EXTICR4_EXTI14_PC ((uint16_t)0x0200) /* PC[14] pin */ +#define AFIO_EXTICR4_EXTI14_PD ((uint16_t)0x0300) /* PD[14] pin */ + +#define AFIO_EXTICR4_EXTI15_PA ((uint16_t)0x0000) /* PA[15] pin */ +#define AFIO_EXTICR4_EXTI15_PB ((uint16_t)0x1000) /* PB[15] pin */ +#define AFIO_EXTICR4_EXTI15_PC ((uint16_t)0x2000) /* PC[15] pin */ +#define AFIO_EXTICR4_EXTI15_PD ((uint16_t)0x3000) /* PD[15] pin */ + +/***************** Bit definition for AFIO_CR register *****************/ +#define AFIO_CR_USBPD_IN_HVT ((uint32_t)0x00000200) +#define AFIO_CR_UPD_BC_VSRC ((uint32_t)0x00010000) +#define AFIO_CR_UDM_BC_VSRC ((uint32_t)0x00020000) +#define AFIO_CR_UPD_BC_CMPE ((uint32_t)0x00040000) +#define AFIO_CR_UDM_BC_CMPE ((uint32_t)0x00080000) +#define AFIO_CR_UPD_BC_CMPO ((uint32_t)0x00100000) +#define AFIO_CR_UDM_BC_CMPO ((uint32_t)0x00200000) + +/***************** Bit definition for AFIO_PCFR2 register *****************/ +#define AFIO_PCFR2_USART4_RM ((uint32_t)0x00010000) +#define AFIO_PCFR2_USART2_RM_H ((uint32_t)0x00040000) + +#define AFIO_PCFR2_USART1_RM_H ((uint32_t)0x00180000) +#define AFIO_PCFR2_USART1_RM_H_0 ((uint32_t)0x00080000) +#define AFIO_PCFR2_USART1_RM_H_1 ((uint32_t)0x00100000) + +#define AFIO_PCFR2_TIM2_RM_H ((uint32_t)0x00200000) +#define AFIO_PCFR2_TIM1_RM_H ((uint32_t)0x00400000) +#define AFIO_PCFR2_I2C_RM_H ((uint32_t)0x00800000) +#define AFIO_PCFR2_SPI1_RM_H ((uint32_t)0x01000000) +#define AFIO_PCFR2_LPTIM_RM ((uint32_t)0x02000000) + +/******************************************************************************/ +/* Independent WATCHDOG */ +/******************************************************************************/ + +/******************* Bit definition for IWDG_CTLR register ********************/ +#define IWDG_KEY ((uint16_t)0xFFFF) /* Key value (write only, read 0000h) */ + +/******************* Bit definition for IWDG_PSCR register ********************/ +#define IWDG_PR ((uint8_t)0x07) /* PR[2:0] (Prescaler divider) */ +#define IWDG_PR_0 ((uint8_t)0x01) /* Bit 0 */ +#define IWDG_PR_1 ((uint8_t)0x02) /* Bit 1 */ +#define IWDG_PR_2 ((uint8_t)0x04) /* Bit 2 */ + +/******************* Bit definition for IWDG_RLDR register *******************/ +#define IWDG_RL ((uint16_t)0x0FFF) /* Watchdog counter reload value */ + +/******************* Bit definition for IWDG_STATR register ********************/ +#define IWDG_PVU ((uint8_t)0x01) /* Watchdog prescaler value update */ +#define IWDG_RVU ((uint8_t)0x02) /* Watchdog counter reload value update */ + +/******************************************************************************/ +/* Inter-integrated Circuit Interface */ +/******************************************************************************/ + +/******************* Bit definition for I2C_CTLR1 register ********************/ +#define I2C_CTLR1_PE ((uint16_t)0x0001) /* Peripheral Enable */ +#define I2C_CTLR1_SMBUS ((uint16_t)0x0002) /* SMBus Mode */ +#define I2C_CTLR1_SMBTYPE ((uint16_t)0x0008) /* SMBus Type */ +#define I2C_CTLR1_ENARP ((uint16_t)0x0010) /* ARP Enable */ +#define I2C_CTLR1_ENPEC ((uint16_t)0x0020) /* PEC Enable */ +#define I2C_CTLR1_ENGC ((uint16_t)0x0040) /* General Call Enable */ +#define I2C_CTLR1_NOSTRETCH ((uint16_t)0x0080) /* Clock Stretching Disable (Slave mode) */ +#define I2C_CTLR1_START ((uint16_t)0x0100) /* Start Generation */ +#define I2C_CTLR1_STOP ((uint16_t)0x0200) /* Stop Generation */ +#define I2C_CTLR1_ACK ((uint16_t)0x0400) /* Acknowledge Enable */ +#define I2C_CTLR1_POS ((uint16_t)0x0800) /* Acknowledge/PEC Position (for data reception) */ +#define I2C_CTLR1_PEC ((uint16_t)0x1000) /* Packet Error Checking */ +#define I2C_CTLR1_ALERT ((uint16_t)0x2000) /* SMBus Alert */ +#define I2C_CTLR1_SWRST ((uint16_t)0x8000) /* Software Reset */ + +/******************* Bit definition for I2C_CTLR2 register ********************/ +#define I2C_CTLR2_FREQ ((uint16_t)0x003F) /* FREQ[5:0] bits (Peripheral Clock Frequency) */ +#define I2C_CTLR2_FREQ_0 ((uint16_t)0x0001) /* Bit 0 */ +#define I2C_CTLR2_FREQ_1 ((uint16_t)0x0002) /* Bit 1 */ +#define I2C_CTLR2_FREQ_2 ((uint16_t)0x0004) /* Bit 2 */ +#define I2C_CTLR2_FREQ_3 ((uint16_t)0x0008) /* Bit 3 */ +#define I2C_CTLR2_FREQ_4 ((uint16_t)0x0010) /* Bit 4 */ +#define I2C_CTLR2_FREQ_5 ((uint16_t)0x0020) /* Bit 5 */ + +#define I2C_CTLR2_ITERREN ((uint16_t)0x0100) /* Error Interrupt Enable */ +#define I2C_CTLR2_ITEVTEN ((uint16_t)0x0200) /* Event Interrupt Enable */ +#define I2C_CTLR2_ITBUFEN ((uint16_t)0x0400) /* Buffer Interrupt Enable */ +#define I2C_CTLR2_DMAEN ((uint16_t)0x0800) /* DMA Requests Enable */ +#define I2C_CTLR2_LAST ((uint16_t)0x1000) /* DMA Last Transfer */ + +/******************* Bit definition for I2C_OADDR1 register *******************/ +#define I2C_OADDR1_ADD1_7 ((uint16_t)0x00FE) /* Interface Address */ +#define I2C_OADDR1_ADD8_9 ((uint16_t)0x0300) /* Interface Address */ + +#define I2C_OADDR1_ADD0 ((uint16_t)0x0001) /* Bit 0 */ +#define I2C_OADDR1_ADD1 ((uint16_t)0x0002) /* Bit 1 */ +#define I2C_OADDR1_ADD2 ((uint16_t)0x0004) /* Bit 2 */ +#define I2C_OADDR1_ADD3 ((uint16_t)0x0008) /* Bit 3 */ +#define I2C_OADDR1_ADD4 ((uint16_t)0x0010) /* Bit 4 */ +#define I2C_OADDR1_ADD5 ((uint16_t)0x0020) /* Bit 5 */ +#define I2C_OADDR1_ADD6 ((uint16_t)0x0040) /* Bit 6 */ +#define I2C_OADDR1_ADD7 ((uint16_t)0x0080) /* Bit 7 */ +#define I2C_OADDR1_ADD8 ((uint16_t)0x0100) /* Bit 8 */ +#define I2C_OADDR1_ADD9 ((uint16_t)0x0200) /* Bit 9 */ + +#define I2C_OADDR1_ADDMODE ((uint16_t)0x8000) /* Addressing Mode (Slave mode) */ + +/******************* Bit definition for I2C_OADDR2 register *******************/ +#define I2C_OADDR2_ENDUAL ((uint8_t)0x01) /* Dual addressing mode enable */ +#define I2C_OADDR2_ADD2 ((uint8_t)0xFE) /* Interface address */ + +/******************** Bit definition for I2C_DATAR register ********************/ +#define I2C_DR_DATAR ((uint8_t)0xFF) /* 8-bit Data Register */ + +/******************* Bit definition for I2C_STAR1 register ********************/ +#define I2C_STAR1_SB ((uint16_t)0x0001) /* Start Bit (Master mode) */ +#define I2C_STAR1_ADDR ((uint16_t)0x0002) /* Address sent (master mode)/matched (slave mode) */ +#define I2C_STAR1_BTF ((uint16_t)0x0004) /* Byte Transfer Finished */ +#define I2C_STAR1_ADD10 ((uint16_t)0x0008) /* 10-bit header sent (Master mode) */ +#define I2C_STAR1_STOPF ((uint16_t)0x0010) /* Stop detection (Slave mode) */ +#define I2C_STAR1_RXNE ((uint16_t)0x0040) /* Data Register not Empty (receivers) */ +#define I2C_STAR1_TXE ((uint16_t)0x0080) /* Data Register Empty (transmitters) */ +#define I2C_STAR1_BERR ((uint16_t)0x0100) /* Bus Error */ +#define I2C_STAR1_ARLO ((uint16_t)0x0200) /* Arbitration Lost (master mode) */ +#define I2C_STAR1_AF ((uint16_t)0x0400) /* Acknowledge Failure */ +#define I2C_STAR1_OVR ((uint16_t)0x0800) /* Overrun/Underrun */ +#define I2C_STAR1_PECERR ((uint16_t)0x1000) /* PEC Error in reception */ +#define I2C_STAR1_TIMEOUT ((uint16_t)0x4000) /* Timeout or Tlow Error */ +#define I2C_STAR1_SMBALERT ((uint16_t)0x8000) /* SMBus Alert */ + +/******************* Bit definition for I2C_STAR2 register ********************/ +#define I2C_STAR2_MSL ((uint16_t)0x0001) /* Master/Slave */ +#define I2C_STAR2_BUSY ((uint16_t)0x0002) /* Bus Busy */ +#define I2C_STAR2_TRA ((uint16_t)0x0004) /* Transmitter/Receiver */ +#define I2C_STAR2_GENCALL ((uint16_t)0x0010) /* General Call Address (Slave mode) */ +#define I2C_STAR2_SMBDEFAULT ((uint16_t)0x0020) /* SMBus Device Default Address (Slave mode) */ +#define I2C_STAR2_SMBHOST ((uint16_t)0x0040) /* SMBus Host Header (Slave mode) */ +#define I2C_STAR2_DUALF ((uint16_t)0x0080) /* Dual Flag (Slave mode) */ +#define I2C_STAR2_PEC ((uint16_t)0xFF00) /* Packet Error Checking Register */ + +/******************* Bit definition for I2C_CKCFGR register ********************/ +#define I2C_CKCFGR_CCR ((uint16_t)0x0FFF) /* Clock Control Register in Fast/Standard mode (Master mode) */ +#define I2C_CKCFGR_DUTY ((uint16_t)0x4000) /* Fast Mode Duty Cycle */ +#define I2C_CKCFGR_FS ((uint16_t)0x8000) /* I2C Master Mode Selection */ + +/****************** Bit definition for I2C_RTR register *******************/ +#define I2C_RTR_TRISE ((uint8_t)0x3F) /* Maximum Rise Time in Fast/Standard mode (Master mode) */ + +/******************************************************************************/ +/* Power Control */ +/******************************************************************************/ + +/******************** Bit definition for PWR_CTLR register ********************/ +#define PWR_CTLR_LPDS ((uint16_t)0x0001) /* Low-Power Deepsleep */ +#define PWR_CTLR_PDDS ((uint16_t)0x0002) /* Power Down Deepsleep */ +#define PWR_CTLR_CWUF ((uint16_t)0x0004) /* Clear Wakeup Flag */ +#define PWR_CTLR_CSBF ((uint16_t)0x0008) /* Clear Standby Flag */ +#define PWR_CTLR_PVDE ((uint16_t)0x0010) /* Power Voltage Detector Enable */ + +#define PWR_CTLR_PLS ((uint16_t)0x00E0) /* PLS[2:0] bits (PVD Level Selection) */ +#define PWR_CTLR_PLS_0 ((uint16_t)0x0020) /* Bit 0 */ +#define PWR_CTLR_PLS_1 ((uint16_t)0x0040) /* Bit 1 */ +#define PWR_CTLR_PLS_2 ((uint16_t)0x0080) /* Bit 2 */ + +#define PWR_CTLR_PLS_MODE0 ((uint16_t)0x0000) /* PVD level 0 */ +#define PWR_CTLR_PLS_MODE1 ((uint16_t)0x0020) /* PVD level 1 */ +#define PWR_CTLR_PLS_MODE2 ((uint16_t)0x0040) /* PVD level 2 */ +#define PWR_CTLR_PLS_MODE3 ((uint16_t)0x0060) /* PVD level 3 */ +#define PWR_CTLR_PLS_MODE4 ((uint16_t)0x0080) /* PVD level 4 */ +#define PWR_CTLR_PLS_MODE5 ((uint16_t)0x00A0) /* PVD level 5 */ +#define PWR_CTLR_PLS_MODE6 ((uint16_t)0x00C0) /* PVD level 6 */ +#define PWR_CTLR_PLS_MODE7 ((uint16_t)0x00E0) /* PVD level 7 */ + +#define PWR_CTLR_DBP ((uint16_t)0x0100) /* Disable Backup Domain write protection */ + +#define PWR_CTLR_FLASH_LP_REG ((uint16_t)0x0200) + +#define PWR_CTLR_FLASH_LP ((uint16_t)0x0C00) /* FLASH_LP [1:0]*/ +#define PWR_CTLR_FLASH_LP_0 ((uint16_t)0x0400) +#define PWR_CTLR_FLASH_LP_1 ((uint16_t)0x0800) + +#define PWR_CTLR_AUTO_LDO_EC ((uint16_t)0x1000) +#define PWR_CTLR_LDO_EC ((uint16_t)0x2000) +#define PWR_CTLR_R2KSTY ((uint32_t)0x00010000) +#define PWR_CTLR_R18KSTY ((uint32_t)0x00020000) +#define PWR_CTLR_R2KVBAT ((uint32_t)0x00040000) +#define PWR_CTLR_R18KVBAT ((uint32_t)0x00080000) +#define PWR_RAMLV ((uint32_t)0x00100000) + +/******************* Bit definition for PWR_CSR register ********************/ +#define PWR_CSR_WUF ((uint16_t)0x0001) /* Wakeup Flag */ +#define PWR_CSR_SBF ((uint16_t)0x0002) /* Standby Flag */ +#define PWR_CSR_PVDO ((uint16_t)0x0004) /* PVD Output */ +#define PWR_CSR_EWUP ((uint16_t)0x0100) /* Enable WKUP pin */ + +/******************************************************************************/ +/* Reset and Clock Control */ +/******************************************************************************/ + +/******************** Bit definition for RCC_CTLR register ********************/ +#define RCC_HSION ((uint32_t)0x00000001) /* Internal High Speed clock enable */ +#define RCC_HSIRDY ((uint32_t)0x00000002) /* Internal High Speed clock ready flag */ +#define RCC_HSILP ((uint32_t)0x00000004) +#define RCC_HSITRIM ((uint32_t)0x000000F8) /* Internal High Speed clock trimming */ +#define RCC_HSICAL ((uint32_t)0x0000FF00) /* Internal High Speed clock Calibration */ +#define RCC_HSEON ((uint32_t)0x00010000) /* External High Speed clock enable */ +#define RCC_HSERDY ((uint32_t)0x00020000) /* External High Speed clock ready flag */ +#define RCC_HSEBYP ((uint32_t)0x00040000) /* External High Speed clock Bypass */ +#define RCC_CSSON ((uint32_t)0x00080000) /* Clock Security System enable */ +#define RCC_HSELP ((uint32_t)0x00100000) +#define RCC_PLLON ((uint32_t)0x01000000) /* PLL enable */ +#define RCC_PLLRDY ((uint32_t)0x02000000) /* PLL clock ready flag */ + +/******************* Bit definition for RCC_CFGR0 register *******************/ +#define RCC_SW ((uint32_t)0x00000003) /* SW[1:0] bits (System clock Switch) */ +#define RCC_SW_0 ((uint32_t)0x00000001) /* Bit 0 */ +#define RCC_SW_1 ((uint32_t)0x00000002) /* Bit 1 */ + +#define RCC_SW_HSI ((uint32_t)0x00000000) /* HSI selected as system clock */ +#define RCC_SW_HSE ((uint32_t)0x00000001) /* HSE selected as system clock */ +#define RCC_SW_PLL ((uint32_t)0x00000002) /* PLL selected as system clock */ + +#define RCC_SWS ((uint32_t)0x0000000C) /* SWS[1:0] bits (System Clock Switch Status) */ +#define RCC_SWS_0 ((uint32_t)0x00000004) /* Bit 0 */ +#define RCC_SWS_1 ((uint32_t)0x00000008) /* Bit 1 */ + +#define RCC_SWS_HSI ((uint32_t)0x00000000) /* HSI oscillator used as system clock */ +#define RCC_SWS_HSE ((uint32_t)0x00000004) /* HSE oscillator used as system clock */ +#define RCC_SWS_PLL ((uint32_t)0x00000008) /* PLL used as system clock */ + +#define RCC_HPRE ((uint32_t)0x000000F0) /* HPRE[3:0] bits (HB prescaler) */ +#define RCC_HPRE_0 ((uint32_t)0x00000010) /* Bit 0 */ +#define RCC_HPRE_1 ((uint32_t)0x00000020) /* Bit 1 */ +#define RCC_HPRE_2 ((uint32_t)0x00000040) /* Bit 2 */ +#define RCC_HPRE_3 ((uint32_t)0x00000080) /* Bit 3 */ + +#define RCC_HPRE_DIV1 ((uint32_t)0x00000000) /* SYSCLK not divided */ +#define RCC_HPRE_DIV2 ((uint32_t)0x00000080) /* SYSCLK divided by 2 */ +#define RCC_HPRE_DIV4 ((uint32_t)0x00000090) /* SYSCLK divided by 4 */ +#define RCC_HPRE_DIV8 ((uint32_t)0x000000A0) /* SYSCLK divided by 8 */ +#define RCC_HPRE_DIV16 ((uint32_t)0x000000B0) /* SYSCLK divided by 16 */ +#define RCC_HPRE_DIV64 ((uint32_t)0x000000C0) /* SYSCLK divided by 64 */ +#define RCC_HPRE_DIV128 ((uint32_t)0x000000D0) /* SYSCLK divided by 128 */ +#define RCC_HPRE_DIV256 ((uint32_t)0x000000E0) /* SYSCLK divided by 256 */ +#define RCC_HPRE_DIV512 ((uint32_t)0x000000F0) /* SYSCLK divided by 512 */ + +#define RCC_PPRE1 ((uint32_t)0x00000700) /* PRE1[2:0] bits (PB1 prescaler) */ +#define RCC_PPRE1_0 ((uint32_t)0x00000100) /* Bit 0 */ +#define RCC_PPRE1_1 ((uint32_t)0x00000200) /* Bit 1 */ +#define RCC_PPRE1_2 ((uint32_t)0x00000400) /* Bit 2 */ + +#define RCC_PPRE1_DIV1 ((uint32_t)0x00000000) /* PPRE1 not divided */ +#define RCC_PPRE1_DIV2 ((uint32_t)0x00000400) /* PPRE1 divided by 2 */ +#define RCC_PPRE1_DIV4 ((uint32_t)0x00000500) /* PPRE1 divided by 4 */ +#define RCC_PPRE1_DIV8 ((uint32_t)0x00000600) /* PPRE1 divided by 8 */ +#define RCC_PPRE1_DIV16 ((uint32_t)0x00000700) /* PPRE1 divided by 16 */ + +#define RCC_PPRE2 ((uint32_t)0x00003800) /* PRE2[2:0] bits (PB2 prescaler) */ +#define RCC_PPRE2_0 ((uint32_t)0x00000800) /* Bit 0 */ +#define RCC_PPRE2_1 ((uint32_t)0x00001000) /* Bit 1 */ +#define RCC_PPRE2_2 ((uint32_t)0x00002000) /* Bit 2 */ + +#define RCC_PPRE2_DIV1 ((uint32_t)0x00000000) /* PPRE2 not divided */ +#define RCC_PPRE2_DIV2 ((uint32_t)0x00002000) /* PPRE2 divided by 2 */ +#define RCC_PPRE2_DIV4 ((uint32_t)0x00002800) /* PPRE2 divided by 4 */ +#define RCC_PPRE2_DIV8 ((uint32_t)0x00003000) /* PPRE2 divided by 8 */ +#define RCC_PPRE2_DIV16 ((uint32_t)0x00003800) /* PPRE2 divided by 16 */ + +#define RCC_ADCPRE ((uint32_t)0x0000C000) /* ADCPRE[1:0] bits (ADC prescaler) */ +#define RCC_ADCPRE_0 ((uint32_t)0x00004000) /* Bit 0 */ +#define RCC_ADCPRE_1 ((uint32_t)0x00008000) /* Bit 1 */ + +#define RCC_ADCPRE_DIV2 ((uint32_t)0x00000000) /* ADCPRE divided by 2 */ +#define RCC_ADCPRE_DIV4 ((uint32_t)0x00004000) /* ADCPRE divided by 4 */ +#define RCC_ADCPRE_DIV6 ((uint32_t)0x00008000) /* ADCPRE divided by 6 */ +#define RCC_ADCPRE_DIV8 ((uint32_t)0x0000C000) /* ADCPRE divided by 8 */ + +#define RCC_PLLSRC ((uint32_t)0x00010000) /* PLL entry clock source */ + +#define RCC_PLLXTPRE ((uint32_t)0x00020000) /* HSE divider for PLL entry */ + +#define RCC_PLLMULL ((uint32_t)0x003C0000) /* PLLMUL[3:0] bits (PLL multiplication factor) */ +#define RCC_PLLMULL_0 ((uint32_t)0x00040000) /* Bit 0 */ +#define RCC_PLLMULL_1 ((uint32_t)0x00080000) /* Bit 1 */ +#define RCC_PLLMULL_2 ((uint32_t)0x00100000) /* Bit 2 */ +#define RCC_PLLMULL_3 ((uint32_t)0x00200000) /* Bit 3 */ + +#define RCC_PLLSRC_HSI_Div2 ((uint32_t)0x00000000) /* HSI clock divided by 2 selected as PLL entry clock source */ +#define RCC_PLLSRC_HSE ((uint32_t)0x00010000) /* HSE clock selected as PLL entry clock source */ + +#define RCC_PLLXTPRE_HSE ((uint32_t)0x00000000) /* HSE clock not divided for PLL entry */ +#define RCC_PLLXTPRE_HSE_Div2 ((uint32_t)0x00020000) /* HSE clock divided by 2 for PLL entry */ + +/* for other CH32L103 */ +#define RCC_PLLMULL2 ((uint32_t)0x00000000) /* PLL input clock*2 */ +#define RCC_PLLMULL3 ((uint32_t)0x00040000) /* PLL input clock*3 */ +#define RCC_PLLMULL4 ((uint32_t)0x00080000) /* PLL input clock*4 */ +#define RCC_PLLMULL5 ((uint32_t)0x000C0000) /* PLL input clock*5 */ +#define RCC_PLLMULL6 ((uint32_t)0x00100000) /* PLL input clock*6 */ +#define RCC_PLLMULL7 ((uint32_t)0x00140000) /* PLL input clock*7 */ +#define RCC_PLLMULL8 ((uint32_t)0x00180000) /* PLL input clock*8 */ +#define RCC_PLLMULL9 ((uint32_t)0x001C0000) /* PLL input clock*9 */ +#define RCC_PLLMULL10 ((uint32_t)0x00200000) /* PLL input clock10 */ +#define RCC_PLLMULL11 ((uint32_t)0x00240000) /* PLL input clock*11 */ +#define RCC_PLLMULL12 ((uint32_t)0x00280000) /* PLL input clock*12 */ +#define RCC_PLLMULL13 ((uint32_t)0x002C0000) /* PLL input clock*13 */ +#define RCC_PLLMULL14 ((uint32_t)0x00300000) /* PLL input clock*14 */ +#define RCC_PLLMULL15 ((uint32_t)0x00340000) /* PLL input clock*15 */ +#define RCC_PLLMULL16 ((uint32_t)0x00380000) /* PLL input clock*16 */ +#define RCC_PLLMULL18 ((uint32_t)0x003C0000) /* PLL input clock*18 */ + +#define RCC_CFGR0_USBPRE ((uint32_t)0x00C00000) /* USBPRE[1:0] bits*/ +#define RCC_USBPRE_0 ((uint32_t)0x00400000) /* Bit 0 */ +#define RCC_USBPRE_1 ((uint32_t)0x00800000) /* Bit 1 */ + +#define RCC_CFGR0_MCO ((uint32_t)0x07000000) /* MCO[2:0] bits (Microcontroller Clock Output) */ +#define RCC_MCO_0 ((uint32_t)0x01000000) /* Bit 0 */ +#define RCC_MCO_1 ((uint32_t)0x02000000) /* Bit 1 */ +#define RCC_MCO_2 ((uint32_t)0x04000000) /* Bit 2 */ + +#define RCC_MCO_NOCLOCK ((uint32_t)0x00000000) /* No clock */ +#define RCC_CFGR0_MCO_SYSCLK ((uint32_t)0x04000000) /* System clock selected as MCO source */ +#define RCC_CFGR0_MCO_HSI ((uint32_t)0x05000000) /* HSI clock selected as MCO source */ +#define RCC_CFGR0_MCO_HSE ((uint32_t)0x06000000) /* HSE clock selected as MCO source */ +#define RCC_CFGR0_MCO_PLL ((uint32_t)0x07000000) /* PLL clock divided by 2 selected as MCO source */ + +#define RCC_ADC_DUTY_CHG ((uint32_t)0x70000000) /* DUTY_CHG[2:0] bits */ +#define RCC_ADC_DUTY_CHG_0 ((uint32_t)0x10000000) +#define RCC_ADC_DUTY_CHG_1 ((uint32_t)0x20000000) +#define RCC_ADC_DUTY_CHG_2 ((uint32_t)0x40000000) + +#define RCC_ADC_PRE_ADJ ((uint32_t)0x80000000) + +/******************* Bit definition for RCC_INTR register ********************/ +#define RCC_LSIRDYF ((uint32_t)0x00000001) /* LSI Ready Interrupt flag */ +#define RCC_LSERDYF ((uint32_t)0x00000002) /* LSE Ready Interrupt flag */ +#define RCC_HSIRDYF ((uint32_t)0x00000004) /* HSI Ready Interrupt flag */ +#define RCC_HSERDYF ((uint32_t)0x00000008) /* HSE Ready Interrupt flag */ +#define RCC_PLLRDYF ((uint32_t)0x00000010) /* PLL Ready Interrupt flag */ +#define RCC_CSSF ((uint32_t)0x00000080) /* Clock Security System Interrupt flag */ +#define RCC_LSIRDYIE ((uint32_t)0x00000100) /* LSI Ready Interrupt Enable */ +#define RCC_LSERDYIE ((uint32_t)0x00000200) /* LSE Ready Interrupt Enable */ +#define RCC_HSIRDYIE ((uint32_t)0x00000400) /* HSI Ready Interrupt Enable */ +#define RCC_HSERDYIE ((uint32_t)0x00000800) /* HSE Ready Interrupt Enable */ +#define RCC_PLLRDYIE ((uint32_t)0x00001000) /* PLL Ready Interrupt Enable */ +#define RCC_LSIRDYC ((uint32_t)0x00010000) /* LSI Ready Interrupt Clear */ +#define RCC_LSERDYC ((uint32_t)0x00020000) /* LSE Ready Interrupt Clear */ +#define RCC_HSIRDYC ((uint32_t)0x00040000) /* HSI Ready Interrupt Clear */ +#define RCC_HSERDYC ((uint32_t)0x00080000) /* HSE Ready Interrupt Clear */ +#define RCC_PLLRDYC ((uint32_t)0x00100000) /* PLL Ready Interrupt Clear */ +#define RCC_CSSC ((uint32_t)0x00800000) /* Clock Security System Interrupt Clear */ + +/***************** Bit definition for RCC_PB2PRSTR register *****************/ +#define RCC_AFIORST ((uint32_t)0x00000001) /* Alternate Function I/O reset */ +#define RCC_IOPARST ((uint32_t)0x00000004) /* I/O port A reset */ +#define RCC_IOPBRST ((uint32_t)0x00000008) /* I/O port B reset */ +#define RCC_IOPCRST ((uint32_t)0x00000010) /* I/O port C reset */ +#define RCC_IOPDRST ((uint32_t)0x00000020) /* I/O port D reset */ +#define RCC_ADCRST ((uint32_t)0x00000200) /* ADC interface reset */ +#define RCC_TIM1RST ((uint32_t)0x00000800) /* TIM1 Timer reset */ +#define RCC_SPI1RST ((uint32_t)0x00001000) /* SPI 1 reset */ +#define RCC_USART1RST ((uint32_t)0x00004000) /* USART1 reset */ + +/***************** Bit definition for RCC_PB1PRSTR register *****************/ +#define RCC_TIM2RST ((uint32_t)0x00000001) /* Timer 2 reset */ +#define RCC_TIM3RST ((uint32_t)0x00000002) /* Timer 3 reset */ +#define RCC_TIM4RST ((uint32_t)0x00000004) +#define RCC_WWDGRST ((uint32_t)0x00000800) /* Window Watchdog reset */ +#define RCC_SPI2RST ((uint32_t)0x00004000) +#define RCC_USART2RST ((uint32_t)0x00020000) /* USART 2 reset */ +#define RCC_USART3RST ((uint32_t)0x00040000) /* USART 2 reset */ +#define RCC_USART4RST ((uint32_t)0x00080000) /* USART 2 reset */ +#define RCC_I2C1RST ((uint32_t)0x00200000) /* I2C 1 reset */ +#define RCC_I2C2RST ((uint32_t)0x00400000) /* I2C 1 reset */ +#define RCC_CANRST ((uint32_t)0x02000000) /* CAN reset */ +#define RCC_BKPRST ((uint32_t)0x08000000) /* Backup interface reset */ +#define RCC_PWRRST ((uint32_t)0x10000000) /* Power interface reset */ +#define RCC_LPTIMRST ((uint32_t)0x80000000) /* USB Device reset */ + +/****************** Bit definition for RCC_HBPCENR register ******************/ +#define RCC_DMAEN ((uint16_t)0x0001) /* DMA clock enable */ +#define RCC_SRAMEN ((uint16_t)0x0004) /* SRAM interface clock enable */ +#define RCC_CRCEN ((uint16_t)0x0040) /* CRC clock enable */ +#define RCC_USBFSEN ((uint16_t)0x1000) +#define RCC_USBPDEN ((uint32_t)0x00020000) + +/****************** Bit definition for RCC_PB2PCENR register *****************/ +#define RCC_AFIOEN ((uint32_t)0x00000001) /* Alternate Function I/O clock enable */ +#define RCC_IOPAEN ((uint32_t)0x00000004) /* I/O port A clock enable */ +#define RCC_IOPBEN ((uint32_t)0x00000008) /* I/O port B clock enable */ +#define RCC_IOPCEN ((uint32_t)0x00000010) /* I/O port C clock enable */ +#define RCC_IOPDEN ((uint32_t)0x00000020) /* I/O port D clock enable */ +#define RCC_ADCEN ((uint32_t)0x00000200) /* ADC interface clock enable */ +#define RCC_TIM1EN ((uint32_t)0x00000800) /* TIM1 Timer clock enable */ +#define RCC_SPI1EN ((uint32_t)0x00001000) /* SPI 1 clock enable */ +#define RCC_USART1EN ((uint32_t)0x00004000) /* USART1 clock enable */ + +/***************** Bit definition for RCC_PB1PCENR register ******************/ +#define RCC_TIM2EN ((uint32_t)0x00000001) /* Timer 2 clock enabled*/ +#define RCC_TIM3EN ((uint32_t)0x00000002) /* Timer 3 clock enable */ +#define RCC_TIM4EN ((uint32_t)0x00000004) +#define RCC_WWDGEN ((uint32_t)0x00000800) /* Window Watchdog clock enable */ +#define RCC_SPI2EN ((uint32_t)0x00004000) +#define RCC_USART2EN ((uint32_t)0x00020000) /* USART 2 clock enable */ +#define RCC_USART3EN ((uint32_t)0x00040000) /* USART 3 clock enable */ +#define RCC_USART4EN ((uint32_t)0x00080000) /* USART 4 clock enable */ +#define RCC_I2C1EN ((uint32_t)0x00200000) /* I2C 1 clock enable */ +#define RCC_I2C2EN ((uint32_t)0x00400000) /* I2C 2 clock enable */ +#define RCC_CANEN ((uint32_t)0x02000000) +#define RCC_BKPEN ((uint32_t)0x08000000) /* Backup interface clock enable */ +#define RCC_PWREN ((uint32_t)0x10000000) /* Power interface clock enable */ +#define RCC_LPTIMEN ((uint32_t)0x80000000) + +/******************* Bit definition for RCC_BDCTLR register *******************/ +#define RCC_LSEON ((uint32_t)0x00000001) /* External Low Speed oscillator enable */ +#define RCC_LSERDY ((uint32_t)0x00000002) /* External Low Speed oscillator Ready */ +#define RCC_LSEBYP ((uint32_t)0x00000004) /* External Low Speed oscillator Bypass */ + +#define RCC_RTCSEL ((uint32_t)0x00000300) /* RTCSEL[1:0] bits (RTC clock source selection) */ +#define RCC_RTCSEL_0 ((uint32_t)0x00000100) /* Bit 0 */ +#define RCC_RTCSEL_1 ((uint32_t)0x00000200) /* Bit 1 */ + +#define RCC_RTCEN ((uint32_t)0x00008000) /* RTC clock enable */ +#define RCC_BDRST ((uint32_t)0x00010000) /* Backup domain software reset */ + +/******************* Bit definition for RCC_RSTSCKR register ********************/ +#define RCC_LSION ((uint32_t)0x00000001) /* Internal Low Speed oscillator enable */ +#define RCC_LSIRDY ((uint32_t)0x00000002) /* Internal Low Speed oscillator Ready */ +#define RCC_RMVF ((uint32_t)0x01000000) /* Remove reset flag */ +#define RCC_PINRSTF ((uint32_t)0x04000000) /* PIN reset flag */ +#define RCC_PORRSTF ((uint32_t)0x08000000) /* POR/PDR reset flag */ +#define RCC_SFTRSTF ((uint32_t)0x10000000) /* Software Reset flag */ +#define RCC_IWDGRSTF ((uint32_t)0x20000000) /* Independent Watchdog reset flag */ +#define RCC_WWDGRSTF ((uint32_t)0x40000000) /* Window watchdog reset flag */ +#define RCC_LPWRRSTF ((uint32_t)0x80000000) /* Low-Power reset flag */ + +/******************************************************************************/ +/* Real-Time Clock */ +/******************************************************************************/ + +/******************* Bit definition for RTC_CTLRH register ********************/ +#define RTC_CTLRH_SECIE ((uint8_t)0x01) /* Second Interrupt Enable */ +#define RTC_CTLRH_ALRIE ((uint8_t)0x02) /* Alarm Interrupt Enable */ +#define RTC_CTLRH_OWIE ((uint8_t)0x04) /* OverfloW Interrupt Enable */ + +/******************* Bit definition for RTC_CTLRL register ********************/ +#define RTC_CTLRL_SECF ((uint8_t)0x01) /* Second Flag */ +#define RTC_CTLRL_ALRF ((uint8_t)0x02) /* Alarm Flag */ +#define RTC_CTLRL_OWF ((uint8_t)0x04) /* OverfloW Flag */ +#define RTC_CTLRL_RSF ((uint8_t)0x08) /* Registers Synchronized Flag */ +#define RTC_CTLRL_CNF ((uint8_t)0x10) /* Configuration Flag */ +#define RTC_CTLRL_RTOFF ((uint8_t)0x20) /* RTC operation OFF */ + +/******************* Bit definition for RTC_PSCRH register *******************/ +#define RTC_PSCRH_PRL ((uint16_t)0x000F) /* RTC Prescaler Reload Value High */ + +/******************* Bit definition for RTC_PRCRL register *******************/ +#define RTC_PRCRL_PRL ((uint16_t)0xFFFF) /* RTC Prescaler Reload Value Low */ + +/******************* Bit definition for RTC_DIVH register *******************/ +#define RTC_DIVH_RTC_DIV ((uint16_t)0x000F) /* RTC Clock Divider High */ + +/******************* Bit definition for RTC_DIVL register *******************/ +#define RTC_DIVL_RTC_DIV ((uint16_t)0xFFFF) /* RTC Clock Divider Low */ + +/******************* Bit definition for RTC_CNTH register *******************/ +#define RTC_CNTH_RTC_CNT ((uint16_t)0xFFFF) /* RTC Counter High */ + +/******************* Bit definition for RTC_CNTL register *******************/ +#define RTC_CNTL_RTC_CNT ((uint16_t)0xFFFF) /* RTC Counter Low */ + +/******************* Bit definition for RTC_ALRMH register *******************/ +#define RTC_ALRMH_RTC_ALRM ((uint16_t)0xFFFF) /* RTC Alarm High */ + +/******************* Bit definition for RTC_ALRML register *******************/ +#define RTC_ALRML_RTC_ALRM ((uint16_t)0xFFFF) /* RTC Alarm Low */ + +/******************************************************************************/ +/* Serial Peripheral Interface */ +/******************************************************************************/ + +/******************* Bit definition for SPI_CTLR1 register ********************/ +#define SPI_CTLR1_CPHA ((uint16_t)0x0001) /* Clock Phase */ +#define SPI_CTLR1_CPOL ((uint16_t)0x0002) /* Clock Polarity */ +#define SPI_CTLR1_MSTR ((uint16_t)0x0004) /* Master Selection */ + +#define SPI_CTLR1_BR ((uint16_t)0x0038) /* BR[2:0] bits (Baud Rate Control) */ +#define SPI_CTLR1_BR_0 ((uint16_t)0x0008) /* Bit 0 */ +#define SPI_CTLR1_BR_1 ((uint16_t)0x0010) /* Bit 1 */ +#define SPI_CTLR1_BR_2 ((uint16_t)0x0020) /* Bit 2 */ + +#define SPI_CTLR1_SPE ((uint16_t)0x0040) /* SPI Enable */ +#define SPI_CTLR1_LSBFIRST ((uint16_t)0x0080) /* Frame Format */ +#define SPI_CTLR1_SSI ((uint16_t)0x0100) /* Internal slave select */ +#define SPI_CTLR1_SSM ((uint16_t)0x0200) /* Software slave management */ +#define SPI_CTLR1_RXONLY ((uint16_t)0x0400) /* Receive only */ +#define SPI_CTLR1_DFF ((uint16_t)0x0800) /* Data Frame Format */ +#define SPI_CTLR1_CRCNEXT ((uint16_t)0x1000) /* Transmit CRC next */ +#define SPI_CTLR1_CRCEN ((uint16_t)0x2000) /* Hardware CRC calculation enable */ +#define SPI_CTLR1_BIDIOE ((uint16_t)0x4000) /* Output enable in bidirectional mode */ +#define SPI_CTLR1_BIDIMODE ((uint16_t)0x8000) /* Bidirectional data mode enable */ + +/******************* Bit definition for SPI_CTLR2 register ********************/ +#define SPI_CTLR2_RXDMAEN ((uint8_t)0x01) /* Rx Buffer DMA Enable */ +#define SPI_CTLR2_TXDMAEN ((uint8_t)0x02) /* Tx Buffer DMA Enable */ +#define SPI_CTLR2_SSOE ((uint8_t)0x04) /* SS Output Enable */ +#define SPI_CTLR2_ERRIE ((uint8_t)0x20) /* Error Interrupt Enable */ +#define SPI_CTLR2_RXNEIE ((uint8_t)0x40) /* RX buffer Not Empty Interrupt Enable */ +#define SPI_CTLR2_TXEIE ((uint8_t)0x80) /* Tx buffer Empty Interrupt Enable */ + +/******************** Bit definition for SPI_STATR register ********************/ +#define SPI_STATR_RXNE ((uint8_t)0x01) /* Receive buffer Not Empty */ +#define SPI_STATR_TXE ((uint8_t)0x02) /* Transmit buffer Empty */ +#define SPI_STATR_CRCERR ((uint8_t)0x10) /* CRC Error flag */ +#define SPI_STATR_MODF ((uint8_t)0x20) /* Mode fault */ +#define SPI_STATR_OVR ((uint8_t)0x40) /* Overrun flag */ +#define SPI_STATR_BSY ((uint8_t)0x80) /* Busy flag */ + +/******************** Bit definition for SPI_DATAR register ********************/ +#define SPI_DATAR_DR ((uint16_t)0xFFFF) /* Data Register */ + +/******************* Bit definition for SPI_CRCR register ******************/ +#define SPI_CRCR_CRCPOLY ((uint16_t)0xFFFF) /* CRC polynomial register */ + +/****************** Bit definition for SPI_RCRCR register ******************/ +#define SPI_RCRCR_RXCRC ((uint16_t)0xFFFF) /* Rx CRC Register */ + +/****************** Bit definition for SPI_TCRCR register ******************/ +#define SPI_TCRCR_TXCRC ((uint16_t)0xFFFF) /* Tx CRC Register */ + +/****************** Bit definition for SPI_HSCR register ******************/ +#define SPI_HSRXEN ((uint16_t)0x0001) + + +/******************************************************************************/ +/* TIM */ +/******************************************************************************/ + +/******************* Bit definition for TIM_CTLR1 register ********************/ +#define TIM_CEN ((uint16_t)0x0001) /* Counter enable */ +#define TIM_UDIS ((uint16_t)0x0002) /* Update disable */ +#define TIM_URS ((uint16_t)0x0004) /* Update request source */ +#define TIM_OPM ((uint16_t)0x0008) /* One pulse mode */ +#define TIM_DIR ((uint16_t)0x0010) /* Direction */ + +#define TIM_CMS ((uint16_t)0x0060) /* CMS[1:0] bits (Center-aligned mode selection) */ +#define TIM_CMS_0 ((uint16_t)0x0020) /* Bit 0 */ +#define TIM_CMS_1 ((uint16_t)0x0040) /* Bit 1 */ + +#define TIM_ARPE ((uint16_t)0x0080) /* Auto-reload preload enable */ + +#define TIM_CTLR1_CKD ((uint16_t)0x0300) /* CKD[1:0] bits (clock division) */ +#define TIM_CKD_0 ((uint16_t)0x0100) /* Bit 0 */ +#define TIM_CKD_1 ((uint16_t)0x0200) /* Bit 1 */ + +#define TIM_BKSEL ((uint16_t)0x1000) +#define TIM_TMR_CAP_OV_EN ((uint16_t)0x4000) +#define TIM_TMR_CAP_LVL_EN ((uint16_t)0x8000) + +/******************* Bit definition for TIM_CTLR2 register ********************/ +#define TIM_CCPC ((uint16_t)0x0001) /* Capture/Compare Preloaded Control */ +#define TIM_CCUS ((uint16_t)0x0004) /* Capture/Compare Control Update Selection */ +#define TIM_CCDS ((uint16_t)0x0008) /* Capture/Compare DMA Selection */ + +#define TIM_MMS ((uint16_t)0x0070) /* MMS[2:0] bits (Master Mode Selection) */ +#define TIM_MMS_0 ((uint16_t)0x0010) /* Bit 0 */ +#define TIM_MMS_1 ((uint16_t)0x0020) /* Bit 1 */ +#define TIM_MMS_2 ((uint16_t)0x0040) /* Bit 2 */ + +#define TIM_TI1S ((uint16_t)0x0080) /* TI1 Selection */ +#define TIM_OIS1 ((uint16_t)0x0100) /* Output Idle state 1 (OC1 output) */ +#define TIM_OIS1N ((uint16_t)0x0200) /* Output Idle state 1 (OC1N output) */ +#define TIM_OIS2 ((uint16_t)0x0400) /* Output Idle state 2 (OC2 output) */ +#define TIM_OIS2N ((uint16_t)0x0800) /* Output Idle state 2 (OC2N output) */ +#define TIM_OIS3 ((uint16_t)0x1000) /* Output Idle state 3 (OC3 output) */ +#define TIM_OIS3N ((uint16_t)0x2000) /* Output Idle state 3 (OC3N output) */ +#define TIM_OIS4 ((uint16_t)0x4000) /* Output Idle state 4 (OC4 output) */ + +/******************* Bit definition for TIM_SMCFGR register *******************/ +#define TIM_SMS ((uint16_t)0x0007) /* SMS[2:0] bits (Slave mode selection) */ +#define TIM_SMS_0 ((uint16_t)0x0001) /* Bit 0 */ +#define TIM_SMS_1 ((uint16_t)0x0002) /* Bit 1 */ +#define TIM_SMS_2 ((uint16_t)0x0004) /* Bit 2 */ + +#define TIM_TS ((uint16_t)0x0070) /* TS[2:0] bits (Trigger selection) */ +#define TIM_TS_0 ((uint16_t)0x0010) /* Bit 0 */ +#define TIM_TS_1 ((uint16_t)0x0020) /* Bit 1 */ +#define TIM_TS_2 ((uint16_t)0x0040) /* Bit 2 */ + +#define TIM_MSM ((uint16_t)0x0080) /* Master/slave mode */ + +#define TIM_ETF ((uint16_t)0x0F00) /* ETF[3:0] bits (External trigger filter) */ +#define TIM_ETF_0 ((uint16_t)0x0100) /* Bit 0 */ +#define TIM_ETF_1 ((uint16_t)0x0200) /* Bit 1 */ +#define TIM_ETF_2 ((uint16_t)0x0400) /* Bit 2 */ +#define TIM_ETF_3 ((uint16_t)0x0800) /* Bit 3 */ + +#define TIM_ETPS ((uint16_t)0x3000) /* ETPS[1:0] bits (External trigger prescaler) */ +#define TIM_ETPS_0 ((uint16_t)0x1000) /* Bit 0 */ +#define TIM_ETPS_1 ((uint16_t)0x2000) /* Bit 1 */ + +#define TIM_ECE ((uint16_t)0x4000) /* External clock enable */ +#define TIM_ETP ((uint16_t)0x8000) /* External trigger polarity */ + +/******************* Bit definition for TIM_DMAINTENR register *******************/ +#define TIM_UIE ((uint16_t)0x0001) /* Update interrupt enable */ +#define TIM_CC1IE ((uint16_t)0x0002) /* Capture/Compare 1 interrupt enable */ +#define TIM_CC2IE ((uint16_t)0x0004) /* Capture/Compare 2 interrupt enable */ +#define TIM_CC3IE ((uint16_t)0x0008) /* Capture/Compare 3 interrupt enable */ +#define TIM_CC4IE ((uint16_t)0x0010) /* Capture/Compare 4 interrupt enable */ +#define TIM_COMIE ((uint16_t)0x0020) /* COM interrupt enable */ +#define TIM_TIE ((uint16_t)0x0040) /* Trigger interrupt enable */ +#define TIM_BIE ((uint16_t)0x0080) /* Break interrupt enable */ +#define TIM_UDE ((uint16_t)0x0100) /* Update DMA request enable */ +#define TIM_CC1DE ((uint16_t)0x0200) /* Capture/Compare 1 DMA request enable */ +#define TIM_CC2DE ((uint16_t)0x0400) /* Capture/Compare 2 DMA request enable */ +#define TIM_CC3DE ((uint16_t)0x0800) /* Capture/Compare 3 DMA request enable */ +#define TIM_CC4DE ((uint16_t)0x1000) /* Capture/Compare 4 DMA request enable */ +#define TIM_COMDE ((uint16_t)0x2000) /* COM DMA request enable */ +#define TIM_TDE ((uint16_t)0x4000) /* Trigger DMA request enable */ + +/******************** Bit definition for TIM_INTFR register ********************/ +#define TIM_UIF ((uint16_t)0x0001) /* Update interrupt Flag */ +#define TIM_CC1IF ((uint16_t)0x0002) /* Capture/Compare 1 interrupt Flag */ +#define TIM_CC2IF ((uint16_t)0x0004) /* Capture/Compare 2 interrupt Flag */ +#define TIM_CC3IF ((uint16_t)0x0008) /* Capture/Compare 3 interrupt Flag */ +#define TIM_CC4IF ((uint16_t)0x0010) /* Capture/Compare 4 interrupt Flag */ +#define TIM_COMIF ((uint16_t)0x0020) /* COM interrupt Flag */ +#define TIM_TIF ((uint16_t)0x0040) /* Trigger interrupt Flag */ +#define TIM_BIF ((uint16_t)0x0080) /* Break interrupt Flag */ +#define TIM_CC1OF ((uint16_t)0x0200) /* Capture/Compare 1 Overcapture Flag */ +#define TIM_CC2OF ((uint16_t)0x0400) /* Capture/Compare 2 Overcapture Flag */ +#define TIM_CC3OF ((uint16_t)0x0800) /* Capture/Compare 3 Overcapture Flag */ +#define TIM_CC4OF ((uint16_t)0x1000) /* Capture/Compare 4 Overcapture Flag */ + +/******************* Bit definition for TIM_SWEVGR register ********************/ +#define TIM_UG ((uint8_t)0x01) /* Update Generation */ +#define TIM_CC1G ((uint8_t)0x02) /* Capture/Compare 1 Generation */ +#define TIM_CC2G ((uint8_t)0x04) /* Capture/Compare 2 Generation */ +#define TIM_CC3G ((uint8_t)0x08) /* Capture/Compare 3 Generation */ +#define TIM_CC4G ((uint8_t)0x10) /* Capture/Compare 4 Generation */ +#define TIM_COMG ((uint8_t)0x20) /* Capture/Compare Control Update Generation */ +#define TIM_TG ((uint8_t)0x40) /* Trigger Generation */ +#define TIM_BG ((uint8_t)0x80) /* Break Generation */ + +/****************** Bit definition for TIM_CHCTLR1 register *******************/ +#define TIM_CC1S ((uint16_t)0x0003) /* CC1S[1:0] bits (Capture/Compare 1 Selection) */ +#define TIM_CC1S_0 ((uint16_t)0x0001) /* Bit 0 */ +#define TIM_CC1S_1 ((uint16_t)0x0002) /* Bit 1 */ + +#define TIM_OC1FE ((uint16_t)0x0004) /* Output Compare 1 Fast enable */ +#define TIM_OC1PE ((uint16_t)0x0008) /* Output Compare 1 Preload enable */ + +#define TIM_OC1M ((uint16_t)0x0070) /* OC1M[2:0] bits (Output Compare 1 Mode) */ +#define TIM_OC1M_0 ((uint16_t)0x0010) /* Bit 0 */ +#define TIM_OC1M_1 ((uint16_t)0x0020) /* Bit 1 */ +#define TIM_OC1M_2 ((uint16_t)0x0040) /* Bit 2 */ + +#define TIM_OC1CE ((uint16_t)0x0080) /* Output Compare 1Clear Enable */ + +#define TIM_CC2S ((uint16_t)0x0300) /* CC2S[1:0] bits (Capture/Compare 2 Selection) */ +#define TIM_CC2S_0 ((uint16_t)0x0100) /* Bit 0 */ +#define TIM_CC2S_1 ((uint16_t)0x0200) /* Bit 1 */ + +#define TIM_OC2FE ((uint16_t)0x0400) /* Output Compare 2 Fast enable */ +#define TIM_OC2PE ((uint16_t)0x0800) /* Output Compare 2 Preload enable */ + +#define TIM_OC2M ((uint16_t)0x7000) /* OC2M[2:0] bits (Output Compare 2 Mode) */ +#define TIM_OC2M_0 ((uint16_t)0x1000) /* Bit 0 */ +#define TIM_OC2M_1 ((uint16_t)0x2000) /* Bit 1 */ +#define TIM_OC2M_2 ((uint16_t)0x4000) /* Bit 2 */ + +#define TIM_OC2CE ((uint16_t)0x8000) /* Output Compare 2 Clear Enable */ + +#define TIM_IC1PSC ((uint16_t)0x000C) /* IC1PSC[1:0] bits (Input Capture 1 Prescaler) */ +#define TIM_IC1PSC_0 ((uint16_t)0x0004) /* Bit 0 */ +#define TIM_IC1PSC_1 ((uint16_t)0x0008) /* Bit 1 */ + +#define TIM_IC1F ((uint16_t)0x00F0) /* IC1F[3:0] bits (Input Capture 1 Filter) */ +#define TIM_IC1F_0 ((uint16_t)0x0010) /* Bit 0 */ +#define TIM_IC1F_1 ((uint16_t)0x0020) /* Bit 1 */ +#define TIM_IC1F_2 ((uint16_t)0x0040) /* Bit 2 */ +#define TIM_IC1F_3 ((uint16_t)0x0080) /* Bit 3 */ + +#define TIM_IC2PSC ((uint16_t)0x0C00) /* IC2PSC[1:0] bits (Input Capture 2 Prescaler) */ +#define TIM_IC2PSC_0 ((uint16_t)0x0400) /* Bit 0 */ +#define TIM_IC2PSC_1 ((uint16_t)0x0800) /* Bit 1 */ + +#define TIM_IC2F ((uint16_t)0xF000) /* IC2F[3:0] bits (Input Capture 2 Filter) */ +#define TIM_IC2F_0 ((uint16_t)0x1000) /* Bit 0 */ +#define TIM_IC2F_1 ((uint16_t)0x2000) /* Bit 1 */ +#define TIM_IC2F_2 ((uint16_t)0x4000) /* Bit 2 */ +#define TIM_IC2F_3 ((uint16_t)0x8000) /* Bit 3 */ + +/****************** Bit definition for TIM_CHCTLR2 register *******************/ +#define TIM_CC3S ((uint16_t)0x0003) /* CC3S[1:0] bits (Capture/Compare 3 Selection) */ +#define TIM_CC3S_0 ((uint16_t)0x0001) /* Bit 0 */ +#define TIM_CC3S_1 ((uint16_t)0x0002) /* Bit 1 */ + +#define TIM_OC3FE ((uint16_t)0x0004) /* Output Compare 3 Fast enable */ +#define TIM_OC3PE ((uint16_t)0x0008) /* Output Compare 3 Preload enable */ + +#define TIM_OC3M ((uint16_t)0x0070) /* OC3M[2:0] bits (Output Compare 3 Mode) */ +#define TIM_OC3M_0 ((uint16_t)0x0010) /* Bit 0 */ +#define TIM_OC3M_1 ((uint16_t)0x0020) /* Bit 1 */ +#define TIM_OC3M_2 ((uint16_t)0x0040) /* Bit 2 */ + +#define TIM_OC3CE ((uint16_t)0x0080) /* Output Compare 3 Clear Enable */ + +#define TIM_CC4S ((uint16_t)0x0300) /* CC4S[1:0] bits (Capture/Compare 4 Selection) */ +#define TIM_CC4S_0 ((uint16_t)0x0100) /* Bit 0 */ +#define TIM_CC4S_1 ((uint16_t)0x0200) /* Bit 1 */ + +#define TIM_OC4FE ((uint16_t)0x0400) /* Output Compare 4 Fast enable */ +#define TIM_OC4PE ((uint16_t)0x0800) /* Output Compare 4 Preload enable */ + +#define TIM_OC4M ((uint16_t)0x7000) /* OC4M[2:0] bits (Output Compare 4 Mode) */ +#define TIM_OC4M_0 ((uint16_t)0x1000) /* Bit 0 */ +#define TIM_OC4M_1 ((uint16_t)0x2000) /* Bit 1 */ +#define TIM_OC4M_2 ((uint16_t)0x4000) /* Bit 2 */ + +#define TIM_OC4CE ((uint16_t)0x8000) /* Output Compare 4 Clear Enable */ + +#define TIM_IC3PSC ((uint16_t)0x000C) /* IC3PSC[1:0] bits (Input Capture 3 Prescaler) */ +#define TIM_IC3PSC_0 ((uint16_t)0x0004) /* Bit 0 */ +#define TIM_IC3PSC_1 ((uint16_t)0x0008) /* Bit 1 */ + +#define TIM_IC3F ((uint16_t)0x00F0) /* IC3F[3:0] bits (Input Capture 3 Filter) */ +#define TIM_IC3F_0 ((uint16_t)0x0010) /* Bit 0 */ +#define TIM_IC3F_1 ((uint16_t)0x0020) /* Bit 1 */ +#define TIM_IC3F_2 ((uint16_t)0x0040) /* Bit 2 */ +#define TIM_IC3F_3 ((uint16_t)0x0080) /* Bit 3 */ + +#define TIM_IC4PSC ((uint16_t)0x0C00) /* IC4PSC[1:0] bits (Input Capture 4 Prescaler) */ +#define TIM_IC4PSC_0 ((uint16_t)0x0400) /* Bit 0 */ +#define TIM_IC4PSC_1 ((uint16_t)0x0800) /* Bit 1 */ + +#define TIM_IC4F ((uint16_t)0xF000) /* IC4F[3:0] bits (Input Capture 4 Filter) */ +#define TIM_IC4F_0 ((uint16_t)0x1000) /* Bit 0 */ +#define TIM_IC4F_1 ((uint16_t)0x2000) /* Bit 1 */ +#define TIM_IC4F_2 ((uint16_t)0x4000) /* Bit 2 */ +#define TIM_IC4F_3 ((uint16_t)0x8000) /* Bit 3 */ + +/******************* Bit definition for TIM_CCER register *******************/ +#define TIM_CC1E ((uint16_t)0x0001) /* Capture/Compare 1 output enable */ +#define TIM_CC1P ((uint16_t)0x0002) /* Capture/Compare 1 output Polarity */ +#define TIM_CC1NE ((uint16_t)0x0004) /* Capture/Compare 1 Complementary output enable */ +#define TIM_CC1NP ((uint16_t)0x0008) /* Capture/Compare 1 Complementary output Polarity */ +#define TIM_CC2E ((uint16_t)0x0010) /* Capture/Compare 2 output enable */ +#define TIM_CC2P ((uint16_t)0x0020) /* Capture/Compare 2 output Polarity */ +#define TIM_CC2NE ((uint16_t)0x0040) /* Capture/Compare 2 Complementary output enable */ +#define TIM_CC2NP ((uint16_t)0x0080) /* Capture/Compare 2 Complementary output Polarity */ +#define TIM_CC3E ((uint16_t)0x0100) /* Capture/Compare 3 output enable */ +#define TIM_CC3P ((uint16_t)0x0200) /* Capture/Compare 3 output Polarity */ +#define TIM_CC3NE ((uint16_t)0x0400) /* Capture/Compare 3 Complementary output enable */ +#define TIM_CC3NP ((uint16_t)0x0800) /* Capture/Compare 3 Complementary output Polarity */ +#define TIM_CC4E ((uint16_t)0x1000) /* Capture/Compare 4 output enable */ +#define TIM_CC4P ((uint16_t)0x2000) /* Capture/Compare 4 output Polarity */ + +/******************* Bit definition for TIM_CNT register ********************/ +#define TIM_CNT ((uint16_t)0xFFFF) /* Counter Value */ + +#define TIM4_CNT ((uint32_t)0xFFFFFFFF) /* Counter Value */ + +/******************* Bit definition for TIM_PSC register ********************/ +#define TIM_PSC ((uint16_t)0xFFFF) /* Prescaler Value */ + +/******************* Bit definition for TIM_ATRLR register ********************/ +#define TIM_ARR ((uint16_t)0xFFFF) /* actual auto-reload Value */ + +/******************* Bit definition for TIM_RPTCR register ********************/ +#define TIM_REP ((uint8_t)0xFF) /* Repetition Counter Value */ + +/******************* Bit definition for TIM_CH1CVR register *******************/ +#define TIM_CCR1 ((uint16_t)0xFFFF) /* Capture/Compare 1 Value */ +#define TIM_LEVEL1 ((uint32_t)0x00010000) + +/******************* Bit definition for TIM_CH2CVR register *******************/ +#define TIM_CCR2 ((uint16_t)0xFFFF) /* Capture/Compare 2 Value */ +#define TIM_LEVEL2 ((uint32_t)0x00010000) + +/******************* Bit definition for TIM_CH3CVR register *******************/ +#define TIM_CCR3 ((uint16_t)0xFFFF) /* Capture/Compare 3 Value */ +#define TIM_LEVEL3 ((uint32_t)0x00010000) + +/******************* Bit definition for TIM_CH4CVR register *******************/ +#define TIM_CCR4 ((uint16_t)0xFFFF) /* Capture/Compare 4 Value */ +#define TIM_LEVEL4 ((uint32_t)0x00010000) + +/******************* Bit definition for TIM_BDTR register *******************/ +#define TIM_DTG ((uint16_t)0x00FF) /* DTG[0:7] bits (Dead-Time Generator set-up) */ +#define TIM_DTG_0 ((uint16_t)0x0001) /* Bit 0 */ +#define TIM_DTG_1 ((uint16_t)0x0002) /* Bit 1 */ +#define TIM_DTG_2 ((uint16_t)0x0004) /* Bit 2 */ +#define TIM_DTG_3 ((uint16_t)0x0008) /* Bit 3 */ +#define TIM_DTG_4 ((uint16_t)0x0010) /* Bit 4 */ +#define TIM_DTG_5 ((uint16_t)0x0020) /* Bit 5 */ +#define TIM_DTG_6 ((uint16_t)0x0040) /* Bit 6 */ +#define TIM_DTG_7 ((uint16_t)0x0080) /* Bit 7 */ + +#define TIM_LOCK ((uint16_t)0x0300) /* LOCK[1:0] bits (Lock Configuration) */ +#define TIM_LOCK_0 ((uint16_t)0x0100) /* Bit 0 */ +#define TIM_LOCK_1 ((uint16_t)0x0200) /* Bit 1 */ + +#define TIM_OSSI ((uint16_t)0x0400) /* Off-State Selection for Idle mode */ +#define TIM_OSSR ((uint16_t)0x0800) /* Off-State Selection for Run mode */ +#define TIM_BKE ((uint16_t)0x1000) /* Break enable */ +#define TIM_BKP ((uint16_t)0x2000) /* Break Polarity */ +#define TIM_AOE ((uint16_t)0x4000) /* Automatic Output enable */ +#define TIM_MOE ((uint16_t)0x8000) /* Main Output enable */ + +/******************* Bit definition for TIM_DMACFGR register ********************/ +#define TIM_DBA ((uint16_t)0x001F) /* DBA[4:0] bits (DMA Base Address) */ +#define TIM_DBA_0 ((uint16_t)0x0001) /* Bit 0 */ +#define TIM_DBA_1 ((uint16_t)0x0002) /* Bit 1 */ +#define TIM_DBA_2 ((uint16_t)0x0004) /* Bit 2 */ +#define TIM_DBA_3 ((uint16_t)0x0008) /* Bit 3 */ +#define TIM_DBA_4 ((uint16_t)0x0010) /* Bit 4 */ + +#define TIM_DBL ((uint16_t)0x1F00) /* DBL[4:0] bits (DMA Burst Length) */ +#define TIM_DBL_0 ((uint16_t)0x0100) /* Bit 0 */ +#define TIM_DBL_1 ((uint16_t)0x0200) /* Bit 1 */ +#define TIM_DBL_2 ((uint16_t)0x0400) /* Bit 2 */ +#define TIM_DBL_3 ((uint16_t)0x0800) /* Bit 3 */ +#define TIM_DBL_4 ((uint16_t)0x1000) /* Bit 4 */ + +/******************* Bit definition for TIM_DMAADR register *******************/ +#define TIM_DMAR_DMAB ((uint32_t)0xFFFFFFFF) /* DMA register for burst accesses */ + +/******************************************************************************/ +/* Universal Synchronous Asynchronous Receiver Transmitter */ +/******************************************************************************/ + +/******************* Bit definition for USART_STATR register *******************/ +#define USART_STATR_PE ((uint16_t)0x0001) /* Parity Error */ +#define USART_STATR_FE ((uint16_t)0x0002) /* Framing Error */ +#define USART_STATR_NE ((uint16_t)0x0004) /* Noise Error Flag */ +#define USART_STATR_ORE ((uint16_t)0x0008) /* OverRun Error */ +#define USART_STATR_IDLE ((uint16_t)0x0010) /* IDLE line detected */ +#define USART_STATR_RXNE ((uint16_t)0x0020) /* Read Data Register Not Empty */ +#define USART_STATR_TC ((uint16_t)0x0040) /* Transmission Complete */ +#define USART_STATR_TXE ((uint16_t)0x0080) /* Transmit Data Register Empty */ +#define USART_STATR_LBD ((uint16_t)0x0100) /* LIN Break Detection Flag */ +#define USART_STATR_CTS ((uint16_t)0x0200) /* CTS Flag */ + +/******************* Bit definition for USART_DATAR register *******************/ +#define USART_DATAR_DR ((uint16_t)0x01FF) /* Data value */ + +/****************** Bit definition for USART_BRR register *******************/ +#define USART_BRR_DIV_Fraction ((uint16_t)0x000F) /* Fraction of USARTDIV */ +#define USART_BRR_DIV_Mantissa ((uint16_t)0xFFF0) /* Mantissa of USARTDIV */ + +/****************** Bit definition for USART_CTLR1 register *******************/ +#define USART_CTLR1_SBK ((uint16_t)0x0001) /* Send Break */ +#define USART_CTLR1_RWU ((uint16_t)0x0002) /* Receiver wakeup */ +#define USART_CTLR1_RE ((uint16_t)0x0004) /* Receiver Enable */ +#define USART_CTLR1_TE ((uint16_t)0x0008) /* Transmitter Enable */ +#define USART_CTLR1_IDLEIE ((uint16_t)0x0010) /* IDLE Interrupt Enable */ +#define USART_CTLR1_RXNEIE ((uint16_t)0x0020) /* RXNE Interrupt Enable */ +#define USART_CTLR1_TCIE ((uint16_t)0x0040) /* Transmission Complete Interrupt Enable */ +#define USART_CTLR1_TXEIE ((uint16_t)0x0080) /* PE Interrupt Enable */ +#define USART_CTLR1_PEIE ((uint16_t)0x0100) /* PE Interrupt Enable */ +#define USART_CTLR1_PS ((uint16_t)0x0200) /* Parity Selection */ +#define USART_CTLR1_PCE ((uint16_t)0x0400) /* Parity Control Enable */ +#define USART_CTLR1_WAKE ((uint16_t)0x0800) /* Wakeup method */ +#define USART_CTLR1_M ((uint16_t)0x1000) /* Word length */ +#define USART_CTLR1_UE ((uint16_t)0x2000) /* USART Enable */ + +/****************** Bit definition for USART_CTLR2 register *******************/ +#define USART_CTLR2_ADD ((uint16_t)0x000F) /* Address of the USART node */ +#define USART_CTLR2_LBDL ((uint16_t)0x0020) /* LIN Break Detection Length */ +#define USART_CTLR2_LBDIE ((uint16_t)0x0040) /* LIN Break Detection Interrupt Enable */ +#define USART_CTLR2_LBCL ((uint16_t)0x0100) /* Last Bit Clock pulse */ +#define USART_CTLR2_CPHA ((uint16_t)0x0200) /* Clock Phase */ +#define USART_CTLR2_CPOL ((uint16_t)0x0400) /* Clock Polarity */ +#define USART_CTLR2_CLKEN ((uint16_t)0x0800) /* Clock Enable */ + +#define USART_CTLR2_STOP ((uint16_t)0x3000) /* STOP[1:0] bits (STOP bits) */ +#define USART_CTLR2_STOP_0 ((uint16_t)0x1000) /* Bit 0 */ +#define USART_CTLR2_STOP_1 ((uint16_t)0x2000) /* Bit 1 */ + +#define USART_CTLR2_LINEN ((uint16_t)0x4000) /* LIN mode enable */ + +/****************** Bit definition for USART_CTLR3 register *******************/ +#define USART_CTLR3_EIE ((uint16_t)0x0001) /* Error Interrupt Enable */ +#define USART_CTLR3_IREN ((uint16_t)0x0002) /* IrDA mode Enable */ +#define USART_CTLR3_IRLP ((uint16_t)0x0004) /* IrDA Low-Power */ +#define USART_CTLR3_HDSEL ((uint16_t)0x0008) /* Half-Duplex Selection */ +#define USART_CTLR3_NACK ((uint16_t)0x0010) /* Smartcard NACK enable */ +#define USART_CTLR3_SCEN ((uint16_t)0x0020) /* Smartcard mode enable */ +#define USART_CTLR3_DMAR ((uint16_t)0x0040) /* DMA Enable Receiver */ +#define USART_CTLR3_DMAT ((uint16_t)0x0080) /* DMA Enable Transmitter */ +#define USART_CTLR3_RTSE ((uint16_t)0x0100) /* RTS Enable */ +#define USART_CTLR3_CTSE ((uint16_t)0x0200) /* CTS Enable */ +#define USART_CTLR3_CTSIE ((uint16_t)0x0400) /* CTS Interrupt Enable */ + +/****************** Bit definition for USART_GPR register ******************/ +#define USART_GPR_PSC ((uint16_t)0x00FF) /* PSC[7:0] bits (Prescaler value) */ +#define USART_GPR_PSC_0 ((uint16_t)0x0001) /* Bit 0 */ +#define USART_GPR_PSC_1 ((uint16_t)0x0002) /* Bit 1 */ +#define USART_GPR_PSC_2 ((uint16_t)0x0004) /* Bit 2 */ +#define USART_GPR_PSC_3 ((uint16_t)0x0008) /* Bit 3 */ +#define USART_GPR_PSC_4 ((uint16_t)0x0010) /* Bit 4 */ +#define USART_GPR_PSC_5 ((uint16_t)0x0020) /* Bit 5 */ +#define USART_GPR_PSC_6 ((uint16_t)0x0040) /* Bit 6 */ +#define USART_GPR_PSC_7 ((uint16_t)0x0080) /* Bit 7 */ + +#define USART_GPR_GT ((uint16_t)0xFF00) /* Guard time value */ + +/******************************************************************************/ +/* Window WATCHDOG */ +/******************************************************************************/ + +/******************* Bit definition for WWDG_CTLR register ********************/ +#define WWDG_CTLR_T ((uint8_t)0x7F) /* T[6:0] bits (7-Bit counter (MSB to LSB)) */ +#define WWDG_CTLR_T0 ((uint8_t)0x01) /* Bit 0 */ +#define WWDG_CTLR_T1 ((uint8_t)0x02) /* Bit 1 */ +#define WWDG_CTLR_T2 ((uint8_t)0x04) /* Bit 2 */ +#define WWDG_CTLR_T3 ((uint8_t)0x08) /* Bit 3 */ +#define WWDG_CTLR_T4 ((uint8_t)0x10) /* Bit 4 */ +#define WWDG_CTLR_T5 ((uint8_t)0x20) /* Bit 5 */ +#define WWDG_CTLR_T6 ((uint8_t)0x40) /* Bit 6 */ + +#define WWDG_CTLR_WDGA ((uint8_t)0x80) /* Activation bit */ + +/******************* Bit definition for WWDG_CFGR register *******************/ +#define WWDG_CFGR_W ((uint16_t)0x007F) /* W[6:0] bits (7-bit window value) */ +#define WWDG_CFGR_W0 ((uint16_t)0x0001) /* Bit 0 */ +#define WWDG_CFGR_W1 ((uint16_t)0x0002) /* Bit 1 */ +#define WWDG_CFGR_W2 ((uint16_t)0x0004) /* Bit 2 */ +#define WWDG_CFGR_W3 ((uint16_t)0x0008) /* Bit 3 */ +#define WWDG_CFGR_W4 ((uint16_t)0x0010) /* Bit 4 */ +#define WWDG_CFGR_W5 ((uint16_t)0x0020) /* Bit 5 */ +#define WWDG_CFGR_W6 ((uint16_t)0x0040) /* Bit 6 */ + +#define WWDG_CFGR_WDGTB ((uint16_t)0x0180) /* WDGTB[1:0] bits (Timer Base) */ +#define WWDG_CFGR_WDGTB0 ((uint16_t)0x0080) /* Bit 0 */ +#define WWDG_CFGR_WDGTB1 ((uint16_t)0x0100) /* Bit 1 */ + +#define WWDG_CFGR_EWI ((uint16_t)0x0200) /* Early Wakeup Interrupt */ + +/******************* Bit definition for WWDG_STATR register ********************/ +#define WWDG_STATR_EWIF ((uint8_t)0x01) /* Early Wakeup Interrupt Flag */ + +/******************************************************************************/ +/* ENHANCED FUNNCTION */ +/******************************************************************************/ + +/**************************** Enhanced register *****************************/ +#define EXTEN_PLL_HSI_PRE ((uint32_t)0x00000010) /* Bit 4 */ +#define EXTEN_LOCKUP_EN ((uint32_t)0x00000040) /* Bit 5 */ +#define EXTEN_LOCKUP_RSTF ((uint32_t)0x00000080) /* Bit 7 */ + +#define EXTEN_ULLDO_TRIM ((uint32_t)0x00000700) /* ULLDO_TRIM[2:0] bits */ +#define EXTEN_ULLDO_TRIM0 ((uint32_t)0x00000100) /* Bit 0 */ +#define EXTEN_ULLDO_TRIM1 ((uint32_t)0x00000200) /* Bit 1 */ +#define EXTEN_ULLDO_TRIM2 ((uint32_t)0x00000400) /* Bit 2 */ + +#define EXTEN_LDO_TRIM ((uint32_t)0x00003000) /* LDO_TRIM[1:0] bits */ +#define EXTEN_LDO_TRIM0 ((uint32_t)0x00001000) /* Bit 0 */ +#define EXTEN_LDO_TRIM1 ((uint32_t)0x00002000) /* Bit 1 */ + +/******************************************************************************/ +/* DEBUG SUPPORT */ +/******************************************************************************/ +/******************* Bit definition for DBGMCU_DR register *******************/ +#define DBG_DEBUGMCU_SLEEP ((uint32_t)0x00000001) +#define DBG_DEBUGMCU_STOP ((uint32_t)0x00000002) +#define DBG_DEBUGMCU_STBY ((uint32_t)0x00000004) +#define DBG_DEBUGMCU_IWDG_STOP ((uint32_t)0x00000100) +#define DBG_DEBUGMCU_WWDG_STOP ((uint32_t)0x00000200) +#define DBG_DEBUGMCU_I2C1SMBUS_TOUT ((uint32_t)0x00000400) +#define DBG_DEBUGMCU_I2C2SMBUS_TOUT ((uint32_t)0x00000800) +#define DBG_DEBUGMCU_TIM1_STOP ((uint32_t)0x00001000) +#define DBG_DEBUGMCU_TIM2_STOP ((uint32_t)0x00002000) +#define DBG_DEBUGMCU_TIM3_STOP ((uint32_t)0x00004000) +#define DBG_DEBUGMCU_TIM4_STOP ((uint32_t)0x00008000) +#define DBG_DEBUGMCU_CAN_STOP ((uint32_t)0x00010000) + +/******************************************************************************/ +/* OPTICAL PARAMETER */ +/******************************************************************************/ + +/******************* Bit definition for OPA_CFGR1 register *******************/ +#define OPA_CFGR1_POLLEN ((uint32_t)0x00000001) +#define OPA_CFGR1_BKINEN ((uint32_t)0x00000004) +#define OPA_CFGR1_RSTEN ((uint32_t)0x00000010) +#define OPA_CFGR1_OPCMLOCK ((uint32_t)0x00000080) +#define OPA_CFGR1_IEOUT ((uint32_t)0x00000100) +#define OPA_CFGR1_IECNT ((uint32_t)0x00000400) +#define OPA_CFGR1_NMIEN ((uint32_t)0x00000800) +#define OPA_CFGR1_IFOUT ((uint32_t)0x00001000) +#define OPA_CFGR1_IFCNT ((uint32_t)0x00004000) + +/******************* Bit definition for OPA_CFGR2 register *******************/ +#define OPA_CFGR2_POLL_VLU ((uint32_t)0x000001FF) +#define OPA_CFGR2_POLL_NUM ((uint32_t)0x00000E00) +#define OPA_CFGR2_POLL_CNT ((uint32_t)0x00007000) + +/******************* Bit definition for OPA_CTLR1 register *******************/ +#define OPA_CTLR1_EN1 ((uint32_t)0x00000001) +#define OPA_CTLR1_MODE1 ((uint32_t)0x0000000E) +#define OPA_CTLR1_PSEL1 ((uint32_t)0x00000070) +#define OPA_CTLR1_FBEN1 ((uint32_t)0x00000080) +#define OPA_CTLR1_NSEL1 ((uint32_t)0x00000F00) +#define OPA_CTLR1_LP1 ((uint32_t)0x00001000) +#define OPA_CTLR1_INTRIMP ((uint32_t)0x00010000) +#define OPA_CTLR1_ITRIMP ((uint32_t)0x003E0000) +#define OPA_CTLR1_INTRIMN ((uint32_t)0x01000000) +#define OPA_CTLR1_ITRIMN ((uint32_t)0x3E000000) + +/******************* Bit definition for OPA_CTLR2 register *******************/ +#define OPA_CTLR2_EN1 ((uint32_t)0x00000001) +#define OPA_CTLR2_MODE1 ((uint32_t)0x00000006) +#define OPA_CTLR2_NSEL1 ((uint32_t)0x00000008) +#define OPA_CTLR2_PSEL1 ((uint32_t)0x00000010) +#define OPA_CTLR2_HYEN1 ((uint32_t)0x00000020) +#define OPA_CTLR2_LP1 ((uint32_t)0x00000040) +#define OPA_CTLR2_EN2 ((uint32_t)0x00000100) +#define OPA_CTLR2_MODE2 ((uint32_t)0x00000600) +#define OPA_CTLR2_NSEL2 ((uint32_t)0x00000800) +#define OPA_CTLR2_PSEL2 ((uint32_t)0x00001000) +#define OPA_CTLR2_HYEN2 ((uint32_t)0x00002000) +#define OPA_CTLR2_LP2 ((uint32_t)0x00004000) +#define OPA_CTLR2_EN3 ((uint32_t)0x00010000) +#define OPA_CTLR2_MODE3 ((uint32_t)0x00060000) +#define OPA_CTLR2_NSEL3 ((uint32_t)0x00080000) +#define OPA_CTLR2_PSEL3 ((uint32_t)0x00100000) +#define OPA_CTLR2_HYEN3 ((uint32_t)0x00200000) +#define OPA_CTLR2_LP3 ((uint32_t)0x00400000) + +#define OPA_CTLR2_WKUP_MD ((uint32_t)0x03000000) +#define OPA_CTLR2_WKUP_MD_0 ((uint32_t)0x01000000) +#define OPA_CTLR2_WKUP_MD_1 ((uint32_t)0x02000000) + +/******************* Bit definition for OPCMKEY register *******************/ +#define OPCM_KEY ((uint32_t)0xFFFFFFFF) + +/******************************************************************************/ +/* LOW POWER TIM */ +/******************************************************************************/ +/******************* Bit definition for LPTIM_ISR register *******************/ +#define LPTIM_ISR_CMPM ((uint32_t)0x00000001) +#define LPTIM_ISR_ARRM ((uint32_t)0x00000002) +#define LPTIM_ISR_EXTTRIG ((uint32_t)0x00000004) +#define LPTIM_ISR_CMPOK ((uint32_t)0x00000008) +#define LPTIM_ISR_ARROK ((uint32_t)0000000010) +#define LPTIM_ISR_UP ((uint32_t)0x00000020) +#define LPTIM_ISR_DOWN ((uint32_t)0x00000040) +#define LPTIM_ISR_DIRSYNC ((uint32_t)0x00000080) + +/******************* Bit definition for LPTIM_ICR register *******************/ +#define LPTIM_ICR_CMPMCF ((uint32_t)0x00000001) +#define LPTIM_ICR_ARRMCF ((uint32_t)0x00000002) +#define LPTIM_ICR_EXTTRIGCF ((uint32_t)0x00000004) +#define LPTIM_ICR_CMPOKCF ((uint32_t)0x00000008) +#define LPTIM_ICR_ARROKCF ((uint32_t)0x00000010) +#define LPTIM_ICR_UPCF ((uint32_t)0x00000020) +#define LPTIM_ICR_DOWNCF ((uint32_t)0x00000040) + +/******************* Bit definition for LPTIM_IER register *******************/ +#define LPTIM_IER_CMPMIE ((uint32_t)0x00000001) +#define LPTIM_IER_ARRMIE ((uint32_t)0x00000002) +#define LPTIM_IER_EXTTRIGIE ((uint32_t)0x00000004) +#define LPTIM_IER_CMPOKIE ((uint32_t)0x00000008) +#define LPTIM_IER_ARROKIE ((uint32_t)0x00000010) +#define LPTIM_IER_UPIE ((uint32_t)0x00000020) +#define LPTIM_IER_DOWNIE ((uint32_t)0x00000040) + +/******************* Bit definition for LPTIM_CFGR register *******************/ +#define LPTIM_CFGR_CKSEL ((uint32_t)0x00000001) +#define LPTIM_CFGR_CKPOL ((uint32_t)0x00000006) +#define LPTIM_CFGR_CKFLT ((uint32_t)0x00000018) +#define LPTIM_CFGR_TRGFLT ((uint32_t)0x000000C0) +#define LPTIM_CFGR_PRESC ((uint32_t)0x00000E00) +#define LPTIM_CFGR_TRIGSEL ((uint32_t)0x00006000) +#define LPTIM_CFGR_TRIGEN ((uint32_t)0x00060000) +#define LPTIM_CFGR_TIMOUT ((uint32_t)0x00080000) +#define LPTIM_CFGR_WAVE ((uint32_t)0x00100000) +#define LPTIM_CFGR_WAVPOL ((uint32_t)0x00200000) +#define LPTIM_CFGR_PRELOAD ((uint32_t)0x00400000) +#define LPTIM_CFGR_CONTMODE ((uint32_t)0x00800000) +#define LPTIM_CFGR_ENC ((uint32_t)0x01000000) +#define LPTIM_CFGR_CLKSEL ((uint32_t)0x06000000) +#define LPTIM_CFGR_FORCEPWM ((uint32_t)0x08000000) + +/******************* Bit definition for LPTIM_CR register *******************/ +#define LPTIM_CR_ENABLE ((uint32_t)0x00000001) +#define LPTIM_CR_SNGSTRT ((uint32_t)0x00000002) +#define LPTIM_CR_CNTSTRT ((uint32_t)0x00000004) +#define LPTIM_CR_OUTEN ((uint32_t)0x00000008) +#define LPTIM_CR_DIR_EXTEN ((uint32_t)0x00000010) + +/******************* Bit definition for LPTIM_CMP register *******************/ +#define LPTIM_CMP ((uint32_t)0x0000FFFF) + +/******************* Bit definition for LPTIM_ARR register *******************/ +#define LPTIM_ARR ((uint32_t)0x0000FFFF) + +/******************* Bit definition for LPTIM_CNT register *******************/ +#define LPTIM_COUNT ((uint32_t)0x0000FFFF) + +/******************************************************************************/ +/* TOUCH KEY */ +/******************************************************************************/ +/******************* Bit definition for TKEY_CHARGE register *******************/ +#define TKEY_CHGOFFSET ((uint32_t)0x000003FF) + +/******************* Bit definition for TKEY_ACT_DCG register *******************/ +#define TKEY_TKACTDCG ((uint32_t)0x000003FF) + +/******************* Bit definition for TKEY_DR register *******************/ +#define TKEY_DR ((uint32_t)0x0000FFFF) + +#include "ch32l103_conf.h" + +#ifdef __cplusplus +} +#endif + +#endif + diff --git a/ZDBMS/BMS_MC/Peripheral/inc/ch32l103_adc.h b/ZDBMS/BMS_MC/Peripheral/inc/ch32l103_adc.h new file mode 100644 index 0000000..7494a2c --- /dev/null +++ b/ZDBMS/BMS_MC/Peripheral/inc/ch32l103_adc.h @@ -0,0 +1,211 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32l103_adc.h + * Author : WCH + * Version : V1.0.0 + * Date : 2024/05/06 + * Description : This file contains all the functions prototypes for the + * ADC firmware library. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#ifndef __CH32L103_ADC_H +#define __CH32L103_ADC_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "ch32l103.h" + +/* ADC Init structure definition */ +typedef struct +{ + uint32_t ADC_Mode; /* Configures the ADC to operate in independent or + dual mode. + This parameter can be a value of @ref ADC_mode */ + + FunctionalState ADC_ScanConvMode; /* Specifies whether the conversion is performed in + Scan (multichannels) or Single (one channel) mode. + This parameter can be set to ENABLE or DISABLE */ + + FunctionalState ADC_ContinuousConvMode; /* Specifies whether the conversion is performed in + Continuous or Single mode. + This parameter can be set to ENABLE or DISABLE. */ + + uint32_t ADC_ExternalTrigConv; /* Defines the external trigger used to start the analog + to digital conversion of regular channels. This parameter + can be a value of @ref ADC_external_trigger_sources_for_regular_channels_conversion */ + + uint32_t ADC_DataAlign; /* Specifies whether the ADC data alignment is left or right. + This parameter can be a value of @ref ADC_data_align */ + + uint8_t ADC_NbrOfChannel; /* Specifies the number of ADC channels that will be converted + using the sequencer for regular channel group. + This parameter must range from 1 to 16. */ + + uint32_t ADC_OutputBuffer; /* Specifies whether the ADC channel output buffer is enabled or disabled. + This parameter can be a value of @ref ADC_OutputBuffer */ + + uint32_t ADC_Pga; /* Specifies the PGA gain multiple. + This parameter can be a value of @ref ADC_Pga */ +} ADC_InitTypeDef; + +/* ADC_mode */ +#define ADC_Mode_Independent ((uint32_t)0x00000000) +#define ADC_Mode_RegInjecSimult ((uint32_t)0x00010000) +#define ADC_Mode_RegSimult_AlterTrig ((uint32_t)0x00020000) +#define ADC_Mode_InjecSimult_FastInterl ((uint32_t)0x00030000) +#define ADC_Mode_InjecSimult_SlowInterl ((uint32_t)0x00040000) +#define ADC_Mode_InjecSimult ((uint32_t)0x00050000) +#define ADC_Mode_RegSimult ((uint32_t)0x00060000) +#define ADC_Mode_FastInterl ((uint32_t)0x00070000) +#define ADC_Mode_SlowInterl ((uint32_t)0x00080000) +#define ADC_Mode_AlterTrig ((uint32_t)0x00090000) + +/* ADC_external_trigger_sources_for_regular_channels_conversion */ +#define ADC_ExternalTrigConv_T1_CC1 ((uint32_t)0x00000000) +#define ADC_ExternalTrigConv_T1_CC2 ((uint32_t)0x00020000) +#define ADC_ExternalTrigConv_T1_CC3 ((uint32_t)0x00040000) +#define ADC_ExternalTrigConv_T2_CC2 ((uint32_t)0x00060000) +#define ADC_ExternalTrigConv_T3_TRGO ((uint32_t)0x00080000) +#define ADC_ExternalTrigConv_T4_CC4 ((uint32_t)0x000A0000) +#define ADC_ExternalTrigConv_Ext_IT11 ((uint32_t)0x000C0000) +#define ADC_ExternalTrigConv_None ((uint32_t)0x000E0000) + +/* ADC_data_align */ +#define ADC_DataAlign_Right ((uint32_t)0x00000000) +#define ADC_DataAlign_Left ((uint32_t)0x00000800) + +/* ADC_channels */ +#define ADC_Channel_0 ((uint8_t)0x00) +#define ADC_Channel_1 ((uint8_t)0x01) +#define ADC_Channel_2 ((uint8_t)0x02) +#define ADC_Channel_3 ((uint8_t)0x03) +#define ADC_Channel_4 ((uint8_t)0x04) +#define ADC_Channel_5 ((uint8_t)0x05) +#define ADC_Channel_6 ((uint8_t)0x06) +#define ADC_Channel_7 ((uint8_t)0x07) +#define ADC_Channel_8 ((uint8_t)0x08) +#define ADC_Channel_9 ((uint8_t)0x09) +#define ADC_Channel_16 ((uint8_t)0x10) +#define ADC_Channel_17 ((uint8_t)0x11) +#define ADC_Channel_18 ((uint8_t)0x12) +#define ADC_Channel_TempSensor ((uint8_t)ADC_Channel_16) +#define ADC_Channel_Vrefint ((uint8_t)ADC_Channel_17) +#define ADC_Channel_CalInternal ((uint8_t)ADC_Channel_18) + +/*ADC_output_buffer*/ +#define ADC_OutputBuffer_Enable ((uint32_t)0x04000000) +#define ADC_OutputBuffer_Disable ((uint32_t)0x00000000) + +/*ADC_pga*/ +#define ADC_Pga_1 ((uint32_t)0x00000000) +#define ADC_Pga_4 ((uint32_t)0x08000000) +#define ADC_Pga_16 ((uint32_t)0x10000000) +#define ADC_Pga_64 ((uint32_t)0x18000000) + +/* ADC_sampling_time */ +#define ADC_SampleTime_CyclesMode0 ((uint8_t)0x00) +#define ADC_SampleTime_CyclesMode1 ((uint8_t)0x01) +#define ADC_SampleTime_CyclesMode2 ((uint8_t)0x02) +#define ADC_SampleTime_CyclesMode3 ((uint8_t)0x03) +#define ADC_SampleTime_CyclesMode4 ((uint8_t)0x04) +#define ADC_SampleTime_CyclesMode5 ((uint8_t)0x05) +#define ADC_SampleTime_CyclesMode6 ((uint8_t)0x06) +#define ADC_SampleTime_CyclesMode7 ((uint8_t)0x07) + +/* ADC_external_trigger_sources_for_injected_channels_conversion */ +#define ADC_ExternalTrigInjecConv_T1_TRGO ((uint32_t)0x00000000) +#define ADC_ExternalTrigInjecConv_T1_CC4 ((uint32_t)0x00001000) +#define ADC_ExternalTrigInjecConv_T2_TRGO ((uint32_t)0x00002000) +#define ADC_ExternalTrigInjecConv_T2_CC1 ((uint32_t)0x00003000) +#define ADC_ExternalTrigInjecConv_T3_CC4 ((uint32_t)0x00004000) +#define ADC_ExternalTrigInjecConv_T4_TRGO ((uint32_t)0x00005000) +#define ADC_ExternalTrigInjecConv_Ext_IT15 ((uint32_t)0x00006000) +#define ADC_ExternalTrigInjecConv_None ((uint32_t)0x00007000) + +/* ADC_injected_channel_selection */ +#define ADC_InjectedChannel_1 ((uint8_t)0x14) +#define ADC_InjectedChannel_2 ((uint8_t)0x18) +#define ADC_InjectedChannel_3 ((uint8_t)0x1C) +#define ADC_InjectedChannel_4 ((uint8_t)0x20) + +/* ADC_analog_watchdog_selection */ +#define ADC_AnalogWatchdog_SingleRegEnable ((uint32_t)0x00800200) +#define ADC_AnalogWatchdog_SingleInjecEnable ((uint32_t)0x00400200) +#define ADC_AnalogWatchdog_SingleRegOrInjecEnable ((uint32_t)0x00C00200) +#define ADC_AnalogWatchdog_AllRegEnable ((uint32_t)0x00800000) +#define ADC_AnalogWatchdog_AllInjecEnable ((uint32_t)0x00400000) +#define ADC_AnalogWatchdog_AllRegAllInjecEnable ((uint32_t)0x00C00000) +#define ADC_AnalogWatchdog_None ((uint32_t)0x00000000) + +/* ADC_interrupts_definition */ +#define ADC_IT_EOC ((uint16_t)0x0220) +#define ADC_IT_AWD ((uint16_t)0x0140) +#define ADC_IT_JEOC ((uint16_t)0x0480) + +/* ADC_flags_definition */ +#define ADC_FLAG_AWD ((uint8_t)0x01) +#define ADC_FLAG_EOC ((uint8_t)0x02) +#define ADC_FLAG_JEOC ((uint8_t)0x04) +#define ADC_FLAG_JSTRT ((uint8_t)0x08) +#define ADC_FLAG_STRT ((uint8_t)0x10) + +/* ADC_Sample_mode_definition */ +#define ADC_Sample_NoOver_1M_Mode ((uint32_t)0x00000000) +#define ADC_Sample_Over_1M_Mode ((uint32_t)0x00000020) + + +void ADC_DeInit(ADC_TypeDef *ADCx); +void ADC_Init(ADC_TypeDef *ADCx, ADC_InitTypeDef *ADC_InitStruct); +void ADC_StructInit(ADC_InitTypeDef *ADC_InitStruct); +void ADC_Cmd(ADC_TypeDef *ADCx, FunctionalState NewState); +void ADC_DMACmd(ADC_TypeDef *ADCx, FunctionalState NewState); +void ADC_ITConfig(ADC_TypeDef *ADCx, uint16_t ADC_IT, FunctionalState NewState); +void ADC_ResetCalibration(ADC_TypeDef *ADCx); +FlagStatus ADC_GetResetCalibrationStatus(ADC_TypeDef *ADCx); +void ADC_StartCalibration(ADC_TypeDef *ADCx); +FlagStatus ADC_GetCalibrationStatus(ADC_TypeDef *ADCx); +void ADC_SoftwareStartConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState); +FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef *ADCx); +void ADC_DiscModeChannelCountConfig(ADC_TypeDef *ADCx, uint8_t Number); +void ADC_DiscModeCmd(ADC_TypeDef *ADCx, FunctionalState NewState); +void ADC_RegularChannelConfig(ADC_TypeDef *ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime); +void ADC_ExternalTrigConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState); +uint16_t ADC_GetConversionValue(ADC_TypeDef *ADCx); +uint32_t ADC_GetDualModeConversionValue(void); +void ADC_AutoInjectedConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState); +void ADC_InjectedDiscModeCmd(ADC_TypeDef *ADCx, FunctionalState NewState); +void ADC_ExternalTrigInjectedConvConfig(ADC_TypeDef *ADCx, uint32_t ADC_ExternalTrigInjecConv); +void ADC_ExternalTrigInjectedConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState); +void ADC_SoftwareStartInjectedConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState); +FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_TypeDef *ADCx); +void ADC_InjectedChannelConfig(ADC_TypeDef *ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime); +void ADC_InjectedSequencerLengthConfig(ADC_TypeDef *ADCx, uint8_t Length); +void ADC_SetInjectedOffset(ADC_TypeDef *ADCx, uint8_t ADC_InjectedChannel, uint16_t Offset); +uint16_t ADC_GetInjectedConversionValue(ADC_TypeDef *ADCx, uint8_t ADC_InjectedChannel); +void ADC_AnalogWatchdogCmd(ADC_TypeDef *ADCx, uint32_t ADC_AnalogWatchdog); +void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef *ADCx, uint16_t HighThreshold, uint16_t LowThreshold); +void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef *ADCx, uint8_t ADC_Channel); +void ADC_TempSensorVrefintCmd(FunctionalState NewState); +FlagStatus ADC_GetFlagStatus(ADC_TypeDef *ADCx, uint8_t ADC_FLAG); +void ADC_ClearFlag(ADC_TypeDef *ADCx, uint8_t ADC_FLAG); +ITStatus ADC_GetITStatus(ADC_TypeDef *ADCx, uint16_t ADC_IT); +void ADC_ClearITPendingBit(ADC_TypeDef *ADCx, uint16_t ADC_IT); +s32 TempSensor_Volt_To_Temper(s32 Value); +void ADC_BufferCmd(ADC_TypeDef *ADCx, FunctionalState NewState); +void ADC_TKey_ChannelxMulShieldCmd(ADC_TypeDef *ADCx, uint8_t ADC_Channel, FunctionalState NewState); +void ADC_TKey_MulShieldCmd(ADC_TypeDef *ADCx, FunctionalState NewState); +void ADC_DutyDelayCmd(ADC_TypeDef *ADCx, FunctionalState NewState); +void ADC_FIFO_Cmd(ADC_TypeDef *ADCx, FunctionalState NewState); +void ADC_Sample_ModeConfig(ADC_TypeDef *ADCx, uint32_t ADC_Sample_Mode); +void ADC_OffsetCalibrationConfig(ADC_TypeDef *ADCx); +void ADC_AnalogWatchdogResetCmd(ADC_TypeDef *ADCx, FunctionalState NewState); +int16_t Get_CalibrationValue(ADC_TypeDef *ADCx); +#ifdef __cplusplus +} +#endif + +#endif diff --git a/ZDBMS/BMS_MC/Peripheral/inc/ch32l103_bkp.h b/ZDBMS/BMS_MC/Peripheral/inc/ch32l103_bkp.h new file mode 100644 index 0000000..ccc57d4 --- /dev/null +++ b/ZDBMS/BMS_MC/Peripheral/inc/ch32l103_bkp.h @@ -0,0 +1,65 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32l103_bkp.h + * Author : WCH + * Version : V1.0.0 + * Date : 2023/07/08 + * Description : This file contains all the functions prototypes for the + * BKP firmware library. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#ifndef __CH32L103_BKP_H +#define __CH32L103_BKP_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "ch32l103.h" + +/* Tamper_Pin_active_level */ +#define BKP_TamperPinLevel_High ((uint16_t)0x0000) +#define BKP_TamperPinLevel_Low ((uint16_t)0x0001) + +/* RTC_output_source_to_output_on_the_Tamper_pin */ +#define BKP_RTCOutputSource_None ((uint16_t)0x0000) +#define BKP_RTCOutputSource_CalibClock ((uint16_t)0x0080) +#define BKP_RTCOutputSource_Alarm ((uint16_t)0x0100) +#define BKP_RTCOutputSource_Second ((uint16_t)0x0300) + +/* Data_Backup_Register */ +#define BKP_DR1 ((uint16_t)0x0004) +#define BKP_DR2 ((uint16_t)0x0008) +#define BKP_DR3 ((uint16_t)0x000C) +#define BKP_DR4 ((uint16_t)0x0010) +#define BKP_DR5 ((uint16_t)0x0014) +#define BKP_DR6 ((uint16_t)0x0018) +#define BKP_DR7 ((uint16_t)0x001C) +#define BKP_DR8 ((uint16_t)0x0020) +#define BKP_DR9 ((uint16_t)0x0024) +#define BKP_DR10 ((uint16_t)0x0028) +#define BKP_DR11 ((uint16_t)0x0040) +#define BKP_DR12 ((uint16_t)0x0044) +#define BKP_DR13 ((uint16_t)0x0048) + + +void BKP_DeInit(void); +void BKP_TamperPinLevelConfig(uint16_t BKP_TamperPinLevel); +void BKP_TamperPinCmd(FunctionalState NewState); +void BKP_ITConfig(FunctionalState NewState); +void BKP_RTCOutputConfig(uint16_t BKP_RTCOutputSource); +void BKP_SetRTCCalibrationValue(uint8_t CalibrationValue); +void BKP_WriteBackupRegister(uint16_t BKP_DR, uint16_t Data); +uint16_t BKP_ReadBackupRegister(uint16_t BKP_DR); +FlagStatus BKP_GetFlagStatus(void); +void BKP_ClearFlag(void); +ITStatus BKP_GetITStatus(void); +void BKP_ClearITPendingBit(void); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/ZDBMS/BMS_MC/Peripheral/inc/ch32l103_can.h b/ZDBMS/BMS_MC/Peripheral/inc/ch32l103_can.h new file mode 100644 index 0000000..0c0e313 --- /dev/null +++ b/ZDBMS/BMS_MC/Peripheral/inc/ch32l103_can.h @@ -0,0 +1,630 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32l103_can.h + * Author : WCH + * Version : V1.0.0 + * Date : 2023/07/08 + * Description : This file contains all the functions prototypes for the + * CAN firmware library. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#ifndef __CH32L103_CAN_H +#define __CH32L103_CAN_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "ch32l103.h" + +/* CAN init structure definition */ +typedef struct +{ + uint16_t CAN_Prescaler; /* Specifies the length of a time quantum. + It ranges from 1 to 1024. */ + + uint8_t CAN_Mode; /* Specifies the CAN operating mode. + This parameter can be a value of + @ref CAN_operating_mode */ + + uint8_t CAN_SJW; /* Specifies the maximum number of time quanta + the CAN hardware is allowed to lengthen or + shorten a bit to perform resynchronization. + This parameter can be a value of + @ref CAN_synchronisation_jump_width */ + + uint8_t CAN_BS1; /* Specifies the number of time quanta in Bit + Segment 1. This parameter can be a value of + @ref CAN_time_quantum_in_bit_segment_1 */ + + uint8_t CAN_BS2; /* Specifies the number of time quanta in Bit + Segment 2. + This parameter can be a value of + @ref CAN_time_quantum_in_bit_segment_2 */ + + FunctionalState CAN_TTCM; /* Enable or disable the time triggered + communication mode. This parameter can be set + either to ENABLE or DISABLE. */ + + FunctionalState CAN_ABOM; /* Enable or disable the automatic bus-off + management. This parameter can be set either + to ENABLE or DISABLE. */ + + FunctionalState CAN_AWUM; /* Enable or disable the automatic wake-up mode. + This parameter can be set either to ENABLE or + DISABLE. */ + + FunctionalState CAN_NART; /* Enable or disable the no-automatic + retransmission mode. This parameter can be + set either to ENABLE or DISABLE. */ + + FunctionalState CAN_RFLM; /* Enable or disable the Receive FIFO Locked mode. + This parameter can be set either to ENABLE + or DISABLE. */ + + FunctionalState CAN_TXFP; /* Enable or disable the transmit FIFO priority. + This parameter can be set either to ENABLE + or DISABLE. */ +} CAN_InitTypeDef; + +/* CAN filter init structure definition */ +typedef struct +{ + uint16_t CAN_FilterIdHigh; /* Specifies the filter identification number (MSBs for a 32-bit + configuration, first one for a 16-bit configuration). + This parameter can be a value between 0x0000 and 0xFFFF */ + + uint16_t CAN_FilterIdLow; /* Specifies the filter identification number (LSBs for a 32-bit + configuration, second one for a 16-bit configuration). + This parameter can be a value between 0x0000 and 0xFFFF */ + + uint16_t CAN_FilterMaskIdHigh; /* Specifies the filter mask number or identification number, + according to the mode (MSBs for a 32-bit configuration, + first one for a 16-bit configuration). + This parameter can be a value between 0x0000 and 0xFFFF */ + + uint16_t CAN_FilterMaskIdLow; /* Specifies the filter mask number or identification number, + according to the mode (LSBs for a 32-bit configuration, + second one for a 16-bit configuration). + This parameter can be a value between 0x0000 and 0xFFFF */ + + uint16_t CAN_FilterFIFOAssignment; /* Specifies the FIFO (0 or 1) which will be assigned to the filter. + This parameter can be a value of @ref CAN_filter_FIFO */ + + uint8_t CAN_FilterNumber; /* Specifies the filter which will be initialized. It ranges from 0 to 13. */ + + uint8_t CAN_FilterMode; /* Specifies the filter mode to be initialized. + This parameter can be a value of @ref CAN_filter_mode */ + + uint8_t CAN_FilterScale; /* Specifies the filter scale. + This parameter can be a value of @ref CAN_filter_scale */ + + FunctionalState CAN_FilterActivation; /* Enable or disable the filter. + This parameter can be set either to ENABLE or DISABLE. */ +} CAN_FilterInitTypeDef; + +/* CAN Tx message structure definition */ +typedef struct +{ + uint32_t StdId; /* Specifies the standard identifier. + This parameter can be a value between 0 to 0x7FF. */ + + uint32_t ExtId; /* Specifies the extended identifier. + This parameter can be a value between 0 to 0x1FFFFFFF. */ + + uint8_t IDE; /* Specifies the type of identifier for the message that + will be transmitted. This parameter can be a value + of @ref CAN_identifier_type */ + + uint8_t RTR; /* Specifies the type of frame for the message that will + be transmitted. This parameter can be a value of + @ref CAN_remote_transmission_request */ + + uint8_t DLC; /* Specifies the length of the frame that will be + transmitted. This parameter can be a value between + 0 to 8 */ + + uint8_t Data[8]; /* Contains the data to be transmitted. It ranges from 0 + to 0xFF. */ +} CanTxMsg; + +/* CAN Rx message structure definition */ +typedef struct +{ + uint32_t StdId; /* Specifies the standard identifier. + This parameter can be a value between 0 to 0x7FF. */ + + uint32_t ExtId; /* Specifies the extended identifier. + This parameter can be a value between 0 to 0x1FFFFFFF. */ + + uint8_t IDE; /* Specifies the type of identifier for the message that + will be received. This parameter can be a value of + @ref CAN_identifier_type */ + + uint8_t RTR; /* Specifies the type of frame for the received message. + This parameter can be a value of + @ref CAN_remote_transmission_request */ + + uint8_t DLC; /* Specifies the length of the frame that will be received. + This parameter can be a value between 0 to 8 */ + + uint8_t Data[8]; /* Contains the data to be received. It ranges from 0 to + 0xFF. */ + + uint8_t FMI; /* Specifies the index of the filter the message stored in + the mailbox passes through. This parameter can be a + value between 0 to 0xFF */ +} CanRxMsg; + +/* CANFD init structure definition */ +typedef struct +{ + uint16_t CANFD_Prescaler; /* Specifies the length of a time quantum. + It ranges from 1 to 32. */ + + uint8_t CANFD_Mode; /* Specifies the CAN operating mode. + This parameter can be a value of + @ref CAN_operating_mode */ + + uint8_t CANFD_SJW; /* Specifies the maximum number of time quanta + the CAN hardware is allowed to lengthen or + shorten a bit to perform resynchronization. + This parameter can be a value of + @ref CANFD_synchronisation_jump_width */ + + uint8_t CANFD_BS1; /* Specifies the number of time quanta in Bit + Segment 1. This parameter can be a value of + @ref CANFD_time_quantum_in_bit_segment_1 */ + + uint8_t CANFD_BS2; /* Specifies the number of time quanta in Bit + Segment 2. + This parameter can be a value of + @ref CANFD_time_quantum_in_bit_segment_2 */ + + uint8_t CANFD_TDC_FILTER; /* Specifies the number of time quanta in Bit Segment + Minimum delay of internal delay counter. + It ranges from 0 to 63. */ + + uint8_t CANFD_TDC0; /* Specifies the number of time quanta in Bit Segment + transmission delay compensation offset. + It ranges from 0 to 63. */ + + FunctionalState CANFD_TDCE; /* Enable or disable transmission delay compensation offset. + This parameter can be set either to ENABLE or DISABLE. */ + + FunctionalState CANFD_TTCM; /* Enable or disable the time triggered + communication mode. This parameter can be set + either to ENABLE or DISABLE. */ + + FunctionalState CANFD_ABOM; /* Enable or disable the automatic bus-off + management. This parameter can be set either + to ENABLE or DISABLE. */ + + FunctionalState CANFD_AWUM; /* Enable or disable the automatic wake-up mode. + This parameter can be set either to ENABLE or + DISABLE. */ + + FunctionalState CANFD_NART; /* Enable or disable the no-automatic + retransmission mode. This parameter can be + set either to ENABLE or DISABLE. */ + + FunctionalState CANFD_TXFP; /* Enable or disable the transmit FIFO priority. + This parameter can be set either to ENABLE + or DISABLE. */ + + FunctionalState CANFD_RES_Error; /* Enable or disable the RES bit can generate error . + This parameter can be set either to ENABLE + or DISABLE. */ + + FunctionalState CANFD_ESI_Auto_TXM0; /* Enable or disable the ESI bit auto mode for Tx mailbox 0. + This parameter can be set either to ENABLE + or DISABLE. */ + + FunctionalState CANFD_ESI_Auto_TXM1; /* Enable or disable the ESI bit auto mode for Tx mailbox 1. + This parameter can be set either to ENABLE + or DISABLE. */ + + FunctionalState CANFD_ESI_Auto_TXM2; /* Enable or disable the ESI bit auto mode for Tx mailbox 2. + This parameter can be set either to ENABLE + or DISABLE. */ + + FunctionalState CANFD_BRS_TXM0; /* Enable or disable the BRS bit speed switch for Tx mailbox 0. + This parameter can be set either to ENABLE + or DISABLE. */ + + FunctionalState CANFD_BRS_TXM1; /* Enable or disable the BRS bit speed switch for Tx mailbox 1. + This parameter can be set either to ENABLE + or DISABLE. */ + + FunctionalState CANFD_BRS_TXM2; /* Enable or disable the BRS bit speed switch for Tx mailbox 2. + This parameter can be set either to ENABLE + or DISABLE. */ +} CANFD_InitTypeDef; + +/* CANFD Tx message structure definition */ +typedef struct +{ + uint32_t StdId; /* Specifies the standard identifier. + This parameter can be a value between 0 to 0x7FF. */ + + uint32_t ExtId; /* Specifies the extended identifier. + This parameter can be a value between 0 to 0x1FFFFFFF. */ + + uint8_t Data[64]; /* Contains the data to be transmitted. It ranges from 0 + to 0xFF. */ + + uint8_t IDE; /* Specifies the type of identifier for the message that + will be transmitted. This parameter can be a value + of @ref CAN_identifier_type */ + + uint8_t RTR; /* Specifies the type of frame for the message that will + be transmitted. This parameter can be a value of + @ref CAN_remote_transmission_request */ + + uint8_t DLC; /* Specifies the length of the frame that will be + transmitted. + This parameter can be a value of + @ref CANFD_data_length_code */ +} CanFDTxMsg; + +/* CANFD Rx message structure definition */ +typedef struct +{ + uint32_t StdId; /* Specifies the standard identifier. + This parameter can be a value between 0 to 0x7FF. */ + + uint32_t ExtId; /* Specifies the extended identifier. + This parameter can be a value between 0 to 0x1FFFFFFF. */ + + uint8_t Data[64]; /* Contains the data to be received. It ranges from 0 to + 0xFF. */ + + uint8_t IDE; /* Specifies the type of identifier for the message that + will be received. This parameter can be a value of + @ref CAN_identifier_type */ + + uint8_t RTR; /* Specifies the type of frame for the received message. + This parameter can be a value of + @ref CAN_remote_transmission_request */ + + uint8_t DLC; /* Specifies the length of the frame that will be received. + This parameter can be a value of + 0, 1, 2, 3, 4, 5, 6, 7, 8, 12, 16, 20, 24, 32, 48, 64 */ + + uint8_t BRS; /* Specifies the length of the frame that will be received. + This parameter can be a value of + @ref CANFD_data_length_code */ + + uint8_t ESI; /* Specifies the length of the frame that will be received. + This parameter can be a value of + @ref CANFD_data_length_code */ + + uint8_t RES; /* Specifies the length of the frame that will be received. + This parameter can be a value of + @ref CANFD_data_length_code */ + + uint8_t FMI; /* Specifies the index of the filter the message stored in + the mailbox passes through. This parameter can be a + value between 0 to 0xFF */ +} CanFDRxMsg; + +/* CAN_sleep_constants */ +#define CAN_InitStatus_Failed ((uint8_t)0x00) /* CAN initialization failed */ +#define CAN_InitStatus_Success ((uint8_t)0x01) /* CAN initialization OK */ + +/* CAN_Mode */ +#define CAN_Mode_Normal ((uint8_t)0x00) /* normal mode */ +#define CAN_Mode_LoopBack ((uint8_t)0x01) /* loopback mode */ +#define CAN_Mode_Silent ((uint8_t)0x02) /* silent mode */ +#define CAN_Mode_Silent_LoopBack ((uint8_t)0x03) /* loopback combined with silent mode */ + +/* CAN_Operating_Mode */ +#define CAN_OperatingMode_Initialization ((uint8_t)0x00) /* Initialization mode */ +#define CAN_OperatingMode_Normal ((uint8_t)0x01) /* Normal mode */ +#define CAN_OperatingMode_Sleep ((uint8_t)0x02) /* sleep mode */ + +/* CAN_Mode_Status */ +#define CAN_ModeStatus_Failed ((uint8_t)0x00) /* CAN entering the specific mode failed */ +#define CAN_ModeStatus_Success ((uint8_t)!CAN_ModeStatus_Failed) /* CAN entering the specific mode Succeed */ + +/* CAN_synchronisation_jump_width */ +#define CAN_SJW_1tq ((uint8_t)0x00) /* 1 time quantum */ +#define CAN_SJW_2tq ((uint8_t)0x01) /* 2 time quantum */ +#define CAN_SJW_3tq ((uint8_t)0x02) /* 3 time quantum */ +#define CAN_SJW_4tq ((uint8_t)0x03) /* 4 time quantum */ + +/* CAN_time_quantum_in_bit_segment_1 */ +#define CAN_BS1_1tq ((uint8_t)0x00) /* 1 time quantum */ +#define CAN_BS1_2tq ((uint8_t)0x01) /* 2 time quantum */ +#define CAN_BS1_3tq ((uint8_t)0x02) /* 3 time quantum */ +#define CAN_BS1_4tq ((uint8_t)0x03) /* 4 time quantum */ +#define CAN_BS1_5tq ((uint8_t)0x04) /* 5 time quantum */ +#define CAN_BS1_6tq ((uint8_t)0x05) /* 6 time quantum */ +#define CAN_BS1_7tq ((uint8_t)0x06) /* 7 time quantum */ +#define CAN_BS1_8tq ((uint8_t)0x07) /* 8 time quantum */ +#define CAN_BS1_9tq ((uint8_t)0x08) /* 9 time quantum */ +#define CAN_BS1_10tq ((uint8_t)0x09) /* 10 time quantum */ +#define CAN_BS1_11tq ((uint8_t)0x0A) /* 11 time quantum */ +#define CAN_BS1_12tq ((uint8_t)0x0B) /* 12 time quantum */ +#define CAN_BS1_13tq ((uint8_t)0x0C) /* 13 time quantum */ +#define CAN_BS1_14tq ((uint8_t)0x0D) /* 14 time quantum */ +#define CAN_BS1_15tq ((uint8_t)0x0E) /* 15 time quantum */ +#define CAN_BS1_16tq ((uint8_t)0x0F) /* 16 time quantum */ + +/* CAN_time_quantum_in_bit_segment_2 */ +#define CAN_BS2_1tq ((uint8_t)0x00) /* 1 time quantum */ +#define CAN_BS2_2tq ((uint8_t)0x01) /* 2 time quantum */ +#define CAN_BS2_3tq ((uint8_t)0x02) /* 3 time quantum */ +#define CAN_BS2_4tq ((uint8_t)0x03) /* 4 time quantum */ +#define CAN_BS2_5tq ((uint8_t)0x04) /* 5 time quantum */ +#define CAN_BS2_6tq ((uint8_t)0x05) /* 6 time quantum */ +#define CAN_BS2_7tq ((uint8_t)0x06) /* 7 time quantum */ +#define CAN_BS2_8tq ((uint8_t)0x07) /* 8 time quantum */ + +/* CAN_filter_mode */ +#define CAN_FilterMode_IdMask ((uint8_t)0x00) /* identifier/mask mode */ +#define CAN_FilterMode_IdList ((uint8_t)0x01) /* identifier list mode */ + +/* CAN_filter_scale */ +#define CAN_FilterScale_16bit ((uint8_t)0x00) /* Two 16-bit filters */ +#define CAN_FilterScale_32bit ((uint8_t)0x01) /* One 32-bit filter */ + +/* CAN_filter_FIFO */ +#define CAN_Filter_FIFO0 ((uint8_t)0x00) /* Filter FIFO 0 assignment for filter x */ +#define CAN_Filter_FIFO1 ((uint8_t)0x01) /* Filter FIFO 1 assignment for filter x */ + +/* CAN_identifier_type */ +#define CAN_Id_Standard ((uint32_t)0x00000000) /* Standard Id */ +#define CAN_Id_Extended ((uint32_t)0x00000004) /* Extended Id */ + +/* CAN_remote_transmission_request */ +#define CAN_RTR_Data ((uint32_t)0x00000000) /* Data frame */ +#define CAN_RTR_Remote ((uint32_t)0x00000002) /* Remote frame */ + +/* CAN_transmit_constants */ +#define CAN_TxStatus_Failed ((uint8_t)0x00) /* CAN transmission failed */ +#define CAN_TxStatus_Ok ((uint8_t)0x01) /* CAN transmission succeeded */ +#define CAN_TxStatus_Pending ((uint8_t)0x02) /* CAN transmission pending */ +#define CAN_TxStatus_NoMailBox ((uint8_t)0x04) /* CAN cell did not provide an empty mailbox */ + +/* CAN_receive_FIFO_number_constants */ +#define CAN_FIFO0 ((uint8_t)0x00) /* CAN FIFO 0 used to receive */ +#define CAN_FIFO1 ((uint8_t)0x01) /* CAN FIFO 1 used to receive */ + +/* CAN_sleep_constants */ +#define CAN_Sleep_Failed ((uint8_t)0x00) /* CAN did not enter the sleep mode */ +#define CAN_Sleep_Ok ((uint8_t)0x01) /* CAN entered the sleep mode */ + +/* CAN_wake_up_constants */ +#define CAN_WakeUp_Failed ((uint8_t)0x00) /* CAN did not leave the sleep mode */ +#define CAN_WakeUp_Ok ((uint8_t)0x01) /* CAN leaved the sleep mode */ + +/* CAN_Error_Code_constants */ +#define CAN_ErrorCode_NoErr ((uint8_t)0x00) /* No Error */ +#define CAN_ErrorCode_StuffErr ((uint8_t)0x10) /* Stuff Error */ +#define CAN_ErrorCode_FormErr ((uint8_t)0x20) /* Form Error */ +#define CAN_ErrorCode_ACKErr ((uint8_t)0x30) /* Acknowledgment Error */ +#define CAN_ErrorCode_BitRecessiveErr ((uint8_t)0x40) /* Bit Recessive Error */ +#define CAN_ErrorCode_BitDominantErr ((uint8_t)0x50) /* Bit Dominant Error */ +#define CAN_ErrorCode_CRCErr ((uint8_t)0x60) /* CRC Error */ +#define CAN_ErrorCode_SoftwareSetErr ((uint8_t)0x70) /* Software Set Error */ + +/* CAN_flags */ +/* Transmit Flags */ +/* If the flag is 0x3XXXXXXX, it means that it can be used with CAN_GetFlagStatus() + * and CAN_ClearFlag() functions. + * If the flag is 0x1XXXXXXX, it means that it can only be used with CAN_GetFlagStatus() function. +*/ +#define CAN_FLAG_RQCP0 ((uint32_t)0x38000001) /* Request MailBox0 Flag */ +#define CAN_FLAG_RQCP1 ((uint32_t)0x38000100) /* Request MailBox1 Flag */ +#define CAN_FLAG_RQCP2 ((uint32_t)0x38010000) /* Request MailBox2 Flag */ + +/* Receive Flags */ +#define CAN_FLAG_FMP0 ((uint32_t)0x12000003) /* FIFO 0 Message Pending Flag */ +#define CAN_FLAG_FF0 ((uint32_t)0x32000008) /* FIFO 0 Full Flag */ +#define CAN_FLAG_FOV0 ((uint32_t)0x32000010) /* FIFO 0 Overrun Flag */ +#define CAN_FLAG_FMP1 ((uint32_t)0x14000003) /* FIFO 1 Message Pending Flag */ +#define CAN_FLAG_FF1 ((uint32_t)0x34000008) /* FIFO 1 Full Flag */ +#define CAN_FLAG_FOV1 ((uint32_t)0x34000010) /* FIFO 1 Overrun Flag */ + +/* Operating Mode Flags */ +#define CAN_FLAG_WKU ((uint32_t)0x31000008) /* Wake up Flag */ +#define CAN_FLAG_SLAK ((uint32_t)0x31000012) /* Sleep acknowledge Flag */ +/* Note: + *When SLAK intterupt is disabled (SLKIE=0), no polling on SLAKI is possible. + *In this case the SLAK bit can be polled. +*/ + + +/* Error Flags */ +#define CAN_FLAG_EWG ((uint32_t)0x10F00001) /* Error Warning Flag */ +#define CAN_FLAG_EPV ((uint32_t)0x10F00002) /* Error Passive Flag */ +#define CAN_FLAG_BOF ((uint32_t)0x10F00004) /* Bus-Off Flag */ +#define CAN_FLAG_LEC ((uint32_t)0x30F00070) /* Last error code Flag */ + +/* CAN_interrupts */ +#define CAN_IT_TME ((uint32_t)0x00000001) /* Transmit mailbox empty Interrupt*/ + +/* Receive Interrupts */ +#define CAN_IT_FMP0 ((uint32_t)0x00000002) /* FIFO 0 message pending Interrupt*/ +#define CAN_IT_FF0 ((uint32_t)0x00000004) /* FIFO 0 full Interrupt*/ +#define CAN_IT_FOV0 ((uint32_t)0x00000008) /* FIFO 0 overrun Interrupt*/ +#define CAN_IT_FMP1 ((uint32_t)0x00000010) /* FIFO 1 message pending Interrupt*/ +#define CAN_IT_FF1 ((uint32_t)0x00000020) /* FIFO 1 full Interrupt*/ +#define CAN_IT_FOV1 ((uint32_t)0x00000040) /* FIFO 1 overrun Interrupt*/ + +/* Operating Mode Interrupts */ +#define CAN_IT_WKU ((uint32_t)0x00010000) /* Wake-up Interrupt*/ +#define CAN_IT_SLK ((uint32_t)0x00020000) /* Sleep acknowledge Interrupt*/ + +/* Error Interrupts */ +#define CAN_IT_EWG ((uint32_t)0x00000100) /* Error warning Interrupt*/ +#define CAN_IT_EPV ((uint32_t)0x00000200) /* Error passive Interrupt*/ +#define CAN_IT_BOF ((uint32_t)0x00000400) /* Bus-off Interrupt*/ +#define CAN_IT_LEC ((uint32_t)0x00000800) /* Last error code Interrupt*/ +#define CAN_IT_ERR ((uint32_t)0x00008000) /* Error Interrupt*/ + +/* Flags named as Interrupts : kept only for FW compatibility */ +#define CAN_IT_RQCP0 CAN_IT_TME +#define CAN_IT_RQCP1 CAN_IT_TME +#define CAN_IT_RQCP2 CAN_IT_TME + +/* CAN_Legacy */ +#define CANINITFAILED CAN_InitStatus_Failed +#define CANINITOK CAN_InitStatus_Success +#define CAN_FilterFIFO0 CAN_Filter_FIFO0 +#define CAN_FilterFIFO1 CAN_Filter_FIFO1 +#define CAN_ID_STD CAN_Id_Standard +#define CAN_ID_EXT CAN_Id_Extended +#define CAN_RTR_DATA CAN_RTR_Data +#define CAN_RTR_REMOTE CAN_RTR_Remote +#define CANTXFAILE CAN_TxStatus_Failed +#define CANTXOK CAN_TxStatus_Ok +#define CANTXPENDING CAN_TxStatus_Pending +#define CAN_NO_MB CAN_TxStatus_NoMailBox +#define CANSLEEPFAILED CAN_Sleep_Failed +#define CANSLEEPOK CAN_Sleep_Ok +#define CANWAKEUPFAILED CAN_WakeUp_Failed +#define CANWAKEUPOK CAN_WakeUp_Ok + +/* CAN_BS1_Mode */ +#define CAN_BS1_4bit ((uint32_t)0x00000000) +#define CAN_BS1_6bit ((uint32_t)0x00000100) + +/* CANFD_data_length_code */ +#define CANFD_DLC_BYTES_0 ((uint32_t)0x0000) /* 0 bytes data field */ +#define CANFD_DLC_BYTES_1 ((uint32_t)0x0001) /* 1 bytes data field */ +#define CANFD_DLC_BYTES_2 ((uint32_t)0x0002) /* 2 bytes data field */ +#define CANFD_DLC_BYTES_3 ((uint32_t)0x0003) /* 3 bytes data field */ +#define CANFD_DLC_BYTES_4 ((uint32_t)0x0004) /* 4 bytes data field */ +#define CANFD_DLC_BYTES_5 ((uint32_t)0x0005) /* 5 bytes data field */ +#define CANFD_DLC_BYTES_6 ((uint32_t)0x0006) /* 6 bytes data field */ +#define CANFD_DLC_BYTES_7 ((uint32_t)0x0007) /* 7 bytes data field */ +#define CANFD_DLC_BYTES_8 ((uint32_t)0x0008) /* 8 bytes data field */ +#define CANFD_DLC_BYTES_12 ((uint32_t)0x0009) /* 12 bytes data field */ +#define CANFD_DLC_BYTES_16 ((uint32_t)0x000A) /* 16 bytes data field */ +#define CANFD_DLC_BYTES_20 ((uint32_t)0x000B) /* 20 bytes data field */ +#define CANFD_DLC_BYTES_24 ((uint32_t)0x000C) /* 24 bytes data field */ +#define CANFD_DLC_BYTES_32 ((uint32_t)0x000D) /* 32 bytes data field */ +#define CANFD_DLC_BYTES_48 ((uint32_t)0x000E) /* 48 bytes data field */ +#define CANFD_DLC_BYTES_64 ((uint32_t)0x000F) /* 64 bytes data field */ + +/* CANFD_synchronisation_jump_width */ +#define CANFD_SJW_1tq ((uint8_t)0x00) /* 1 time quantum */ +#define CANFD_SJW_2tq ((uint8_t)0x01) /* 2 time quantum */ +#define CANFD_SJW_3tq ((uint8_t)0x02) /* 3 time quantum */ +#define CANFD_SJW_4tq ((uint8_t)0x03) /* 4 time quantum */ +#define CANFD_SJW_5tq ((uint8_t)0x04) /* 5 time quantum */ +#define CANFD_SJW_6tq ((uint8_t)0x05) /* 6 time quantum */ +#define CANFD_SJW_7tq ((uint8_t)0x06) /* 7 time quantum */ +#define CANFD_SJW_8tq ((uint8_t)0x07) /* 8 time quantum */ +#define CANFD_SJW_9tq ((uint8_t)0x08) /* 9 time quantum */ +#define CANFD_SJW_10tq ((uint8_t)0x09) /* 10 time quantum */ +#define CANFD_SJW_11tq ((uint8_t)0x0A) /* 11 time quantum */ +#define CANFD_SJW_12tq ((uint8_t)0x0B) /* 12 time quantum */ +#define CANFD_SJW_13tq ((uint8_t)0x0C) /* 13 time quantum */ +#define CANFD_SJW_14tq ((uint8_t)0x0D) /* 14 time quantum */ +#define CANFD_SJW_15tq ((uint8_t)0x0E) /* 15 time quantum */ +#define CANFD_SJW_16tq ((uint8_t)0x0F) /* 16 time quantum */ + +/* CANFD_time_quantum_in_bit_segment_1 */ +#define CANFD_BS1_1tq ((uint8_t)0x00) /* 1 time quantum */ +#define CANFD_BS1_2tq ((uint8_t)0x01) /* 2 time quantum */ +#define CANFD_BS1_3tq ((uint8_t)0x02) /* 3 time quantum */ +#define CANFD_BS1_4tq ((uint8_t)0x03) /* 4 time quantum */ +#define CANFD_BS1_5tq ((uint8_t)0x04) /* 5 time quantum */ +#define CANFD_BS1_6tq ((uint8_t)0x05) /* 6 time quantum */ +#define CANFD_BS1_7tq ((uint8_t)0x06) /* 7 time quantum */ +#define CANFD_BS1_8tq ((uint8_t)0x07) /* 8 time quantum */ +#define CANFD_BS1_9tq ((uint8_t)0x08) /* 9 time quantum */ +#define CANFD_BS1_10tq ((uint8_t)0x09) /* 10 time quantum */ +#define CANFD_BS1_11tq ((uint8_t)0x0A) /* 11 time quantum */ +#define CANFD_BS1_12tq ((uint8_t)0x0B) /* 12 time quantum */ +#define CANFD_BS1_13tq ((uint8_t)0x0C) /* 13 time quantum */ +#define CANFD_BS1_14tq ((uint8_t)0x0D) /* 14 time quantum */ +#define CANFD_BS1_15tq ((uint8_t)0x0E) /* 15 time quantum */ +#define CANFD_BS1_16tq ((uint8_t)0x0F) /* 16 time quantum */ +#define CANFD_BS1_17tq ((uint8_t)0x10) /* 17 time quantum */ +#define CANFD_BS1_18tq ((uint8_t)0x11) /* 18 time quantum */ +#define CANFD_BS1_19tq ((uint8_t)0x12) /* 19 time quantum */ +#define CANFD_BS1_20tq ((uint8_t)0x13) /* 20 time quantum */ +#define CANFD_BS1_21tq ((uint8_t)0x14) /* 21 time quantum */ +#define CANFD_BS1_22tq ((uint8_t)0x15) /* 22 time quantum */ +#define CANFD_BS1_23tq ((uint8_t)0x16) /* 23 time quantum */ +#define CANFD_BS1_24tq ((uint8_t)0x17) /* 24 time quantum */ +#define CANFD_BS1_25tq ((uint8_t)0x18) /* 25 time quantum */ +#define CANFD_BS1_26tq ((uint8_t)0x19) /* 26 time quantum */ +#define CANFD_BS1_27tq ((uint8_t)0x1A) /* 27 time quantum */ +#define CANFD_BS1_28tq ((uint8_t)0x1B) /* 28 time quantum */ +#define CANFD_BS1_29tq ((uint8_t)0x1C) /* 29 time quantum */ +#define CANFD_BS1_30tq ((uint8_t)0x1D) /* 30 time quantum */ +#define CANFD_BS1_31tq ((uint8_t)0x1E) /* 31 time quantum */ +#define CANFD_BS1_32tq ((uint8_t)0x1F) /* 32 time quantum */ + +/* CANFD_time_quantum_in_bit_segment_2 */ +#define CANFD_BS2_1tq ((uint8_t)0x00) /* 1 time quantum */ +#define CANFD_BS2_2tq ((uint8_t)0x01) /* 2 time quantum */ +#define CANFD_BS2_3tq ((uint8_t)0x02) /* 3 time quantum */ +#define CANFD_BS2_4tq ((uint8_t)0x03) /* 4 time quantum */ +#define CANFD_BS2_5tq ((uint8_t)0x04) /* 5 time quantum */ +#define CANFD_BS2_6tq ((uint8_t)0x05) /* 6 time quantum */ +#define CANFD_BS2_7tq ((uint8_t)0x06) /* 7 time quantum */ +#define CANFD_BS2_8tq ((uint8_t)0x07) /* 8 time quantum */ +#define CANFD_BS2_9tq ((uint8_t)0x08) /* 9 time quantum */ +#define CANFD_BS2_10tq ((uint8_t)0x09) /* 10 time quantum */ +#define CANFD_BS2_11tq ((uint8_t)0x0A) /* 11 time quantum */ +#define CANFD_BS2_12tq ((uint8_t)0x0B) /* 12 time quantum */ +#define CANFD_BS2_13tq ((uint8_t)0x0C) /* 13 time quantum */ +#define CANFD_BS2_14tq ((uint8_t)0x0D) /* 14 time quantum */ +#define CANFD_BS2_15tq ((uint8_t)0x0E) /* 15 time quantum */ +#define CANFD_BS2_16tq ((uint8_t)0x0F) /* 16 time quantum */ + +/* CAN_Transmit_Mailbox_number_constants */ +#define CAN_Transmit_Mailbox0 ((uint8_t)0x00) +#define CAN_Transmit_Mailbox1 ((uint8_t)0x01) +#define CAN_Transmit_Mailbox2 ((uint8_t)0x02) + + +void CAN_DeInit(CAN_TypeDef *CANx); +uint8_t CAN_Init(CAN_TypeDef *CANx, CAN_InitTypeDef *CAN_InitStruct); +void CAN_FilterInit(CAN_FilterInitTypeDef *CAN_FilterInitStruct); +void CAN_StructInit(CAN_InitTypeDef *CAN_InitStruct); +void CAN_SlaveStartBank(uint8_t CAN_BankNumber); +void CAN_DBGFreeze(CAN_TypeDef *CANx, FunctionalState NewState); +void CAN_TTComModeCmd(CAN_TypeDef *CANx, FunctionalState NewState); +uint8_t CAN_Transmit(CAN_TypeDef *CANx, CanTxMsg *TxMessage); +uint8_t CAN_TransmitStatus(CAN_TypeDef *CANx, uint8_t TransmitMailbox); +void CAN_CancelTransmit(CAN_TypeDef *CANx, uint8_t Mailbox); +void CAN_Receive(CAN_TypeDef *CANx, uint8_t FIFONumber, CanRxMsg *RxMessage); +void CAN_FIFORelease(CAN_TypeDef *CANx, uint8_t FIFONumber); +uint8_t CAN_MessagePending(CAN_TypeDef *CANx, uint8_t FIFONumber); +uint8_t CAN_OperatingModeRequest(CAN_TypeDef *CANx, uint8_t CAN_OperatingMode); +uint8_t CAN_Sleep(CAN_TypeDef *CANx); +uint8_t CAN_WakeUp(CAN_TypeDef *CANx); +uint8_t CAN_GetLastErrorCode(CAN_TypeDef *CANx); +uint8_t CAN_GetReceiveErrorCounter(CAN_TypeDef *CANx); +uint8_t CAN_GetLSBTransmitErrorCounter(CAN_TypeDef *CANx); +void CAN_ITConfig(CAN_TypeDef *CANx, uint32_t CAN_IT, FunctionalState NewState); +FlagStatus CAN_GetFlagStatus(CAN_TypeDef *CANx, uint32_t CAN_FLAG); +void CAN_ClearFlag(CAN_TypeDef *CANx, uint32_t CAN_FLAG); +ITStatus CAN_GetITStatus(CAN_TypeDef *CANx, uint32_t CAN_IT); +void CAN_ClearITPendingBit(CAN_TypeDef *CANx, uint32_t CAN_IT); +void CAN_BS1_ModeConfig(CAN_TypeDef* CANx, uint32_t CAN_BS1_Mode, uint8_t CAN_BS1_tq); +void CAN_BusOff_ErrCntConfig(CAN_TypeDef *CANx, uint8_t BusOff_ErrCnt); +void CANFD_Restrict_ModeCmd(CAN_TypeDef *CANx, FunctionalState NewState); +uint8_t CANFD_Init(CAN_TypeDef *CANx, CANFD_InitTypeDef *CANFD_InitStruct); +void CANFD_StructInit(CANFD_InitTypeDef *CANFD_InitStruct); +uint8_t CANFD_Transmit(CAN_TypeDef *CANx, CanFDTxMsg *TxMessage); +ErrorStatus CANFD_Receive(CAN_TypeDef *CANx, uint8_t FIFONumber, CanFDRxMsg *RxMessage); +uint8_t CANFD_GetTransmitDelayOffsetVal(CAN_TypeDef *CANx); +void CANFD_TransmitMailbox_DMAAdr(CAN_TypeDef *CANx, uint8_t MailboxNumber, uint32_t Address); +void CANFD_ReceiveFIFO_DMAAdr(CAN_TypeDef *CANx, uint8_t FIFONumber, uint32_t Address); + + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/ZDBMS/BMS_MC/Peripheral/inc/ch32l103_crc.h b/ZDBMS/BMS_MC/Peripheral/inc/ch32l103_crc.h new file mode 100644 index 0000000..114754c --- /dev/null +++ b/ZDBMS/BMS_MC/Peripheral/inc/ch32l103_crc.h @@ -0,0 +1,33 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32l103_crc.h + * Author : WCH + * Version : V1.0.0 + * Date : 2023/07/08 + * Description : This file contains all the functions prototypes for the + * CRC firmware library. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#ifndef __CH32L103_CRC_H +#define __CH32L103_CRC_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "ch32l103.h" + +void CRC_ResetDR(void); +uint32_t CRC_CalcCRC(uint32_t Data); +uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength); +uint32_t CRC_GetCRC(void); +void CRC_SetIDRegister(uint8_t IDValue); +uint8_t CRC_GetIDRegister(void); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/ZDBMS/BMS_MC/Peripheral/inc/ch32l103_dbgmcu.h b/ZDBMS/BMS_MC/Peripheral/inc/ch32l103_dbgmcu.h new file mode 100644 index 0000000..4797b18 --- /dev/null +++ b/ZDBMS/BMS_MC/Peripheral/inc/ch32l103_dbgmcu.h @@ -0,0 +1,46 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32l103_dbgmcu.h + * Author : WCH + * Version : V1.0.0 + * Date : 2023/07/08 + * Description : This file contains all the functions prototypes for the + * DBGMCU firmware library. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#ifndef __CH32L103_DBGMCU_H +#define __CH32L103_DBGMCU_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "ch32l103.h" + +#define DBGMCU_SLEEP ((uint32_t)0x00000001) +#define DBGMCU_STOP ((uint32_t)0x00000002) +#define DBGMCU_STANDBY ((uint32_t)0x00000004) +#define DBGMCU_IWDG_STOP ((uint32_t)0x00000100) +#define DBGMCU_WWDG_STOP ((uint32_t)0x00000200) +#define DBGMCU_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00000400) +#define DBGMCU_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00000800) +#define DBGMCU_TIM1_STOP ((uint32_t)0x00001000) +#define DBGMCU_TIM2_STOP ((uint32_t)0x00002000) +#define DBGMCU_TIM3_STOP ((uint32_t)0x00004000) +#define DBGMCU_TIM4_STOP ((uint32_t)0x00008000) +#define DBGMCU_CAN1_STOP ((uint32_t)0x00100000) + + +uint32_t DBGMCU_GetREVID(void); +uint32_t DBGMCU_GetDEVID(void); +uint32_t __get_DEBUG_CR(void); +void __set_DEBUG_CR(uint32_t value); +void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState); +uint32_t DBGMCU_GetCHIPID( void ); +#ifdef __cplusplus +} +#endif + +#endif diff --git a/ZDBMS/BMS_MC/Peripheral/inc/ch32l103_dma.h b/ZDBMS/BMS_MC/Peripheral/inc/ch32l103_dma.h new file mode 100644 index 0000000..7042b81 --- /dev/null +++ b/ZDBMS/BMS_MC/Peripheral/inc/ch32l103_dma.h @@ -0,0 +1,184 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32l103_dma.h + * Author : WCH + * Version : V1.0.0 + * Date : 2023/07/08 + * Description : This file contains all the functions prototypes for the + * DMA firmware library. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#ifndef __CH32L103_DMA_H +#define __CH32L103_DMA_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "ch32l103.h" + +/* DMA Init structure definition */ +typedef struct +{ + uint32_t DMA_PeripheralBaseAddr; /* Specifies the peripheral base address for DMAy Channelx. */ + + uint32_t DMA_MemoryBaseAddr; /* Specifies the memory base address for DMAy Channelx. */ + + uint32_t DMA_DIR; /* Specifies if the peripheral is the source or destination. + This parameter can be a value of @ref DMA_data_transfer_direction */ + + uint32_t DMA_BufferSize; /* Specifies the buffer size, in data unit, of the specified Channel. + The data unit is equal to the configuration set in DMA_PeripheralDataSize + or DMA_MemoryDataSize members depending in the transfer direction. */ + + uint32_t DMA_PeripheralInc; /* Specifies whether the Peripheral address register is incremented or not. + This parameter can be a value of @ref DMA_peripheral_incremented_mode */ + + uint32_t DMA_MemoryInc; /* Specifies whether the memory address register is incremented or not. + This parameter can be a value of @ref DMA_memory_incremented_mode */ + + uint32_t DMA_PeripheralDataSize; /* Specifies the Peripheral data width. + This parameter can be a value of @ref DMA_peripheral_data_size */ + + uint32_t DMA_MemoryDataSize; /* Specifies the Memory data width. + This parameter can be a value of @ref DMA_memory_data_size */ + + uint32_t DMA_Mode; /* Specifies the operation mode of the DMAy Channelx. + This parameter can be a value of @ref DMA_circular_normal_mode. + @note: The circular buffer mode cannot be used if the memory-to-memory + data transfer is configured on the selected Channel */ + + uint32_t DMA_Priority; /* Specifies the software priority for the DMAy Channelx. + This parameter can be a value of @ref DMA_priority_level */ + + uint32_t DMA_M2M; /* Specifies if the DMAy Channelx will be used in memory-to-memory transfer. + This parameter can be a value of @ref DMA_memory_to_memory */ +} DMA_InitTypeDef; + +/* DMA_data_transfer_direction */ +#define DMA_DIR_PeripheralDST ((uint32_t)0x00000010) +#define DMA_DIR_PeripheralSRC ((uint32_t)0x00000000) + +/* DMA_peripheral_incremented_mode */ +#define DMA_PeripheralInc_Enable ((uint32_t)0x00000040) +#define DMA_PeripheralInc_Disable ((uint32_t)0x00000000) + +/* DMA_memory_incremented_mode */ +#define DMA_MemoryInc_Enable ((uint32_t)0x00000080) +#define DMA_MemoryInc_Disable ((uint32_t)0x00000000) + +/* DMA_peripheral_data_size */ +#define DMA_PeripheralDataSize_Byte ((uint32_t)0x00000000) +#define DMA_PeripheralDataSize_HalfWord ((uint32_t)0x00000100) +#define DMA_PeripheralDataSize_Word ((uint32_t)0x00000200) + +/* DMA_memory_data_size */ +#define DMA_MemoryDataSize_Byte ((uint32_t)0x00000000) +#define DMA_MemoryDataSize_HalfWord ((uint32_t)0x00000400) +#define DMA_MemoryDataSize_Word ((uint32_t)0x00000800) + +/* DMA_circular_normal_mode */ +#define DMA_Mode_Circular ((uint32_t)0x00000020) +#define DMA_Mode_Normal ((uint32_t)0x00000000) + +/* DMA_priority_level */ +#define DMA_Priority_VeryHigh ((uint32_t)0x00003000) +#define DMA_Priority_High ((uint32_t)0x00002000) +#define DMA_Priority_Medium ((uint32_t)0x00001000) +#define DMA_Priority_Low ((uint32_t)0x00000000) + +/* DMA_memory_to_memory */ +#define DMA_M2M_Enable ((uint32_t)0x00004000) +#define DMA_M2M_Disable ((uint32_t)0x00000000) + +/* DMA_interrupts_definition */ +#define DMA_IT_TC ((uint32_t)0x00000002) +#define DMA_IT_HT ((uint32_t)0x00000004) +#define DMA_IT_TE ((uint32_t)0x00000008) + +#define DMA1_IT_GL1 ((uint32_t)0x00000001) +#define DMA1_IT_TC1 ((uint32_t)0x00000002) +#define DMA1_IT_HT1 ((uint32_t)0x00000004) +#define DMA1_IT_TE1 ((uint32_t)0x00000008) +#define DMA1_IT_GL2 ((uint32_t)0x00000010) +#define DMA1_IT_TC2 ((uint32_t)0x00000020) +#define DMA1_IT_HT2 ((uint32_t)0x00000040) +#define DMA1_IT_TE2 ((uint32_t)0x00000080) +#define DMA1_IT_GL3 ((uint32_t)0x00000100) +#define DMA1_IT_TC3 ((uint32_t)0x00000200) +#define DMA1_IT_HT3 ((uint32_t)0x00000400) +#define DMA1_IT_TE3 ((uint32_t)0x00000800) +#define DMA1_IT_GL4 ((uint32_t)0x00001000) +#define DMA1_IT_TC4 ((uint32_t)0x00002000) +#define DMA1_IT_HT4 ((uint32_t)0x00004000) +#define DMA1_IT_TE4 ((uint32_t)0x00008000) +#define DMA1_IT_GL5 ((uint32_t)0x00010000) +#define DMA1_IT_TC5 ((uint32_t)0x00020000) +#define DMA1_IT_HT5 ((uint32_t)0x00040000) +#define DMA1_IT_TE5 ((uint32_t)0x00080000) +#define DMA1_IT_GL6 ((uint32_t)0x00100000) +#define DMA1_IT_TC6 ((uint32_t)0x00200000) +#define DMA1_IT_HT6 ((uint32_t)0x00400000) +#define DMA1_IT_TE6 ((uint32_t)0x00800000) +#define DMA1_IT_GL7 ((uint32_t)0x01000000) +#define DMA1_IT_TC7 ((uint32_t)0x02000000) +#define DMA1_IT_HT7 ((uint32_t)0x04000000) +#define DMA1_IT_TE7 ((uint32_t)0x08000000) +#define DMA1_IT_GL8 ((uint32_t)0x10000000) +#define DMA1_IT_TC8 ((uint32_t)0x20000000) +#define DMA1_IT_HT8 ((uint32_t)0x40000000) +#define DMA1_IT_TE8 ((uint32_t)0x80000000) + +/* DMA_flags_definition */ +#define DMA1_FLAG_GL1 ((uint32_t)0x00000001) +#define DMA1_FLAG_TC1 ((uint32_t)0x00000002) +#define DMA1_FLAG_HT1 ((uint32_t)0x00000004) +#define DMA1_FLAG_TE1 ((uint32_t)0x00000008) +#define DMA1_FLAG_GL2 ((uint32_t)0x00000010) +#define DMA1_FLAG_TC2 ((uint32_t)0x00000020) +#define DMA1_FLAG_HT2 ((uint32_t)0x00000040) +#define DMA1_FLAG_TE2 ((uint32_t)0x00000080) +#define DMA1_FLAG_GL3 ((uint32_t)0x00000100) +#define DMA1_FLAG_TC3 ((uint32_t)0x00000200) +#define DMA1_FLAG_HT3 ((uint32_t)0x00000400) +#define DMA1_FLAG_TE3 ((uint32_t)0x00000800) +#define DMA1_FLAG_GL4 ((uint32_t)0x00001000) +#define DMA1_FLAG_TC4 ((uint32_t)0x00002000) +#define DMA1_FLAG_HT4 ((uint32_t)0x00004000) +#define DMA1_FLAG_TE4 ((uint32_t)0x00008000) +#define DMA1_FLAG_GL5 ((uint32_t)0x00010000) +#define DMA1_FLAG_TC5 ((uint32_t)0x00020000) +#define DMA1_FLAG_HT5 ((uint32_t)0x00040000) +#define DMA1_FLAG_TE5 ((uint32_t)0x00080000) +#define DMA1_FLAG_GL6 ((uint32_t)0x00100000) +#define DMA1_FLAG_TC6 ((uint32_t)0x00200000) +#define DMA1_FLAG_HT6 ((uint32_t)0x00400000) +#define DMA1_FLAG_TE6 ((uint32_t)0x00800000) +#define DMA1_FLAG_GL7 ((uint32_t)0x01000000) +#define DMA1_FLAG_TC7 ((uint32_t)0x02000000) +#define DMA1_FLAG_HT7 ((uint32_t)0x04000000) +#define DMA1_FLAG_TE7 ((uint32_t)0x08000000) +#define DMA1_FLAG_GL8 ((uint32_t)0x10000000) +#define DMA1_FLAG_TC8 ((uint32_t)0x20000000) +#define DMA1_FLAG_HT8 ((uint32_t)0x40000000) +#define DMA1_FLAG_TE8 ((uint32_t)0x80000000) + +void DMA_DeInit(DMA_Channel_TypeDef *DMAy_Channelx); +void DMA_Init(DMA_Channel_TypeDef *DMAy_Channelx, DMA_InitTypeDef *DMA_InitStruct); +void DMA_StructInit(DMA_InitTypeDef *DMA_InitStruct); +void DMA_Cmd(DMA_Channel_TypeDef *DMAy_Channelx, FunctionalState NewState); +void DMA_ITConfig(DMA_Channel_TypeDef *DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState); +void DMA_SetCurrDataCounter(DMA_Channel_TypeDef *DMAy_Channelx, uint16_t DataNumber); +uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef *DMAy_Channelx); +FlagStatus DMA_GetFlagStatus(uint32_t DMAy_FLAG); +void DMA_ClearFlag(uint32_t DMAy_FLAG); +ITStatus DMA_GetITStatus(uint32_t DMAy_IT); +void DMA_ClearITPendingBit(uint32_t DMAy_IT); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/ZDBMS/BMS_MC/Peripheral/inc/ch32l103_exti.h b/ZDBMS/BMS_MC/Peripheral/inc/ch32l103_exti.h new file mode 100644 index 0000000..058a195 --- /dev/null +++ b/ZDBMS/BMS_MC/Peripheral/inc/ch32l103_exti.h @@ -0,0 +1,90 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32l103_exti.h + * Author : WCH + * Version : V1.0.0 + * Date : 2024/05/06 + * Description : This file contains all the functions prototypes for the + * EXTI firmware library. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#ifndef __CH32L103_EXTI_H +#define __CH32L103_EXTI_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "ch32l103.h" + +/* EXTI mode enumeration */ +typedef enum +{ + EXTI_Mode_Interrupt = 0x00, + EXTI_Mode_Event = 0x04 +} EXTIMode_TypeDef; + +/* EXTI Trigger enumeration */ +typedef enum +{ + EXTI_Trigger_Rising = 0x08, + EXTI_Trigger_Falling = 0x0C, + EXTI_Trigger_Rising_Falling = 0x10 +} EXTITrigger_TypeDef; + +/* EXTI Init Structure definition */ +typedef struct +{ + uint32_t EXTI_Line; /* Specifies the EXTI lines to be enabled or disabled. + This parameter can be any combination of @ref EXTI_Lines */ + + EXTIMode_TypeDef EXTI_Mode; /* Specifies the mode for the EXTI lines. + This parameter can be a value of @ref EXTIMode_TypeDef */ + + EXTITrigger_TypeDef EXTI_Trigger; /* Specifies the trigger signal active edge for the EXTI lines. + This parameter can be a value of @ref EXTIMode_TypeDef */ + + FunctionalState EXTI_LineCmd; /* Specifies the new state of the selected EXTI lines. + This parameter can be set either to ENABLE or DISABLE */ +} EXTI_InitTypeDef; + +/* EXTI_Lines */ +#define EXTI_Line0 ((uint32_t)0x00001) /* External interrupt line 0 */ +#define EXTI_Line1 ((uint32_t)0x00002) /* External interrupt line 1 */ +#define EXTI_Line2 ((uint32_t)0x00004) /* External interrupt line 2 */ +#define EXTI_Line3 ((uint32_t)0x00008) /* External interrupt line 3 */ +#define EXTI_Line4 ((uint32_t)0x00010) /* External interrupt line 4 */ +#define EXTI_Line5 ((uint32_t)0x00020) /* External interrupt line 5 */ +#define EXTI_Line6 ((uint32_t)0x00040) /* External interrupt line 6 */ +#define EXTI_Line7 ((uint32_t)0x00080) /* External interrupt line 7 */ +#define EXTI_Line8 ((uint32_t)0x00100) /* External interrupt line 8 */ +#define EXTI_Line9 ((uint32_t)0x00200) /* External interrupt line 9 */ +#define EXTI_Line10 ((uint32_t)0x00400) /* External interrupt line 10 */ +#define EXTI_Line11 ((uint32_t)0x00800) /* External interrupt line 11 */ +#define EXTI_Line12 ((uint32_t)0x01000) /* External interrupt line 12 */ +#define EXTI_Line13 ((uint32_t)0x02000) /* External interrupt line 13 */ +#define EXTI_Line14 ((uint32_t)0x04000) /* External interrupt line 14 */ +#define EXTI_Line15 ((uint32_t)0x08000) /* External interrupt line 15 */ +#define EXTI_Line16 ((uint32_t)0x10000) /* External interrupt line 16 Connected to the PVD Output */ +#define EXTI_Line17 ((uint32_t)0x20000) /* External interrupt line 17 Connected to the RTC Alarm event */ +#define EXTI_Line19 ((uint32_t)0x80000) /* External interrupt line 19 Connected to the USBPD Wakeup event */ +#define EXTI_Line20 ((uint32_t)0x100000) /* External interrupt line 20 Connected to the USBFS Wakeup event */ +#define EXTI_Line21 ((uint32_t)0x200000) /* External interrupt line 21 Connected to the LPTIM Wakeup event */ +#define EXTI_Line22 ((uint32_t)0x400000) /* External interrupt line 22 Connected to the COMP Wakeup event */ + +void EXTI_DeInit(void); +void EXTI_Init(EXTI_InitTypeDef *EXTI_InitStruct); +void EXTI_StructInit(EXTI_InitTypeDef *EXTI_InitStruct); +void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line); +FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line); +void EXTI_ClearFlag(uint32_t EXTI_Line); +ITStatus EXTI_GetITStatus(uint32_t EXTI_Line); +void EXTI_ClearITPendingBit(uint32_t EXTI_Line); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/ZDBMS/BMS_MC/Peripheral/inc/ch32l103_flash.h b/ZDBMS/BMS_MC/Peripheral/inc/ch32l103_flash.h new file mode 100644 index 0000000..bda3664 --- /dev/null +++ b/ZDBMS/BMS_MC/Peripheral/inc/ch32l103_flash.h @@ -0,0 +1,142 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32l103_flash.h + * Author : WCH + * Version : V1.0.0 + * Date : 2023/07/08 + * Description : This file contains all the functions prototypes for the FLASH + * firmware library. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#ifndef __CH32L103_FLASH_H +#define __CH32L103_FLASH_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "ch32l103.h" + +/* FLASH Status */ +typedef enum +{ + FLASH_BUSY = 1, + FLASH_ERROR_PG, + FLASH_ERROR_WRP, + FLASH_COMPLETE, + FLASH_TIMEOUT, + FLASH_RDP, + FLASH_OP_RANGE_ERROR = 0xFD, + FLASH_ALIGN_ERROR = 0xFE, + FLASH_ADR_RANGE_ERROR = 0xFF, +} FLASH_Status; + +/* Flash_Latency */ +#define FLASH_Latency_0 ((uint32_t)0x00000000) /* FLASH Zero Latency cycle */ +#define FLASH_Latency_1 ((uint32_t)0x00000001) /* FLASH One Latency cycle */ +#define FLASH_Latency_2 ((uint32_t)0x00000002) /* FLASH Two Latency cycle */ + +/* Write Protect 1Sectors = 2KB */ +#define FLASH_WRProt_Sectors0 ((uint32_t)0x00000001) /* Write protection of sector 0 */ +#define FLASH_WRProt_Sectors1 ((uint32_t)0x00000002) /* Write protection of sector 1 */ +#define FLASH_WRProt_Sectors2 ((uint32_t)0x00000004) /* Write protection of sector 2 */ +#define FLASH_WRProt_Sectors3 ((uint32_t)0x00000008) /* Write protection of sector 3 */ +#define FLASH_WRProt_Sectors4 ((uint32_t)0x00000010) /* Write protection of sector 4 */ +#define FLASH_WRProt_Sectors5 ((uint32_t)0x00000020) /* Write protection of sector 5 */ +#define FLASH_WRProt_Sectors6 ((uint32_t)0x00000040) /* Write protection of sector 6 */ +#define FLASH_WRProt_Sectors7 ((uint32_t)0x00000080) /* Write protection of sector 7 */ +#define FLASH_WRProt_Sectors8 ((uint32_t)0x00000100) /* Write protection of sector 8 */ +#define FLASH_WRProt_Sectors9 ((uint32_t)0x00000200) /* Write protection of sector 9 */ +#define FLASH_WRProt_Sectors10 ((uint32_t)0x00000400) /* Write protection of sector 10 */ +#define FLASH_WRProt_Sectors11 ((uint32_t)0x00000800) /* Write protection of sector 11 */ +#define FLASH_WRProt_Sectors12 ((uint32_t)0x00001000) /* Write protection of sector 12 */ +#define FLASH_WRProt_Sectors13 ((uint32_t)0x00002000) /* Write protection of sector 13 */ +#define FLASH_WRProt_Sectors14 ((uint32_t)0x00004000) /* Write protection of sector 14 */ +#define FLASH_WRProt_Sectors15 ((uint32_t)0x00008000) /* Write protection of sector 15 */ +#define FLASH_WRProt_Sectors16 ((uint32_t)0x00010000) /* Write protection of sector 16 */ +#define FLASH_WRProt_Sectors17 ((uint32_t)0x00020000) /* Write protection of sector 17 */ +#define FLASH_WRProt_Sectors18 ((uint32_t)0x00040000) /* Write protection of sector 18 */ +#define FLASH_WRProt_Sectors19 ((uint32_t)0x00080000) /* Write protection of sector 19 */ +#define FLASH_WRProt_Sectors20 ((uint32_t)0x00100000) /* Write protection of sector 20 */ +#define FLASH_WRProt_Sectors21 ((uint32_t)0x00200000) /* Write protection of sector 21 */ +#define FLASH_WRProt_Sectors22 ((uint32_t)0x00400000) /* Write protection of sector 22 */ +#define FLASH_WRProt_Sectors23 ((uint32_t)0x00800000) /* Write protection of sector 23 */ +#define FLASH_WRProt_Sectors24 ((uint32_t)0x01000000) /* Write protection of sector 24 */ +#define FLASH_WRProt_Sectors25 ((uint32_t)0x02000000) /* Write protection of sector 25 */ +#define FLASH_WRProt_Sectors26 ((uint32_t)0x04000000) /* Write protection of sector 26 */ +#define FLASH_WRProt_Sectors27 ((uint32_t)0x08000000) /* Write protection of sector 27 */ +#define FLASH_WRProt_Sectors28 ((uint32_t)0x10000000) /* Write protection of sector 28 */ +#define FLASH_WRProt_Sectors29 ((uint32_t)0x20000000) /* Write protection of sector 29 */ +#define FLASH_WRProt_Sectors30 ((uint32_t)0x40000000) /* Write protection of sector 30 */ +#define FLASH_WRProt_Sectors31 ((uint32_t)0x80000000) /* Write protection of sector 31 */ + +#define FLASH_WRProt_AllSectors ((uint32_t)0xFFFFFFFF) /* Write protection of all Sectors */ + +/* Option_Bytes_IWatchdog */ +#define OB_IWDG_SW ((uint16_t)0x0001) /* Software IWDG selected */ +#define OB_IWDG_HW ((uint16_t)0x0000) /* Hardware IWDG selected */ + +/* Option_Bytes_nRST_STOP */ +#define OB_STOP_NoRST ((uint16_t)0x0002) /* No reset generated when entering in STOP */ +#define OB_STOP_RST ((uint16_t)0x0000) /* Reset generated when entering in STOP */ + +/* Option_Bytes_nRST_STDBY */ +#define OB_STDBY_NoRST ((uint16_t)0x0004) /* No reset generated when entering in STANDBY */ +#define OB_STDBY_RST ((uint16_t)0x0000) /* Reset generated when entering in STANDBY */ + +/* Option_Bytes_OB_CAN_BusOff_MODE */ +#define OB_CAN_BusOff_MODE1 ((uint16_t)0x0020) /* Bus off recovery mode1 */ +#define OB_CAN_BusOff_MODE2 ((uint16_t)0x0000) /* Bus off recovery mode2 */ + +/* FLASH_Interrupts */ +#define FLASH_IT_ERROR ((uint32_t)0x00000400) /* FPEC error interrupt source */ +#define FLASH_IT_EOP ((uint32_t)0x00001000) /* End of FLASH Operation Interrupt source */ +#define FLASH_IT_BANK1_ERROR FLASH_IT_ERROR /* FPEC BANK1 error interrupt source */ +#define FLASH_IT_BANK1_EOP FLASH_IT_EOP /* End of FLASH BANK1 Operation Interrupt source */ + +/* FLASH_Flags */ +#define FLASH_FLAG_BSY ((uint32_t)0x00000001) /* FLASH Busy flag */ +#define FLASH_FLAG_WRPRTERR ((uint32_t)0x00000010) /* FLASH Write protected error flag */ +#define FLASH_FLAG_EOP ((uint32_t)0x00000020) /* FLASH End of Operation flag */ +#define FLASH_FLAG_WAKE_UP ((uint32_t)0x00000040) /* FLASH Wake up of Operation flag */ +#define FLASH_FLAG_OPTERR ((uint32_t)0x00000001) /* FLASH Option Byte error flag */ + +#define FLASH_FLAG_BANK1_BSY FLASH_FLAG_BSY /* FLASH BANK1 Busy flag*/ +#define FLASH_FLAG_BANK1_EOP FLASH_FLAG_EOP /* FLASH BANK1 End of Operation flag */ +#define FLASH_FLAG_BANK1_WRPRTERR FLASH_FLAG_WRPRTERR /* FLASH BANK1 Write protected error flag */ + +/*Functions used for all devices*/ +void FLASH_SetLatency(uint32_t FLASH_Latency); +void FLASH_Unlock(void); +void FLASH_Lock(void); +FLASH_Status FLASH_ErasePage(uint32_t Page_Address); +FLASH_Status FLASH_EraseAllPages(void); +FLASH_Status FLASH_EraseOptionBytes(void); +FLASH_Status FLASH_EnableWriteProtection(uint32_t FLASH_Pages); +FLASH_Status FLASH_EnableReadOutProtection(void); +FLASH_Status FLASH_UserOptionByteConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY, uint8_t OB_RST); +uint32_t FLASH_GetUserOptionByte(void); +uint32_t FLASH_GetWriteProtectionOptionByte(void); +FlagStatus FLASH_GetReadOutProtectionStatus(void); +void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState); +FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG); +void FLASH_ClearFlag(uint32_t FLASH_FLAG); +FLASH_Status FLASH_GetStatus(void); +FLASH_Status FLASH_WaitForLastOperation(uint32_t Timeout); +void FLASH_Unlock_Fast(void); +void FLASH_Lock_Fast(void); +void FLASH_BufReset(void); +void FLASH_BufLoad(uint32_t Address, uint32_t Data0); +void FLASH_ErasePage_Fast(uint32_t Page_Address); +void FLASH_EraseBlock_32K_Fast(uint32_t Block_Address); +void FLASH_ProgramPage_Fast(uint32_t Page_Address); +FLASH_Status FLASH_ROM_ERASE(uint32_t StartAddr, uint32_t Length); +FLASH_Status FLASH_ROM_WRITE(uint32_t StartAddr, uint32_t *pbuf, uint32_t Length); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/ZDBMS/BMS_MC/Peripheral/inc/ch32l103_gpio.h b/ZDBMS/BMS_MC/Peripheral/inc/ch32l103_gpio.h new file mode 100644 index 0000000..810bf66 --- /dev/null +++ b/ZDBMS/BMS_MC/Peripheral/inc/ch32l103_gpio.h @@ -0,0 +1,178 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32l103_gpio.h + * Author : WCH + * Version : V1.0.0 + * Date : 2024/03/01 + * Description : This file contains all the functions prototypes for the + * GPIO firmware library. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#ifndef __CH32L103_GPIO_H +#define __CH32L103_GPIO_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "ch32l103.h" + +/* Output Maximum frequency selection */ +typedef enum +{ + GPIO_Speed_10MHz = 1, + GPIO_Speed_2MHz, + GPIO_Speed_50MHz +} GPIOSpeed_TypeDef; + +/* Configuration Mode enumeration */ +typedef enum +{ + GPIO_Mode_AIN = 0x0, + GPIO_Mode_IN_FLOATING = 0x04, + GPIO_Mode_IPD = 0x28, + GPIO_Mode_IPU = 0x48, + GPIO_Mode_Out_OD = 0x14, + GPIO_Mode_Out_PP = 0x10, + GPIO_Mode_AF_OD = 0x1C, + GPIO_Mode_AF_PP = 0x18 +} GPIOMode_TypeDef; + +/* GPIO Init structure definition */ +typedef struct +{ + uint16_t GPIO_Pin; /* Specifies the GPIO pins to be configured. + This parameter can be any value of @ref GPIO_pins_define */ + + GPIOSpeed_TypeDef GPIO_Speed; /* Specifies the speed for the selected pins. + This parameter can be a value of @ref GPIOSpeed_TypeDef */ + + GPIOMode_TypeDef GPIO_Mode; /* Specifies the operating mode for the selected pins. + This parameter can be a value of @ref GPIOMode_TypeDef */ +} GPIO_InitTypeDef; + +/* Bit_SET and Bit_RESET enumeration */ +typedef enum +{ + Bit_RESET = 0, + Bit_SET +} BitAction; + +/* GPIO_pins_define */ +#define GPIO_Pin_0 ((uint16_t)0x0001) /* Pin 0 selected */ +#define GPIO_Pin_1 ((uint16_t)0x0002) /* Pin 1 selected */ +#define GPIO_Pin_2 ((uint16_t)0x0004) /* Pin 2 selected */ +#define GPIO_Pin_3 ((uint16_t)0x0008) /* Pin 3 selected */ +#define GPIO_Pin_4 ((uint16_t)0x0010) /* Pin 4 selected */ +#define GPIO_Pin_5 ((uint16_t)0x0020) /* Pin 5 selected */ +#define GPIO_Pin_6 ((uint16_t)0x0040) /* Pin 6 selected */ +#define GPIO_Pin_7 ((uint16_t)0x0080) /* Pin 7 selected */ +#define GPIO_Pin_8 ((uint16_t)0x0100) /* Pin 8 selected */ +#define GPIO_Pin_9 ((uint16_t)0x0200) /* Pin 9 selected */ +#define GPIO_Pin_10 ((uint16_t)0x0400) /* Pin 10 selected */ +#define GPIO_Pin_11 ((uint16_t)0x0800) /* Pin 11 selected */ +#define GPIO_Pin_12 ((uint16_t)0x1000) /* Pin 12 selected */ +#define GPIO_Pin_13 ((uint16_t)0x2000) /* Pin 13 selected */ +#define GPIO_Pin_14 ((uint16_t)0x4000) /* Pin 14 selected */ +#define GPIO_Pin_15 ((uint16_t)0x8000) /* Pin 15 selected */ +#define GPIO_Pin_All ((uint16_t)0xFFFF) /* All pins selected */ + +/* GPIO_Remap_define */ +//bit[31:30] = 11b - PCFR1-bit[15-0] and PCFR2-bit[26:16] +/* bit[29:27] = 000b */ +#define GPIO_PartialRemap1_SPI1 ((uint32_t)0xC0000001) /* SPI1 Partial1 Alternate Function mapping */ +#define GPIO_PartialRemap2_SPI1 ((uint32_t)0xC1000000) /* SPI1 Partial2 Alternate Function mapping */ +#define GPIO_FullRemap_SPI1 ((uint32_t)0xC1000001) /* SPI1 Full Alternate Function mapping */ +/* bit[29:27] = 001b */ +#define GPIO_PartialRemap1_I2C1 ((uint32_t)0xC8800000) /* I2C1 Partial1 Alternate Function mapping */ +#define GPIO_FullRemap_I2C1 ((uint32_t)0xC8800002) /* I2C1 Full Alternate Function mapping */ +/* bit[29:27] = 010b */ +#define GPIO_PartialRemap1_USART1 ((uint32_t)0xD0000004) /* USART1 Partial1 Alternate Function mapping */ +#define GPIO_PartialRemap2_USART1 ((uint32_t)0xD0080000) /* USART1 Partial2 Alternate Function mapping */ +#define GPIO_PartialRemap3_USART1 ((uint32_t)0xD0080004) /* USART1 Partial3 Alternate Function mapping */ +#define GPIO_PartialRemap4_USART1 ((uint32_t)0xD0100000) /* USART1 Partial4 Alternate Function mapping */ +#define GPIO_FullRemap_USART1 ((uint32_t)0xD0100004) /* USART1 Full Alternate Function mapping */ +/* bit[29:27] = 011b */ +#define GPIO_PartialRemap1_USART2 ((uint32_t)0xD8000008) /* USART2 Partial1 Alternate Function mapping */ +#define GPIO_PartialRemap2_USART2 ((uint32_t)0xD8040000) /* USART2 Partial2 Alternate Function mapping */ +#define GPIO_FullRemap_USART2 ((uint32_t)0xD8040008) /* USART2 Full Alternate Function mapping */ +/* bit[29:27] = 100b */ +#define GPIO_PartialRemap1_TIM1 ((uint32_t)0xE0000040) /* TIM1 Partial1 Alternate Function mapping */ +#define GPIO_PartialRemap2_TIM1 ((uint32_t)0xE0000080) /* TIM1 Partial2 Alternate Function mapping */ +#define GPIO_PartialRemap3_TIM1 ((uint32_t)0xE00000C0) /* TIM1 Partial3 Alternate Function mapping */ +#define GPIO_PartialRemap4_TIM1 ((uint32_t)0xE0400000) /* TIM1 Partial4 Alternate Function mapping */ +#define GPIO_PartialRemap5_TIM1 ((uint32_t)0xE0400040) /* TIM1 Partial5 Alternate Function mapping */ +#define GPIO_FullRemap_TIM1 ((uint32_t)0xE04000C0) /* TIM1 Full Alternate Function mapping */ +/* bit[29:27] = 101b */ +#define GPIO_PartialRemap1_TIM2 ((uint32_t)0xE8000100) /* TIM2 Partial1 Alternate Function mapping */ +#define GPIO_PartialRemap2_TIM2 ((uint32_t)0xE8000200) /* TIM2 Partial2 Alternate Function mapping */ +#define GPIO_PartialRemap3_TIM2 ((uint32_t)0xE8000300) /* TIM2 Partial3 Alternate Function mapping */ +#define GPIO_PartialRemap4_TIM2 ((uint32_t)0xE8200000) /* TIM2 Partial4 Alternate Function mapping */ +#define GPIO_PartialRemap5_TIM2 ((uint32_t)0xE8200100) /* TIM2 Partial5 Alternate Function mapping */ +#define GPIO_FullRemap_TIM2 ((uint32_t)0xE8200300) /* TIM2 Full Alternate Function mapping */ + +//bit[31:30] = 00b - PCFR1 +#define GPIO_PartialRemap_USART3 ((uint32_t)0x00140020) /* USART3 Partial Alternate Function mapping */ +#define GPIO_FullRemap_USART3 ((uint32_t)0x00140030) /* USART3 Full Alternate Function mapping */ +#define GPIO_Remap_TIM3 ((uint32_t)0x00000400) /* TIM3 Alternate Function mapping */ +#define GPIO_Remap_TIM4 ((uint32_t)0x00001000) /* TIM4 Alternate Function mapping */ +#define GPIO_Remap1_CAN1 ((uint32_t)0x001D4000) /* CAN1 Alternate Function mapping */ +#define GPIO_Remap2_CAN1 ((uint32_t)0x001D6000) /* CAN1 Alternate Function mapping */ +#define GPIO_Remap_PD01 ((uint32_t)0x00008000) /* PD01 Alternate Function mapping */ +#define GPIO_Remap_SWJ_Disable ((uint32_t)0x00300400) /* GPIO_Remap_SWJ_Disable - Full SDI Disabled (SDI) */ + +//bit[31:30] = 01b - PCFR2 +#define GPIO_Remap_USART4 ((uint32_t)0x40000001) /* USART4 Alternate Function mapping */ +#define GPIO_Remap_LPTIM ((uint32_t)0x40000200) /* LPTIM Alternate Function mapping */ + +/* GPIO_Port_Sources */ +#define GPIO_PortSourceGPIOA ((uint8_t)0x00) +#define GPIO_PortSourceGPIOB ((uint8_t)0x01) +#define GPIO_PortSourceGPIOC ((uint8_t)0x02) +#define GPIO_PortSourceGPIOD ((uint8_t)0x03) + +/* GPIO_Pin_sources */ +#define GPIO_PinSource0 ((uint8_t)0x00) +#define GPIO_PinSource1 ((uint8_t)0x01) +#define GPIO_PinSource2 ((uint8_t)0x02) +#define GPIO_PinSource3 ((uint8_t)0x03) +#define GPIO_PinSource4 ((uint8_t)0x04) +#define GPIO_PinSource5 ((uint8_t)0x05) +#define GPIO_PinSource6 ((uint8_t)0x06) +#define GPIO_PinSource7 ((uint8_t)0x07) +#define GPIO_PinSource8 ((uint8_t)0x08) +#define GPIO_PinSource9 ((uint8_t)0x09) +#define GPIO_PinSource10 ((uint8_t)0x0A) +#define GPIO_PinSource11 ((uint8_t)0x0B) +#define GPIO_PinSource12 ((uint8_t)0x0C) +#define GPIO_PinSource13 ((uint8_t)0x0D) +#define GPIO_PinSource14 ((uint8_t)0x0E) +#define GPIO_PinSource15 ((uint8_t)0x0F) + + +void GPIO_DeInit(GPIO_TypeDef *GPIOx); +void GPIO_AFIODeInit(void); +void GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_InitStruct); +void GPIO_StructInit(GPIO_InitTypeDef *GPIO_InitStruct); +uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin); +uint16_t GPIO_ReadInputData(GPIO_TypeDef *GPIOx); +uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin); +uint16_t GPIO_ReadOutputData(GPIO_TypeDef *GPIOx); +void GPIO_SetBits(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin); +void GPIO_ResetBits(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin); +void GPIO_WriteBit(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, BitAction BitVal); +void GPIO_Write(GPIO_TypeDef *GPIOx, uint16_t PortVal); +void GPIO_PinLockConfig(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin); +void GPIO_EventOutputConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource); +void GPIO_EventOutputCmd(FunctionalState NewState); +void GPIO_PinRemapConfig(uint32_t GPIO_Remap, FunctionalState NewState); +void GPIO_EXTILineConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource); +void GPIO_IPD_Unused(void); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/ZDBMS/BMS_MC/Peripheral/inc/ch32l103_i2c.h b/ZDBMS/BMS_MC/Peripheral/inc/ch32l103_i2c.h new file mode 100644 index 0000000..6489e8e --- /dev/null +++ b/ZDBMS/BMS_MC/Peripheral/inc/ch32l103_i2c.h @@ -0,0 +1,424 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32l103_i2c.h + * Author : WCH + * Version : V1.0.0 + * Date : 2023/07/08 + * Description : This file contains all the functions prototypes for the + * I2C firmware library. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#ifndef __CH32L103_I2C_H +#define __CH32L103_I2C_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "ch32l103.h" + +/* I2C Init structure definition */ +typedef struct +{ + uint32_t I2C_ClockSpeed; /* Specifies the clock frequency. + This parameter must be set to a value lower than 400kHz */ + + uint16_t I2C_Mode; /* Specifies the I2C mode. + This parameter can be a value of @ref I2C_mode */ + + uint16_t I2C_DutyCycle; /* Specifies the I2C fast mode duty cycle. + This parameter can be a value of @ref I2C_duty_cycle_in_fast_mode */ + + uint16_t I2C_OwnAddress1; /* Specifies the first device own address. + This parameter can be a 7-bit or 10-bit address. */ + + uint16_t I2C_Ack; /* Enables or disables the acknowledgement. + This parameter can be a value of @ref I2C_acknowledgement */ + + uint16_t I2C_AcknowledgedAddress; /* Specifies if 7-bit or 10-bit address is acknowledged. + This parameter can be a value of @ref I2C_acknowledged_address */ +} I2C_InitTypeDef; + +/* I2C_mode */ +#define I2C_Mode_I2C ((uint16_t)0x0000) +#define I2C_Mode_SMBusDevice ((uint16_t)0x0002) +#define I2C_Mode_SMBusHost ((uint16_t)0x000A) + +/* I2C_duty_cycle_in_fast_mode */ +#define I2C_DutyCycle_16_9 ((uint16_t)0x4000) /* I2C fast mode Tlow/Thigh = 16/9 */ +#define I2C_DutyCycle_2 ((uint16_t)0xBFFF) /* I2C fast mode Tlow/Thigh = 2 */ + +/* I2C_acknowledgement */ +#define I2C_Ack_Enable ((uint16_t)0x0400) +#define I2C_Ack_Disable ((uint16_t)0x0000) + +/* I2C_transfer_direction */ +#define I2C_Direction_Transmitter ((uint8_t)0x00) +#define I2C_Direction_Receiver ((uint8_t)0x01) + +/* I2C_acknowledged_address */ +#define I2C_AcknowledgedAddress_7bit ((uint16_t)0x4000) +#define I2C_AcknowledgedAddress_10bit ((uint16_t)0xC000) + +/* I2C_registers */ +#define I2C_Register_CTLR1 ((uint8_t)0x00) +#define I2C_Register_CTLR2 ((uint8_t)0x04) +#define I2C_Register_OADDR1 ((uint8_t)0x08) +#define I2C_Register_OADDR2 ((uint8_t)0x0C) +#define I2C_Register_DATAR ((uint8_t)0x10) +#define I2C_Register_STAR1 ((uint8_t)0x14) +#define I2C_Register_STAR2 ((uint8_t)0x18) +#define I2C_Register_CKCFGR ((uint8_t)0x1C) +#define I2C_Register_RTR ((uint8_t)0x20) + +/* I2C_SMBus_alert_pin_level */ +#define I2C_SMBusAlert_Low ((uint16_t)0x2000) +#define I2C_SMBusAlert_High ((uint16_t)0xDFFF) + +/* I2C_PEC_position */ +#define I2C_PECPosition_Next ((uint16_t)0x0800) +#define I2C_PECPosition_Current ((uint16_t)0xF7FF) + +/* I2C_NACK_position */ +#define I2C_NACKPosition_Next ((uint16_t)0x0800) +#define I2C_NACKPosition_Current ((uint16_t)0xF7FF) + +/* I2C_interrupts_definition */ +#define I2C_IT_BUF ((uint16_t)0x0400) +#define I2C_IT_EVT ((uint16_t)0x0200) +#define I2C_IT_ERR ((uint16_t)0x0100) + +/* I2C_interrupts_definition */ +#define I2C_IT_SMBALERT ((uint32_t)0x01008000) +#define I2C_IT_TIMEOUT ((uint32_t)0x01004000) +#define I2C_IT_PECERR ((uint32_t)0x01001000) +#define I2C_IT_OVR ((uint32_t)0x01000800) +#define I2C_IT_AF ((uint32_t)0x01000400) +#define I2C_IT_ARLO ((uint32_t)0x01000200) +#define I2C_IT_BERR ((uint32_t)0x01000100) +#define I2C_IT_TXE ((uint32_t)0x06000080) +#define I2C_IT_RXNE ((uint32_t)0x06000040) +#define I2C_IT_STOPF ((uint32_t)0x02000010) +#define I2C_IT_ADD10 ((uint32_t)0x02000008) +#define I2C_IT_BTF ((uint32_t)0x02000004) +#define I2C_IT_ADDR ((uint32_t)0x02000002) +#define I2C_IT_SB ((uint32_t)0x02000001) + +/* STAR2 register flags */ +#define I2C_FLAG_DUALF ((uint32_t)0x00800000) +#define I2C_FLAG_SMBHOST ((uint32_t)0x00400000) +#define I2C_FLAG_SMBDEFAULT ((uint32_t)0x00200000) +#define I2C_FLAG_GENCALL ((uint32_t)0x00100000) +#define I2C_FLAG_TRA ((uint32_t)0x00040000) +#define I2C_FLAG_BUSY ((uint32_t)0x00020000) +#define I2C_FLAG_MSL ((uint32_t)0x00010000) + +/* STAR1 register flags */ +#define I2C_FLAG_SMBALERT ((uint32_t)0x10008000) +#define I2C_FLAG_TIMEOUT ((uint32_t)0x10004000) +#define I2C_FLAG_PECERR ((uint32_t)0x10001000) +#define I2C_FLAG_OVR ((uint32_t)0x10000800) +#define I2C_FLAG_AF ((uint32_t)0x10000400) +#define I2C_FLAG_ARLO ((uint32_t)0x10000200) +#define I2C_FLAG_BERR ((uint32_t)0x10000100) +#define I2C_FLAG_TXE ((uint32_t)0x10000080) +#define I2C_FLAG_RXNE ((uint32_t)0x10000040) +#define I2C_FLAG_STOPF ((uint32_t)0x10000010) +#define I2C_FLAG_ADD10 ((uint32_t)0x10000008) +#define I2C_FLAG_BTF ((uint32_t)0x10000004) +#define I2C_FLAG_ADDR ((uint32_t)0x10000002) +#define I2C_FLAG_SB ((uint32_t)0x10000001) + +/****************I2C Master Events (Events grouped in order of communication)********************/ + +/******************************************************************************************************************** + * @brief Start communicate + * + * After master use I2C_GenerateSTART() function sending the START condition,the master + * has to wait for event 5(the Start condition has been correctly + * released on the I2C bus ). + * + */ +/* EVT5 */ +#define I2C_EVENT_MASTER_MODE_SELECT ((uint32_t)0x00030001) /* BUSY, MSL and SB flag */ + +/******************************************************************************************************************** + * @brief Address Acknowledge + * + * When start condition correctly released on the bus(check EVT5), the + * master use I2C_Send7bitAddress() function sends the address of the slave(s) with which it will communicate + * it also determines master as transmitter or Receiver. Then the master has to wait that a slave acknowledges + * his address. If an acknowledge is sent on the bus, one of the following events will be set: + * + * 1) In case of Master Receiver (7-bit addressing): the I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED + * event is set. + * + * 2) In case of Master Transmitter (7-bit addressing): the I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED + * is set + * + * 3) In case of 10-Bit addressing mode, the master (after generating the START + * and checking on EVT5) use I2C_SendData() function send the header of 10-bit addressing mode. + * Then master wait EVT9. EVT9 means that the 10-bit addressing header has been correctly sent + * on the bus. Then master should use the function I2C_Send7bitAddress() to send the second part + * of the 10-bit address (LSB) . Then master should wait for event 6. + * + * + */ + +/* EVT6 */ +#define I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED ((uint32_t)0x00070082) /* BUSY, MSL, ADDR, TXE and TRA flags */ +#define I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED ((uint32_t)0x00030002) /* BUSY, MSL and ADDR flags */ +/* EVT9 */ +#define I2C_EVENT_MASTER_MODE_ADDRESS10 ((uint32_t)0x00030008) /* BUSY, MSL and ADD10 flags */ + +/******************************************************************************************************************** + * @brief Communication events + * + * If START condition has generated and slave address + * been acknowledged. then the master has to check one of the following events for + * communication procedures: + * + * 1) Master Receiver mode: The master has to wait on the event EVT7 then use + * I2C_ReceiveData() function to read the data received from the slave. + * + * 2) Master Transmitter mode: The master use I2C_SendData() function to send data + * then to wait on event EVT8 or EVT8_2. + * These two events are similar: + * - EVT8 means that the data has been written in the data register and is + * being shifted out. + * - EVT8_2 means that the data has been physically shifted out and output + * on the bus. + * In most cases, using EVT8 is sufficient for the application. + * Using EVT8_2 will leads to a slower communication speed but will more reliable . + * EVT8_2 is also more suitable than EVT8 for testing on the last data transmission + * + * Note: + * In case the user software does not guarantee that this event EVT7 is managed before + * the current byte end of transfer, then user may check on I2C_EVENT_MASTER_BYTE_RECEIVED + * and I2C_FLAG_BTF flag at the same time .But in this case the communication may be slower. + * + * + */ + +/* Master Receive mode */ +/* EVT7 */ +#define I2C_EVENT_MASTER_BYTE_RECEIVED ((uint32_t)0x00030040) /* BUSY, MSL and RXNE flags */ + +/* Master Transmitter mode*/ +/* EVT8 */ +#define I2C_EVENT_MASTER_BYTE_TRANSMITTING ((uint32_t)0x00070080) /* TRA, BUSY, MSL, TXE flags */ +/* EVT8_2 */ +#define I2C_EVENT_MASTER_BYTE_TRANSMITTED ((uint32_t)0x00070084) /* TRA, BUSY, MSL, TXE and BTF flags */ + +/******************I2C Slave Events (Events grouped in order of communication)******************/ + +/******************************************************************************************************************** + * @brief Start Communicate events + * + * Wait on one of these events at the start of the communication. It means that + * the I2C peripheral detected a start condition of master device generate on the bus. + * If the acknowledge feature is enabled through function I2C_AcknowledgeConfig()),The peripheral generates an ACK condition on the bus. + * + * a) In normal case (only one address managed by the slave), when the address + * sent by the master matches the own address of the peripheral (configured by + * I2C_OwnAddress1 field) the I2C_EVENT_SLAVE_XXX_ADDRESS_MATCHED event is set + * (where XXX could be TRANSMITTER or RECEIVER). + * + * b) In case the address sent by the master matches the second address of the + * peripheral (configured by the function I2C_OwnAddress2Config() and enabled + * by the function I2C_DualAddressCmd()) the events I2C_EVENT_SLAVE_XXX_SECONDADDRESS_MATCHED + * (where XXX could be TRANSMITTER or RECEIVER) are set. + * + * c) In case the address sent by the master is General Call (address 0x00) and + * if the General Call is enabled for the peripheral (using function I2C_GeneralCallCmd()) + * the following event is set I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED. + * + */ + +/* EVT1 */ +/* a) Case of One Single Address managed by the slave */ +#define I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED ((uint32_t)0x00020002) /* BUSY and ADDR flags */ +#define I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED ((uint32_t)0x00060082) /* TRA, BUSY, TXE and ADDR flags */ + +/* b) Case of Dual address managed by the slave */ +#define I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED ((uint32_t)0x00820000) /* DUALF and BUSY flags */ +#define I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED ((uint32_t)0x00860080) /* DUALF, TRA, BUSY and TXE flags */ + +/* c) Case of General Call enabled for the slave */ +#define I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED ((uint32_t)0x00120000) /* GENCALL and BUSY flags */ + +/******************************************************************************************************************** + * @brief Communication events + * + * Wait on one of these events when EVT1 has already been checked : + * + * - Slave Receiver mode: + * - EVT2--The device is expecting to receive a data byte . + * - EVT4--The device is expecting the end of the communication: master + * sends a stop condition and data transmission is stopped. + * + * - Slave Transmitter mode: + * - EVT3--When a byte has been transmitted by the slave and the Master is expecting + * the end of the byte transmission. The two events I2C_EVENT_SLAVE_BYTE_TRANSMITTED and + * I2C_EVENT_SLAVE_BYTE_TRANSMITTING are similar. If the user software doesn't guarantee + * the EVT3 is managed before the current byte end of transfer The second one can optionally + * be used. + * - EVT3_2--When the master sends a NACK to tell slave device that data transmission + * shall end . The slave device has to stop sending + * data bytes and wait a Stop condition from bus. + * + * Note: + * If the user software does not guarantee that the event 2 is + * managed before the current byte end of transfer, User may check on I2C_EVENT_SLAVE_BYTE_RECEIVED + * and I2C_FLAG_BTF flag at the same time . + * In this case the communication will be slower. + * + */ + +/* Slave Receiver mode*/ +/* EVT2 */ +#define I2C_EVENT_SLAVE_BYTE_RECEIVED ((uint32_t)0x00020040) /* BUSY and RXNE flags */ +/* EVT4 */ +#define I2C_EVENT_SLAVE_STOP_DETECTED ((uint32_t)0x00000010) /* STOPF flag */ + +/* Slave Transmitter mode*/ +/* EVT3 */ +#define I2C_EVENT_SLAVE_BYTE_TRANSMITTED ((uint32_t)0x00060084) /* TRA, BUSY, TXE and BTF flags */ +#define I2C_EVENT_SLAVE_BYTE_TRANSMITTING ((uint32_t)0x00060080) /* TRA, BUSY and TXE flags */ +/* EVT3_2 */ +#define I2C_EVENT_SLAVE_ACK_FAILURE ((uint32_t)0x00000400) /* AF flag */ + + +void I2C_DeInit(I2C_TypeDef *I2Cx); +void I2C_Init(I2C_TypeDef *I2Cx, I2C_InitTypeDef *I2C_InitStruct); +void I2C_StructInit(I2C_InitTypeDef *I2C_InitStruct); +void I2C_Cmd(I2C_TypeDef *I2Cx, FunctionalState NewState); +void I2C_DMACmd(I2C_TypeDef *I2Cx, FunctionalState NewState); +void I2C_DMALastTransferCmd(I2C_TypeDef *I2Cx, FunctionalState NewState); +void I2C_GenerateSTART(I2C_TypeDef *I2Cx, FunctionalState NewState); +void I2C_GenerateSTOP(I2C_TypeDef *I2Cx, FunctionalState NewState); +void I2C_AcknowledgeConfig(I2C_TypeDef *I2Cx, FunctionalState NewState); +void I2C_OwnAddress2Config(I2C_TypeDef *I2Cx, uint8_t Address); +void I2C_DualAddressCmd(I2C_TypeDef *I2Cx, FunctionalState NewState); +void I2C_GeneralCallCmd(I2C_TypeDef *I2Cx, FunctionalState NewState); +void I2C_ITConfig(I2C_TypeDef *I2Cx, uint16_t I2C_IT, FunctionalState NewState); +void I2C_SendData(I2C_TypeDef *I2Cx, uint8_t Data); +uint8_t I2C_ReceiveData(I2C_TypeDef *I2Cx); +void I2C_Send7bitAddress(I2C_TypeDef *I2Cx, uint8_t Address, uint8_t I2C_Direction); +uint16_t I2C_ReadRegister(I2C_TypeDef *I2Cx, uint8_t I2C_Register); +void I2C_SoftwareResetCmd(I2C_TypeDef *I2Cx, FunctionalState NewState); +void I2C_NACKPositionConfig(I2C_TypeDef *I2Cx, uint16_t I2C_NACKPosition); +void I2C_SMBusAlertConfig(I2C_TypeDef *I2Cx, uint16_t I2C_SMBusAlert); +void I2C_TransmitPEC(I2C_TypeDef *I2Cx, FunctionalState NewState); +void I2C_PECPositionConfig(I2C_TypeDef *I2Cx, uint16_t I2C_PECPosition); +void I2C_CalculatePEC(I2C_TypeDef *I2Cx, FunctionalState NewState); +uint8_t I2C_GetPEC(I2C_TypeDef *I2Cx); +void I2C_ARPCmd(I2C_TypeDef *I2Cx, FunctionalState NewState); +void I2C_StretchClockCmd(I2C_TypeDef *I2Cx, FunctionalState NewState); +void I2C_FastModeDutyCycleConfig(I2C_TypeDef *I2Cx, uint16_t I2C_DutyCycle); + + +/***************************************************************************************** + * + * I2C State Monitoring Functions + * + **************************************************************************************** + * This I2C driver provides three different ways for I2C state monitoring + * profit the application requirements and constraints: + * + * + * a) First way: + * Using I2C_CheckEvent() function: + * It compares the status registers (STARR1 and STAR2) content to a given event + * (can be the combination of more flags). + * If the current status registers includes the given flags will return SUCCESS. + * and if the current status registers miss flags will returns ERROR. + * - When to use: + * - This function is suitable for most applications as well as for startup + * activity since the events are fully described in the product reference manual + * (CH32FV2x-V3xRM). + * - It is also suitable for users who need to define their own events. + * - Limitations: + * - If an error occurs besides to the monitored error, + * the I2C_CheckEvent() function may return SUCCESS despite the communication + * in corrupted state. it is suggeted to use error interrupts to monitor the error + * events and handle them in IRQ handler. + * + * + * Note: + * The following functions are recommended for error management: : + * - I2C_ITConfig() main function of configure and enable the error interrupts. + * - I2Cx_ER_IRQHandler() will be called when the error interrupt happen. + * Where x is the peripheral instance (I2C1, I2C2 ...) + * - I2Cx_ER_IRQHandler() will call I2C_GetFlagStatus() or I2C_GetITStatus() functions + * to determine which error occurred. + * - I2C_ClearFlag() \ I2C_ClearITPendingBit() \ I2C_SoftwareResetCmd() + * \ I2C_GenerateStop() will be use to clear the error flag and source, + * and return to correct communication status. + * + * + * b) Second way: + * Using the function to get a single word(uint32_t) composed of status register 1 and register 2. + * (Status Register 2 value is shifted left by 16 bits and concatenated to Status Register 1). + * - When to use: + * + * - This function is suitable for the same applications above but it + * don't have the limitations of I2C_GetFlagStatus() function . + * The returned value could be compared to events already defined in the + * library (CH32L103_i2c.h) or to custom values defined by user. + * - This function can be used to monitor the status of multiple flags simultaneously. + * - Contrary to the I2C_CheckEvent () function, this function can choose the time to + * accept the event according to the user's needs (when all event flags are set and + * no other flags are set, or only when the required flags are set) + * + * - Limitations: + * - User may need to define his own events. + * - Same remark concerning the error management is applicable for this + * function if user decides to check only regular communication flags (and + * ignores error flags). + * + * + * c) Third way: + * Using the function I2C_GetFlagStatus() get the status of + * one single flag . + * - When to use: + * - This function could be used for specific applications or in debug phase. + * - It is suitable when only one flag checking is needed . + * + * - Limitations: + * - Call this function to access the status register. Some flag bits may be cleared. + * - Function may need to be called twice or more in order to monitor one single event. + */ + + + +/********************************************************* + * + * a) Basic state monitoring(First way) + ******************************************************** + */ +ErrorStatus I2C_CheckEvent(I2C_TypeDef* I2Cx, uint32_t I2C_EVENT); +/********************************************************* + * + * b) Advanced state monitoring(Second way) + ******************************************************** + */ +uint32_t I2C_GetLastEvent(I2C_TypeDef* I2Cx); +/********************************************************* + * + * c) Flag-based state monitoring(Third way) + ********************************************************* + */ +FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG); + +void I2C_ClearFlag(I2C_TypeDef *I2Cx, uint32_t I2C_FLAG); +ITStatus I2C_GetITStatus(I2C_TypeDef *I2Cx, uint32_t I2C_IT); +void I2C_ClearITPendingBit(I2C_TypeDef *I2Cx, uint32_t I2C_IT); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/ZDBMS/BMS_MC/Peripheral/inc/ch32l103_iwdg.h b/ZDBMS/BMS_MC/Peripheral/inc/ch32l103_iwdg.h new file mode 100644 index 0000000..b72715d --- /dev/null +++ b/ZDBMS/BMS_MC/Peripheral/inc/ch32l103_iwdg.h @@ -0,0 +1,50 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32l103_iwdg.h + * Author : WCH + * Version : V1.0.0 + * Date : 2023/07/08 + * Description : This file contains all the functions prototypes for the + * IWDG firmware library. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#ifndef __CH32L103_IWDG_H +#define __CH32L103_IWDG_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "ch32l103.h" + +/* IWDG_WriteAccess */ +#define IWDG_WriteAccess_Enable ((uint16_t)0x5555) +#define IWDG_WriteAccess_Disable ((uint16_t)0x0000) + +/* IWDG_prescaler */ +#define IWDG_Prescaler_4 ((uint8_t)0x00) +#define IWDG_Prescaler_8 ((uint8_t)0x01) +#define IWDG_Prescaler_16 ((uint8_t)0x02) +#define IWDG_Prescaler_32 ((uint8_t)0x03) +#define IWDG_Prescaler_64 ((uint8_t)0x04) +#define IWDG_Prescaler_128 ((uint8_t)0x05) +#define IWDG_Prescaler_256 ((uint8_t)0x06) + +/* IWDG_Flag */ +#define IWDG_FLAG_PVU ((uint16_t)0x0001) +#define IWDG_FLAG_RVU ((uint16_t)0x0002) + +void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess); +void IWDG_SetPrescaler(uint8_t IWDG_Prescaler); +void IWDG_SetReload(uint16_t Reload); +void IWDG_ReloadCounter(void); +void IWDG_Enable(void); +FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/ZDBMS/BMS_MC/Peripheral/inc/ch32l103_lptim.h b/ZDBMS/BMS_MC/Peripheral/inc/ch32l103_lptim.h new file mode 100644 index 0000000..5f4a1ad --- /dev/null +++ b/ZDBMS/BMS_MC/Peripheral/inc/ch32l103_lptim.h @@ -0,0 +1,200 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32l103_lptim.h + * Author : WCH + * Version : V1.0.0 + * Date : 2024/07/15 + * Description : This file contains all the functions prototypes for the + * TIM firmware library. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#ifndef __CH32L103_LPTIM_H +#define __CH32L103_LPTIM_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "ch32l103.h" + +typedef struct +{ + uint32_t LPTIM_ClockSource; /* Selects the clock source. + This parameter can be a value of @ref LPTIM_Clock_Source */ + + union{ + uint32_t LPTIM_ClockPolarity; /* Configures Clock Polarity(No Encoder mode). + This parameter can be a value of @ref LPTIM_ClockPolarity */ + + uint32_t LPTIM_EncoderMode; /* Configures Encoder mode. + This parameter can be a value of @ref LPTIM_EncoderMode */ + }; + + uint32_t LPTIM_ClockSampleTime; /* Configures Clock Sample Time. + This parameter can be a value of @ref LPTIM_ClockSampleTime */ + + uint32_t LPTIM_TriggerSampleTime; /* Configures Trigger Sample Time. + This parameter can be a value of @ref LPTIM_TriggerSampleTime */ + + uint32_t LPTIM_ClockPrescaler; /* Configures the clock Prescaler. + This parameter can be a value of @ref LPTIM_ClockPrescaler */ + + uint32_t LPTIM_TriggerSource; /* Configures trigger source. + This parameter can be a value of @ref LPTIM_TriggerSource */ + + uint32_t LPTIM_ExTriggerPolarity; /* Configures external trigger polarity. + This parameter can be a value of @ref LPTIM_ExTriggerPolarity */ + + FunctionalState LPTIM_TimeOut; /* Specifies whether the time out function. + This parameter can be set to ENABLE or DISABLE */ + + FunctionalState LPTIM_OnePulseMode; /* Specifies whether the PWM out one pulse. + This parameter can be set to ENABLE or DISABLE */ + + uint32_t LPTIM_OutputPolarity; /* Configures output polarity. + This parameter can be a value of @ref LPTIM_OutputPolarity */ + + uint32_t LPTIM_UpdateMode; /* Configures update mode. + This parameter can be a value of @ref LPTIM_UpdateMode */ + + uint32_t LPTIM_CountSource; /* Configures Counter Source. + This parameter can be a value of @ref LPTIM_CountSource */ + + FunctionalState LPTIM_Encoder; /* Specifies whether open Encoder function. + This parameter can be set to ENABLE or DISABLE */ + + uint32_t LPTIM_InClockSource; /* Specifies Internal clock source. + This parameter can be a value of @ref LPTIM_InClockSource */ + + FunctionalState LPTIM_ForceOutHigh; /* Specifies whether the PWM out high level. + This parameter can be set to ENABLE or DISABLE */ + + FunctionalState LPTIM_SingleMode; /* Specifies whether single mode. + This parameter can be set to ENABLE or DISABLE */ + + FunctionalState LPTIM_ContinuousMode; /* Specifies whether continuous mode. + This parameter can be set to ENABLE or DISABLE */ + + FunctionalState LPTIM_PWMOut; /* Specifies whether PWM out function. + This parameter can be set to ENABLE or DISABLE */ + + FunctionalState LPTIM_CounterDirIndicat; /* Specifies whether counter direction indicate function. + This parameter can be set to ENABLE or DISABLE */ + + uint16_t LPTIM_Pulse; /* Specifies the pulse value to be loaded into the Capture Compare Register. + This parameter can be a number between 0x0000 and 0xFFFF */ + + uint16_t LPTIM_Period; /* Specifies the period value to be loaded into the active + This parameter must be a number between 0x0000 and 0xFFFF. */ +} LPTIM_TimeBaseInitTypeDef; + + +/* LPTIM_Clock_Source */ +#define LPTIM_ClockSource_In ((uint32_t)0x00000000) +#define LPTIM_ClockSource_Ex ((uint32_t)0x00000001) + +/* LPTIM_ClockPolarity */ +#define LPTIM_ClockPolarity_Rising ((uint32_t)0x00000000) +#define LPTIM_ClockPolarity_Falling ((uint32_t)0x00000002) +#define LPTIM_ClockPolarity_Rising_Falling ((uint32_t)0x00000004) + +/* LPTIM_ClockPrescalerTime */ +#define LPTIM_ClockSampleTime_0T ((uint32_t)0x00000000) +#define LPTIM_ClockSampleTime_2T ((uint32_t)0x00000008) +#define LPTIM_ClockSampleTime_4T ((uint32_t)0x00000010) +#define LPTIM_ClockSampleTime_8T ((uint32_t)0x00000018) + +/* LPTIM_TriggerSampleTime */ +#define LPTIM_TriggerSampleTime_0T ((uint32_t)0x00000000) +#define LPTIM_TriggerSampleTime_2T ((uint32_t)0x00000040) +#define LPTIM_TriggerSampleTime_4T ((uint32_t)0x00000080) +#define LPTIM_TriggerSampleTime_8T ((uint32_t)0x000000C0) + +/* LPTIM_ClockPrescaler */ +#define LPTIM_TClockPrescaler_DIV1 ((uint32_t)0x00000000) +#define LPTIM_TClockPrescaler_DIV2 ((uint32_t)0x00000200) +#define LPTIM_TClockPrescaler_DIV4 ((uint32_t)0x00000400) +#define LPTIM_TClockPrescaler_DIV8 ((uint32_t)0x00000600) +#define LPTIM_TClockPrescaler_DIV16 ((uint32_t)0x00000800) +#define LPTIM_TClockPrescaler_DIV32 ((uint32_t)0x00000A00) +#define LPTIM_TClockPrescaler_DIV64 ((uint32_t)0x00000C00) +#define LPTIM_TClockPrescaler_DIV128 ((uint32_t)0x00000E00) + +/* LPTIM_TriggerSource */ +#define LPTIM_TriggerSource_ETR ((uint32_t)0x00000000) +#define LPTIM_TriggerSource_RTC_ALARM ((uint32_t)0x00002000) +#define LPTIM_TriggerSource_TAMP ((uint32_t)0x00004000) + +/* LPTIM_ExTriggerPolarity */ +#define LPTIM_ExTriggerPolarity_Disable ((uint32_t)0x00000000) +#define LPTIM_ExTriggerPolarity_Rising ((uint32_t)0x00020000) +#define LPTIM_ExTriggerPolarity_Falling ((uint32_t)0x00040000) +#define LPTIM_ExTriggerPolarity_Rising_Falling ((uint32_t)0x00060000) + +/* LPTIM_OutputPolarity */ +#define LPTIM_OutputPolarity_High ((uint32_t)0x00000000) +#define LPTIM_OutputPolarity_Low ((uint32_t)0x00200000) + +/* LPTIM_UpdateMode */ +#define LPTIM_UpdateMode0 ((uint32_t)0x00000000) +#define LPTIM_UpdateMode1 ((uint32_t)0x00400000) + +/* LPTIM_CountSource */ +#define LPTIM_CountSource_Internal ((uint32_t)0x00000000) +#define LPTIM_CountSource_External ((uint32_t)0x00800000) + +/* LPTIM_InClockSource */ +#define LPTIM_InClockSource_PCLK1 ((uint32_t)0x00000000) +#define LPTIM_InClockSource_HSI ((uint32_t)0x02000000) +#define LPTIM_InClockSource_LSE ((uint32_t)0x04000000) +#define LPTIM_InClockSource_LSI ((uint32_t)0x06000000) + +/* LPTIM_Flag_Definition */ +#define LPTIM_FLAG_DIR_SYNC ((uint32_t)0x00000080) +#define LPTIM_FLAG_DOWN ((uint32_t)0x00000040) +#define LPTIM_FLAG_UP ((uint32_t)0x00000020) +#define LPTIM_FLAG_ARROK ((uint32_t)0x00000010) +#define LPTIM_FLAG_CMPOK ((uint32_t)0x00000008) +#define LPTIM_FLAG_EXTTRIG ((uint32_t)0x00000004) +#define LPTIM_FLAG_ARRM ((uint32_t)0x00000002) +#define LPTIM_FLAG_CMPM ((uint32_t)0x00000001) + +/* LPTIM_Interrupts_Definition */ +#define LPTIM_IT_DOWN ((uint32_t)0x00000040) +#define LPTIM_IT_UP ((uint32_t)0x00000020) +#define LPTIM_IT_ARROK ((uint32_t)0x00000010) +#define LPTIM_IT_CMPOK ((uint32_t)0x00000008) +#define LPTIM_IT_EXTTRIG ((uint32_t)0x00000004) +#define LPTIM_IT_ARRM ((uint32_t)0x00000002) +#define LPTIM_IT_CMPM ((uint32_t)0x00000001) + + +#define LPYIM_OutputPolarity_High LPTIM_OutputPolarity_High +#define LPYIM_OutputPolarity_Low LPTIM_OutputPolarity_Low +#define LPYIM_UpdateMode0 LPTIM_UpdateMode0 +#define LPYIM_UpdateMode1 LPTIM_UpdateMode1 + + +void LPTIM_DeInit(void); +void LPTIM_TimeBaseInit(LPTIM_TimeBaseInitTypeDef* LPTIM_TimeBaseInitStruct); +void LPTIM_TimeBaseStructInit(LPTIM_TimeBaseInitTypeDef* LPTIM_TimeBaseInitStruct); +void LPTIM_CounterDirIndicat_Cmd(FunctionalState NewState); +void LPTIM_OutCmd(FunctionalState NewState); +void LPTIM_Cmd(FunctionalState NewState); +uint16_t LPTIM_GetCounter(void); +void LPTIM_SetAutoreload(uint16_t Autoreload); +void LPTIM_SetCompare(uint16_t Compare); +void LPTIM_ITConfig(uint32_t LPTIM_IT, FunctionalState NewState); +FlagStatus LPTIM_GetFlagStatus(uint32_t LPTIM_FLAG); +void LPTIM_ClearFlag(uint32_t LPTIM_FLAG); +ITStatus LPTIM_GetITStatus(uint32_t LPTIM_IT); +void LPTIM_ClearITPendingBit(uint32_t LPTIM_IT); + + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/ZDBMS/BMS_MC/Peripheral/inc/ch32l103_misc.h b/ZDBMS/BMS_MC/Peripheral/inc/ch32l103_misc.h new file mode 100644 index 0000000..15cd9f9 --- /dev/null +++ b/ZDBMS/BMS_MC/Peripheral/inc/ch32l103_misc.h @@ -0,0 +1,72 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32l103_misc.h + * Author : WCH + * Version : V1.0.0 + * Date : 2023/12/26 + * Description : This file contains all the functions prototypes for the + * miscellaneous firmware library functions. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#ifndef __CH32L103_MISC_H +#define __CH32L103_MISC_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "ch32l103.h" + +/* CSR_INTSYSCR_INEST_definition */ +#define INTSYSCR_INEST_NoEN 0x00 /* interrupt nesting disable(CSR-0x804 bit1 = 0) */ +#define INTSYSCR_INEST_EN 0x01 /* interrupt nesting enable(CSR-0x804 bit1 = 1) */ + +/* Check the configuration of CSR(0x804) in the startup file(.S) + * interrupt nesting enable(CSR-0x804 bit1 = 1) + * priority - bit[7] - Preemption Priority + * bit[6:5] - Sub priority + * bit[4:0] - Reserve + * interrupt nesting disable(CSR-0x804 bit1 = 0) + * priority - bit[7:5] - Sub priority + * bit[4:0] - Reserve + */ + +#ifndef INTSYSCR_INEST +#define INTSYSCR_INEST INTSYSCR_INEST_EN +#endif + +/* NVIC Init Structure definition + * interrupt nesting enable(CSR-0x804 bit1 = 1) + * NVIC_IRQChannelPreemptionPriority - range from 0 to 1. + * NVIC_IRQChannelSubPriority - range from 0 to 3. + * + * interrupt nesting disable(CSR-0x804 bit1 = 0) + * NVIC_IRQChannelPreemptionPriority - range is 0. + * NVIC_IRQChannelSubPriority - range from 0 to 7. + * + */ +typedef struct +{ + uint8_t NVIC_IRQChannel; + uint8_t NVIC_IRQChannelPreemptionPriority; + uint8_t NVIC_IRQChannelSubPriority; + FunctionalState NVIC_IRQChannelCmd; +} NVIC_InitTypeDef; + +/* Preemption_Priority_Group */ +#if (INTSYSCR_INEST == INTSYSCR_INEST_NoEN) +#define NVIC_PriorityGroup_0 ((uint32_t)0x00) /* interrupt nesting disable(CSR-0x804 bit1 = 0) */ +#else +#define NVIC_PriorityGroup_1 ((uint32_t)0x01) /* interrupt nesting enable(CSR-0x804 bit1 = 1) */ +#endif + +void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup); +void NVIC_Init(NVIC_InitTypeDef *NVIC_InitStruct); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/ZDBMS/BMS_MC/Peripheral/inc/ch32l103_opa.h b/ZDBMS/BMS_MC/Peripheral/inc/ch32l103_opa.h new file mode 100644 index 0000000..93a5901 --- /dev/null +++ b/ZDBMS/BMS_MC/Peripheral/inc/ch32l103_opa.h @@ -0,0 +1,243 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32l103_opa.h + * Author : WCH + * Version : V1.0.0 + * Date : 2024/11/05 + * Description : This file contains all the functions prototypes for the + * OPA firmware library. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#ifndef __CH32L103_OPA_H +#define __CH32L103_OPA_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "ch32l103.h" + +/* OPA_member_enumeration */ +typedef enum +{ + OPA1 = 0, +} OPA_Num_TypeDef; + +/* OPA_out_channel_enumeration */ +typedef enum +{ + OUT_IO_OUT0 = 0, /* PA3 */ + OUT_IO_OUT1, /* PB1 */ + OUT_IO_OUT2, /* PA2 */ + OUT_IO_OUT3, /* PA4 */ + OUT_IO_OUT4, /* PB0 */ + OUT_IO_OFF +} OPA_Mode_TypeDef; + +/* OPA_PSEL_enumeration */ +typedef enum +{ + CHP0 = 0, /* PB15 */ + CHP1, /* PB0 */ + CHP2, /* PB14 */ + CHP3, /* PA7 */ + CHP4, /* PA0 */ + CHP5, /* PA6 */ + CHP_OFF +} OPA_PSEL_TypeDef; + +/* OPA_FB_enumeration */ +typedef enum +{ + FB_OFF = 0, + FB_ON +} OPA_FB_TypeDef; + +/* OPA_NSEL_enumeration */ +typedef enum +{ + CHN0 = 0, /* PB11 */ + CHN1, /* PA6 */ + CHN2, /* PB10 */ + CHN3, /* PA5 */ + CHN4, /* PA1 */ + CHN5, /* PA7 */ + CHN2_PGA_32xIN, /* PB10 */ + CHN_PGA_8xIN, + CHN_PGA_16xIN, + CHN_PGA_32xIN, + CHN_PGA_64xIN, + CHN_OFF = 0xF +} OPA_NSEL_TypeDef; + +/* OPA_PSEL_POLL_enumeration */ +typedef enum +{ + CHP_OPA1_OFF = 0, + CHP_OPA1_ON, +} OPA_PSEL_POLL_TypeDef; + +/* OPA_BKIN_EN_enumeration */ +typedef enum +{ + BKIN_OPA1_OFF = 0, /* TIM1 braking signal source form IO input */ + BKIN_OPA1_ON, /* TIM1 braking signal source form OPA output */ +} OPA_BKIN_EN_TypeDef; + +/* OPA_RST_EN_enumeration */ +typedef enum +{ + RST_OPA1_OFF = 0, + RST_OPA1_ON, +} OPA_RST_EN_TypeDef; + +/* OPA_OUT_IE_enumeration */ +typedef enum +{ + OUT_IE_OPA1_OFF = 0, + OUT_IE_OPA1_ON, +} OPA_OUT_IE_TypeDef; + +/* OPA_CNT_IE_enumeration */ +typedef enum +{ + CNT_IE_OFF = 0, + CNT_IE_ON, +} OPA_CNT_IE_TypeDef; + +/* OPA_NMI_IE_enumeration */ +typedef enum +{ + NMI_IE_OFF = 0, + NMI_IE_ON, +} OPA_NMI_IE_TypeDef; + +/* OPA_PSEL_POLL_NUM_enumeration */ +typedef enum +{ + CHP_POLL_NUM_1 = 0, + CHP_POLL_NUM_2, + CHP_POLL_NUM_3, + CHP_POLL_NUM_4, + CHP_POLL_NUM_5, + CHP_POLL_NUM_6 +} OPA_PSEL_POLL_NUM_TypeDef; + +/* Offset_voltage_adjustment_value_polarity */ +typedef enum +{ + OPA_Vos_Ads_N = 0, + OPA_Vos_Ads_P +} OPA_Vos_ADS_POLARITY_TypeDef; + +/* OPA Init Structure definition */ +typedef struct +{ + uint16_t OPA_POLL_Interval; /* OPA polling interval = (OPA_POLL_Interval+1)*1us + This parameter must range from 0 to 0x1FF.*/ + OPA_Num_TypeDef OPA_NUM; /* Specifies the members of OPA */ + OPA_Mode_TypeDef Mode; /* Specifies the mode of OPA */ + OPA_PSEL_TypeDef PSEL; /* Specifies the positive channel of OPA */ + OPA_FB_TypeDef FB; /* Specifies the internal feedback resistor of OPA */ + OPA_NSEL_TypeDef NSEL; /* Specifies the negative channel of OPA */ + OPA_PSEL_POLL_TypeDef PSEL_POLL; /* Specifies the positive channel poll of OPA */ + OPA_BKIN_EN_TypeDef BKIN_EN; /* Specifies the brake input source of OPA */ + OPA_RST_EN_TypeDef RST_EN; /* Specifies the reset source of OPA */ + OPA_OUT_IE_TypeDef OUT_IE; /* Specifies the out interrupt of OPA */ + OPA_CNT_IE_TypeDef CNT_IE; /* Specifies the out interrupt rising edge of sampling data */ + OPA_NMI_IE_TypeDef NMI_IE; /* Specifies the out NIM interrupt of OPA */ + OPA_PSEL_POLL_NUM_TypeDef POLL_NUM; /* Specifies the number of forward inputs*/ +} OPA_InitTypeDef; + +/* CMP_member_enumeration */ +typedef enum +{ + CMP1 = 0, + CMP2, + CMP3 +} CMP_Num_TypeDef; + +/* CMP_out_channel_enumeration */ +typedef enum +{ + OUT_IO0 = 0, + OUT_IO1, + OUT_IO_TIM2 +} CMP_Mode_TypeDef; + +/* CMP_NSEL_enumeration */ +typedef enum +{ + CMP_CHN0 = 0, + CMP_CHN1, +} CMP_NSEL_TypeDef; + +/* CMP_PSEL_enumeration */ +typedef enum +{ + CMP_CHP_0 = 0, + CMP_CHP_1, +} CMP_PSEL_TypeDef; + +#define CMP_CHP1 CMP_CHP_0 +#define CMP_CHP2 CMP_CHP_1 + +/* CMP_HYEN_enumeration */ +typedef enum +{ + CMP_HYEN0 = 0, + CMP_HYEN1, +} CMP_HYEN_TypeDef; + +/* CMP Init Structure definition */ +typedef struct +{ + CMP_Num_TypeDef CMP_NUM; /* Specifies the members of CMP */ + CMP_Mode_TypeDef Mode; /* Specifies the mode of CMP */ + CMP_NSEL_TypeDef NSEL; /* Specifies the negative channel of CMP */ + CMP_PSEL_TypeDef PSEL; /* Specifies the positive channel of CMP */ + CMP_HYEN_TypeDef HYEN; /* Specifies the hysteresis comparator of CMP */ +} CMP_InitTypeDef; + +/* Current channel for OPA polling enumeration */ +typedef enum +{ + O1P0 = 0, + O1P1, + O1P2, + O1P3, + O1P4, + O1P5, +} OPA_POLL_NUM_TypeDef; + +/* OPA_flags_definition */ +#define OPA_FLAG_OUT_OPA1 ((uint16_t)0x1000) +#define OPA_FLAG_OUT_CNT ((uint16_t)0x4000) + +/* CMP_WakeUp_IO_mode_definition */ +#define CMP_WakeUp_Rising_Falling ((uint32_t)0x01000000) +#define CMP_WakeUp_Rising ((uint32_t)0x02000000) +#define CMP_WakeUp_Falling ((uint32_t)0x03000000) + +void OPCM_Unlock(void); +void OPCM_Lock(void); +void OPA_Init(OPA_InitTypeDef *OPA_InitStruct); +void OPA_StructInit(OPA_InitTypeDef *OPA_InitStruct); +void OPA_Cmd(OPA_Num_TypeDef OPA_NUM, FunctionalState NewState); +void OPA_LP_Cmd(FunctionalState NewState); +void OPA_CMP_Init(CMP_InitTypeDef *CMP_InitStruct); +void OPA_CMP_StructInit(CMP_InitTypeDef *CMP_InitStruct); +void OPA_CMP_Cmd(CMP_Num_TypeDef CMP_NUM, FunctionalState NewState); +void OPA_CMP_LP_Cmd(CMP_Num_TypeDef CMP_NUM, FunctionalState NewState); +void OPA_CMP_WakeUp_ModeConfig(uint32_t CMP_WakeUP_Mode); +FlagStatus OPA_GetFlagStatus( uint16_t OPA_FLAG); +void OPA_ClearFlag(uint16_t OPA_FLAG); +OPA_POLL_NUM_TypeDef OPA_POLL_CNT(void); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/ZDBMS/BMS_MC/Peripheral/inc/ch32l103_pwr.h b/ZDBMS/BMS_MC/Peripheral/inc/ch32l103_pwr.h new file mode 100644 index 0000000..2607430 --- /dev/null +++ b/ZDBMS/BMS_MC/Peripheral/inc/ch32l103_pwr.h @@ -0,0 +1,68 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32l103_pwr.h + * Author : WCH + * Version : V1.0.0 + * Date : 2023/07/08 + * Description : This file contains all the functions prototypes for the PWR + * firmware library. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#ifndef __CH32L103_PWR_H +#define __CH32L103_PWR_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "ch32l103.h" + +/* PVD_detection_level */ +#define PWR_PVDLevel_0 ((uint32_t)0x00000000) +#define PWR_PVDLevel_1 ((uint32_t)0x00000020) +#define PWR_PVDLevel_2 ((uint32_t)0x00000040) +#define PWR_PVDLevel_3 ((uint32_t)0x00000060) +#define PWR_PVDLevel_4 ((uint32_t)0x00000080) +#define PWR_PVDLevel_5 ((uint32_t)0x000000A0) +#define PWR_PVDLevel_6 ((uint32_t)0x000000C0) +#define PWR_PVDLevel_7 ((uint32_t)0x000000E0) + +/* Regulator_state_is_STOP_mode */ +#define PWR_Regulator_ON ((uint32_t)0x00000000) +#define PWR_Regulator_LowPower ((uint32_t)0x00000001) + +/* STOP_mode_entry */ +#define PWR_STOPEntry_WFI ((uint8_t)0x01) +#define PWR_STOPEntry_WFE ((uint8_t)0x02) + +/* PWR_Flag */ +#define PWR_FLAG_WU ((uint32_t)0x00000001) +#define PWR_FLAG_SB ((uint32_t)0x00000002) +#define PWR_FLAG_PVDO ((uint32_t)0x00000004) + +void PWR_DeInit(void); +void PWR_BackupAccessCmd(FunctionalState NewState); +void PWR_PVDCmd(FunctionalState NewState); +void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel); +void PWR_WakeUpPinCmd(FunctionalState NewState); +void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry); +void PWR_EnterSTANDBYMode(void); +FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG); +void PWR_ClearFlag(uint32_t PWR_FLAG); +void PWR_EnterSTANDBYMode_RAM(void); +void PWR_EnterSTANDBYMode_RAM_LV(void); +void PWR_EnterSTANDBYMode_RAM_VBAT_EN(void); +void PWR_EnterSTANDBYMode_RAM_LV_VBAT_EN(void); +void PWR_EnterSTOPMode_RAM_LV(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry); +void PWR_LDO_LP_Cmd(FunctionalState NewState); +void PWR_STOPMode_Auto_LDO_LP_Cmd(FunctionalState NewState); +void PWR_FLASH_LP_Cmd(FunctionalState NewState); + + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/ZDBMS/BMS_MC/Peripheral/inc/ch32l103_rcc.h b/ZDBMS/BMS_MC/Peripheral/inc/ch32l103_rcc.h new file mode 100644 index 0000000..150e4f5 --- /dev/null +++ b/ZDBMS/BMS_MC/Peripheral/inc/ch32l103_rcc.h @@ -0,0 +1,220 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32l103_rcc.h + * Author : WCH + * Version : V1.0.0 + * Date : 2023/07/08 + * Description : This file provides all the RCC firmware functions. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#ifndef __CH32L103_RCC_H +#define __CH32L103_RCC_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "ch32l103.h" + +/* RCC_Exported_Types */ +typedef struct +{ + uint32_t SYSCLK_Frequency; /* returns SYSCLK clock frequency expressed in Hz */ + uint32_t HCLK_Frequency; /* returns HCLK clock frequency expressed in Hz */ + uint32_t PCLK1_Frequency; /* returns PCLK1 clock frequency expressed in Hz */ + uint32_t PCLK2_Frequency; /* returns PCLK2 clock frequency expressed in Hz */ + uint32_t ADCCLK_Frequency; /* returns ADCCLK clock frequency expressed in Hz */ +} RCC_ClocksTypeDef; + +/* HSE_configuration */ +#define RCC_HSE_OFF ((uint32_t)0x00000000) +#define RCC_HSE_ON ((uint32_t)0x00010000) +#define RCC_HSE_Bypass ((uint32_t)0x00040000) + +/* PLL_entry_clock_source */ +#define RCC_PLLSource_HSI_Div2 ((uint32_t)0x00000000) +#define RCC_PLLSource_HSE_Div1 ((uint32_t)0x00010000) +#define RCC_PLLSource_HSE_Div2 ((uint32_t)0x00030000) + +/* PLL_multiplication_factor for other CH32L103 */ +#define RCC_PLLMul_2 ((uint32_t)0x00000000) +#define RCC_PLLMul_3 ((uint32_t)0x00040000) +#define RCC_PLLMul_4 ((uint32_t)0x00080000) +#define RCC_PLLMul_5 ((uint32_t)0x000C0000) +#define RCC_PLLMul_6 ((uint32_t)0x00100000) +#define RCC_PLLMul_7 ((uint32_t)0x00140000) +#define RCC_PLLMul_8 ((uint32_t)0x00180000) +#define RCC_PLLMul_9 ((uint32_t)0x001C0000) +#define RCC_PLLMul_10 ((uint32_t)0x00200000) +#define RCC_PLLMul_11 ((uint32_t)0x00240000) +#define RCC_PLLMul_12 ((uint32_t)0x00280000) +#define RCC_PLLMul_13 ((uint32_t)0x002C0000) +#define RCC_PLLMul_14 ((uint32_t)0x00300000) +#define RCC_PLLMul_15 ((uint32_t)0x00340000) +#define RCC_PLLMul_16 ((uint32_t)0x00380000) +#define RCC_PLLMul_18 ((uint32_t)0x003C0000) + +/* System_clock_source */ +#define RCC_SYSCLKSource_HSI ((uint32_t)0x00000000) +#define RCC_SYSCLKSource_HSE ((uint32_t)0x00000001) +#define RCC_SYSCLKSource_PLLCLK ((uint32_t)0x00000002) + +/* HB_clock_source */ +#define RCC_SYSCLK_Div1 ((uint32_t)0x00000000) +#define RCC_SYSCLK_Div2 ((uint32_t)0x00000080) +#define RCC_SYSCLK_Div4 ((uint32_t)0x00000090) +#define RCC_SYSCLK_Div8 ((uint32_t)0x000000A0) +#define RCC_SYSCLK_Div16 ((uint32_t)0x000000B0) +#define RCC_SYSCLK_Div64 ((uint32_t)0x000000C0) +#define RCC_SYSCLK_Div128 ((uint32_t)0x000000D0) +#define RCC_SYSCLK_Div256 ((uint32_t)0x000000E0) +#define RCC_SYSCLK_Div512 ((uint32_t)0x000000F0) + +/* PB1_PB2_clock_source */ +#define RCC_HCLK_Div1 ((uint32_t)0x00000000) +#define RCC_HCLK_Div2 ((uint32_t)0x00000400) +#define RCC_HCLK_Div4 ((uint32_t)0x00000500) +#define RCC_HCLK_Div8 ((uint32_t)0x00000600) +#define RCC_HCLK_Div16 ((uint32_t)0x00000700) + +/* RCC_Interrupt_source */ +#define RCC_IT_LSIRDY ((uint8_t)0x01) +#define RCC_IT_LSERDY ((uint8_t)0x02) +#define RCC_IT_HSIRDY ((uint8_t)0x04) +#define RCC_IT_HSERDY ((uint8_t)0x08) +#define RCC_IT_PLLRDY ((uint8_t)0x10) +#define RCC_IT_CSS ((uint8_t)0x80) + +/* USB_Device_clock_source */ +#define RCC_USBCLKSource_PLLCLK_Div1 ((uint32_t)0x00000000) +#define RCC_USBCLKSource_PLLCLK_Div2 ((uint32_t)0x00400000) +#define RCC_USBCLKSource_PLLCLK_Div1_5 ((uint32_t)0x00800000) + +/* ADC_clock_source */ +#define RCC_PCLK2_Div2 ((uint32_t)0x00000000) +#define RCC_PCLK2_Div4 ((uint32_t)0x00004000) +#define RCC_PCLK2_Div6 ((uint32_t)0x00008000) +#define RCC_PCLK2_Div8 ((uint32_t)0x0000C000) +#define RCC_HCLK_ADC ((uint32_t)0x80000000) + +/* LSE_configuration */ +#define RCC_LSE_OFF ((uint8_t)0x00) +#define RCC_LSE_ON ((uint8_t)0x01) +#define RCC_LSE_Bypass ((uint8_t)0x04) + +/* RTC_clock_source */ +#define RCC_RTCCLKSource_LSE ((uint32_t)0x00000100) +#define RCC_RTCCLKSource_LSI ((uint32_t)0x00000200) +#define RCC_RTCCLKSource_HSE_Div128 ((uint32_t)0x00000300) + +/* HB_peripheral */ +#define RCC_HBPeriph_DMA1 ((uint32_t)0x00000001) +#define RCC_HBPeriph_SRAM ((uint32_t)0x00000004) +#define RCC_HBPeriph_CRC ((uint32_t)0x00000040) +#define RCC_HBPeriph_USBFS ((uint32_t)0x00001000) +#define RCC_HBPeriph_USBPD ((uint32_t)0x00020000) + +/* PB2_peripheral */ +#define RCC_PB2Periph_AFIO ((uint32_t)0x00000001) +#define RCC_PB2Periph_GPIOA ((uint32_t)0x00000004) +#define RCC_PB2Periph_GPIOB ((uint32_t)0x00000008) +#define RCC_PB2Periph_GPIOC ((uint32_t)0x00000010) +#define RCC_PB2Periph_GPIOD ((uint32_t)0x00000020) +#define RCC_PB2Periph_ADC1 ((uint32_t)0x00000200) +#define RCC_PB2Periph_TIM1 ((uint32_t)0x00000800) +#define RCC_PB2Periph_SPI1 ((uint32_t)0x00001000) +#define RCC_PB2Periph_USART1 ((uint32_t)0x00004000) + +/* PB1_peripheral */ +#define RCC_PB1Periph_TIM2 ((uint32_t)0x00000001) +#define RCC_PB1Periph_TIM3 ((uint32_t)0x00000002) +#define RCC_PB1Periph_TIM4 ((uint32_t)0x00000004) +#define RCC_PB1Periph_WWDG ((uint32_t)0x00000800) +#define RCC_PB1Periph_SPI2 ((uint32_t)0x00004000) +#define RCC_PB1Periph_USART2 ((uint32_t)0x00020000) +#define RCC_PB1Periph_USART3 ((uint32_t)0x00040000) +#define RCC_PB1Periph_USART4 ((uint32_t)0x00080000) +#define RCC_PB1Periph_I2C1 ((uint32_t)0x00200000) +#define RCC_PB1Periph_I2C2 ((uint32_t)0x00400000) +#define RCC_PB1Periph_CAN1 ((uint32_t)0x02000000) +#define RCC_PB1Periph_BKP ((uint32_t)0x08000000) +#define RCC_PB1Periph_PWR ((uint32_t)0x10000000) +#define RCC_PB1Periph_LPTIM ((uint32_t)0x80000000) + +/* Clock_source_to_output_on_MCO_pin */ +#define RCC_MCO_NoClock ((uint8_t)0x00) +#define RCC_MCO_SYSCLK ((uint8_t)0x04) +#define RCC_MCO_HSI ((uint8_t)0x05) +#define RCC_MCO_HSE ((uint8_t)0x06) +#define RCC_MCO_PLLCLK_Div2 ((uint8_t)0x07) + +/* RCC_Flag */ +#define RCC_FLAG_HSIRDY ((uint8_t)0x21) +#define RCC_FLAG_HSERDY ((uint8_t)0x31) +#define RCC_FLAG_PLLRDY ((uint8_t)0x39) +#define RCC_FLAG_LSERDY ((uint8_t)0x41) +#define RCC_FLAG_LSIRDY ((uint8_t)0x61) +#define RCC_FLAG_PINRST ((uint8_t)0x7A) +#define RCC_FLAG_PORRST ((uint8_t)0x7B) +#define RCC_FLAG_SFTRST ((uint8_t)0x7C) +#define RCC_FLAG_IWDGRST ((uint8_t)0x7D) +#define RCC_FLAG_WWDGRST ((uint8_t)0x7E) +#define RCC_FLAG_LPWRRST ((uint8_t)0x7F) + +/* SysTick_clock_source */ +#define SysTick_CLKSource_HCLK_Div8 ((uint32_t)0xFFFFFFFB) +#define SysTick_CLKSource_HCLK ((uint32_t)0x00000004) + +/* ADC_clock_H_Level_Duty_Cycle */ +#define RCC_ADC_H_Level_Mode0 ((uint32_t)0x00000000) +#define RCC_ADC_H_Level_Mode1 ((uint32_t)0x10000000) +#define RCC_ADC_H_Level_Mode2 ((uint32_t)0x20000000) +#define RCC_ADC_H_Level_Mode3 ((uint32_t)0x30000000) +#define RCC_ADC_H_Level_Mode4 ((uint32_t)0x40000000) +#define RCC_ADC_H_Level_Mode5 ((uint32_t)0x50000000) +#define RCC_ADC_H_Level_Mode6 ((uint32_t)0x60000000) +#define RCC_ADC_H_Level_Mode7 ((uint32_t)0x70000000) + +void RCC_DeInit(void); +void RCC_HSEConfig(uint32_t RCC_HSE); +ErrorStatus RCC_WaitForHSEStartUp(void); +void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue); +void RCC_HSICmd(FunctionalState NewState); +void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t RCC_PLLMul); +void RCC_PLLCmd(FunctionalState NewState); +void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource); +uint8_t RCC_GetSYSCLKSource(void); +void RCC_HCLKConfig(uint32_t RCC_SYSCLK); +void RCC_PCLK1Config(uint32_t RCC_HCLK); +void RCC_PCLK2Config(uint32_t RCC_HCLK); +void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState); +void RCC_USBCLKConfig(uint32_t RCC_USBCLKSource); +void RCC_ADCCLKConfig(uint32_t RCC_PCLK2); +void RCC_LSEConfig(uint8_t RCC_LSE); +void RCC_LSICmd(FunctionalState NewState); +void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource); +void RCC_RTCCLKCmd(FunctionalState NewState); +void RCC_GetClocksFreq(RCC_ClocksTypeDef *RCC_Clocks); +void RCC_HBPeriphClockCmd(uint32_t RCC_HBPeriph, FunctionalState NewState); +void RCC_PB2PeriphClockCmd(uint32_t RCC_PB2Periph, FunctionalState NewState); +void RCC_PB1PeriphClockCmd(uint32_t RCC_PB1Periph, FunctionalState NewState); +void RCC_PB2PeriphResetCmd(uint32_t RCC_PB2Periph, FunctionalState NewState); +void RCC_PB1PeriphResetCmd(uint32_t RCC_PB1Periph, FunctionalState NewState); +void RCC_BackupResetCmd(FunctionalState NewState); +void RCC_ClockSecuritySystemCmd(FunctionalState NewState); +void RCC_MCOConfig(uint8_t RCC_MCO); +FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG); +void RCC_ClearFlag(void); +ITStatus RCC_GetITStatus(uint8_t RCC_IT); +void RCC_ClearITPendingBit(uint8_t RCC_IT); +void RCC_ADCCLKDutyCycleConfig(uint32_t RCC_DutyCycle); +void RCC_HSE_LP_Cmd(FunctionalState NewState); +void RCC_HSI_LP_Cmd(FunctionalState NewState); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/ZDBMS/BMS_MC/Peripheral/inc/ch32l103_rtc.h b/ZDBMS/BMS_MC/Peripheral/inc/ch32l103_rtc.h new file mode 100644 index 0000000..77ae7a0 --- /dev/null +++ b/ZDBMS/BMS_MC/Peripheral/inc/ch32l103_rtc.h @@ -0,0 +1,55 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32l103_rtc.h + * Author : WCH + * Version : V1.0.0 + * Date : 2023/07/08 + * Description : This file contains all the functions prototypes for the RTC + * firmware library. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#ifndef __CH32L103_RTC_H +#define __CH32L103_RTC_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "ch32l103.h" + + +/* RTC_interrupts_define */ +#define RTC_IT_OW ((uint16_t)0x0004) /* Overflow interrupt */ +#define RTC_IT_ALR ((uint16_t)0x0002) /* Alarm interrupt */ +#define RTC_IT_SEC ((uint16_t)0x0001) /* Second interrupt */ + +/* RTC_interrupts_flags */ +#define RTC_FLAG_RTOFF ((uint16_t)0x0020) /* RTC Operation OFF flag */ +#define RTC_FLAG_RSF ((uint16_t)0x0008) /* Registers Synchronized flag */ +#define RTC_FLAG_OW ((uint16_t)0x0004) /* Overflow flag */ +#define RTC_FLAG_ALR ((uint16_t)0x0002) /* Alarm flag */ +#define RTC_FLAG_SEC ((uint16_t)0x0001) /* Second flag */ + + +void RTC_ITConfig(uint16_t RTC_IT, FunctionalState NewState); +void RTC_EnterConfigMode(void); +void RTC_ExitConfigMode(void); +uint32_t RTC_GetCounter(void); +void RTC_SetCounter(uint32_t CounterValue); +void RTC_SetPrescaler(uint32_t PrescalerValue); +void RTC_SetAlarm(uint32_t AlarmValue); +uint32_t RTC_GetDivider(void); +void RTC_WaitForLastTask(void); +void RTC_WaitForSynchro(void); +FlagStatus RTC_GetFlagStatus(uint16_t RTC_FLAG); +void RTC_ClearFlag(uint16_t RTC_FLAG); +ITStatus RTC_GetITStatus(uint16_t RTC_IT); +void RTC_ClearITPendingBit(uint16_t RTC_IT); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/ZDBMS/BMS_MC/Peripheral/inc/ch32l103_spi.h b/ZDBMS/BMS_MC/Peripheral/inc/ch32l103_spi.h new file mode 100644 index 0000000..d1189a9 --- /dev/null +++ b/ZDBMS/BMS_MC/Peripheral/inc/ch32l103_spi.h @@ -0,0 +1,158 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32l103_spi.h + * Author : WCH + * Version : V1.0.0 + * Date : 2024/06/05 + * Description : This file contains all the functions prototypes for the + * SPI firmware library. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#ifndef __CH32L103_SPI_H +#define __CH32L103_SPI_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "ch32l103.h" + +/* SPI Init structure definition */ +typedef struct +{ + uint16_t SPI_Direction; /* Specifies the SPI unidirectional or bidirectional data mode. + This parameter can be a value of @ref SPI_data_direction */ + + uint16_t SPI_Mode; /* Specifies the SPI operating mode. + This parameter can be a value of @ref SPI_mode */ + + uint16_t SPI_DataSize; /* Specifies the SPI data size. + This parameter can be a value of @ref SPI_data_size */ + + uint16_t SPI_CPOL; /* Specifies the serial clock steady state. + This parameter can be a value of @ref SPI_Clock_Polarity + When using SPI slave mode to send data, the CPOL bit should be set to 1 */ + + uint16_t SPI_CPHA; /* Specifies the clock active edge for the bit capture. + This parameter can be a value of @ref SPI_Clock_Phase */ + + uint16_t SPI_NSS; /* Specifies whether the NSS signal is managed by + hardware (NSS pin) or by software using the SSI bit. + This parameter can be a value of @ref SPI_Slave_Select_management */ + + uint16_t SPI_BaudRatePrescaler; /* Specifies the Baud Rate prescaler value which will be + used to configure the transmit and receive SCK clock. + This parameter can be a value of @ref SPI_BaudRate_Prescaler. + @note The communication clock is derived from the master + clock. The slave clock does not need to be set. */ + + uint16_t SPI_FirstBit; /* Specifies whether data transfers start from MSB or LSB bit. + This parameter can be a value of @ref SPI_MSB_LSB_transmission */ + + uint16_t SPI_CRCPolynomial; /* Specifies the polynomial used for the CRC calculation. */ +} SPI_InitTypeDef; + +/* SPI_data_direction */ +#define SPI_Direction_2Lines_FullDuplex ((uint16_t)0x0000) +#define SPI_Direction_2Lines_RxOnly ((uint16_t)0x0400) +#define SPI_Direction_1Line_Rx ((uint16_t)0x8000) +#define SPI_Direction_1Line_Tx ((uint16_t)0xC000) + +/* SPI_mode */ +#define SPI_Mode_Master ((uint16_t)0x0104) +#define SPI_Mode_Slave ((uint16_t)0x0000) + +/* SPI_data_size */ +#define SPI_DataSize_16b ((uint16_t)0x0800) +#define SPI_DataSize_8b ((uint16_t)0x0000) + +/* SPI_Clock_Polarity */ +#define SPI_CPOL_Low ((uint16_t)0x0000) +#define SPI_CPOL_High ((uint16_t)0x0002)//When using SPI slave mode to send data, the CPOL bit should be set to 1. + +/* SPI_Clock_Phase */ +#define SPI_CPHA_1Edge ((uint16_t)0x0000) +#define SPI_CPHA_2Edge ((uint16_t)0x0001) + +/* SPI_Slave_Select_management */ +#define SPI_NSS_Soft ((uint16_t)0x0200) +#define SPI_NSS_Hard ((uint16_t)0x0000) + +/* SPI_BaudRate_Prescaler */ +#define SPI_BaudRatePrescaler_2 ((uint16_t)0x0000) +#define SPI_BaudRatePrescaler_4 ((uint16_t)0x0008) +#define SPI_BaudRatePrescaler_8 ((uint16_t)0x0010) +#define SPI_BaudRatePrescaler_16 ((uint16_t)0x0018) +#define SPI_BaudRatePrescaler_32 ((uint16_t)0x0020) +#define SPI_BaudRatePrescaler_64 ((uint16_t)0x0028) +#define SPI_BaudRatePrescaler_128 ((uint16_t)0x0030) +#define SPI_BaudRatePrescaler_256 ((uint16_t)0x0038) + +/* SPI_MSB_LSB_transmission */ +#define SPI_FirstBit_MSB ((uint16_t)0x0000) +#define SPI_FirstBit_LSB ((uint16_t)0x0080) + +/* SPI_DMA_transfer_requests */ +#define SPI_I2S_DMAReq_Tx ((uint16_t)0x0002) +#define SPI_I2S_DMAReq_Rx ((uint16_t)0x0001) + +/* SPI_NSS_internal_software_management */ +#define SPI_NSSInternalSoft_Set ((uint16_t)0x0100) +#define SPI_NSSInternalSoft_Reset ((uint16_t)0xFEFF) + +/* SPI_CRC_Transmit_Receive */ +#define SPI_CRC_Tx ((uint8_t)0x00) +#define SPI_CRC_Rx ((uint8_t)0x01) + +/* SPI_direction_transmit_receive */ +#define SPI_Direction_Rx ((uint16_t)0xBFFF) +#define SPI_Direction_Tx ((uint16_t)0x4000) + +/* SPI_interrupts_definition */ +#define SPI_I2S_IT_TXE ((uint8_t)0x71) +#define SPI_I2S_IT_RXNE ((uint8_t)0x60) +#define SPI_I2S_IT_ERR ((uint8_t)0x50) +#define SPI_I2S_IT_OVR ((uint8_t)0x56) +#define SPI_IT_MODF ((uint8_t)0x55) +#define SPI_IT_CRCERR ((uint8_t)0x54) + +/* SPI_flags_definition */ +#define SPI_I2S_FLAG_RXNE ((uint16_t)0x0001) +#define SPI_I2S_FLAG_TXE ((uint16_t)0x0002) +#define SPI_FLAG_CRCERR ((uint16_t)0x0010) +#define SPI_FLAG_MODF ((uint16_t)0x0020) +#define SPI_I2S_FLAG_OVR ((uint16_t)0x0040) +#define SPI_I2S_FLAG_BSY ((uint16_t)0x0080) + + + +void SPI_I2S_DeInit(SPI_TypeDef *SPIx); +void SPI_Init(SPI_TypeDef *SPIx, SPI_InitTypeDef *SPI_InitStruct); +void SPI_StructInit(SPI_InitTypeDef *SPI_InitStruct); +void SPI_Cmd(SPI_TypeDef *SPIx, FunctionalState NewState); +void I2S_Cmd(SPI_TypeDef *SPIx, FunctionalState NewState); +void SPI_I2S_ITConfig(SPI_TypeDef *SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState); +void SPI_I2S_DMACmd(SPI_TypeDef *SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState); +void SPI_I2S_SendData(SPI_TypeDef *SPIx, uint16_t Data); +uint16_t SPI_I2S_ReceiveData(SPI_TypeDef *SPIx); +void SPI_NSSInternalSoftwareConfig(SPI_TypeDef *SPIx, uint16_t SPI_NSSInternalSoft); +void SPI_SSOutputCmd(SPI_TypeDef *SPIx, FunctionalState NewState); +void SPI_DataSizeConfig(SPI_TypeDef *SPIx, uint16_t SPI_DataSize); +void SPI_TransmitCRC(SPI_TypeDef *SPIx); +void SPI_CalculateCRC(SPI_TypeDef *SPIx, FunctionalState NewState); +uint16_t SPI_GetCRC(SPI_TypeDef *SPIx, uint8_t SPI_CRC); +uint16_t SPI_GetCRCPolynomial(SPI_TypeDef *SPIx); +void SPI_BiDirectionalLineConfig(SPI_TypeDef *SPIx, uint16_t SPI_Direction); +FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef *SPIx, uint16_t SPI_I2S_FLAG); +void SPI_I2S_ClearFlag(SPI_TypeDef *SPIx, uint16_t SPI_I2S_FLAG); +ITStatus SPI_I2S_GetITStatus(SPI_TypeDef *SPIx, uint8_t SPI_I2S_IT); +void SPI_I2S_ClearITPendingBit(SPI_TypeDef *SPIx, uint8_t SPI_I2S_IT); +void SPI_HighSpeedRead_Cmd(SPI_TypeDef *SPIx, FunctionalState NewState); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/ZDBMS/BMS_MC/Peripheral/inc/ch32l103_tim.h b/ZDBMS/BMS_MC/Peripheral/inc/ch32l103_tim.h new file mode 100644 index 0000000..9043720 --- /dev/null +++ b/ZDBMS/BMS_MC/Peripheral/inc/ch32l103_tim.h @@ -0,0 +1,517 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32l103_tim.h + * Author : WCH + * Version : V1.0.0 + * Date : 2023/07/08 + * Description : This file contains all the functions prototypes for the + * TIM firmware library. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#ifndef __CH32L103_TIM_H +#define __CH32L103_TIM_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "ch32l103.h" + +/* TIM Time Base Init structure definition */ +typedef struct +{ + uint32_t TIM_Period; /* Specifies the period value to be loaded into the active + Auto-Reload Register at the next update event. + This parameter must be a number between 0x0000 and 0xFFFF for TIM1-TIM2-TIM3. + This parameter must be a number between 0x00000000 and 0xFFFFFFFF for TIM4. */ + + uint16_t TIM_Prescaler; /* Specifies the prescaler value used to divide the TIM clock. + This parameter can be a number between 0x0000 and 0xFFFF */ + + uint16_t TIM_CounterMode; /* Specifies the counter mode. + This parameter can be a value of @ref TIM_Counter_Mode */ + + uint16_t TIM_ClockDivision; /* Specifies the clock division. + This parameter can be a value of @ref TIM_Clock_Division_CKD */ + + uint8_t TIM_RepetitionCounter; /* Specifies the repetition counter value. Each time the RCR downcounter + reaches zero, an update event is generated and counting restarts + from the RCR value (N). + This means in PWM mode that (N+1) corresponds to: + - the number of PWM periods in edge-aligned mode + - the number of half PWM period in center-aligned mode + This parameter must be a number between 0x00 and 0xFF. + @note This parameter is valid only for TIM1 and TIM8. */ +} TIM_TimeBaseInitTypeDef; + +/* TIM Output Compare Init structure definition */ +typedef struct +{ + uint32_t TIM_Pulse; /* Specifies the pulse value to be loaded into the Capture Compare Register. + This parameter can be a number between 0x0000 and 0xFFFF for TIM1-TIM2-TIM3. + This parameter must be a number between 0x00000000 and 0xFFFFFFFF for TIM4. */ + + uint16_t TIM_OCMode; /* Specifies the TIM mode. + This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */ + + uint16_t TIM_OutputState; /* Specifies the TIM Output Compare state. + This parameter can be a value of @ref TIM_Output_Compare_state */ + + uint16_t TIM_OutputNState; /* Specifies the TIM complementary Output Compare state. + This parameter can be a value of @ref TIM_Output_Compare_N_state + @note This parameter is valid only for TIM1 and TIM8. */ + + uint16_t TIM_OCPolarity; /* Specifies the output polarity. + This parameter can be a value of @ref TIM_Output_Compare_Polarity */ + + uint16_t TIM_OCNPolarity; /* Specifies the complementary output polarity. + This parameter can be a value of @ref TIM_Output_Compare_N_Polarity + @note This parameter is valid only for TIM1 and TIM8. */ + + uint16_t TIM_OCIdleState; /* Specifies the TIM Output Compare pin state during Idle state. + This parameter can be a value of @ref TIM_Output_Compare_Idle_State + @note This parameter is valid only for TIM1 and TIM8. */ + + uint16_t TIM_OCNIdleState; /* Specifies the TIM Output Compare pin state during Idle state. + This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State + @note This parameter is valid only for TIM1 and TIM8. */ +} TIM_OCInitTypeDef; + +/* TIM Input Capture Init structure definition */ +typedef struct +{ + uint16_t TIM_Channel; /* Specifies the TIM channel. + This parameter can be a value of @ref TIM_Channel */ + + uint16_t TIM_ICPolarity; /* Specifies the active edge of the input signal. + This parameter can be a value of @ref TIM_Input_Capture_Polarity */ + + uint16_t TIM_ICSelection; /* Specifies the input. + This parameter can be a value of @ref TIM_Input_Capture_Selection */ + + uint16_t TIM_ICPrescaler; /* Specifies the Input Capture Prescaler. + This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ + + uint16_t TIM_ICFilter; /* Specifies the input capture filter. + This parameter can be a number between 0x0 and 0xF */ +} TIM_ICInitTypeDef; + +/* BDTR structure definition */ +typedef struct +{ + uint16_t TIM_OSSRState; /* Specifies the Off-State selection used in Run mode. + This parameter can be a value of @ref OSSR_Off_State_Selection_for_Run_mode_state */ + + uint16_t TIM_OSSIState; /* Specifies the Off-State used in Idle state. + This parameter can be a value of @ref OSSI_Off_State_Selection_for_Idle_mode_state */ + + uint16_t TIM_LOCKLevel; /* Specifies the LOCK level parameters. + This parameter can be a value of @ref Lock_level */ + + uint16_t TIM_DeadTime; /* Specifies the delay time between the switching-off and the + switching-on of the outputs. + This parameter can be a number between 0x00 and 0xFF */ + + uint16_t TIM_Break; /* Specifies whether the TIM Break input is enabled or not. + This parameter can be a value of @ref Break_Input_enable_disable */ + + uint16_t TIM_BreakPolarity; /* Specifies the TIM Break Input pin polarity. + This parameter can be a value of @ref Break_Polarity */ + + uint16_t TIM_AutomaticOutput; /* Specifies whether the TIM Automatic Output feature is enabled or not. + This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */ +} TIM_BDTRInitTypeDef; + +/* TIM_Output_Compare_and_PWM_modes */ +#define TIM_OCMode_Timing ((uint16_t)0x0000) +#define TIM_OCMode_Active ((uint16_t)0x0010) +#define TIM_OCMode_Inactive ((uint16_t)0x0020) +#define TIM_OCMode_Toggle ((uint16_t)0x0030) +#define TIM_OCMode_PWM1 ((uint16_t)0x0060) +#define TIM_OCMode_PWM2 ((uint16_t)0x0070) + +/* TIM_One_Pulse_Mode */ +#define TIM_OPMode_Single ((uint16_t)0x0008) +#define TIM_OPMode_Repetitive ((uint16_t)0x0000) + +/* TIM_Channel */ +#define TIM_Channel_1 ((uint16_t)0x0000) +#define TIM_Channel_2 ((uint16_t)0x0004) +#define TIM_Channel_3 ((uint16_t)0x0008) +#define TIM_Channel_4 ((uint16_t)0x000C) + +/* TIM_Clock_Division_CKD */ +#define TIM_CKD_DIV1 ((uint16_t)0x0000) +#define TIM_CKD_DIV2 ((uint16_t)0x0100) +#define TIM_CKD_DIV4 ((uint16_t)0x0200) + +/* TIM_Counter_Mode */ +#define TIM_CounterMode_Up ((uint16_t)0x0000) +#define TIM_CounterMode_Down ((uint16_t)0x0010) +#define TIM_CounterMode_CenterAligned1 ((uint16_t)0x0020) +#define TIM_CounterMode_CenterAligned2 ((uint16_t)0x0040) +#define TIM_CounterMode_CenterAligned3 ((uint16_t)0x0060) + +/* TIM_Output_Compare_Polarity */ +#define TIM_OCPolarity_High ((uint16_t)0x0000) +#define TIM_OCPolarity_Low ((uint16_t)0x0002) + +/* TIM_Output_Compare_N_Polarity */ +#define TIM_OCNPolarity_High ((uint16_t)0x0000) +#define TIM_OCNPolarity_Low ((uint16_t)0x0008) + +/* TIM_Output_Compare_state */ +#define TIM_OutputState_Disable ((uint16_t)0x0000) +#define TIM_OutputState_Enable ((uint16_t)0x0001) + +/* TIM_Output_Compare_N_state */ +#define TIM_OutputNState_Disable ((uint16_t)0x0000) +#define TIM_OutputNState_Enable ((uint16_t)0x0004) + +/* TIM_Capture_Compare_state */ +#define TIM_CCx_Enable ((uint16_t)0x0001) +#define TIM_CCx_Disable ((uint16_t)0x0000) + +/* TIM_Capture_Compare_N_state */ +#define TIM_CCxN_Enable ((uint16_t)0x0004) +#define TIM_CCxN_Disable ((uint16_t)0x0000) + +/* Break_Input_enable_disable */ +#define TIM_Break_Enable ((uint16_t)0x1000) +#define TIM_Break_Disable ((uint16_t)0x0000) + +/* Break_Polarity */ +#define TIM_BreakPolarity_Low ((uint16_t)0x0000) +#define TIM_BreakPolarity_High ((uint16_t)0x2000) + +/* TIM_AOE_Bit_Set_Reset */ +#define TIM_AutomaticOutput_Enable ((uint16_t)0x4000) +#define TIM_AutomaticOutput_Disable ((uint16_t)0x0000) + +/* Lock_level */ +#define TIM_LOCKLevel_OFF ((uint16_t)0x0000) +#define TIM_LOCKLevel_1 ((uint16_t)0x0100) +#define TIM_LOCKLevel_2 ((uint16_t)0x0200) +#define TIM_LOCKLevel_3 ((uint16_t)0x0300) + +/* OSSI_Off_State_Selection_for_Idle_mode_state */ +#define TIM_OSSIState_Enable ((uint16_t)0x0400) +#define TIM_OSSIState_Disable ((uint16_t)0x0000) + +/* OSSR_Off_State_Selection_for_Run_mode_state */ +#define TIM_OSSRState_Enable ((uint16_t)0x0800) +#define TIM_OSSRState_Disable ((uint16_t)0x0000) + +/* TIM_Output_Compare_Idle_State */ +#define TIM_OCIdleState_Set ((uint16_t)0x0100) +#define TIM_OCIdleState_Reset ((uint16_t)0x0000) + +/* TIM_Output_Compare_N_Idle_State */ +#define TIM_OCNIdleState_Set ((uint16_t)0x0200) +#define TIM_OCNIdleState_Reset ((uint16_t)0x0000) + +/* TIM_Input_Capture_Polarity */ +#define TIM_ICPolarity_Rising ((uint16_t)0x0000) +#define TIM_ICPolarity_Falling ((uint16_t)0x0002) +#define TIM_ICPolarity_BothEdge ((uint16_t)0x000A) + +/* TIM_Input_Capture_Selection */ +#define TIM_ICSelection_DirectTI ((uint16_t)0x0001) /* TIM Input 1, 2, 3 or 4 is selected to be \ + connected to IC1, IC2, IC3 or IC4, respectively */ +#define TIM_ICSelection_IndirectTI ((uint16_t)0x0002) /* TIM Input 1, 2, 3 or 4 is selected to be \ + connected to IC2, IC1, IC4 or IC3, respectively. */ +#define TIM_ICSelection_TRC ((uint16_t)0x0003) /* TIM Input 1, 2, 3 or 4 is selected to be connected to TRC. */ + +/* TIM_Input_Capture_Prescaler */ +#define TIM_ICPSC_DIV1 ((uint16_t)0x0000) /* Capture performed each time an edge is detected on the capture input. */ +#define TIM_ICPSC_DIV2 ((uint16_t)0x0004) /* Capture performed once every 2 events. */ +#define TIM_ICPSC_DIV4 ((uint16_t)0x0008) /* Capture performed once every 4 events. */ +#define TIM_ICPSC_DIV8 ((uint16_t)0x000C) /* Capture performed once every 8 events. */ + +/* TIM_interrupt_sources */ +#define TIM_IT_Update ((uint16_t)0x0001) +#define TIM_IT_CC1 ((uint16_t)0x0002) +#define TIM_IT_CC2 ((uint16_t)0x0004) +#define TIM_IT_CC3 ((uint16_t)0x0008) +#define TIM_IT_CC4 ((uint16_t)0x0010) +#define TIM_IT_COM ((uint16_t)0x0020) +#define TIM_IT_Trigger ((uint16_t)0x0040) +#define TIM_IT_Break ((uint16_t)0x0080) + +/* TIM_DMA_Base_address */ +#define TIM_DMABase_CR1 ((uint16_t)0x0000) +#define TIM_DMABase_CR2 ((uint16_t)0x0001) +#define TIM_DMABase_SMCR ((uint16_t)0x0002) +#define TIM_DMABase_DIER ((uint16_t)0x0003) +#define TIM_DMABase_SR ((uint16_t)0x0004) +#define TIM_DMABase_EGR ((uint16_t)0x0005) +#define TIM_DMABase_CCMR1 ((uint16_t)0x0006) +#define TIM_DMABase_CCMR2 ((uint16_t)0x0007) +#define TIM_DMABase_CCER ((uint16_t)0x0008) +#define TIM_DMABase_CNT ((uint16_t)0x0009) +#define TIM_DMABase_PSC ((uint16_t)0x000A) +#define TIM_DMABase_ARR ((uint16_t)0x000B) +#define TIM_DMABase_RCR ((uint16_t)0x000C) +#define TIM_DMABase_CCR1 ((uint16_t)0x000D) +#define TIM_DMABase_CCR2 ((uint16_t)0x000E) +#define TIM_DMABase_CCR3 ((uint16_t)0x000F) +#define TIM_DMABase_CCR4 ((uint16_t)0x0010) +#define TIM_DMABase_BDTR ((uint16_t)0x0011) +#define TIM_DMABase_DCR ((uint16_t)0x0012) + +/* TIM_DMA_Burst_Length */ +#define TIM_DMABurstLength_1Transfer ((uint16_t)0x0000) +#define TIM_DMABurstLength_2Transfers ((uint16_t)0x0100) +#define TIM_DMABurstLength_3Transfers ((uint16_t)0x0200) +#define TIM_DMABurstLength_4Transfers ((uint16_t)0x0300) +#define TIM_DMABurstLength_5Transfers ((uint16_t)0x0400) +#define TIM_DMABurstLength_6Transfers ((uint16_t)0x0500) +#define TIM_DMABurstLength_7Transfers ((uint16_t)0x0600) +#define TIM_DMABurstLength_8Transfers ((uint16_t)0x0700) +#define TIM_DMABurstLength_9Transfers ((uint16_t)0x0800) +#define TIM_DMABurstLength_10Transfers ((uint16_t)0x0900) +#define TIM_DMABurstLength_11Transfers ((uint16_t)0x0A00) +#define TIM_DMABurstLength_12Transfers ((uint16_t)0x0B00) +#define TIM_DMABurstLength_13Transfers ((uint16_t)0x0C00) +#define TIM_DMABurstLength_14Transfers ((uint16_t)0x0D00) +#define TIM_DMABurstLength_15Transfers ((uint16_t)0x0E00) +#define TIM_DMABurstLength_16Transfers ((uint16_t)0x0F00) +#define TIM_DMABurstLength_17Transfers ((uint16_t)0x1000) +#define TIM_DMABurstLength_18Transfers ((uint16_t)0x1100) + +/* TIM_DMA_sources */ +#define TIM_DMA_Update ((uint16_t)0x0100) +#define TIM_DMA_CC1 ((uint16_t)0x0200) +#define TIM_DMA_CC2 ((uint16_t)0x0400) +#define TIM_DMA_CC3 ((uint16_t)0x0800) +#define TIM_DMA_CC4 ((uint16_t)0x1000) +#define TIM_DMA_COM ((uint16_t)0x2000) +#define TIM_DMA_Trigger ((uint16_t)0x4000) + +/* TIM_External_Trigger_Prescaler */ +#define TIM_ExtTRGPSC_OFF ((uint16_t)0x0000) +#define TIM_ExtTRGPSC_DIV2 ((uint16_t)0x1000) +#define TIM_ExtTRGPSC_DIV4 ((uint16_t)0x2000) +#define TIM_ExtTRGPSC_DIV8 ((uint16_t)0x3000) + +/* TIM_Internal_Trigger_Selection */ +#define TIM_TS_ITR0 ((uint16_t)0x0000) +#define TIM_TS_ITR1 ((uint16_t)0x0010) +#define TIM_TS_ITR2 ((uint16_t)0x0020) +#define TIM_TS_ITR3 ((uint16_t)0x0030) +#define TIM_TS_TI1F_ED ((uint16_t)0x0040) +#define TIM_TS_TI1FP1 ((uint16_t)0x0050) +#define TIM_TS_TI2FP2 ((uint16_t)0x0060) +#define TIM_TS_ETRF ((uint16_t)0x0070) + +/* TIM_TIx_External_Clock_Source */ +#define TIM_TIxExternalCLK1Source_TI1 ((uint16_t)0x0050) +#define TIM_TIxExternalCLK1Source_TI2 ((uint16_t)0x0060) +#define TIM_TIxExternalCLK1Source_TI1ED ((uint16_t)0x0040) + +/* TIM_External_Trigger_Polarity */ +#define TIM_ExtTRGPolarity_Inverted ((uint16_t)0x8000) +#define TIM_ExtTRGPolarity_NonInverted ((uint16_t)0x0000) + +/* TIM_Prescaler_Reload_Mode */ +#define TIM_PSCReloadMode_Update ((uint16_t)0x0000) +#define TIM_PSCReloadMode_Immediate ((uint16_t)0x0001) + +/* TIM_Forced_Action */ +#define TIM_ForcedAction_Active ((uint16_t)0x0050) +#define TIM_ForcedAction_InActive ((uint16_t)0x0040) + +/* TIM_Encoder_Mode */ +#define TIM_EncoderMode_TI1 ((uint16_t)0x0001) +#define TIM_EncoderMode_TI2 ((uint16_t)0x0002) +#define TIM_EncoderMode_TI12 ((uint16_t)0x0003) + +/* TIM_Event_Source */ +#define TIM_EventSource_Update ((uint16_t)0x0001) +#define TIM_EventSource_CC1 ((uint16_t)0x0002) +#define TIM_EventSource_CC2 ((uint16_t)0x0004) +#define TIM_EventSource_CC3 ((uint16_t)0x0008) +#define TIM_EventSource_CC4 ((uint16_t)0x0010) +#define TIM_EventSource_COM ((uint16_t)0x0020) +#define TIM_EventSource_Trigger ((uint16_t)0x0040) +#define TIM_EventSource_Break ((uint16_t)0x0080) + +/* TIM_Update_Source */ +#define TIM_UpdateSource_Global ((uint16_t)0x0000) /* Source of update is the counter overflow/underflow \ + or the setting of UG bit, or an update generation \ + through the slave mode controller. */ +#define TIM_UpdateSource_Regular ((uint16_t)0x0001) /* Source of update is counter overflow/underflow. */ + +/* TIM_Output_Compare_Preload_State */ +#define TIM_OCPreload_Enable ((uint16_t)0x0008) +#define TIM_OCPreload_Disable ((uint16_t)0x0000) + +/* TIM_Output_Compare_Fast_State */ +#define TIM_OCFast_Enable ((uint16_t)0x0004) +#define TIM_OCFast_Disable ((uint16_t)0x0000) + +/* TIM_Output_Compare_Clear_State */ +#define TIM_OCClear_Enable ((uint16_t)0x0080) +#define TIM_OCClear_Disable ((uint16_t)0x0000) + +/* TIM_Trigger_Output_Source */ +#define TIM_TRGOSource_Reset ((uint16_t)0x0000) +#define TIM_TRGOSource_Enable ((uint16_t)0x0010) +#define TIM_TRGOSource_Update ((uint16_t)0x0020) +#define TIM_TRGOSource_OC1 ((uint16_t)0x0030) +#define TIM_TRGOSource_OC1Ref ((uint16_t)0x0040) +#define TIM_TRGOSource_OC2Ref ((uint16_t)0x0050) +#define TIM_TRGOSource_OC3Ref ((uint16_t)0x0060) +#define TIM_TRGOSource_OC4Ref ((uint16_t)0x0070) + +/* TIM_Slave_Mode */ +#define TIM_SlaveMode_Reset ((uint16_t)0x0004) +#define TIM_SlaveMode_Gated ((uint16_t)0x0005) +#define TIM_SlaveMode_Trigger ((uint16_t)0x0006) +#define TIM_SlaveMode_External1 ((uint16_t)0x0007) + +/* TIM_Master_Slave_Mode */ +#define TIM_MasterSlaveMode_Enable ((uint16_t)0x0080) +#define TIM_MasterSlaveMode_Disable ((uint16_t)0x0000) + +/* TIM_Flags */ +#define TIM_FLAG_Update ((uint16_t)0x0001) +#define TIM_FLAG_CC1 ((uint16_t)0x0002) +#define TIM_FLAG_CC2 ((uint16_t)0x0004) +#define TIM_FLAG_CC3 ((uint16_t)0x0008) +#define TIM_FLAG_CC4 ((uint16_t)0x0010) +#define TIM_FLAG_COM ((uint16_t)0x0020) +#define TIM_FLAG_Trigger ((uint16_t)0x0040) +#define TIM_FLAG_Break ((uint16_t)0x0080) +#define TIM_FLAG_CC1OF ((uint16_t)0x0200) +#define TIM_FLAG_CC2OF ((uint16_t)0x0400) +#define TIM_FLAG_CC3OF ((uint16_t)0x0800) +#define TIM_FLAG_CC4OF ((uint16_t)0x1000) + +/* TIM_Legacy */ +#define TIM_DMABurstLength_1Byte TIM_DMABurstLength_1Transfer +#define TIM_DMABurstLength_2Bytes TIM_DMABurstLength_2Transfers +#define TIM_DMABurstLength_3Bytes TIM_DMABurstLength_3Transfers +#define TIM_DMABurstLength_4Bytes TIM_DMABurstLength_4Transfers +#define TIM_DMABurstLength_5Bytes TIM_DMABurstLength_5Transfers +#define TIM_DMABurstLength_6Bytes TIM_DMABurstLength_6Transfers +#define TIM_DMABurstLength_7Bytes TIM_DMABurstLength_7Transfers +#define TIM_DMABurstLength_8Bytes TIM_DMABurstLength_8Transfers +#define TIM_DMABurstLength_9Bytes TIM_DMABurstLength_9Transfers +#define TIM_DMABurstLength_10Bytes TIM_DMABurstLength_10Transfers +#define TIM_DMABurstLength_11Bytes TIM_DMABurstLength_11Transfers +#define TIM_DMABurstLength_12Bytes TIM_DMABurstLength_12Transfers +#define TIM_DMABurstLength_13Bytes TIM_DMABurstLength_13Transfers +#define TIM_DMABurstLength_14Bytes TIM_DMABurstLength_14Transfers +#define TIM_DMABurstLength_15Bytes TIM_DMABurstLength_15Transfers +#define TIM_DMABurstLength_16Bytes TIM_DMABurstLength_16Transfers +#define TIM_DMABurstLength_17Bytes TIM_DMABurstLength_17Transfers +#define TIM_DMABurstLength_18Bytes TIM_DMABurstLength_18Transfers + +/* TIM_Capture_Mode */ +#define TIM_Capture_Mode0 ((uint16_t)0x0000) +#define TIM_Capture_Mode1 ((uint16_t)0x4000) + +void TIM_DeInit(TIM_TypeDef *TIMx); +void TIM_TimeBaseInit(TIM_TypeDef *TIMx, TIM_TimeBaseInitTypeDef *TIM_TimeBaseInitStruct); +void TIM_OC1Init(TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct); +void TIM_OC2Init(TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct); +void TIM_OC3Init(TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct); +void TIM_OC4Init(TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct); +void TIM_ICInit(TIM_TypeDef *TIMx, TIM_ICInitTypeDef *TIM_ICInitStruct); +void TIM_PWMIConfig(TIM_TypeDef *TIMx, TIM_ICInitTypeDef *TIM_ICInitStruct); +void TIM_BDTRConfig(TIM_TypeDef *TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct); +void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef *TIM_TimeBaseInitStruct); +void TIM_OCStructInit(TIM_OCInitTypeDef *TIM_OCInitStruct); +void TIM_ICStructInit(TIM_ICInitTypeDef *TIM_ICInitStruct); +void TIM_BDTRStructInit(TIM_BDTRInitTypeDef *TIM_BDTRInitStruct); +void TIM_Cmd(TIM_TypeDef *TIMx, FunctionalState NewState); +void TIM_CtrlPWMOutputs(TIM_TypeDef *TIMx, FunctionalState NewState); +void TIM_ITConfig(TIM_TypeDef *TIMx, uint16_t TIM_IT, FunctionalState NewState); +void TIM_GenerateEvent(TIM_TypeDef *TIMx, uint16_t TIM_EventSource); +void TIM_DMAConfig(TIM_TypeDef *TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength); +void TIM_DMACmd(TIM_TypeDef *TIMx, uint16_t TIM_DMASource, FunctionalState NewState); +void TIM_InternalClockConfig(TIM_TypeDef *TIMx); +void TIM_ITRxExternalClockConfig(TIM_TypeDef *TIMx, uint16_t TIM_InputTriggerSource); +void TIM_TIxExternalClockConfig(TIM_TypeDef *TIMx, uint16_t TIM_TIxExternalCLKSource, + uint16_t TIM_ICPolarity, uint16_t ICFilter); +void TIM_ETRClockMode1Config(TIM_TypeDef *TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, + uint16_t ExtTRGFilter); +void TIM_ETRClockMode2Config(TIM_TypeDef *TIMx, uint16_t TIM_ExtTRGPrescaler, + uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter); +void TIM_ETRConfig(TIM_TypeDef *TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, + uint16_t ExtTRGFilter); +void TIM_PrescalerConfig(TIM_TypeDef *TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode); +void TIM_CounterModeConfig(TIM_TypeDef *TIMx, uint16_t TIM_CounterMode); +void TIM_SelectInputTrigger(TIM_TypeDef *TIMx, uint16_t TIM_InputTriggerSource); +void TIM_EncoderInterfaceConfig(TIM_TypeDef *TIMx, uint16_t TIM_EncoderMode, + uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity); +void TIM_ForcedOC1Config(TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction); +void TIM_ForcedOC2Config(TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction); +void TIM_ForcedOC3Config(TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction); +void TIM_ForcedOC4Config(TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction); +void TIM_ARRPreloadConfig(TIM_TypeDef *TIMx, FunctionalState NewState); +void TIM_SelectCOM(TIM_TypeDef *TIMx, FunctionalState NewState); +void TIM_SelectCCDMA(TIM_TypeDef *TIMx, FunctionalState NewState); +void TIM_CCPreloadControl(TIM_TypeDef *TIMx, FunctionalState NewState); +void TIM_OC1PreloadConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPreload); +void TIM_OC2PreloadConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPreload); +void TIM_OC3PreloadConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPreload); +void TIM_OC4PreloadConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPreload); +void TIM_OC1FastConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCFast); +void TIM_OC2FastConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCFast); +void TIM_OC3FastConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCFast); +void TIM_OC4FastConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCFast); +void TIM_ClearOC1Ref(TIM_TypeDef *TIMx, uint16_t TIM_OCClear); +void TIM_ClearOC2Ref(TIM_TypeDef *TIMx, uint16_t TIM_OCClear); +void TIM_ClearOC3Ref(TIM_TypeDef *TIMx, uint16_t TIM_OCClear); +void TIM_ClearOC4Ref(TIM_TypeDef *TIMx, uint16_t TIM_OCClear); +void TIM_OC1PolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity); +void TIM_OC1NPolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCNPolarity); +void TIM_OC2PolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity); +void TIM_OC2NPolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCNPolarity); +void TIM_OC3PolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity); +void TIM_OC3NPolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCNPolarity); +void TIM_OC4PolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity); +void TIM_CCxCmd(TIM_TypeDef *TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx); +void TIM_CCxNCmd(TIM_TypeDef *TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN); +void TIM_SelectOCxM(TIM_TypeDef *TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode); +void TIM_UpdateDisableConfig(TIM_TypeDef *TIMx, FunctionalState NewState); +void TIM_UpdateRequestConfig(TIM_TypeDef *TIMx, uint16_t TIM_UpdateSource); +void TIM_SelectHallSensor(TIM_TypeDef *TIMx, FunctionalState NewState); +void TIM_SelectOnePulseMode(TIM_TypeDef *TIMx, uint16_t TIM_OPMode); +void TIM_SelectOutputTrigger(TIM_TypeDef *TIMx, uint16_t TIM_TRGOSource); +void TIM_SelectSlaveMode(TIM_TypeDef *TIMx, uint16_t TIM_SlaveMode); +void TIM_SelectMasterSlaveMode(TIM_TypeDef *TIMx, uint16_t TIM_MasterSlaveMode); +void TIM_SetCounter(TIM_TypeDef *TIMx, uint32_t Counter); +void TIM_SetAutoreload(TIM_TypeDef *TIMx, uint32_t Autoreload); +void TIM_SetCompare1(TIM_TypeDef *TIMx, uint32_t Compare1); +void TIM_SetCompare2(TIM_TypeDef *TIMx, uint32_t Compare2); +void TIM_SetCompare3(TIM_TypeDef *TIMx, uint32_t Compare3); +void TIM_SetCompare4(TIM_TypeDef *TIMx, uint32_t Compare4); +void TIM_SetIC1Prescaler(TIM_TypeDef *TIMx, uint16_t TIM_ICPSC); +void TIM_SetIC2Prescaler(TIM_TypeDef *TIMx, uint16_t TIM_ICPSC); +void TIM_SetIC3Prescaler(TIM_TypeDef *TIMx, uint16_t TIM_ICPSC); +void TIM_SetIC4Prescaler(TIM_TypeDef *TIMx, uint16_t TIM_ICPSC); +void TIM_SetClockDivision(TIM_TypeDef *TIMx, uint16_t TIM_CKD); +uint32_t TIM_GetCapture1(TIM_TypeDef *TIMx); +uint32_t TIM_GetCapture2(TIM_TypeDef *TIMx); +uint32_t TIM_GetCapture3(TIM_TypeDef *TIMx); +uint32_t TIM_GetCapture4(TIM_TypeDef *TIMx); +uint32_t TIM_GetCounter(TIM_TypeDef *TIMx); +uint16_t TIM_GetPrescaler(TIM_TypeDef *TIMx); +FlagStatus TIM_GetFlagStatus(TIM_TypeDef *TIMx, uint16_t TIM_FLAG); +void TIM_ClearFlag(TIM_TypeDef *TIMx, uint16_t TIM_FLAG); +ITStatus TIM_GetITStatus(TIM_TypeDef *TIMx, uint16_t TIM_IT); +void TIM_ClearITPendingBit(TIM_TypeDef *TIMx, uint16_t TIM_IT); +void TIM_CaptureLevelIndicate_Cmd(TIM_TypeDef *TIMx, FunctionalState NewState); +void TIM_CaptureModeConfig(TIM_TypeDef *TIMx, uint16_t TIM_CaptureMode); + + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/ZDBMS/BMS_MC/Peripheral/inc/ch32l103_usart.h b/ZDBMS/BMS_MC/Peripheral/inc/ch32l103_usart.h new file mode 100644 index 0000000..c981f49 --- /dev/null +++ b/ZDBMS/BMS_MC/Peripheral/inc/ch32l103_usart.h @@ -0,0 +1,188 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32l103_usart.h + * Author : WCH + * Version : V1.0.0 + * Date : 2023/07/08 + * Description : This file contains all the functions prototypes for the + * USART firmware library. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#ifndef __CH32L103_USART_H +#define __CH32L103_USART_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "ch32l103.h" + +/* USART Init Structure definition */ +typedef struct +{ + uint32_t USART_BaudRate; /* This member configures the USART communication baud rate. + The baud rate is computed using the following formula: + - IntegerDivider = ((PCLKx) / (16 * (USART_InitStruct->USART_BaudRate))) + - FractionalDivider = ((IntegerDivider - ((u32) IntegerDivider)) * 16) + 0.5 */ + + uint16_t USART_WordLength; /* Specifies the number of data bits transmitted or received in a frame. + This parameter can be a value of @ref USART_Word_Length */ + + uint16_t USART_StopBits; /* Specifies the number of stop bits transmitted. + This parameter can be a value of @ref USART_Stop_Bits */ + + uint16_t USART_Parity; /* Specifies the parity mode. + This parameter can be a value of @ref USART_Parity + @note When parity is enabled, the computed parity is inserted + at the MSB position of the transmitted data (9th bit when + the word length is set to 9 data bits; 8th bit when the + word length is set to 8 data bits). */ + + uint16_t USART_Mode; /* Specifies wether the Receive or Transmit mode is enabled or disabled. + This parameter can be a value of @ref USART_Mode */ + + uint16_t USART_HardwareFlowControl; /* Specifies wether the hardware flow control mode is enabled + or disabled. + This parameter can be a value of @ref USART_Hardware_Flow_Control */ +} USART_InitTypeDef; + +/* USART Clock Init Structure definition */ +typedef struct +{ + uint16_t USART_Clock; /* Specifies whether the USART clock is enabled or disabled. + This parameter can be a value of @ref USART_Clock */ + + uint16_t USART_CPOL; /* Specifies the steady state value of the serial clock. + This parameter can be a value of @ref USART_Clock_Polarity */ + + uint16_t USART_CPHA; /* Specifies the clock transition on which the bit capture is made. + This parameter can be a value of @ref USART_Clock_Phase */ + + uint16_t USART_LastBit; /* Specifies whether the clock pulse corresponding to the last transmitted + data bit (MSB) has to be output on the SCLK pin in synchronous mode. + This parameter can be a value of @ref USART_Last_Bit */ +} USART_ClockInitTypeDef; + +/* USART_Word_Length */ +#define USART_WordLength_8b ((uint16_t)0x0000) +#define USART_WordLength_9b ((uint16_t)0x1000) + +/* USART_Stop_Bits */ +#define USART_StopBits_1 ((uint16_t)0x0000) +#define USART_StopBits_0_5 ((uint16_t)0x1000) +#define USART_StopBits_2 ((uint16_t)0x2000) +#define USART_StopBits_1_5 ((uint16_t)0x3000) + +/* USART_Parity */ +#define USART_Parity_No ((uint16_t)0x0000) +#define USART_Parity_Even ((uint16_t)0x0400) +#define USART_Parity_Odd ((uint16_t)0x0600) + +/* USART_Mode */ +#define USART_Mode_Rx ((uint16_t)0x0004) +#define USART_Mode_Tx ((uint16_t)0x0008) + +/* USART_Hardware_Flow_Control */ +#define USART_HardwareFlowControl_None ((uint16_t)0x0000) +#define USART_HardwareFlowControl_RTS ((uint16_t)0x0100) +#define USART_HardwareFlowControl_CTS ((uint16_t)0x0200) +#define USART_HardwareFlowControl_RTS_CTS ((uint16_t)0x0300) + +/* USART_Clock */ +#define USART_Clock_Disable ((uint16_t)0x0000) +#define USART_Clock_Enable ((uint16_t)0x0800) + +/* USART_Clock_Polarity */ +#define USART_CPOL_Low ((uint16_t)0x0000) +#define USART_CPOL_High ((uint16_t)0x0400) + +/* USART_Clock_Phase */ +#define USART_CPHA_1Edge ((uint16_t)0x0000) +#define USART_CPHA_2Edge ((uint16_t)0x0200) + +/* USART_Last_Bit */ +#define USART_LastBit_Disable ((uint16_t)0x0000) +#define USART_LastBit_Enable ((uint16_t)0x0100) + +/* USART_Interrupt_definition */ +#define USART_IT_PE ((uint16_t)0x0028) +#define USART_IT_TXE ((uint16_t)0x0727) +#define USART_IT_TC ((uint16_t)0x0626) +#define USART_IT_RXNE ((uint16_t)0x0525) +#define USART_IT_ORE_RX ((uint16_t)0x0325) +#define USART_IT_IDLE ((uint16_t)0x0424) +#define USART_IT_LBD ((uint16_t)0x0846) +#define USART_IT_CTS ((uint16_t)0x096A) +#define USART_IT_ERR ((uint16_t)0x0060) +#define USART_IT_ORE_ER ((uint16_t)0x0360) +#define USART_IT_NE ((uint16_t)0x0260) +#define USART_IT_FE ((uint16_t)0x0160) + +#define USART_IT_ORE USART_IT_ORE_ER + +/* USART_DMA_Requests */ +#define USART_DMAReq_Tx ((uint16_t)0x0080) +#define USART_DMAReq_Rx ((uint16_t)0x0040) + +/* USART_WakeUp_methods */ +#define USART_WakeUp_IdleLine ((uint16_t)0x0000) +#define USART_WakeUp_AddressMark ((uint16_t)0x0800) + +/* USART_LIN_Break_Detection_Length */ +#define USART_LINBreakDetectLength_10b ((uint16_t)0x0000) +#define USART_LINBreakDetectLength_11b ((uint16_t)0x0020) + +/* USART_IrDA_Low_Power */ +#define USART_IrDAMode_LowPower ((uint16_t)0x0004) +#define USART_IrDAMode_Normal ((uint16_t)0x0000) + +/* USART_Flags */ +#define USART_FLAG_RX_BUSY ((uint16_t)0x0400) +#define USART_FLAG_CTS ((uint16_t)0x0200) +#define USART_FLAG_LBD ((uint16_t)0x0100) +#define USART_FLAG_TXE ((uint16_t)0x0080) +#define USART_FLAG_TC ((uint16_t)0x0040) +#define USART_FLAG_RXNE ((uint16_t)0x0020) +#define USART_FLAG_IDLE ((uint16_t)0x0010) +#define USART_FLAG_ORE ((uint16_t)0x0008) +#define USART_FLAG_NE ((uint16_t)0x0004) +#define USART_FLAG_FE ((uint16_t)0x0002) +#define USART_FLAG_PE ((uint16_t)0x0001) + +void USART_DeInit(USART_TypeDef *USARTx); +void USART_Init(USART_TypeDef *USARTx, USART_InitTypeDef *USART_InitStruct); +void USART_StructInit(USART_InitTypeDef *USART_InitStruct); +void USART_ClockInit(USART_TypeDef *USARTx, USART_ClockInitTypeDef *USART_ClockInitStruct); +void USART_ClockStructInit(USART_ClockInitTypeDef *USART_ClockInitStruct); +void USART_Cmd(USART_TypeDef *USARTx, FunctionalState NewState); +void USART_ITConfig(USART_TypeDef *USARTx, uint16_t USART_IT, FunctionalState NewState); +void USART_DMACmd(USART_TypeDef *USARTx, uint16_t USART_DMAReq, FunctionalState NewState); +void USART_SetAddress(USART_TypeDef *USARTx, uint8_t USART_Address); +void USART_WakeUpConfig(USART_TypeDef *USARTx, uint16_t USART_WakeUp); +void USART_ReceiverWakeUpCmd(USART_TypeDef *USARTx, FunctionalState NewState); +void USART_LINBreakDetectLengthConfig(USART_TypeDef *USARTx, uint16_t USART_LINBreakDetectLength); +void USART_LINCmd(USART_TypeDef *USARTx, FunctionalState NewState); +void USART_SendData(USART_TypeDef *USARTx, uint16_t Data); +uint16_t USART_ReceiveData(USART_TypeDef *USARTx); +void USART_SendBreak(USART_TypeDef *USARTx); +void USART_SetGuardTime(USART_TypeDef *USARTx, uint8_t USART_GuardTime); +void USART_SetPrescaler(USART_TypeDef *USARTx, uint8_t USART_Prescaler); +void USART_SmartCardCmd(USART_TypeDef *USARTx, FunctionalState NewState); +void USART_SmartCardNACKCmd(USART_TypeDef *USARTx, FunctionalState NewState); +void USART_HalfDuplexCmd(USART_TypeDef *USARTx, FunctionalState NewState); +void USART_OverSampling8Cmd(USART_TypeDef *USARTx, FunctionalState NewState); +void USART_OneBitMethodCmd(USART_TypeDef *USARTx, FunctionalState NewState); +void USART_IrDAConfig(USART_TypeDef *USARTx, uint16_t USART_IrDAMode); +void USART_IrDACmd(USART_TypeDef *USARTx, FunctionalState NewState); +FlagStatus USART_GetFlagStatus(USART_TypeDef *USARTx, uint16_t USART_FLAG); +void USART_ClearFlag(USART_TypeDef *USARTx, uint16_t USART_FLAG); +ITStatus USART_GetITStatus(USART_TypeDef *USARTx, uint16_t USART_IT); +void USART_ClearITPendingBit(USART_TypeDef *USARTx, uint16_t USART_IT); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/ZDBMS/BMS_MC/Peripheral/inc/ch32l103_usb.h b/ZDBMS/BMS_MC/Peripheral/inc/ch32l103_usb.h new file mode 100644 index 0000000..a3689f0 --- /dev/null +++ b/ZDBMS/BMS_MC/Peripheral/inc/ch32l103_usb.h @@ -0,0 +1,513 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32l103_usb.h + * Author : WCH + * Version : V1.0.0 + * Date : 2024/01/19 + * Description : This file contains all the functions prototypes for the USB + * firmware library. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#ifndef __CH32L103_USB_H +#define __CH32L103_USB_H + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef __cplusplus + extern "C" { +#endif + +/*******************************************************************************/ +/* Header File */ +#include "stdint.h" + +/*******************************************************************************/ +/* USB Communication Related Macro Definition */ + +/* USB Endpoint0 Size */ +#ifndef DEFAULT_ENDP0_SIZE +#define DEFAULT_ENDP0_SIZE 8 +#endif + +/* USB Buffer Size */ +#ifndef USBFS_MAX_PACKET_SIZE +#define USBFS_MAX_PACKET_SIZE 64 +#endif + +/* USB PID */ +#ifndef USB_PID_SETUP +#define USB_PID_NULL 0x00 +#define USB_PID_SOF 0x05 +#define USB_PID_SETUP 0x0D +#define USB_PID_IN 0x09 +#define USB_PID_OUT 0x01 +#define USB_PID_NYET 0x06 +#define USB_PID_ACK 0x02 +#define USB_PID_NAK 0x0A +#define USB_PID_STALL 0x0E +#define USB_PID_DATA0 0x03 +#define USB_PID_DATA1 0x0B +#define USB_PID_PRE 0x0C +#endif + +/* USB standard device request code */ +#ifndef USB_GET_DESCRIPTOR +#define USB_GET_STATUS 0x00 +#define USB_CLEAR_FEATURE 0x01 +#define USB_SET_FEATURE 0x03 +#define USB_SET_ADDRESS 0x05 +#define USB_GET_DESCRIPTOR 0x06 +#define USB_SET_DESCRIPTOR 0x07 +#define USB_GET_CONFIGURATION 0x08 +#define USB_SET_CONFIGURATION 0x09 +#define USB_GET_INTERFACE 0x0A +#define USB_SET_INTERFACE 0x0B +#define USB_SYNCH_FRAME 0x0C +#endif + +#define DEF_STRING_DESC_LANG 0x00 +#define DEF_STRING_DESC_MANU 0x01 +#define DEF_STRING_DESC_PROD 0x02 +#define DEF_STRING_DESC_SERN 0x03 + +/* USB hub class request code */ +#ifndef HUB_GET_DESCRIPTOR +#define HUB_GET_STATUS 0x00 +#define HUB_CLEAR_FEATURE 0x01 +#define HUB_GET_STATE 0x02 +#define HUB_SET_FEATURE 0x03 +#define HUB_GET_DESCRIPTOR 0x06 +#define HUB_SET_DESCRIPTOR 0x07 +#endif + +/* USB HID class request code */ +#ifndef HID_GET_REPORT +#define HID_GET_REPORT 0x01 +#define HID_GET_IDLE 0x02 +#define HID_GET_PROTOCOL 0x03 +#define HID_SET_REPORT 0x09 +#define HID_SET_IDLE 0x0A +#define HID_SET_PROTOCOL 0x0B +#endif + +/* Bit Define for USB Request Type */ +#ifndef USB_REQ_TYP_MASK +#define USB_REQ_TYP_IN 0x80 +#define USB_REQ_TYP_OUT 0x00 +#define USB_REQ_TYP_READ 0x80 +#define USB_REQ_TYP_WRITE 0x00 +#define USB_REQ_TYP_MASK 0x60 +#define USB_REQ_TYP_STANDARD 0x00 +#define USB_REQ_TYP_CLASS 0x20 +#define USB_REQ_TYP_VENDOR 0x40 +#define USB_REQ_TYP_RESERVED 0x60 +#define USB_REQ_RECIP_MASK 0x1F +#define USB_REQ_RECIP_DEVICE 0x00 +#define USB_REQ_RECIP_INTERF 0x01 +#define USB_REQ_RECIP_ENDP 0x02 +#define USB_REQ_RECIP_OTHER 0x03 +#define USB_REQ_FEAT_REMOTE_WAKEUP 0x01 +#define USB_REQ_FEAT_ENDP_HALT 0x00 +#endif + +/* USB Descriptor Type */ +#ifndef USB_DESCR_TYP_DEVICE +#define USB_DESCR_TYP_DEVICE 0x01 +#define USB_DESCR_TYP_CONFIG 0x02 +#define USB_DESCR_TYP_STRING 0x03 +#define USB_DESCR_TYP_INTERF 0x04 +#define USB_DESCR_TYP_ENDP 0x05 +#define USB_DESCR_TYP_QUALIF 0x06 +#define USB_DESCR_TYP_SPEED 0x07 +#define USB_DESCR_TYP_OTG 0x09 +#define USB_DESCR_TYP_BOS 0X0F +#define USB_DESCR_TYP_HID 0x21 +#define USB_DESCR_TYP_REPORT 0x22 +#define USB_DESCR_TYP_PHYSIC 0x23 +#define USB_DESCR_TYP_CS_INTF 0x24 +#define USB_DESCR_TYP_CS_ENDP 0x25 +#define USB_DESCR_TYP_HUB 0x29 +#endif + +/* USB Device Class */ +#ifndef USB_DEV_CLASS_HUB +#define USB_DEV_CLASS_RESERVED 0x00 +#define USB_DEV_CLASS_AUDIO 0x01 +#define USB_DEV_CLASS_COMMUNIC 0x02 +#define USB_DEV_CLASS_HID 0x03 +#define USB_DEV_CLASS_MONITOR 0x04 +#define USB_DEV_CLASS_PHYSIC_IF 0x05 +#define USB_DEV_CLASS_POWER 0x06 +#define USB_DEV_CLASS_IMAGE 0x06 +#define USB_DEV_CLASS_PRINTER 0x07 +#define USB_DEV_CLASS_STORAGE 0x08 +#define USB_DEV_CLASS_HUB 0x09 +#define USB_DEV_CLASS_VEN_SPEC 0xFF +#endif + +/* USB Hub Class Request */ +#ifndef HUB_GET_HUB_DESCRIPTOR +#define HUB_CLEAR_HUB_FEATURE 0x20 +#define HUB_CLEAR_PORT_FEATURE 0x23 +#define HUB_GET_BUS_STATE 0xA3 +#define HUB_GET_HUB_DESCRIPTOR 0xA0 +#define HUB_GET_HUB_STATUS 0xA0 +#define HUB_GET_PORT_STATUS 0xA3 +#define HUB_SET_HUB_DESCRIPTOR 0x20 +#define HUB_SET_HUB_FEATURE 0x20 +#define HUB_SET_PORT_FEATURE 0x23 +#endif + +/* Hub Class Feature Selectors */ +#ifndef HUB_PORT_RESET +#define HUB_C_HUB_LOCAL_POWER 0 +#define HUB_C_HUB_OVER_CURRENT 1 +#define HUB_PORT_CONNECTION 0 +#define HUB_PORT_ENABLE 1 +#define HUB_PORT_SUSPEND 2 +#define HUB_PORT_OVER_CURRENT 3 +#define HUB_PORT_RESET 4 +#define HUB_PORT_POWER 8 +#define HUB_PORT_LOW_SPEED 9 +#define HUB_C_PORT_CONNECTION 16 +#define HUB_C_PORT_ENABLE 17 +#define HUB_C_PORT_SUSPEND 18 +#define HUB_C_PORT_OVER_CURRENT 19 +#define HUB_C_PORT_RESET 20 +#endif + +/* USB HID Class Request Code */ +#ifndef HID_GET_REPORT +#define HID_GET_REPORT 0x01 +#define HID_GET_IDLE 0x02 +#define HID_GET_PROTOCOL 0x03 +#define HID_SET_REPORT 0x09 +#define HID_SET_IDLE 0x0A +#define HID_SET_PROTOCOL 0x0B +#endif + +/* USB CDC Class request code */ +#ifndef CDC_GET_LINE_CODING +#define CDC_GET_LINE_CODING 0x21 /* This request allows the host to find out the currently configured line coding */ +#define CDC_SET_LINE_CODING 0x20 /* Configures DTE rate, stop-bits, parity, and number-of-character */ +#define CDC_SET_LINE_CTLSTE 0x22 /* This request generates RS-232/V.24 style control signals */ +#define CDC_SEND_BREAK 0x23 /* Sends special carrier modulation used to specify RS-232 style break */ +#endif + +/* USB UDisk */ +#ifndef USB_BO_CBW_SIZE +#define USB_BO_CBW_SIZE 0x1F +#define USB_BO_CSW_SIZE 0x0D +#endif +#ifndef USB_BO_CBW_SIG0 +#define USB_BO_CBW_SIG0 0x55 +#define USB_BO_CBW_SIG1 0x53 +#define USB_BO_CBW_SIG2 0x42 +#define USB_BO_CBW_SIG3 0x43 +#define USB_BO_CSW_SIG0 0x55 +#define USB_BO_CSW_SIG1 0x53 +#define USB_BO_CSW_SIG2 0x42 +#define USB_BO_CSW_SIG3 0x53 +#endif + +/*******************************************************************************/ +/* USBFS Related Register Macro Definition */ + +/* R8_USB_CTRL */ +#define USBFS_UC_HOST_MODE 0x80 +#define USBFS_UC_LOW_SPEED 0x40 +#define USBFS_UC_SYS_CTRL_MASK 0x30 +#define USBFS_UC_SYS_CTRL0 0x00 +#define USBFS_UC_SYS_CTRL1 0x10 +#define USBFS_UC_SYS_CTRL2 0x20 +#define USBFS_UC_SYS_CTRL3 0x30 +#define USBFS_UC_DEV_PU_EN 0x20 +#define USBFS_UC_INT_BUSY 0x08 +#define USBFS_UC_RESET_SIE 0x04 +#define USBFS_UC_CLR_ALL 0x02 +#define USBFS_UC_DMA_EN 0x01 + +/* R8_USB_INT_EN */ +#define USBFS_UIE_DEV_NAK 0x40 +#define USBFS_UID_1_WIRE 0x20 +#define USBFS_UIE_FIFO_OV 0x10 +#define USBFS_UIE_HST_SOF 0x08 +#define USBFS_UIE_SUSPEND 0x04 +#define USBFS_UIE_TRANSFER 0x02 +#define USBFS_UIE_DETECT 0x01 +#define USBFS_UIE_BUS_RST 0x01 + +/* R8_USB_DEV_AD */ +#define USBFS_UDA_GP_BIT 0x80 +#define USBFS_USB_ADDR_MASK 0x7F + +/* R8_USB_MIS_ST */ +#define USBFS_UMS_SOF_PRES 0x80 +#define USBFS_UMS_SOF_ACT 0x40 +#define USBFS_UMS_SIE_FREE 0x20 +#define USBFS_UMS_R_FIFO_RDY 0x10 +#define USBFS_UMS_BUS_RESET 0x08 +#define USBFS_UMS_SUSPEND 0x04 +#define USBFS_UMS_DM_LEVEL 0x02 +#define USBFS_UMS_DEV_ATTACH 0x01 + +/* R8_USB_INT_FG */ +#define USBFS_U_IS_NAK 0x80 // RO, indicate current USB transfer is NAK received +#define USBFS_U_TOG_OK 0x40 // RO, indicate current USB transfer toggle is OK +#define USBFS_U_SIE_FREE 0x20 // RO, indicate USB SIE free status +#define USBFS_UIF_FIFO_OV 0x10 // FIFO overflow interrupt flag for USB, direct bit address clear or write 1 to clear +#define USBFS_UIF_HST_SOF 0x08 // host SOF timer interrupt flag for USB host, direct bit address clear or write 1 to clear +#define USBFS_UIF_SUSPEND 0x04 // USB suspend or resume event interrupt flag, direct bit address clear or write 1 to clear +#define USBFS_UIF_TRANSFER 0x02 // USB transfer completion interrupt flag, direct bit address clear or write 1 to clear +#define USBFS_UIF_DETECT 0x01 // device detected event interrupt flag for USB host mode, direct bit address clear or write 1 to clear +#define USBFS_UIF_BUS_RST 0x01 // bus reset event interrupt flag for USB device mode, direct bit address clear or write 1 to clear + +/* R8_USB_INT_ST */ +#define USBFS_SETUP_ACT 0x80 // RO, indicate current SETUP transaction completed +#define USBFS_UIS_TOG_OK 0x40 // RO, indicate current USB transfer toggle is OK +#define USBFS_UIS_TOKEN_MASK 0x30 // RO, bit mask of current token PID code received for USB device mode +#define USBFS_UIS_TOKEN_OUT 0x00 +#define USBFS_UIS_TOKEN_IN 0x20 +#define USBFS_UIS_TOKEN_SETUP 0x30 +// bUIS_TOKEN1 & bUIS_TOKEN0: current token PID code received for USB device mode +// 00: OUT token PID received +// 10: IN token PID received +// 11: SETUP token PID received +#define USBFS_UIS_ENDP_MASK 0x0F // RO, bit mask of current transfer endpoint number for USB device mode +#define USBFS_UIS_H_RES_MASK 0x0F // RO, bit mask of current transfer handshake response for USB host mode: 0000=no response, time out from device, others=handshake response PID received + +/* R8_UDEV_CTRL */ +#define USBFS_UD_PD_DIS 0x80 // disable USB UDP/UDM pulldown resistance: 0=enable pulldown, 1=disable +#define USBFS_UD_DP_PIN 0x20 // ReadOnly: indicate current UDP pin level +#define USBFS_UD_DM_PIN 0x10 // ReadOnly: indicate current UDM pin level +#define USBFS_UD_LOW_SPEED 0x04 // enable USB physical port low speed: 0=full speed, 1=low speed +#define USBFS_UD_GP_BIT 0x02 // general purpose bit +#define USBFS_UD_PORT_EN 0x01 // enable USB physical port I/O: 0=disable, 1=enable + +/* R8_UEP4_1_MOD */ +#define USBFS_UEP1_RX_EN 0x80 // enable USB endpoint 1 receiving (OUT) +#define USBFS_UEP1_TX_EN 0x40 // enable USB endpoint 1 transmittal (IN) +#define USBFS_UEP1_BUF_MOD 0x10 // buffer mode of USB endpoint 1 +#define USBFS_UEP4_RX_EN 0x08 // enable USB endpoint 4 receiving (OUT) +#define USBFS_UEP4_TX_EN 0x04 // enable USB endpoint 4 transmittal (IN) +#define USBFS_UEP4_BUF_MOD 0x01 + +/* R8_UEP2_3_MOD */ +#define USBFS_UEP3_RX_EN 0x80 // enable USB endpoint 3 receiving (OUT) +#define USBFS_UEP3_TX_EN 0x40 // enable USB endpoint 3 transmittal (IN) +#define USBFS_UEP3_BUF_MOD 0x10 // buffer mode of USB endpoint 3 +#define USBFS_UEP2_RX_EN 0x08 // enable USB endpoint 2 receiving (OUT) +#define USBFS_UEP2_TX_EN 0x04 // enable USB endpoint 2 transmittal (IN) +#define USBFS_UEP2_BUF_MOD 0x01 // buffer mode of USB endpoint 2 + +/* R8_UEP5_6_MOD */ +#define USBFS_UEP6_RX_EN 0x80 // enable USB endpoint 6 receiving (OUT) +#define USBFS_UEP6_TX_EN 0x40 // enable USB endpoint 6 transmittal (IN) +#define USBFS_UEP6_BUF_MOD 0x10 // buffer mode of USB endpoint 6 +#define USBFS_UEP5_RX_EN 0x08 // enable USB endpoint 5 receiving (OUT) +#define USBFS_UEP5_TX_EN 0x04 // enable USB endpoint 5 transmittal (IN) +#define USBFS_UEP5_BUF_MOD 0x01 // buffer mode of USB endpoint 5 + +/* R8_UEP7_MOD */ +#define USBFS_UEP7_RX_EN 0x08 // enable USB endpoint 7 receiving (OUT) +#define USBFS_UEP7_TX_EN 0x04 // enable USB endpoint 7 transmittal (IN) +#define USBFS_UEP7_BUF_MOD 0x01 // buffer mode of USB endpoint 7 + +/* R8_UEPn_TX_CTRL */ +#define USBFS_UEP_T_AUTO_TOG 0x08 // enable automatic toggle after successful transfer completion on endpoint 1/2/3: 0=manual toggle, 1=automatic toggle +#define USBFS_UEP_T_TOG 0x04 // prepared data toggle flag of USB endpoint X transmittal (IN): 0=DATA0, 1=DATA1 +#define USBFS_UEP_T_RES_MASK 0x03 // bit mask of handshake response type for USB endpoint X transmittal (IN) +#define USBFS_UEP_T_RES_ACK 0x00 +#define USBFS_UEP_T_RES_NONE 0x01 +#define USBFS_UEP_T_RES_NAK 0x02 +#define USBFS_UEP_T_RES_STALL 0x03 +// bUEP_T_RES1 & bUEP_T_RES0: handshake response type for USB endpoint X transmittal (IN) +// 00: DATA0 or DATA1 then expecting ACK (ready) +// 01: DATA0 or DATA1 then expecting no response, time out from host, for non-zero endpoint isochronous transactions +// 10: NAK (busy) +// 11: STALL (error) +// host aux setup + +/* R8_UEPn_RX_CTRL, n=0-7 */ +#define USBFS_UEP_R_AUTO_TOG 0x08 // enable automatic toggle after successful transfer completion on endpoint 1/2/3: 0=manual toggle, 1=automatic toggle +#define USBFS_UEP_R_TOG 0x04 // expected data toggle flag of USB endpoint X receiving (OUT): 0=DATA0, 1=DATA1 +#define USBFS_UEP_R_RES_MASK 0x03 // bit mask of handshake response type for USB endpoint X receiving (OUT) +#define USBFS_UEP_R_RES_ACK 0x00 +#define USBFS_UEP_R_RES_NONE 0x01 +#define USBFS_UEP_R_RES_NAK 0x02 +#define USBFS_UEP_R_RES_STALL 0x03 +// RB_UEP_R_RES1 & RB_UEP_R_RES0: handshake response type for USB endpoint X receiving (OUT) +// 00: ACK (ready) +// 01: no response, time out to host, for non-zero endpoint isochronous transactions +// 10: NAK (busy) +// 11: STALL (error) + +/* R8_UHOST_CTRL */ +#define USBFS_UH_PD_DIS 0x80 // disable USB UDP/UDM pulldown resistance: 0=enable pulldown, 1=disable +#define USBFS_UH_DP_PIN 0x20 // ReadOnly: indicate current UDP pin level +#define USBFS_UH_DM_PIN 0x10 // ReadOnly: indicate current UDM pin level +#define USBFS_UH_LOW_SPEED 0x04 // enable USB port low speed: 0=full speed, 1=low speed +#define USBFS_UH_BUS_RESET 0x02 // control USB bus reset: 0=normal, 1=force bus reset +#define USBFS_UH_PORT_EN 0x01 // enable USB port: 0=disable, 1=enable port, automatic disabled if USB device detached + +/* R32_UH_EP_MOD */ +#define USBFS_UH_EP_TX_EN 0x40 // enable USB host OUT endpoint transmittal +#define USBFS_UH_EP_TBUF_MOD 0x10 // buffer mode of USB host OUT endpoint +#define USBFS_UH_EP_RX_EN 0x08 // enable USB host IN endpoint receiving +#define USBFS_UH_EP_RBUF_MOD 0x01 // buffer mode of USB host IN endpoint + +/* R16_UH_SETUP */ +#define USBFS_UH_PRE_PID_EN 0x0400 // USB host PRE PID enable for low speed device via hub +#define USBFS_UH_SOF_EN 0x0004 // USB host automatic SOF enable + +/* R8_UH_EP_PID */ +#define USBFS_UH_TOKEN_MASK 0xF0 // bit mask of token PID for USB host transfer +#define USBFS_UH_ENDP_MASK 0x0F // bit mask of endpoint number for USB host transfer + +/* R8_UH_RX_CTRL */ +#define USBFS_UH_R_AUTO_TOG 0x08 // enable automatic toggle after successful transfer completion: 0=manual toggle, 1=automatic toggle +#define USBFS_UH_R_TOG 0x04 // expected data toggle flag of host receiving (IN): 0=DATA0, 1=DATA1 +#define USBFS_UH_R_RES 0x01 // prepared handshake response type for host receiving (IN): 0=ACK (ready), 1=no response, time out to device, for isochronous transactions + +/* R8_UH_TX_CTRL */ +#define USBFS_UH_T_AUTO_TOG 0x08 // enable automatic toggle after successful transfer completion: 0=manual toggle, 1=automatic toggle +#define USBFS_UH_T_TOG 0x04 // prepared data toggle flag of host transmittal (SETUP/OUT): 0=DATA0, 1=DATA1 +#define USBFS_UH_T_RES 0x01 // expected handshake response type for host transmittal (SETUP/OUT): 0=ACK (ready), 1=no response, time out from device, for isochronous transactions + +/*******************************************************************************/ +/* Struct Definition */ + +/* USB Setup Request */ +typedef struct __attribute__((packed)) _USB_SETUP_REQ +{ + uint8_t bRequestType; + uint8_t bRequest; + uint16_t wValue; + uint16_t wIndex; + uint16_t wLength; +} USB_SETUP_REQ, *PUSB_SETUP_REQ; + +/* USB Device Descriptor */ +typedef struct __attribute__((packed)) _USB_DEVICE_DESCR +{ + uint8_t bLength; + uint8_t bDescriptorType; + uint16_t bcdUSB; + uint8_t bDeviceClass; + uint8_t bDeviceSubClass; + uint8_t bDeviceProtocol; + uint8_t bMaxPacketSize0; + uint16_t idVendor; + uint16_t idProduct; + uint16_t bcdDevice; + uint8_t iManufacturer; + uint8_t iProduct; + uint8_t iSerialNumber; + uint8_t bNumConfigurations; +} USB_DEV_DESCR, *PUSB_DEV_DESCR; + +/* USB Configuration Descriptor */ +typedef struct __attribute__((packed)) _USB_CONFIG_DESCR +{ + uint8_t bLength; + uint8_t bDescriptorType; + uint16_t wTotalLength; + uint8_t bNumInterfaces; + uint8_t bConfigurationValue; + uint8_t iConfiguration; + uint8_t bmAttributes; + uint8_t MaxPower; +} USB_CFG_DESCR, *PUSB_CFG_DESCR; + +/* USB Interface Descriptor */ +typedef struct __attribute__((packed)) _USB_INTERF_DESCR +{ + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bInterfaceNumber; + uint8_t bAlternateSetting; + uint8_t bNumEndpoints; + uint8_t bInterfaceClass; + uint8_t bInterfaceSubClass; + uint8_t bInterfaceProtocol; + uint8_t iInterface; +} USB_ITF_DESCR, *PUSB_ITF_DESCR; + +/* USB Endpoint Descriptor */ +typedef struct __attribute__((packed)) _USB_ENDPOINT_DESCR +{ + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bEndpointAddress; + uint8_t bmAttributes; + uint8_t wMaxPacketSizeL; + uint8_t wMaxPacketSizeH; + uint8_t bInterval; +} USB_ENDP_DESCR, *PUSB_ENDP_DESCR; + +/* USB Configuration Descriptor Set */ +typedef struct __attribute__((packed)) _USB_CONFIG_DESCR_LONG +{ + USB_CFG_DESCR cfg_descr; + USB_ITF_DESCR itf_descr; + USB_ENDP_DESCR endp_descr[ 1 ]; +} USB_CFG_DESCR_LONG, *PUSB_CFG_DESCR_LONG; + +/* USB HUB Descriptor */ +typedef struct __attribute__((packed)) _USB_HUB_DESCR +{ + uint8_t bDescLength; + uint8_t bDescriptorType; + uint8_t bNbrPorts; + uint8_t wHubCharacteristicsL; + uint8_t wHubCharacteristicsH; + uint8_t bPwrOn2PwrGood; + uint8_t bHubContrCurrent; + uint8_t DeviceRemovable; + uint8_t PortPwrCtrlMask; +} USB_HUB_DESCR, *PUSB_HUB_DESCR; + +/* USB HID Descriptor */ +typedef struct __attribute__((packed)) _USB_HID_DESCR +{ + uint8_t bLength; + uint8_t bDescriptorType; + uint16_t bcdHID; + uint8_t bCountryCode; + uint8_t bNumDescriptors; + uint8_t bDescriptorTypeX; + uint8_t wDescriptorLengthL; + uint8_t wDescriptorLengthH; +} USB_HID_DESCR, *PUSB_HID_DESCR; + +/* USB UDisk */ +typedef struct __attribute__((packed)) _UDISK_BOC_CBW +{ + uint32_t mCBW_Sig; + uint32_t mCBW_Tag; + uint32_t mCBW_DataLen; + uint8_t mCBW_Flag; + uint8_t mCBW_LUN; + uint8_t mCBW_CB_Len; + uint8_t mCBW_CB_Buf[ 16 ]; +} UDISK_BOC_CBW, *PXUDISK_BOC_CBW; + +/* USB UDisk */ +typedef struct __attribute__((packed)) _UDISK_BOC_CSW +{ + uint32_t mCBW_Sig; + uint32_t mCBW_Tag; + uint32_t mCSW_Residue; + uint8_t mCSW_Status; +} UDISK_BOC_CSW, *PXUDISK_BOC_CSW; + + +#ifdef __cplusplus +} +#endif + +#endif /*_CH32L103_USB_H */ diff --git a/ZDBMS/BMS_MC/Peripheral/inc/ch32l103_usbpd.h b/ZDBMS/BMS_MC/Peripheral/inc/ch32l103_usbpd.h new file mode 100644 index 0000000..f95caba --- /dev/null +++ b/ZDBMS/BMS_MC/Peripheral/inc/ch32l103_usbpd.h @@ -0,0 +1,408 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32l103_can.h + * Author : WCH + * Version : V1.0.0 + * Date : 2023/07/08 + * Description : This file contains all the functions prototypes for the + * CAN firmware library. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#ifndef __CH32L103_USBPD_H +#define __CH32L103_USBPD_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "ch32l103.h" + +#ifndef VOID +#define VOID void +#endif +#ifndef CONST +#define CONST const +#endif +#ifndef BOOL +typedef unsigned char BOOL; +#endif +#ifndef BOOLEAN +typedef unsigned char BOOLEAN; +#endif +#ifndef CHAR +typedef char CHAR; +#endif +#ifndef INT8 +typedef char INT8; +#endif +#ifndef INT16 +typedef short INT16; +#endif +#ifndef INT32 +typedef long INT32; +#endif +#ifndef UINT8 +typedef unsigned char UINT8; +#endif +#ifndef UINT16 +typedef unsigned short UINT16; +#endif +#ifndef UINT32 +typedef unsigned long UINT32; +#endif +#ifndef UINT8V +typedef unsigned char volatile UINT8V; +#endif +#ifndef UINT16V +typedef unsigned short volatile UINT16V; +#endif +#ifndef UINT32V +typedef unsigned long volatile UINT32V; +#endif + +#ifndef PVOID +typedef void *PVOID; +#endif +#ifndef PCHAR +typedef char *PCHAR; +#endif +#ifndef PCHAR +typedef const char *PCCHAR; +#endif +#ifndef PINT8 +typedef char *PINT8; +#endif +#ifndef PINT16 +typedef short *PINT16; +#endif +#ifndef PINT32 +typedef long *PINT32; +#endif +#ifndef PUINT8 +typedef unsigned char *PUINT8; +#endif +#ifndef PUINT16 +typedef unsigned short *PUINT16; +#endif +#ifndef PUINT32 +typedef unsigned long *PUINT32; +#endif +#ifndef PUINT8V +typedef volatile unsigned char *PUINT8V; +#endif +#ifndef PUINT16V +typedef volatile unsigned short *PUINT16V; +#endif +#ifndef PUINT32V +typedef volatile unsigned long *PUINT32V; +#endif + + /******************************************************************************/ +/* Related macro definitions */ + +/* Define the return value of the function */ +#ifndef SUCCESS +#define SUCCESS 0 +#endif +#ifndef FAIL +#define FAIL 0xFF +#endif + +/* Register Bit Definition */ +/* USBPD->CONFIG */ +#define PD_FILT_ED (1<<0) /* PD pin input filter enable */ +#define PD_ALL_CLR (1<<1) /* Clear all interrupt flags */ +#define CC_SEL (1<<2) /* Select PD communication port */ +#define PD_DMA_EN (1<<3) /* Enable DMA for USBPD */ +#define PD_RST_EN (1<<4) /* PD mode reset command enable */ +#define WAKE_POLAR (1<<5) /* PD port wake-up level */ +#define IE_PD_IO (1<<10) /* PD IO interrupt enable */ +#define IE_RX_BIT (1<<11) /* Receive bit interrupt enable */ +#define IE_RX_BYTE (1<<12) /* Receive byte interrupt enable */ +#define IE_RX_ACT (1<<13) /* Receive completion interrupt enable */ +#define IE_RX_RESET (1<<14) /* Reset interrupt enable */ +#define IE_TX_END (1<<15) /* Transfer completion interrupt enable */ + +/* USBPD->CONTROL */ +#define PD_TX_EN (1<<0) /* USBPD transceiver mode and transmit enable */ +#define BMC_START (1<<1) /* BMC send start signal */ +#define RX_STATE_0 (1<<2) /* PD received state bit 0 */ +#define RX_STATE_1 (1<<3) /* PD received state bit 1 */ +#define RX_STATE_2 (1<<4) /* PD received state bit 2 */ +#define DATA_FLAG (1<<5) /* Cache data valid flag bit */ +#define TX_BIT_BACK (1<<6) /* Indicates the current bit status of the BMC when sending the code */ +#define BMC_BYTE_HI (1<<7) /* Indicates the current half-byte status of the PD data being sent and received */ + +/* USBPD->TX_SEL */ +#define TX_SEL1 (0<<0) +#define TX_SEL1_SYNC1 (0<<0) /* 0-SYNC1 */ +#define TX_SEL1_RST1 (1<<0) /* 1-RST1 */ +#define TX_SEL2_Mask (3<<2) +#define TX_SEL2_SYNC1 (0<<2) /* 00-SYNC1 */ +#define TX_SEL2_SYNC3 (1<<2) /* 01-SYNC3 */ +#define TX_SEL2_RST1 (2<<2) /* 1x-RST1 */ +#define TX_SEL3_Mask (3<<4) +#define TX_SEL3_SYNC1 (0<<4) /* 00-SYNC1 */ +#define TX_SEL3_SYNC3 (1<<4) /* 01-SYNC3 */ +#define TX_SEL3_RST1 (2<<4) /* 1x-RST1 */ +#define TX_SEL4_Mask (3<<6) +#define TX_SEL4_SYNC2 (0<<6) /* 00-SYNC2 */ +#define TX_SEL4_SYNC3 (1<<6) /* 01-SYNC3 */ +#define TX_SEL4_RST2 (2<<6) /* 1x-RST2 */ + +/* USBPD->STATUS */ +#define BMC_AUX (3<<0) /* BMC auxiliary information */ +#define BMC_AUX_INVALID (0<<0) /* 00-Invalid */ +#define BMC_AUX_SOP0 (1<<0) /* 01-SOP0 */ +#define BMC_AUX_SOP1_HRST (2<<0) /* 10-SOP1 hard reset */ +#define BMC_AUX_SOP2_CRST (3<<0) /* 11-SOP2 cable reset */ +#define BUF_ERR (1<<2) /* BUFFER or DMA error interrupt flag */ +#define IF_RX_BIT (1<<3) /* Receive bit or 5bit interrupt flag */ +#define IF_RX_BYTE (1<<4) /* Receive byte or SOP interrupt flag */ +#define IF_RX_ACT (1<<5) /* Receive completion interrupt flag */ +#define IF_RX_RESET (1<<6) /* Receive reset interrupt flag */ +#define IF_TX_END (1<<7) /* Transfer completion interrupt flag */ + +/* USBPD->PORT_CC1 */ +/* USBPD->PORT_CC2 */ +#define PA_CC_AI (1<<0) /* CC port comparator analogue input */ +#define CC_PD (1<<1) /* CC port pull-down resistor enable */ +#define CC_PU_Mask (3<<2) /* Clear CC port pull-up current */ +#define CC_NO_PU (0<<2) /* 00-Prohibit pull-up current */ +#define CC_PU_330 (1<<2) /* 01-330uA */ +#define CC_PU_180 (2<<2) /* 10-180uA */ +#define CC_PU_80 (3<<2) /* 11-80uA */ +#define CC_LVE (1<<4) /* CC port output low voltage enable */ +#define CC_CE (7<<5) /* Enable the voltage comparator on port CC */ +#define CC_NO_CMP (0<<5) /* 000-closed */ +#define CC_CMP_22 (2<<5) /* 010-0.22V */ +#define CC_CMP_45 (3<<5) /* 011-0.45V */ +#define CC_CMP_55 (4<<5) /* 100-0.55V */ +#define CC_CMP_66 (5<<5) /* 101-0.66V */ +#define CC_CMP_95 (6<<5) /* 110-0.95V */ +#define CC_CMP_123 (7<<5) /* 111-1.23V */ + +#define USBPD_IN_HVT (1<<9) +/********************************************************* +* PD pin PB6/PB7 high threshold input mode: +* 1: High threshold input (2.2V typical), to reduce the I/O power consumption during PD communication +* 0: Normal GPIO threshold input +* *******************************************************/ + +/* Control Message Types */ +#define DEF_TYPE_RESERVED 0x00 +#define DEF_TYPE_GOODCRC 0x01 /* Send By: Source,Sink,Cable Plug */ +#define DEF_TYPE_GOTOMIN 0x02 /* Send By: Source */ +#define DEF_TYPE_ACCEPT 0x03 /* Send By: Source,Sink,Cable Plug */ +#define DEF_TYPE_REJECT 0x04 /* Send By: Source,Sink,Cable Plug */ +#define DEF_TYPE_PING 0x05 /* Send By: Source */ +#define DEF_TYPE_PS_RDY 0x06 /* Send By: Source,Sink */ +#define DEF_TYPE_GET_SRC_CAP 0x07 /* Send By: Sink,DRP */ +#define DEF_TYPE_GET_SNK_CAP 0x08 /* Send By: Source,DRP */ +#define DEF_TYPE_DR_SWAP 0x09 /* Send By: Source,Sink */ +#define DEF_TYPE_PR_SWAP 0x0A /* Send By: Source,Sink */ +#define DEF_TYPE_VCONN_SWAP 0x0B /* Send By: Source,Sink */ +#define DEF_TYPE_WAIT 0x0C /* Send By: Source,Sink */ +#define DEF_TYPE_SOFT_RESET 0x0D /* Send By: Source,Sink */ +#define DEF_TYPE_DATA_RESET 0x0E /* Send By: Source,Sink */ +#define DEF_TYPE_DATA_RESET_CMP 0x0F /* Send By: Source,Sink */ +#define DEF_TYPE_NOT_SUPPORT 0x10 /* Send By: Source,Sink,Cable Plug */ +#define DEF_TYPE_GET_SRC_CAP_EX 0x11 /* Send By: Sink,DRP */ +#define DEF_TYPE_GET_STATUS 0x12 /* Send By: Source,Sink */ +#define DEF_TYPE_GET_STATUS_R 0X02 /* ext=1 */ +#define DEF_TYPE_FR_SWAP 0x13 /* Send By: Sink */ +#define DEF_TYPE_GET_PPS_STATUS 0x14 /* Send By: Sink */ +#define DEF_TYPE_GET_CTY_CODES 0x15 /* Send By: Source,Sink */ +#define DEF_TYPE_GET_SNK_CAP_EX 0x16 /* Send By: Source,DRP */ +#define DEF_TYPE_GET_SRC_INFO 0x17 /* Send By: Sink,DRP */ +#define DEF_TYPE_GET_REVISION 0x18 /* Send By: Source,Sink */ + +/* Data Message Types */ +#define DEF_TYPE_SRC_CAP 0x01 /* Send By: Source,Dual-Role Power */ +#define DEF_TYPE_REQUEST 0x02 /* Send By: Sink */ +#define DEF_TYPE_BIST 0x03 /* Send By: Tester,Source,Sink */ +#define DEF_TYPE_SNK_CAP 0x04 /* Send By: Sink,Dual-Role Power */ +#define DEF_TYPE_BAT_STATUS 0x05 /* Send By: Source,Sink */ +#define DEF_TYPE_ALERT 0x06 /* Send By: Source,Sink */ +#define DEF_TYPE_GET_CTY_INFO 0x07 /* Send By: Source,Sink */ +#define DEF_TYPE_ENTER_USB 0x08 /* Send By: DFP */ +#define DEF_TYPE_EPR_REQUEST 0x09 /* Send By: Sink */ +#define DEF_TYPE_EPR_MODE 0x0A /* Send By: Source,Sink */ +#define DEF_TYPE_SRC_INFO 0x0B /* Send By: Source */ +#define DEF_TYPE_REVISION 0x0C /* Send By: Source,Sink,Cable Plug */ +#define DEF_TYPE_VENDOR_DEFINED 0x0F /* Send By: Source,Sink,Cable Plug */ + +/* Vendor Define Message Command */ +#define DEF_VDM_DISC_IDENT 0x01 +#define DEF_VDM_DISC_SVID 0x02 +#define DEF_VDM_DISC_MODE 0x03 +#define DEF_VDM_ENTER_MODE 0x04 +#define DEF_VDM_EXIT_MODE 0x05 +#define DEF_VDM_ATTENTION 0x06 +#define DEF_VDM_DP_S_UPDATE 0x10 +#define DEF_VDM_DP_CONFIG 0x11 + +/* PD Revision */ +#define DEF_PD_REVISION_10 0x00 +#define DEF_PD_REVISION_20 0x01 +#define DEF_PD_REVISION_30 0x02 + + +/* PD PHY Channel */ +#define DEF_PD_CC1 0x00 +#define DEF_PD_CC2 0x01 + +#define PIN_CC1 GPIO_Pin_6 +#define PIN_CC2 GPIO_Pin_7 + +/* PD Tx Status */ +#define DEF_PD_TX_OK 0x00 +#define DEF_PD_TX_FAIL 0x01 + +/* PDO INDEX */ +#define PDO_INDEX_1 1 +#define PDO_INDEX_2 2 +#define PDO_INDEX_3 3 +#define PDO_INDEX_4 4 +#define PDO_INDEX_5 5 + +/******************************************************************************/ +#define UPD_TMR_TX_96M (160-1) /* timer value for USB PD BMC transmittal @Fsys=96MHz */ +#define UPD_TMR_RX_96M (240-1) /* timer value for USB PD BMC receiving @Fsys=96MHz */ +#define UPD_TMR_TX_48M (80-1) /* timer value for USB PD BMC transmittal @Fsys=48MHz */ +#define UPD_TMR_RX_48M (120-1) /* timer value for USB PD BMC receiving @Fsys=48MHz */ +#define UPD_TMR_TX_24M (40-1) /* timer value for USB PD BMC transmittal @Fsys=24MHz */ +#define UPD_TMR_RX_24M (60-1) /* timer value for USB PD BMC receiving @Fsys=24MHz */ +#define UPD_TMR_TX_12M (20-1) /* timer value for USB PD BMC transmittal @Fsys=12MHz */ +#define UPD_TMR_RX_12M (30-1) /* timer value for USB PD BMC receiving @Fsys=12MHz */ + +#define MASK_PD_STAT 0x03 /* Bit mask for current PD status */ +#define PD_RX_SOP0 0x01 /* SOP0 received */ +#define PD_RX_SOP1_HRST 0x02 /* SOP1 or Hard Reset received */ +#define PD_RX_SOP2_CRST 0x03 /* SOP2 or Cable Reset received */ + +#define UPD_SOP0 ( TX_SEL1_SYNC1 | TX_SEL2_SYNC1 | TX_SEL3_SYNC1 | TX_SEL4_SYNC2 ) /* SOP1 */ +#define UPD_SOP1 ( TX_SEL1_SYNC1 | TX_SEL2_SYNC1 | TX_SEL3_SYNC3 | TX_SEL4_SYNC3 ) /* SOP2 */ +#define UPD_SOP2 ( TX_SEL1_SYNC1 | TX_SEL2_SYNC3 | TX_SEL3_SYNC1 | TX_SEL4_SYNC3 ) /* SOP3 */ +#define UPD_HARD_RESET ( TX_SEL1_RST1 | TX_SEL2_RST1 | TX_SEL3_RST1 | TX_SEL4_RST2 ) /* Hard Reset*/ +#define UPD_CABLE_RESET ( TX_SEL1_RST1 | TX_SEL2_SYNC1 | TX_SEL3_RST1 | TX_SEL4_SYNC3 ) /* Cable Reset*/ + + +#define bCC_CMP_22 0X01 +#define bCC_CMP_45 0X02 +#define bCC_CMP_55 0X04 +#define bCC_CMP_66 0X08 +#define bCC_CMP_95 0X10 +#define bCC_CMP_123 0X20 +#define bCC_CMP_220 0X40 + +/******************************************************************************/ +/* PD State Machine */ +typedef enum +{ + STA_IDLE = 0, /* 0: No task status */ + STA_DISCONNECT, /* 1: Disconnection */ + STA_SRC_CONNECT, /* 2: SRC connect */ + STA_RX_SRC_CAP_WAIT, /* 3: Waiting to receive SRC_CAP */ + STA_RX_SRC_CAP, /* 4: SRC_CAP received */ + STA_TX_REQ, /* 5: Send REQUEST */ + STA_RX_ACCEPT_WAIT, /* 6: Waiting to receive ACCEPT */ + STA_RX_ACCEPT, /* 7: ACCEPT received */ + STA_RX_REJECT, /* 8: REJECT received */ + STA_RX_PS_RDY_WAIT, /* 9: Waiting to receive PS_RDY */ + STA_RX_PS_RDY, /* 10: PS_RDY received */ + STA_SINK_CONNECT, /* 11: SNK access */ + STA_TX_SRC_CAP, /* 12: Send SRC_CAP */ + STA_RX_REQ_WAIT, /* 13: Waiting to receive REQUEST */ + STA_RX_REQ, /* 14: REQUEST received */ + STA_TX_ACCEPT, /* 15: Send ACCEPT */ + STA_TX_REJECT, /* 16: Send REJECT */ + STA_ADJ_VOL, /* 17: Adjustment of output voltage and current */ + STA_TX_PS_RDY, /* 18: Send PS_RDY */ + STA_TX_DR_SWAP, /* 19: Send DR_SWAP */ + STA_RX_DR_SWAP_ACCEPT, /* 20: Waiting to receive the answer ACCEPT from DR_SWAP */ + STA_TX_PR_SWAP, /* 21: Send PR_SWAP */ + STA_RX_PR_SWAP_ACCEPT, /* 22: Waiting to receive the answer ACCEPT from PR_SWAP */ + STA_RX_PR_SWAP_PS_RDY, /* 23: Waiting to receive the answer PS_RDY from PR_SWAP */ + STA_TX_PR_SWAP_PS_RDY, /* 24: Send answer PS_RDY for PR_SWAP */ + STA_PR_SWAP_RECON_WAIT, /* 25: Wait for PR_SWAP before reconnecting */ + STA_SRC_RECON_WAIT, /* 26: Waiting for SRC to reconnect */ + STA_SINK_RECON_WAIT, /* 27: Waiting for SNK to reconnect */ + STA_RX_APD_PS_RDY_WAIT, /* 28: Waiting for PS_RDY from the receiving adapter */ + STA_RX_APD_PS_RDY, /* 29: PS_RDY received from the adapter */ + STA_MODE_SWITCH, /* 30: Mode switching */ + STA_TX_SOFTRST, /* 31: Sending a software reset */ + STA_TX_HRST, /* 32: Send hardware reset */ + STA_PHY_RST, /* 33: PHY reset */ + STA_APD_IDLE_WAIT, /* 34: Waiting for the adapter to become idle */ +} CC_STATUS; + +/******************************************************************************/ +/* PD Message Header Struct */ +typedef union +{ + struct _Message_Header + { + UINT8 MsgType: 5; /* Message Type */ + UINT8 PDRole: 1; /* 0-UFP; 1-DFP */ + UINT8 SpecRev: 2; /* 00-Rev1.0; 01-Rev2.0; 10-Rev3.0; */ + UINT8 PRRole: 1; /* 0-Sink; 1-Source */ + UINT8 MsgID: 3; + UINT8 NumDO: 3; + UINT8 Ext: 1; + }Message_Header; + UINT16 Data; +}_Message_Header; + +/******************************************************************************/ +/* Bit definition */ +typedef union +{ + struct _BITS_ + { + UINT8 Msg_Recvd: 1; /* Notify the main program of the receipt of a PD packet */ + UINT8 Connected: 1; /* PD Physical Layer Connected Flag */ + UINT8 Stop_Det_Chk: 1; /* 0-Enable detection; 1-Disable disconnection detection */ + UINT8 PD_Role: 1; /* 0-UFP; 1-DFP */ + UINT8 PR_Role: 1; /* 0-Sink; 1-Source */ + UINT8 Auto_Ack_PRRole: 1; /* Role used by auto-responder 0:SINK; 1:SOURCE */ + UINT8 PD_Version: 1; /* PD version 0-PD2.0; 1-PD3.0 */ + UINT8 VDM_Version: 1; /* VDM Version 0-1.0 1-2.0 */ + UINT8 HPD_Connected: 1; /* HPD Physical Layer Connected Flag */ + UINT8 HPD_Det_Chk: 1; /* 0-turn off HPD connection detection; 1-turn on HPD connection detection */ + UINT8 CC_Sel_En: 1; /* 0-CC channel selection toggle enable; 1-CC channel selection toggle disable */ + UINT8 CC_Sel_State: 1; /* 0-CC channel selection switches to 0; 1-CC channel selection switches to 1 */ + UINT8 PD_Comm_Succ: 1; /* 0-PD communication unsuccessful; 1-PD communication successful; */ + UINT8 Recv: 3; + }Bit; + UINT16 Bit_Flag; +}_BIT_FLAG; + +/* PD control-related structures */ +typedef struct _PD_CONTROL +{ + CC_STATUS PD_State; /* PD communication status machine */ + CC_STATUS PD_State_Last; /* PD communication status machine (last value) */ + UINT8 Msg_ID; /* ID of the message sent */ + UINT8 Det_Timer; /* PD connection status detection timing */ + UINT8 Det_Cnt; /* Number of PD connection status detections */ + UINT8 Det_Sel_Cnt; /* Number of SEL toggles for PD connection status detection */ + UINT8 HPD_Det_Timer; /* HPD connection detection timing */ + UINT8 HPD_Det_Cnt; /* HPD pin connection status detection count */ + UINT16 PD_Comm_Timer; /* PD shared timing variables */ + UINT8 ReqPDO_Idx; /* Index of the requested PDO, valid values 1-7 */ + UINT16 PD_BusIdle_Timer; /* Bus Idle Time Timer */ + UINT8 Mode_Try_Cnt; /* Number of retries for current mode, highest bit marks mode */ + UINT8 Err_Op_Cnt; /* Exception operation count */ + UINT8 Adapter_Idle_Cnt; /* Adapter communication idle timing */ + _BIT_FLAG Flag; /* Flag byte bit definition */ +}PD_CONTROL, *pPD_CONTROL; + + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/ZDBMS/BMS_MC/Peripheral/inc/ch32l103_wwdg.h b/ZDBMS/BMS_MC/Peripheral/inc/ch32l103_wwdg.h new file mode 100644 index 0000000..a97fe3f --- /dev/null +++ b/ZDBMS/BMS_MC/Peripheral/inc/ch32l103_wwdg.h @@ -0,0 +1,41 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32l103_wwdg.h + * Author : WCH + * Version : V1.0.0 + * Date : 2023/07/08 + * Description : This file contains all the functions prototypes for the WWDG + * firmware library. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#ifndef __CH32L103_WWDG_H +#define __CH32L103_WWDG_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "ch32l103.h" + +/* WWDG_Prescaler */ +#define WWDG_Prescaler_1 ((uint32_t)0x00000000) +#define WWDG_Prescaler_2 ((uint32_t)0x00000080) +#define WWDG_Prescaler_4 ((uint32_t)0x00000100) +#define WWDG_Prescaler_8 ((uint32_t)0x00000180) + +void WWDG_DeInit(void); +void WWDG_SetPrescaler(uint32_t WWDG_Prescaler); +void WWDG_SetWindowValue(uint8_t WindowValue); +void WWDG_EnableIT(void); +void WWDG_SetCounter(uint8_t Counter); +void WWDG_Enable(uint8_t Counter); +FlagStatus WWDG_GetFlagStatus(void); +void WWDG_ClearFlag(void); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/ZDBMS/BMS_MC/Peripheral/src/ch32l103_adc.c b/ZDBMS/BMS_MC/Peripheral/src/ch32l103_adc.c new file mode 100644 index 0000000..cda926b --- /dev/null +++ b/ZDBMS/BMS_MC/Peripheral/src/ch32l103_adc.c @@ -0,0 +1,1344 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32l103_adc.c + * Author : WCH + * Version : V1.0.1 + * Date : 2025/01/07 + * Description : This file provides all the ADC firmware functions. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#include "ch32l103_adc.h" +#include "ch32l103_rcc.h" + +/* CFG Keys */ +#define CFG_KEY1 ((uint32_t)0x45670123) +#define CFG_KEY2 ((uint32_t)0xCDEF89AB) + +/* ADC DISCNUM mask */ +#define CTLR1_DISCNUM_Reset ((uint32_t)0xFFFF1FFF) + +/* ADC DISCEN mask */ +#define CTLR1_DISCEN_Set ((uint32_t)0x00000800) +#define CTLR1_DISCEN_Reset ((uint32_t)0xFFFFF7FF) + +/* ADC JAUTO mask */ +#define CTLR1_JAUTO_Set ((uint32_t)0x00000400) +#define CTLR1_JAUTO_Reset ((uint32_t)0xFFFFFBFF) + +/* ADC JDISCEN mask */ +#define CTLR1_JDISCEN_Set ((uint32_t)0x00001000) +#define CTLR1_JDISCEN_Reset ((uint32_t)0xFFFFEFFF) + +/* ADC AWDCH mask */ +#define CTLR1_AWDCH_Reset ((uint32_t)0xFFFFFFE0) + +/* ADC Analog watchdog enable mode mask */ +#define CTLR1_AWDMode_Reset ((uint32_t)0xFF3FFDFF) + +/* CTLR1 register Mask */ +#define CTLR1_CLEAR_Mask ((uint32_t)0xE0F0FEFF) + +/* ADC ADON mask */ +#define CTLR2_ADON_Set ((uint32_t)0x00000001) +#define CTLR2_ADON_Reset ((uint32_t)0xFFFFFFFE) + +/* ADC DMA mask */ +#define CTLR2_DMA_Set ((uint32_t)0x00000100) +#define CTLR2_DMA_Reset ((uint32_t)0xFFFFFEFF) + +/* ADC RSTCAL mask */ +#define CTLR2_RSTCAL_Set ((uint32_t)0x00000008) + +/* ADC CAL mask */ +#define CTLR2_CAL_Set ((uint32_t)0x00000004) + +/* ADC SWSTART mask */ +#define CTLR2_SWSTART_Set ((uint32_t)0x00400000) + +/* ADC EXTTRIG mask */ +#define CTLR2_EXTTRIG_Set ((uint32_t)0x00100000) +#define CTLR2_EXTTRIG_Reset ((uint32_t)0xFFEFFFFF) + +/* ADC Software start mask */ +#define CTLR2_EXTTRIG_SWSTART_Set ((uint32_t)0x00500000) +#define CTLR2_EXTTRIG_SWSTART_Reset ((uint32_t)0xFFAFFFFF) + +/* ADC JEXTSEL mask */ +#define CTLR2_JEXTSEL_Reset ((uint32_t)0xFFFF8FFF) + +/* ADC JEXTTRIG mask */ +#define CTLR2_JEXTTRIG_Set ((uint32_t)0x00008000) +#define CTLR2_JEXTTRIG_Reset ((uint32_t)0xFFFF7FFF) + +/* ADC JSWSTART mask */ +#define CTLR2_JSWSTART_Set ((uint32_t)0x00200000) + +/* ADC injected software start mask */ +#define CTLR2_JEXTTRIG_JSWSTART_Set ((uint32_t)0x00208000) +#define CTLR2_JEXTTRIG_JSWSTART_Reset ((uint32_t)0xFFDF7FFF) + +/* ADC TSPD mask */ +#define CTLR2_TSVREFE_Set ((uint32_t)0x00800000) +#define CTLR2_TSVREFE_Reset ((uint32_t)0xFF7FFFFF) + +/* CTLR2 register Mask */ +#define CTLR2_CLEAR_Mask ((uint32_t)0xFFF1F7FD) + +/* ADC SQx mask */ +#define RSQR3_SQ_Set ((uint32_t)0x0000001F) +#define RSQR2_SQ_Set ((uint32_t)0x0000001F) +#define RSQR1_SQ_Set ((uint32_t)0x0000001F) + +/* RSQR1 register Mask */ +#define RSQR1_CLEAR_Mask ((uint32_t)0xFF0FFFFF) + +/* ADC JSQx mask */ +#define ISQR_JSQ_Set ((uint32_t)0x0000001F) + +/* ADC JL mask */ +#define ISQR_JL_Set ((uint32_t)0x00300000) +#define ISQR_JL_Reset ((uint32_t)0xFFCFFFFF) + +/* ADC SMPx mask */ +#define SAMPTR1_SMP_Set ((uint32_t)0x00000007) +#define SAMPTR2_SMP_Set ((uint32_t)0x00000007) + +/* ADC IDATARx registers offset */ +#define IDATAR_Offset ((uint8_t)0x28) + +/* ADC1 RDATAR register base address */ +#define RDATAR_ADDRESS ((uint32_t)0x4001244C) + + +/********************************************************************* + * @fn ADC_DeInit + * + * @brief Deinitializes the ADCx peripheral registers to their default + * reset values. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * + * @return none + */ +void ADC_DeInit(ADC_TypeDef *ADCx) +{ + if(ADCx == ADC1) + { + RCC_PB2PeriphResetCmd(RCC_PB2Periph_ADC1, ENABLE); + RCC_PB2PeriphResetCmd(RCC_PB2Periph_ADC1, DISABLE); + } +} + +/********************************************************************* + * @fn ADC_Init + * + * @brief Initializes the ADCx peripheral according to the specified + * parameters in the ADC_InitStruct. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * ADC_InitStruct - pointer to an ADC_InitTypeDef structure that + * contains the configuration information for the specified ADC + * peripheral. + * + * @return none + */ +void ADC_Init(ADC_TypeDef *ADCx, ADC_InitTypeDef *ADC_InitStruct) +{ + uint32_t tmpreg1 = 0; + uint8_t tmpreg2 = 0; + + tmpreg1 = ADCx->CTLR1; + tmpreg1 &= CTLR1_CLEAR_Mask; + tmpreg1 |= (uint32_t)(ADC_InitStruct->ADC_Mode | (uint32_t)ADC_InitStruct->ADC_OutputBuffer | + (uint32_t)ADC_InitStruct->ADC_Pga | ((uint32_t)ADC_InitStruct->ADC_ScanConvMode << 8)); + ADCx->CTLR1 = tmpreg1; + + tmpreg1 = ADCx->CTLR2; + tmpreg1 &= CTLR2_CLEAR_Mask; + tmpreg1 |= (uint32_t)(ADC_InitStruct->ADC_DataAlign | ADC_InitStruct->ADC_ExternalTrigConv | + ((uint32_t)ADC_InitStruct->ADC_ContinuousConvMode << 1)); + ADCx->CTLR2 = tmpreg1; + + tmpreg1 = ADCx->RSQR1; + tmpreg1 &= RSQR1_CLEAR_Mask; + tmpreg2 |= (uint8_t)(ADC_InitStruct->ADC_NbrOfChannel - (uint8_t)1); + tmpreg1 |= (uint32_t)tmpreg2 << 20; + ADCx->RSQR1 = tmpreg1; +} + +/********************************************************************* + * @fn ADC_StructInit + * + * @brief Fills each ADC_InitStruct member with its default value. + * + * @param ADC_InitStruct - pointer to an ADC_InitTypeDef structure that + * contains the configuration information for the specified ADC + * peripheral. + * + * @return none + */ +void ADC_StructInit(ADC_InitTypeDef *ADC_InitStruct) +{ + ADC_InitStruct->ADC_Mode = ADC_Mode_Independent; + ADC_InitStruct->ADC_ScanConvMode = DISABLE; + ADC_InitStruct->ADC_ContinuousConvMode = DISABLE; + ADC_InitStruct->ADC_ExternalTrigConv = ADC_ExternalTrigConv_T1_CC1; + ADC_InitStruct->ADC_DataAlign = ADC_DataAlign_Right; + ADC_InitStruct->ADC_NbrOfChannel = 1; +} + +/********************************************************************* + * @fn ADC_Cmd + * + * @brief Enables or disables the specified ADC peripheral. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void ADC_Cmd(ADC_TypeDef *ADCx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + ADCx->CTLR2 |= CTLR2_ADON_Set; + } + else + { + ADCx->CTLR2 &= CTLR2_ADON_Reset; + } +} + +/********************************************************************* + * @fn ADC_DMACmd + * + * @brief Enables or disables the specified ADC DMA request. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void ADC_DMACmd(ADC_TypeDef *ADCx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + ADCx->CTLR2 |= CTLR2_DMA_Set; + } + else + { + ADCx->CTLR2 &= CTLR2_DMA_Reset; + } +} + +/********************************************************************* + * @fn ADC_ITConfig + * + * @brief Enables or disables the specified ADC interrupts. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * ADC_IT - specifies the ADC interrupt sources to be enabled or disabled. + * ADC_IT_EOC - End of conversion interrupt mask. + * ADC_IT_AWD - Analog watchdog interrupt mask. + * ADC_IT_JEOC - End of injected conversion interrupt mask. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void ADC_ITConfig(ADC_TypeDef *ADCx, uint16_t ADC_IT, FunctionalState NewState) +{ + uint8_t itmask = 0; + + itmask = (uint8_t)ADC_IT; + + if(NewState != DISABLE) + { + ADCx->CTLR1 |= itmask; + } + else + { + ADCx->CTLR1 &= (~(uint32_t)itmask); + } +} + +/********************************************************************* + * @fn ADC_ResetCalibration + * + * @brief Resets the selected ADC calibration registers. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * + * @return none + */ +void ADC_ResetCalibration(ADC_TypeDef *ADCx) +{ + ADCx->CTLR2 |= CTLR2_RSTCAL_Set; +} + +/********************************************************************* + * @fn ADC_GetResetCalibrationStatus + * + * @brief Gets the selected ADC reset calibration registers status. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * + * @return FlagStatus: SET or RESET. + */ +FlagStatus ADC_GetResetCalibrationStatus(ADC_TypeDef *ADCx) +{ + FlagStatus bitstatus = RESET; + + if((ADCx->CTLR2 & CTLR2_RSTCAL_Set) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn ADC_StartCalibration + * + * @brief Starts the selected ADC calibration process. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * + * @return None + */ +void ADC_StartCalibration(ADC_TypeDef *ADCx) +{ + ADCx->CTLR2 |= CTLR2_CAL_Set; +} + +/********************************************************************* + * @fn ADC_GetCalibrationStatus + * + * @brief Gets the selected ADC calibration status. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * + * @return FlagStatus: SET or RESET. + */ +FlagStatus ADC_GetCalibrationStatus(ADC_TypeDef *ADCx) +{ + FlagStatus bitstatus = RESET; + + if((ADCx->CTLR2 & CTLR2_CAL_Set) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn ADC_SoftwareStartConvCmd + * + * @brief Enables or disables the selected ADC software start conversion. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * NewState - ENABLE or DISABLE. + * + * @return None + */ +void ADC_SoftwareStartConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + ADCx->CTLR2 |= CTLR2_EXTTRIG_SWSTART_Set; + } + else + { + ADCx->CTLR2 &= CTLR2_EXTTRIG_SWSTART_Reset; + } +} + +/********************************************************************* + * @fn ADC_GetSoftwareStartConvStatus + * + * @brief Gets the selected ADC Software start conversion Status. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * + * @return FlagStatus - SET or RESET. + */ + +FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef *ADCx) +{ + FlagStatus bitstatus = RESET; + + if((ADCx->CTLR2 & CTLR2_SWSTART_Set) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn ADC_DiscModeChannelCountConfig + * + * @brief Configures the discontinuous mode for the selected ADC regular + * group channel. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * Number - specifies the discontinuous mode regular channel + * count value(1-8). + * + * @return None + */ +void ADC_DiscModeChannelCountConfig(ADC_TypeDef *ADCx, uint8_t Number) +{ + uint32_t tmpreg1 = 0; + uint32_t tmpreg2 = 0; + + tmpreg1 = ADCx->CTLR1; + tmpreg1 &= CTLR1_DISCNUM_Reset; + tmpreg2 = Number - 1; + tmpreg1 |= tmpreg2 << 13; + ADCx->CTLR1 = tmpreg1; +} + +/********************************************************************* + * @fn ADC_DiscModeCmd + * + * @brief Enables or disables the discontinuous mode on regular group + * channel for the specified ADC. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * NewState - ENABLE or DISABLE. + * + * @return None + */ +void ADC_DiscModeCmd(ADC_TypeDef *ADCx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + ADCx->CTLR1 |= CTLR1_DISCEN_Set; + } + else + { + ADCx->CTLR1 &= CTLR1_DISCEN_Reset; + } +} + +/********************************************************************* + * @fn ADC_RegularChannelConfig + * + * @brief Configures for the selected ADC regular channel its corresponding + * rank in the sequencer and its sample time. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * ADC_Channel - the ADC channel to configure. + * ADC_Channel_0 - ADC Channel0 selected. + * ADC_Channel_1 - ADC Channel1 selected. + * ADC_Channel_2 - ADC Channel2 selected. + * ADC_Channel_3 - ADC Channel3 selected. + * ADC_Channel_4 - ADC Channel4 selected. + * ADC_Channel_5 - ADC Channel5 selected. + * ADC_Channel_6 - ADC Channel6 selected. + * ADC_Channel_7 - ADC Channel7 selected. + * ADC_Channel_8 - ADC Channel8 selected. + * ADC_Channel_9 - ADC Channel9 selected. + * ADC_Channel_16 - ADC Channel16 selected. + * ADC_Channel_17 - ADC Channel17 selected. + * Rank - The rank in the regular group sequencer. + * This parameter must be between 1 to 16. + * ADC_SampleTime - The sample time value to be set for the selected channel. + * ADC_SampleTime_CyclesMode0 - Sample time equal to 1.5 cycles(CFG bit[5]-ADC_LP=0). + * - Sample time equal to 7.5 cycles(CFG bit[5]-ADC_LP=1). + * ADC_SampleTime_CyclesMode1 - Sample time equal to 7.5 cycles(CFG bit[5]-ADC_LP=0). + * - Sample time equal to 11.5 cycles(CFG bit[5]-ADC_LP=1). + * ADC_SampleTime_CyclesMode2 - Sample time equal to 13.5 cycles(CFG bit[5]-ADC_LP=0). + * - Sample time equal to 17.5 cycles(CFG bit[5]-ADC_LP=1). + * ADC_SampleTime_CyclesMode3 - Sample time equal to 28.5 cycles(CFG bit[5]-ADC_LP=0). + * - Sample time equal to 27.5 cycles(CFG bit[5]-ADC_LP=1). + * ADC_SampleTime_CyclesMode4 - Sample time equal to 41.5 cycles(CFG bit[5]-ADC_LP=0). + * - Sample time equal to 47.5 cycles(CFG bit[5]-ADC_LP=1). + * ADC_SampleTime_CyclesMode5 - Sample time equal to 55.5 cycles(CFG bit[5]-ADC_LP=0). + * - Sample time equal to 55.5 cycles(CFG bit[5]-ADC_LP=1). + * ADC_SampleTime_CyclesMode6 - Sample time equal to 71.5 cycles(CFG bit[5]-ADC_LP=0). + * - Sample time equal to 71.5 cycles(CFG bit[5]-ADC_LP=1). + * ADC_SampleTime_CyclesMode7 - Sample time equal to 239.5 cycles(CFG bit[5]-ADC_LP=0). + * - Sample time equal to 239.5 cycles(CFG bit[5]-ADC_LP=1). + * + * @return None + */ +void ADC_RegularChannelConfig(ADC_TypeDef *ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime) +{ + uint32_t tmpreg1 = 0, tmpreg2 = 0; + + if(ADC_Channel > ADC_Channel_9) + { + tmpreg1 = ADCx->SAMPTR1; + tmpreg2 = SAMPTR1_SMP_Set << (3 * (ADC_Channel - 10)); + tmpreg1 &= ~tmpreg2; + tmpreg2 = (uint32_t)ADC_SampleTime << (3 * (ADC_Channel - 10)); + tmpreg1 |= tmpreg2; + ADCx->SAMPTR1 = tmpreg1; + } + else + { + tmpreg1 = ADCx->SAMPTR2; + tmpreg2 = SAMPTR2_SMP_Set << (3 * ADC_Channel); + tmpreg1 &= ~tmpreg2; + tmpreg2 = (uint32_t)ADC_SampleTime << (3 * ADC_Channel); + tmpreg1 |= tmpreg2; + ADCx->SAMPTR2 = tmpreg1; + } + + if(Rank < 7) + { + tmpreg1 = ADCx->RSQR3; + tmpreg2 = RSQR3_SQ_Set << (5 * (Rank - 1)); + tmpreg1 &= ~tmpreg2; + tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 1)); + tmpreg1 |= tmpreg2; + ADCx->RSQR3 = tmpreg1; + } + else if(Rank < 13) + { + tmpreg1 = ADCx->RSQR2; + tmpreg2 = RSQR2_SQ_Set << (5 * (Rank - 7)); + tmpreg1 &= ~tmpreg2; + tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 7)); + tmpreg1 |= tmpreg2; + ADCx->RSQR2 = tmpreg1; + } + else + { + tmpreg1 = ADCx->RSQR1; + tmpreg2 = RSQR1_SQ_Set << (5 * (Rank - 13)); + tmpreg1 &= ~tmpreg2; + tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 13)); + tmpreg1 |= tmpreg2; + ADCx->RSQR1 = tmpreg1; + } +} + +/********************************************************************* + * @fn ADC_ExternalTrigConvCmd + * + * @brief Enables or disables the ADCx conversion through external trigger. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * NewState - ENABLE or DISABLE. + * + * @return None + */ +void ADC_ExternalTrigConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + ADCx->CTLR2 |= CTLR2_EXTTRIG_Set; + } + else + { + ADCx->CTLR2 &= CTLR2_EXTTRIG_Reset; + } +} + +/********************************************************************* + * @fn ADC_GetConversionValue + * + * @brief Returns the last ADCx conversion result data for regular channel. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * + * @return ADCx->RDATAR - The Data conversion value. + */ +uint16_t ADC_GetConversionValue(ADC_TypeDef *ADCx) +{ + return (uint16_t)ADCx->RDATAR; +} + +/********************************************************************* + * @fn ADC_GetDualModeConversionValue + * + * @brief Returns the last ADC1 and conversion result data in dual mode. + * + * @return RDATAR_ADDRESS - The Data conversion value. + */ +uint32_t ADC_GetDualModeConversionValue(void) +{ + return (*(__IO uint32_t *)RDATAR_ADDRESS); +} + +/********************************************************************* + * @fn ADC_AutoInjectedConvCmd + * + * @brief Enables or disables the selected ADC automatic injected group + * conversion after regular one. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * NewState - ENABLE or DISABLE. + * + * @return None + */ +void ADC_AutoInjectedConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + ADCx->CTLR1 |= CTLR1_JAUTO_Set; + } + else + { + ADCx->CTLR1 &= CTLR1_JAUTO_Reset; + } +} + +/********************************************************************* + * @fn ADC_InjectedDiscModeCmd + * + * @brief Enables or disables the discontinuous mode for injected group + * channel for the specified ADC. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * NewState - ENABLE or DISABLE. + * + * @return None + */ +void ADC_InjectedDiscModeCmd(ADC_TypeDef *ADCx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + ADCx->CTLR1 |= CTLR1_JDISCEN_Set; + } + else + { + ADCx->CTLR1 &= CTLR1_JDISCEN_Reset; + } +} + +/********************************************************************* + * @fn ADC_ExternalTrigInjectedConvConfig + * + * @brief Configures the ADCx external trigger for injected channels conversion. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * ADC_ExternalTrigInjecConv - specifies the ADC trigger to start + * injected conversion. + * ADC_ExternalTrigInjecConv_T1_TRGO - Timer1 TRGO event selected. + * ADC_ExternalTrigInjecConv_T1_CC4 - Timer1 capture compare4 selected. + * ADC_ExternalTrigInjecConv_T2_TRGO - Timer2 TRGO event selected. + * ADC_ExternalTrigInjecConv_T2_CC1 - Timer2 capture compare1 selected. + * ADC_ExternalTrigInjecConv_T3_CC4 - Timer3 capture compare4 selected. + * ADC_ExternalTrigInjecConv_T4_TRGO - Timer4 TRGO event selected. + * ADC_ExternalTrigInjecConv_Ext_IT15 - External interrupt + * line 15 event selected. + * ADC_ExternalTrigInjecConv_None - Injected conversion started + * by software and not by external trigger. + * + * @return None + */ +void ADC_ExternalTrigInjectedConvConfig(ADC_TypeDef *ADCx, uint32_t ADC_ExternalTrigInjecConv) +{ + uint32_t tmpreg = 0; + + tmpreg = ADCx->CTLR2; + tmpreg &= CTLR2_JEXTSEL_Reset; + tmpreg |= ADC_ExternalTrigInjecConv; + ADCx->CTLR2 = tmpreg; +} + +/********************************************************************* + * @fn ADC_ExternalTrigInjectedConvCmd + * + * @brief Enables or disables the ADCx injected channels conversion through + * external trigger. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * NewState - ENABLE or DISABLE. + * + * @return None + */ +void ADC_ExternalTrigInjectedConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + ADCx->CTLR2 |= CTLR2_JEXTTRIG_Set; + } + else + { + ADCx->CTLR2 &= CTLR2_JEXTTRIG_Reset; + } +} + +/********************************************************************* + * @fn ADC_SoftwareStartInjectedConvCmd + * + * @brief Enables or disables the selected ADC start of the injected + * channels conversion. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * NewState - ENABLE or DISABLE. + * + * @return None + */ +void ADC_SoftwareStartInjectedConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + ADCx->CTLR2 |= CTLR2_JEXTTRIG_JSWSTART_Set; + } + else + { + ADCx->CTLR2 &= CTLR2_JEXTTRIG_JSWSTART_Reset; + } +} + +/********************************************************************* + * @fn ADC_GetSoftwareStartInjectedConvCmdStatus + * + * @brief Gets the selected ADC Software start injected conversion Status. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * + * @return FlagStatus: SET or RESET. + */ +FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_TypeDef *ADCx) +{ + FlagStatus bitstatus = RESET; + + if((ADCx->CTLR2 & CTLR2_JSWSTART_Set) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn ADC_InjectedChannelConfig + * + * @brief Configures for the selected ADC injected channel its corresponding + * rank in the sequencer and its sample time. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * ADC_Channel - the ADC channel to configure. + * ADC_Channel_0 - ADC Channel0 selected. + * ADC_Channel_1 - ADC Channel1 selected. + * ADC_Channel_2 - ADC Channel2 selected. + * ADC_Channel_3 - ADC Channel3 selected. + * ADC_Channel_4 - ADC Channel4 selected. + * ADC_Channel_5 - ADC Channel5 selected. + * ADC_Channel_6 - ADC Channel6 selected. + * ADC_Channel_7 - ADC Channel7 selected. + * ADC_Channel_8 - ADC Channel8 selected. + * ADC_Channel_9 - ADC Channel9 selected. + * ADC_Channel_16 - ADC Channel16 selected. + * ADC_Channel_17 - ADC Channel17 selected. + * Rank - The rank in the regular group sequencer. + * This parameter must be between 1 to 4. + * ADC_SampleTime - The sample time value to be set for the selected channel. + * ADC_SampleTime_1Cycles5 - Sample time equal to 1.5 cycles. + * ADC_SampleTime_7Cycles5 - Sample time equal to 7.5 cycles. + * ADC_SampleTime_13Cycles5 - Sample time equal to 13.5 cycles. + * ADC_SampleTime_28Cycles5 - Sample time equal to 28.5 cycles. + * ADC_SampleTime_41Cycles5 - Sample time equal to 41.5 cycles. + * ADC_SampleTime_55Cycles5 - Sample time equal to 55.5 cycles. + * ADC_SampleTime_71Cycles5 - Sample time equal to 71.5 cycles. + * ADC_SampleTime_239Cycles5 - Sample time equal to 239.5 cycles. + * + * @return None + */ +void ADC_InjectedChannelConfig(ADC_TypeDef *ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime) +{ + uint32_t tmpreg1 = 0, tmpreg2 = 0, tmpreg3 = 0; + + if(ADC_Channel > ADC_Channel_9) + { + tmpreg1 = ADCx->SAMPTR1; + tmpreg2 = SAMPTR1_SMP_Set << (3 * (ADC_Channel - 10)); + tmpreg1 &= ~tmpreg2; + tmpreg2 = (uint32_t)ADC_SampleTime << (3 * (ADC_Channel - 10)); + tmpreg1 |= tmpreg2; + ADCx->SAMPTR1 = tmpreg1; + } + else + { + tmpreg1 = ADCx->SAMPTR2; + tmpreg2 = SAMPTR2_SMP_Set << (3 * ADC_Channel); + tmpreg1 &= ~tmpreg2; + tmpreg2 = (uint32_t)ADC_SampleTime << (3 * ADC_Channel); + tmpreg1 |= tmpreg2; + ADCx->SAMPTR2 = tmpreg1; + } + + tmpreg1 = ADCx->ISQR; + tmpreg3 = (tmpreg1 & ISQR_JL_Set) >> 20; + tmpreg2 = ISQR_JSQ_Set << (5 * (uint8_t)((Rank + 3) - (tmpreg3 + 1))); + tmpreg1 &= ~tmpreg2; + tmpreg2 = (uint32_t)ADC_Channel << (5 * (uint8_t)((Rank + 3) - (tmpreg3 + 1))); + tmpreg1 |= tmpreg2; + ADCx->ISQR = tmpreg1; +} + +/********************************************************************* + * @fn ADC_InjectedSequencerLengthConfig + * + * @brief Configures the sequencer length for injected channels. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * Length - The sequencer length. + * This parameter must be a number between 1 to 4. + * + * @return None + */ +void ADC_InjectedSequencerLengthConfig(ADC_TypeDef *ADCx, uint8_t Length) +{ + uint32_t tmpreg1 = 0; + uint32_t tmpreg2 = 0; + + tmpreg1 = ADCx->ISQR; + tmpreg1 &= ISQR_JL_Reset; + tmpreg2 = Length - 1; + tmpreg1 |= tmpreg2 << 20; + ADCx->ISQR = tmpreg1; +} + +/********************************************************************* + * @fn ADC_SetInjectedOffset + * + * @brief Set the injected channels conversion value offset. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * ADC_InjectedChannel: the ADC injected channel to set its offset. + * ADC_InjectedChannel_1 - Injected Channel1 selected. + * ADC_InjectedChannel_2 - Injected Channel2 selected. + * ADC_InjectedChannel_3 - Injected Channel3 selected. + * ADC_InjectedChannel_4 - Injected Channel4 selected. + * Offset - the offset value for the selected ADC injected channel. + * This parameter must be a 12bit value. + * + * @return None + */ +void ADC_SetInjectedOffset(ADC_TypeDef *ADCx, uint8_t ADC_InjectedChannel, uint16_t Offset) +{ + __IO uint32_t tmp = 0; + + tmp = (uint32_t)ADCx; + tmp += ADC_InjectedChannel; + + *(__IO uint32_t *)tmp = (uint32_t)Offset; +} + +/********************************************************************* + * @fn ADC_GetInjectedConversionValue + * + * @brief Returns the ADC injected channel conversion result. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * ADC_InjectedChannel - the ADC injected channel to set its offset. + * ADC_InjectedChannel_1 - Injected Channel1 selected. + * ADC_InjectedChannel_2 - Injected Channel2 selected. + * ADC_InjectedChannel_3 - Injected Channel3 selected. + * ADC_InjectedChannel_4 - Injected Channel4 selected. + * + * @return tmp - The Data conversion value. + */ +uint16_t ADC_GetInjectedConversionValue(ADC_TypeDef *ADCx, uint8_t ADC_InjectedChannel) +{ + __IO uint32_t tmp = 0; + + tmp = (uint32_t)ADCx; + tmp += ADC_InjectedChannel + IDATAR_Offset; + + return (uint16_t)(*(__IO uint32_t *)tmp); +} + +/********************************************************************* + * @fn ADC_AnalogWatchdogCmd + * + * @brief Enables or disables the analog watchdog on single/all regular + * or injected channels. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * ADC_AnalogWatchdog - the ADC analog watchdog configuration. + * ADC_AnalogWatchdog_SingleRegEnable - Analog watchdog on a + * single regular channel. + * ADC_AnalogWatchdog_SingleInjecEnable - Analog watchdog on a + * single injected channel. + * ADC_AnalogWatchdog_SingleRegOrInjecEnable - Analog watchdog + * on a single regular or injected channel. + * ADC_AnalogWatchdog_AllRegEnable - Analog watchdog on all + * regular channel. + * ADC_AnalogWatchdog_AllInjecEnable - Analog watchdog on all + * injected channel. + * ADC_AnalogWatchdog_AllRegAllInjecEnable - Analog watchdog on + * all regular and injected channels. + * ADC_AnalogWatchdog_None - No channel guarded by the analog + * watchdog. + * + * @return none + */ +void ADC_AnalogWatchdogCmd(ADC_TypeDef *ADCx, uint32_t ADC_AnalogWatchdog) +{ + uint32_t tmpreg = 0; + + tmpreg = ADCx->CTLR1; + tmpreg &= CTLR1_AWDMode_Reset; + tmpreg |= ADC_AnalogWatchdog; + ADCx->CTLR1 = tmpreg; +} + +/********************************************************************* + * @fn ADC_AnalogWatchdogThresholdsConfig + * + * @brief Configures the high and low thresholds of the analog watchdog. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * HighThreshold - the ADC analog watchdog High threshold value. + * This parameter must be a 12bit value. + * LowThreshold - the ADC analog watchdog Low threshold value. + * This parameter must be a 12bit value. + * + * @return none + */ +void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef *ADCx, uint16_t HighThreshold, + uint16_t LowThreshold) +{ + ADCx->WDHTR = HighThreshold; + ADCx->WDLTR = LowThreshold; +} + +/********************************************************************* + * @fn ADC_AnalogWatchdogSingleChannelConfig + * + * @brief Configures the analog watchdog guarded single channel. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * ADC_Channel - the ADC channel to configure. + * ADC_Channel_0 - ADC Channel0 selected. + * ADC_Channel_1 - ADC Channel1 selected. + * ADC_Channel_2 - ADC Channel2 selected. + * ADC_Channel_3 - ADC Channel3 selected. + * ADC_Channel_4 - ADC Channel4 selected. + * ADC_Channel_5 - ADC Channel5 selected. + * ADC_Channel_6 - ADC Channel6 selected. + * ADC_Channel_7 - ADC Channel7 selected. + * ADC_Channel_8 - ADC Channel8 selected. + * ADC_Channel_9 - ADC Channel9 selected. + * ADC_Channel_16 - ADC Channel16 selected. + * ADC_Channel_17 - ADC Channel17 selected. + * + * @return None + */ +void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef *ADCx, uint8_t ADC_Channel) +{ + uint32_t tmpreg = 0; + + tmpreg = ADCx->CTLR1; + tmpreg &= CTLR1_AWDCH_Reset; + tmpreg |= ADC_Channel; + ADCx->CTLR1 = tmpreg; +} + +/********************************************************************* + * @fn ADC_TempSensorVrefintCmd + * + * @brief Enables or disables the temperature sensor and Vrefint channel. + * + * @param NewState - ENABLE or DISABLE. + * + * @return none + */ +void ADC_TempSensorVrefintCmd(FunctionalState NewState) +{ + if(NewState != DISABLE) + { + ADC1->CTLR2 |= CTLR2_TSVREFE_Set; + } + else + { + ADC1->CTLR2 &= CTLR2_TSVREFE_Reset; + } +} + +/********************************************************************* + * @fn ADC_GetFlagStatus + * + * @brief Checks whether the specified ADC flag is set or not. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * ADC_FLAG - specifies the flag to check. + * ADC_FLAG_AWD - Analog watchdog flag. + * ADC_FLAG_EOC - End of conversion flag. + * ADC_FLAG_JEOC - End of injected group conversion flag. + * ADC_FLAG_JSTRT - Start of injected group conversion flag. + * ADC_FLAG_STRT - Start of regular group conversion flag. + * + * @return FlagStatus: SET or RESET. + */ +FlagStatus ADC_GetFlagStatus(ADC_TypeDef *ADCx, uint8_t ADC_FLAG) +{ + FlagStatus bitstatus = RESET; + + if((ADCx->STATR & ADC_FLAG) != (uint8_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn ADC_ClearFlag + * + * @brief Clears the ADCx's pending flags. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * ADC_FLAG - specifies the flag to clear. + * ADC_FLAG_AWD - Analog watchdog flag. + * ADC_FLAG_EOC - End of conversion flag. + * ADC_FLAG_JEOC - End of injected group conversion flag. + * ADC_FLAG_JSTRT - Start of injected group conversion flag. + * ADC_FLAG_STRT - Start of regular group conversion flag. + * + * @return none + */ +void ADC_ClearFlag(ADC_TypeDef *ADCx, uint8_t ADC_FLAG) +{ + ADCx->STATR = ~(uint32_t)ADC_FLAG; +} + +/********************************************************************* + * @fn ADC_GetITStatus + * + * @brief Checks whether the specified ADC interrupt has occurred or not. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * ADC_IT - specifies the ADC interrupt source to check. + * ADC_IT_EOC - End of conversion interrupt mask. + * ADC_IT_AWD - Analog watchdog interrupt mask. + * ADC_IT_JEOC - End of injected conversion interrupt mask. + * + * @return FlagStatus: SET or RESET. + */ +ITStatus ADC_GetITStatus(ADC_TypeDef *ADCx, uint16_t ADC_IT) +{ + ITStatus bitstatus = RESET; + uint32_t itmask = 0, enablestatus = 0; + + itmask = ADC_IT >> 8; + enablestatus = (ADCx->CTLR1 & (uint8_t)ADC_IT); + + if(((ADCx->STATR & itmask) != (uint32_t)RESET) && enablestatus) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn ADC_ClearITPendingBit + * + * @brief Clears the ADCx's interrupt pending bits. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * ADC_IT - specifies the ADC interrupt pending bit to clear. + * ADC_IT_EOC - End of conversion interrupt mask. + * ADC_IT_AWD - Analog watchdog interrupt mask. + * ADC_IT_JEOC - End of injected conversion interrupt mask. + * + * @return none + */ +void ADC_ClearITPendingBit(ADC_TypeDef *ADCx, uint16_t ADC_IT) +{ + uint8_t itmask = 0; + + itmask = (uint8_t)(ADC_IT >> 8); + ADCx->STATR = ~(uint32_t)itmask; +} + +/********************************************************************* + * @fn TempSensor_Volt_To_Temper + * + * @brief Internal Temperature Sensor Voltage to temperature. + * + * @param Value - Voltage Value(mv). + * + * @return Temper - Temperature Value. + */ +s32 TempSensor_Volt_To_Temper(s32 Value) +{ + s32 Temper, Refer_Volt, Refer_Temper; + s32 k = 42; + + Refer_Volt = (s32)((TS_Val) & 0x0000FFFF); + Refer_Temper = (s32)(((TS_Val) >> 16) & 0x0000FFFF); + + Temper = Refer_Temper - ((Value - Refer_Volt) * 10 + (k >> 1)) / k; + + return Temper; +} + +/********************************************************************* + * @fn ADC_BufferCmd + * + * @brief Enables or disables the ADCx buffer. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void ADC_BufferCmd(ADC_TypeDef *ADCx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + ADCx->CTLR1 |= (1 << 26); + } + else + { + ADCx->CTLR1 &= ~(1 << 26); + } +} + +/********************************************************************* + * @fn ADC_TKey_ChannelxMulShieldCmd + * + * @brief Enables or disables TKey Multiplex shielding of the selected ADC channel. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * ADC_Channel - the ADC channel to configure. + * ADC_Channel_0 - ADC Channel0 selected. + * ADC_Channel_1 - ADC Channel1 selected. + * ADC_Channel_2 - ADC Channel2 selected. + * ADC_Channel_3 - ADC Channel3 selected. + * ADC_Channel_4 - ADC Channel4 selected. + * ADC_Channel_5 - ADC Channel5 selected. + * ADC_Channel_6 - ADC Channel6 selected. + * ADC_Channel_7 - ADC Channel7 selected. + * ADC_Channel_8 - ADC Channel8 selected. + * ADC_Channel_9 - ADC Channel9 selected. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void ADC_TKey_ChannelxMulShieldCmd(ADC_TypeDef *ADCx, uint8_t ADC_Channel, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + ADCx->CFG |= ((1<<9)<< ADC_Channel); + } + else + { + ADCx->CFG &= ~((1<<9)<< ADC_Channel); + } +} + +/********************************************************************* + * @fn ADC_TKey_MulShieldCmd + * + * @brief Enables or disables the TKey Multiplex shielding. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void ADC_TKey_MulShieldCmd(ADC_TypeDef *ADCx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + ADCx->CFG |= (1 << 8); + } + else + { + ADCx->CFG &= ~(1 << 8); + } +} + +/********************************************************************* + * @fn ADC_DutyDelayCmd + * + * @brief Enables or disables the Duty delay. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void ADC_DutyDelayCmd(ADC_TypeDef *ADCx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + ADCx->CFG |= (1 << 7); + } + else + { + ADCx->CFG &= ~(1 << 7); + } +} + +/********************************************************************* + * @fn ADC_FIFO_Cmd + * + * @brief Enables or disables the FIFO. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void ADC_FIFO_Cmd(ADC_TypeDef *ADCx, FunctionalState NewState) +{ + FLASH->KEYR = CFG_KEY1; + FLASH->KEYR = CFG_KEY2; + FLASH->MODEKEYR = CFG_KEY1; + FLASH->OBKEYR = CFG_KEY2; + while((*(vu32*)0x40022034) & (1<<29)); // wait unlock + + *(vu32*)0x4002202C |= (1<<9); //offset calibration + (*(vu32*)0x40022034) |= (1<<29); //lock + while(((*(vu32*)0x40022034) & (1<<29)) == 0); //wait lock + + if(NewState != DISABLE) + { + ADCx->CFG |= (1 << 6); + } + else + { + ADCx->CFG &= ~(1 << 6); + } +} + +/********************************************************************* + * @fn ADC_Sample_ModeConfig + * + * @brief Configures the ADC Sample Mode. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * ADC_Sample_Mode - Sample Mode. + * ADC_Sample_NoOver_1M_Mode - sampling rate no over 1M(<=1M) mode. + * ADC_Sample_Over_1M_Mode - sampling rate over 1M(>1M) mode. + * + * @return none + */ +void ADC_Sample_ModeConfig(ADC_TypeDef *ADCx, uint32_t ADC_Sample_Mode) +{ + ADCx->CFG &= ~ADC_Sample_Over_1M_Mode; + ADCx->CFG |= ADC_Sample_Mode; +} + +/********************************************************************* + * @fn ADC_OffsetCalibrationConfig + * + * @brief Configures the Offset Calibration. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * + * @return None + */ +void ADC_OffsetCalibrationConfig(ADC_TypeDef *ADCx) +{ + uint16_t tmp; + + tmp = ADC_Trim; + ADCx->CFG &= ~0x0000000F; + ADCx->CFG |= (uint32_t)((tmp & 0x07) | (((tmp & 0x8000)^0x8000) >> 12)); +} + +/********************************************************************* + * @fn ADC_AnalogWatchdogResetCmd + * + * @brief Enables or disables the analog watch dog reset function. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void ADC_AnalogWatchdogResetCmd(ADC_TypeDef *ADCx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + ADCx->CFG |= (1 << 4); + } + else + { + ADCx->CFG &= ~(1 << 4); + } +} + +/********************************************************************* + * @fn Get_CalibrationValue + * + * @brief Get ADCx Calibration Value. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * + * @return CalibrationValue + */ +int16_t Get_CalibrationValue(ADC_TypeDef *ADCx) +{ + __IO uint8_t i, j; + uint16_t buf[10]; + __IO uint16_t t; + + ADCx->CTLR2|=(7<<17); + ADC_Cmd(ADCx, ENABLE); + ADC_FIFO_Cmd(ADCx, ENABLE); + ADC_ResetCalibration(ADCx); + while(ADC_GetResetCalibrationStatus(ADCx)); + ADC_StartCalibration(ADCx); + while(ADC_GetCalibrationStatus(ADCx)); + ADC_RegularChannelConfig(ADCx, ADC_Channel_CalInternal, 1, ADC_SampleTime_CyclesMode0); + for(i = 0; i < 10; i++) + { + ADC_SoftwareStartConvCmd(ADCx, ENABLE); + while(!ADC_GetFlagStatus(ADCx, ADC_FLAG_EOC)); + buf[i] = ADC_GetConversionValue(ADCx); + } + for(i = 0; i < 10; i++) + { + for(j = 0; j < 9; j++) + { + if(buf[j] > buf[j + 1]) + { + t = buf[j]; + buf[j] = buf[j + 1]; + buf[j + 1] = t; + } + } + } + + t = 0; + for(i = 0; i < 6; i++) + { + t += buf[i + 2]; + } + t = (t / 6) + ((t % 6) / 3); + ADC_Cmd(ADC1, DISABLE); + return (int16_t)(2048 - (int16_t)t); +} + + diff --git a/ZDBMS/BMS_MC/Peripheral/src/ch32l103_bkp.c b/ZDBMS/BMS_MC/Peripheral/src/ch32l103_bkp.c new file mode 100644 index 0000000..ae9869b --- /dev/null +++ b/ZDBMS/BMS_MC/Peripheral/src/ch32l103_bkp.c @@ -0,0 +1,244 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32l103_bkp.c + * Author : WCH + * Version : V1.0.0 + * Date : 2023/07/08 + * Description : This file provides all the BKP firmware functions. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#include "ch32l103_bkp.h" +#include "ch32l103_rcc.h" + +/* BKP registers bit mask */ + +/* OCTLR register bit mask */ +#define OCTLR_CAL_MASK ((uint16_t)0xFF80) +#define OCTLR_MASK ((uint16_t)0xFC7F) + +/********************************************************************* + * @fn BKP_DeInit + * + * @brief Deinitializes the BKP peripheral registers to their default reset values. + * + * @return none + */ +void BKP_DeInit(void) +{ + RCC_BackupResetCmd(ENABLE); + RCC_BackupResetCmd(DISABLE); +} + +/********************************************************************* + * @fn BKP_TamperPinLevelConfig + * + * @brief Configures the Tamper Pin active level. + * + * @param BKP_TamperPinLevel - specifies the Tamper Pin active level. + * BKP_TamperPinLevel_High - Tamper pin active on high level. + * BKP_TamperPinLevel_Low - Tamper pin active on low level. + * + * @return none + */ +void BKP_TamperPinLevelConfig(uint16_t BKP_TamperPinLevel) +{ + if(BKP_TamperPinLevel) + { + BKP->TPCTLR |= (1 << 1); + } + else + { + BKP->TPCTLR &= ~(1 << 1); + } +} + +/********************************************************************* + * @fn BKP_TamperPinCmd + * + * @brief Enables or disables the Tamper Pin activation. + * + * @param NewState - ENABLE or DISABLE. + * + * @return none + */ +void BKP_TamperPinCmd(FunctionalState NewState) +{ + if(NewState) + { + BKP->TPCTLR |= (1 << 0); + } + else + { + BKP->TPCTLR &= ~(1 << 0); + } +} + +/********************************************************************* + * @fn BKP_ITConfig + * + * @brief Enables or disables the Tamper Pin Interrupt. + * + * @param NewState - ENABLE or DISABLE. + * + * @return none + */ +void BKP_ITConfig(FunctionalState NewState) +{ + if(NewState) + { + BKP->TPCSR |= (1 << 2); + } + else + { + BKP->TPCSR &= ~(1 << 2); + } +} + +/********************************************************************* + * @fn BKP_RTCOutputConfig + * + * @brief Select the RTC output source to output on the Tamper pin. + * + * @param BKP_RTCOutputSource - specifies the RTC output source. + * BKP_RTCOutputSource_None - no RTC output on the Tamper pin. + * BKP_RTCOutputSource_CalibClock - output the RTC clock with + * frequency divided by 64 on the Tamper pin. + * BKP_RTCOutputSource_Alarm - output the RTC Alarm pulse signal + * on the Tamper pin. + * BKP_RTCOutputSource_Second - output the RTC Second pulse + * signal on the Tamper pin. + * + * @return none + */ +void BKP_RTCOutputConfig(uint16_t BKP_RTCOutputSource) +{ + uint16_t tmpreg = 0; + + tmpreg = BKP->OCTLR; + tmpreg &= OCTLR_MASK; + tmpreg |= BKP_RTCOutputSource; + BKP->OCTLR = tmpreg; +} + +/********************************************************************* + * @fn BKP_SetRTCCalibrationValue + * + * @brief Sets RTC Clock Calibration value. + * + * @param CalibrationValue - specifies the RTC Clock Calibration value. + * This parameter must be a number between 0 and 0x1F. + * + * @return none + */ +void BKP_SetRTCCalibrationValue(uint8_t CalibrationValue) +{ + uint16_t tmpreg = 0; + + tmpreg = BKP->OCTLR; + tmpreg &= OCTLR_CAL_MASK; + tmpreg |= CalibrationValue; + BKP->OCTLR = tmpreg; +} + +/********************************************************************* + * @fn BKP_WriteBackupRegister + * + * @brief Writes user data to the specified Data Backup Register. + * + * @param BKP_DR - specifies the Data Backup Register. + * Data - data to write. + * + * @return none + */ +void BKP_WriteBackupRegister(uint16_t BKP_DR, uint16_t Data) +{ + __IO uint32_t tmp = 0; + + tmp = (uint32_t)BKP_BASE; + tmp += BKP_DR; + *(__IO uint32_t *)tmp = Data; +} + +/********************************************************************* + * @fn BKP_ReadBackupRegister + * + * @brief Reads data from the specified Data Backup Register. + * + * @param BKP_DR - specifies the Data Backup Register. + * This parameter can be BKP_DRx where x=[1, 42]. + * + * @return none + */ +uint16_t BKP_ReadBackupRegister(uint16_t BKP_DR) +{ + __IO uint32_t tmp = 0; + + tmp = (uint32_t)BKP_BASE; + tmp += BKP_DR; + + return (*(__IO uint16_t *)tmp); +} + +/********************************************************************* + * @fn BKP_GetFlagStatus + * + * @brief Checks whether the Tamper Pin Event flag is set or not. + * + * @return FlagStatus - SET or RESET. + */ +FlagStatus BKP_GetFlagStatus(void) +{ + if(BKP->TPCSR & (1 << 8)) + { + return SET; + } + else + { + return RESET; + } +} + +/********************************************************************* + * @fn BKP_ClearFlag + * + * @brief Clears Tamper Pin Event pending flag. + * + * @return none + */ +void BKP_ClearFlag(void) +{ + BKP->TPCSR |= BKP_CTE; +} + +/********************************************************************* + * @fn BKP_GetITStatus + * + * @brief Checks whether the Tamper Pin Interrupt has occurred or not. + * + * @return ITStatus - SET or RESET. + */ +ITStatus BKP_GetITStatus(void) +{ + if(BKP->TPCSR & (1 << 9)) + { + return SET; + } + else + { + return RESET; + } +} + +/********************************************************************* + * @fn BKP_ClearITPendingBit + * + * @brief Clears Tamper Pin Interrupt pending bit. + * + * @return none + */ +void BKP_ClearITPendingBit(void) +{ + BKP->TPCSR |= BKP_CTI; +} diff --git a/ZDBMS/BMS_MC/Peripheral/src/ch32l103_can.c b/ZDBMS/BMS_MC/Peripheral/src/ch32l103_can.c new file mode 100644 index 0000000..0e5e240 --- /dev/null +++ b/ZDBMS/BMS_MC/Peripheral/src/ch32l103_can.c @@ -0,0 +1,1697 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32l103_can.c + * Author : WCH + * Version : V1.0.0 + * Date : 2023/07/08 + * Description : This file provides all the CAN firmware functions. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#include "ch32l103_can.h" +#include "ch32l103_rcc.h" + +/* CAN CTLR Register bits */ +#define CTLR_DBF ((uint32_t)0x00010000) + +/* CAN Mailbox Transmit Request */ +#define TMIDxR_TXRQ ((uint32_t)0x00000001) + +/* CAN FCTLR Register bits */ +#define FCTLR_FINIT ((uint32_t)0x00000001) + +/* Time out for INAK bit */ +#define INAK_TIMEOUT ((uint32_t)0x0000FFFF) +/* Time out for SLAK bit */ +#define SLAK_TIMEOUT ((uint32_t)0x0000FFFF) + + +/* Flags in TSTATR register */ +#define CAN_FLAGS_TSTATR ((uint32_t)0x08000000) +/* Flags in RFIFO1 register */ +#define CAN_FLAGS_RFIFO1 ((uint32_t)0x04000000) +/* Flags in RFIFO0 register */ +#define CAN_FLAGS_RFIFO0 ((uint32_t)0x02000000) +/* Flags in STATR register */ +#define CAN_FLAGS_STATR ((uint32_t)0x01000000) +/* Flags in ERRSR register */ +#define CAN_FLAGS_ERRSR ((uint32_t)0x00F00000) + +/* Mailboxes definition */ +#define CAN_TXMAILBOX_0 ((uint8_t)0x00) +#define CAN_TXMAILBOX_1 ((uint8_t)0x01) +#define CAN_TXMAILBOX_2 ((uint8_t)0x02) + + +#define CAN_MODE_MASK ((uint32_t) 0x00000003) + +static ITStatus CheckITStatus(uint32_t CAN_Reg, uint32_t It_Bit); + + +/********************************************************************* + * @fn CAN_DeInit + * + * @brief Deinitializes the CAN peripheral registers to their default reset + * values. + * + * @param CANx - where x can be 1 to select the CAN peripheral. + * + * @return none + */ +void CAN_DeInit(CAN_TypeDef* CANx) +{ + if (CANx == CAN1) + { + RCC_PB1PeriphResetCmd(RCC_PB1Periph_CAN1, ENABLE); + RCC_PB1PeriphResetCmd(RCC_PB1Periph_CAN1, DISABLE); + } +} + +/********************************************************************* + * @fn CAN_Init + * + * @brief Initializes the CAN peripheral according to the specified + * parameters in the CAN_InitStruct. + * + * @param CANx - where x can be 1 to select the CAN peripheral. + * CAN_InitStruct - pointer to a CAN_InitTypeDef structure that + * contains the configuration information for the CAN peripheral. + * + * @return InitStatus - CAN InitStatus state. +* CAN_InitStatus_Failed. +* CAN_InitStatus_Success. + */ +uint8_t CAN_Init(CAN_TypeDef* CANx, CAN_InitTypeDef* CAN_InitStruct) +{ + uint8_t InitStatus = CAN_InitStatus_Failed; + uint32_t wait_ack = 0x00000000; + + CANx->CANFD_CR &= ~(1); + + CANx->CTLR &= (~(uint32_t)CAN_CTLR_SLEEP); + CANx->CTLR |= CAN_CTLR_INRQ ; + + while (((CANx->STATR & CAN_STATR_INAK) != CAN_STATR_INAK) && (wait_ack != INAK_TIMEOUT)) + { + wait_ack++; + } + + if ((CANx->STATR & CAN_STATR_INAK) != CAN_STATR_INAK) + { + InitStatus = CAN_InitStatus_Failed; + } + else + { + if (CAN_InitStruct->CAN_TTCM == ENABLE) + { + CANx->CTLR |= CAN_CTLR_TTCM; + } + else + { + CANx->CTLR &= ~(uint32_t)CAN_CTLR_TTCM; + } + + if (CAN_InitStruct->CAN_ABOM == ENABLE) + { + CANx->CTLR |= CAN_CTLR_ABOM; + } + else + { + CANx->CTLR &= ~(uint32_t)CAN_CTLR_ABOM; + } + + if (CAN_InitStruct->CAN_AWUM == ENABLE) + { + CANx->CTLR |= CAN_CTLR_AWUM; + } + else + { + CANx->CTLR &= ~(uint32_t)CAN_CTLR_AWUM; + } + + if (CAN_InitStruct->CAN_NART == ENABLE) + { + CANx->CTLR |= CAN_CTLR_NART; + } + else + { + CANx->CTLR &= ~(uint32_t)CAN_CTLR_NART; + } + + if (CAN_InitStruct->CAN_RFLM == ENABLE) + { + CANx->CTLR |= CAN_CTLR_RFLM; + } + else + { + CANx->CTLR &= ~(uint32_t)CAN_CTLR_RFLM; + } + + if (CAN_InitStruct->CAN_TXFP == ENABLE) + { + CANx->CTLR |= CAN_CTLR_TXFP; + } + else + { + CANx->CTLR &= ~(uint32_t)CAN_CTLR_TXFP; + } + + CANx->BTIMR = (uint32_t)((uint32_t)CAN_InitStruct->CAN_Mode << 30) | \ + ((uint32_t)CAN_InitStruct->CAN_SJW << 24) | \ + ((uint32_t)CAN_InitStruct->CAN_BS1 << 16) | \ + ((uint32_t)CAN_InitStruct->CAN_BS2 << 20) | \ + ((uint32_t)CAN_InitStruct->CAN_Prescaler - 1); + CANx->CTLR &= ~(uint32_t)CAN_CTLR_INRQ; + wait_ack = 0; + + while (((CANx->STATR & CAN_STATR_INAK) == CAN_STATR_INAK) && (wait_ack != INAK_TIMEOUT)) + { + wait_ack++; + } + + if ((CANx->STATR & CAN_STATR_INAK) == CAN_STATR_INAK) + { + InitStatus = CAN_InitStatus_Failed; + } + else + { + InitStatus = CAN_InitStatus_Success ; + } + } + + return InitStatus; +} + +/********************************************************************* + * @fn CAN_FilterInit + * + * @brief Initializes the CAN peripheral according to the specified + * parameters in the CAN_FilterInitStruct. + * + * @param CAN_FilterInitStruct - pointer to a CAN_FilterInitTypeDef + * structure that contains the configuration information. + * + * @return none + */ +void CAN_FilterInit(CAN_FilterInitTypeDef* CAN_FilterInitStruct) +{ + uint32_t filter_number_bit_pos = 0; + + filter_number_bit_pos = ((uint32_t)1) << CAN_FilterInitStruct->CAN_FilterNumber; + CAN1->FCTLR |= FCTLR_FINIT; + CAN1->FWR &= ~(uint32_t)filter_number_bit_pos; + + if (CAN_FilterInitStruct->CAN_FilterScale == CAN_FilterScale_16bit) + { + CAN1->FSCFGR &= ~(uint32_t)filter_number_bit_pos; + + CAN1->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR1 = + ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdLow) << 16) | + (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdLow); + + CAN1->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR2 = + ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdHigh) << 16) | + (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdHigh); + } + + if (CAN_FilterInitStruct->CAN_FilterScale == CAN_FilterScale_32bit) + { + CAN1->FSCFGR |= filter_number_bit_pos; + + CAN1->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR1 = + ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdHigh) << 16) | + (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdLow); + + CAN1->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR2 = + ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdHigh) << 16) | + (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdLow); + } + + if (CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdMask) + { + CAN1->FMCFGR &= ~(uint32_t)filter_number_bit_pos; + } + else + { + CAN1->FMCFGR |= (uint32_t)filter_number_bit_pos; + } + + if (CAN_FilterInitStruct->CAN_FilterFIFOAssignment == CAN_Filter_FIFO0) + { + CAN1->FAFIFOR &= ~(uint32_t)filter_number_bit_pos; + } + + if (CAN_FilterInitStruct->CAN_FilterFIFOAssignment == CAN_Filter_FIFO1) + { + CAN1->FAFIFOR |= (uint32_t)filter_number_bit_pos; + } + + if (CAN_FilterInitStruct->CAN_FilterActivation == ENABLE) + { + CAN1->FWR |= filter_number_bit_pos; + } + + CAN1->FCTLR &= ~FCTLR_FINIT; +} + +/********************************************************************* + * @fn CAN_StructInit + * + * @brief Fills each CAN_InitStruct member with its default value. + * + * @param CAN_InitStruct - pointer to a CAN_InitTypeDef structure which + * will be initialized. + * + * @return none + */ +void CAN_StructInit(CAN_InitTypeDef* CAN_InitStruct) +{ + CAN_InitStruct->CAN_TTCM = DISABLE; + CAN_InitStruct->CAN_ABOM = DISABLE; + CAN_InitStruct->CAN_AWUM = DISABLE; + CAN_InitStruct->CAN_NART = DISABLE; + CAN_InitStruct->CAN_RFLM = DISABLE; + CAN_InitStruct->CAN_TXFP = DISABLE; + CAN_InitStruct->CAN_Mode = CAN_Mode_Normal; + CAN_InitStruct->CAN_SJW = CAN_SJW_1tq; + CAN_InitStruct->CAN_BS1 = CAN_BS1_4tq; + CAN_InitStruct->CAN_BS2 = CAN_BS2_3tq; + CAN_InitStruct->CAN_Prescaler = 1; +} + +/********************************************************************* + * @fn CAN_SlaveStartBank + * + * @brief This function applies only to CH32 Connectivity line devices. + * + * @param CAN_BankNumber - Select the start slave bank filter from 1..27. + * + * @return none + */ +void CAN_SlaveStartBank(uint8_t CAN_BankNumber) +{ + CAN1->FCTLR |= FCTLR_FINIT; + CAN1->FCTLR &= (uint32_t)0xFFFFC0F1 ; + CAN1->FCTLR |= (uint32_t)(CAN_BankNumber)<<8; + CAN1->FCTLR &= ~FCTLR_FINIT; +} + +/********************************************************************* + * @fn CAN_DBGFreeze + * + * @brief Enables or disables the DBG Freeze for CAN. + * + * @param CANx - where x can be 1 to select the CAN peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void CAN_DBGFreeze(CAN_TypeDef* CANx, FunctionalState NewState) +{ + if (NewState != DISABLE) + { + CANx->CTLR |= CTLR_DBF; + } + else + { + CANx->CTLR &= ~CTLR_DBF; + } +} + +/********************************************************************* + * @fn CAN_TTComModeCmd + * + * @brief Enables or disables the CAN Time TriggerOperation communication mode. + * + * @param CANx - where x can be 1 to select the CAN peripheral. + * NewState - ENABLE or DISABLE. + * Note- + * DLC must be programmed as 8 in order Time Stamp (2 bytes) to be + * sent over the CAN bus. + * + * @return none + */ +void CAN_TTComModeCmd(CAN_TypeDef* CANx, FunctionalState NewState) +{ + if (NewState != DISABLE) + { + CANx->CTLR |= CAN_CTLR_TTCM; + + CANx->sTxMailBox[0].TXMDTR |= ((uint32_t)CAN_TXMDT0R_TGT); + CANx->sTxMailBox[1].TXMDTR |= ((uint32_t)CAN_TXMDT1R_TGT); + CANx->sTxMailBox[2].TXMDTR |= ((uint32_t)CAN_TXMDT2R_TGT); + } + else + { + CANx->CTLR &= (uint32_t)(~(uint32_t)CAN_CTLR_TTCM); + + CANx->sTxMailBox[0].TXMDTR &= ((uint32_t)~CAN_TXMDT0R_TGT); + CANx->sTxMailBox[1].TXMDTR &= ((uint32_t)~CAN_TXMDT1R_TGT); + CANx->sTxMailBox[2].TXMDTR &= ((uint32_t)~CAN_TXMDT2R_TGT); + } +} + +/********************************************************************* + * @fn CAN_Transmit + * + * @brief Initiates the transmission of a message. + * + * @param CANx - where x can be 1 to select the CAN peripheral. + * TxMessage - pointer to a structure which contains CAN Id, CAN + * DLC and CAN data. + * + * @return transmit_mailbox - The number of the mailbox that is used for + * transmission or CAN_TxStatus_NoMailBox if there is no empty mailbox. + */ +uint8_t CAN_Transmit(CAN_TypeDef* CANx, CanTxMsg* TxMessage) +{ + uint8_t transmit_mailbox = 0; + + CANx->CANFD_CR &= ~(1); + + if ((CANx->TSTATR&CAN_TSTATR_TME0) == CAN_TSTATR_TME0) + { + transmit_mailbox = 0; + } + else if ((CANx->TSTATR&CAN_TSTATR_TME1) == CAN_TSTATR_TME1) + { + transmit_mailbox = 1; + } + else if ((CANx->TSTATR&CAN_TSTATR_TME2) == CAN_TSTATR_TME2) + { + transmit_mailbox = 2; + } + else + { + transmit_mailbox = CAN_TxStatus_NoMailBox; + } + + if (transmit_mailbox != CAN_TxStatus_NoMailBox) + { + CANx->sTxMailBox[transmit_mailbox].TXMIR &= TMIDxR_TXRQ; + if (TxMessage->IDE == CAN_Id_Standard) + { + CANx->sTxMailBox[transmit_mailbox].TXMIR |= ((TxMessage->StdId << 21) | \ + TxMessage->RTR); + } + else + { + CANx->sTxMailBox[transmit_mailbox].TXMIR |= ((TxMessage->ExtId << 3) | \ + TxMessage->IDE | \ + TxMessage->RTR); + } + + TxMessage->DLC &= (uint8_t)0x0000000F; + CANx->sTxMailBox[transmit_mailbox].TXMDTR &= (uint32_t)0xFFFFFFF0; + CANx->sTxMailBox[transmit_mailbox].TXMDTR |= TxMessage->DLC; + + CANx->sTxMailBox[transmit_mailbox].TXMDLR = (((uint32_t)TxMessage->Data[3] << 24) | + ((uint32_t)TxMessage->Data[2] << 16) | + ((uint32_t)TxMessage->Data[1] << 8) | + ((uint32_t)TxMessage->Data[0])); + CANx->sTxMailBox[transmit_mailbox].TXMDHR = (((uint32_t)TxMessage->Data[7] << 24) | + ((uint32_t)TxMessage->Data[6] << 16) | + ((uint32_t)TxMessage->Data[5] << 8) | + ((uint32_t)TxMessage->Data[4])); + CANx->sTxMailBox[transmit_mailbox].TXMIR |= TMIDxR_TXRQ; + } + + return transmit_mailbox; +} + +/********************************************************************* + * @fn CAN_TransmitStatus + * + * @brief Checks the transmission of a message. + * + * @param CANx - where x can be 1 to select the CAN peripheral. + * TransmitMailbox - the number of the mailbox that is used for + * transmission. + * + * @return state - + * CAN_TxStatus_Ok. + * CAN_TxStatus_Failed. + */ +uint8_t CAN_TransmitStatus(CAN_TypeDef* CANx, uint8_t TransmitMailbox) +{ + uint32_t state = 0; + + switch (TransmitMailbox) + { + case (CAN_TXMAILBOX_0): + state = CANx->TSTATR & (CAN_TSTATR_RQCP0 | CAN_TSTATR_TXOK0 | CAN_TSTATR_TME0); + break; + + case (CAN_TXMAILBOX_1): + state = CANx->TSTATR & (CAN_TSTATR_RQCP1 | CAN_TSTATR_TXOK1 | CAN_TSTATR_TME1); + break; + + case (CAN_TXMAILBOX_2): + state = CANx->TSTATR & (CAN_TSTATR_RQCP2 | CAN_TSTATR_TXOK2 | CAN_TSTATR_TME2); + break; + + default: + state = CAN_TxStatus_Failed; + break; + } + + switch (state) + { + case (0x0): + state = CAN_TxStatus_Pending; + break; + + case (CAN_TSTATR_RQCP0 | CAN_TSTATR_TME0): + state = CAN_TxStatus_Failed; + break; + + case (CAN_TSTATR_RQCP1 | CAN_TSTATR_TME1): + state = CAN_TxStatus_Failed; + break; + + case (CAN_TSTATR_RQCP2 | CAN_TSTATR_TME2): + state = CAN_TxStatus_Failed; + break; + + case (CAN_TSTATR_RQCP0 | CAN_TSTATR_TXOK0 | CAN_TSTATR_TME0): + state = CAN_TxStatus_Ok; + break; + + case (CAN_TSTATR_RQCP1 | CAN_TSTATR_TXOK1 | CAN_TSTATR_TME1): + state = CAN_TxStatus_Ok; + break; + + case (CAN_TSTATR_RQCP2 | CAN_TSTATR_TXOK2 | CAN_TSTATR_TME2): + state = CAN_TxStatus_Ok; + break; + + default: + state = CAN_TxStatus_Failed; + break; + } + + return (uint8_t) state; +} + +/********************************************************************* + * @fn CAN_CancelTransmit + * + * @brief Cancels a transmit request. + * + * @param CANx - where x can be 1 to select the CAN peripheral. + * Mailbox - Mailbox number. + * CAN_TXMAILBOX_0. + * CAN_TXMAILBOX_1. + * CAN_TXMAILBOX_2. + * + * @return none + */ +void CAN_CancelTransmit(CAN_TypeDef* CANx, uint8_t Mailbox) +{ + switch (Mailbox) + { + case (CAN_TXMAILBOX_0): + CANx->TSTATR |= CAN_TSTATR_ABRQ0; + break; + + case (CAN_TXMAILBOX_1): + CANx->TSTATR |= CAN_TSTATR_ABRQ1; + break; + + case (CAN_TXMAILBOX_2): + CANx->TSTATR |= CAN_TSTATR_ABRQ2; + break; + + default: + break; + } +} + +/********************************************************************* + * @fn CAN_Receive + * + * @brief Receives a message. + * + * @param CANx - where x can be 1 to select the CAN peripheral. + * FIFONumber - Receive FIFO number. + * CAN_FIFO0. + * CAN_FIFO1. + * RxMessage - pointer to a structure receive message which contains + * CAN Id, CAN DLC, CAN datas and FMI number. + * + * @return none + */ +void CAN_Receive(CAN_TypeDef* CANx, uint8_t FIFONumber, CanRxMsg* RxMessage) +{ + RxMessage->IDE = (uint8_t)0x04 & CANx->sFIFOMailBox[FIFONumber].RXMIR; + + if (RxMessage->IDE == CAN_Id_Standard) + { + RxMessage->StdId = (uint32_t)0x000007FF & (CANx->sFIFOMailBox[FIFONumber].RXMIR >> 21); + } + else + { + RxMessage->ExtId = (uint32_t)0x1FFFFFFF & (CANx->sFIFOMailBox[FIFONumber].RXMIR >> 3); + } + + RxMessage->RTR = (uint8_t)0x02 & CANx->sFIFOMailBox[FIFONumber].RXMIR; + RxMessage->DLC = (uint8_t)0x0F & CANx->sFIFOMailBox[FIFONumber].RXMDTR; + RxMessage->FMI = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RXMDTR >> 8); + RxMessage->Data[0] = (uint8_t)0xFF & CANx->sFIFOMailBox[FIFONumber].RXMDLR; + RxMessage->Data[1] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RXMDLR >> 8); + RxMessage->Data[2] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RXMDLR >> 16); + RxMessage->Data[3] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RXMDLR >> 24); + RxMessage->Data[4] = (uint8_t)0xFF & CANx->sFIFOMailBox[FIFONumber].RXMDHR; + RxMessage->Data[5] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RXMDHR >> 8); + RxMessage->Data[6] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RXMDHR >> 16); + RxMessage->Data[7] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RXMDHR >> 24); + + if (FIFONumber == CAN_FIFO0) + { + CANx->RFIFO0 |= CAN_RFIFO0_RFOM0; + } + else + { + CANx->RFIFO1 |= CAN_RFIFO1_RFOM1; + } +} + +/********************************************************************* + * @fn CAN_FIFORelease + * + * @brief Releases the specified FIFO. + * + * @param CANx - where x can be 1 to select the CAN peripheral. + * FIFONumber - Receive FIFO number. + * CAN_FIFO0. + * CAN_FIFO1. + * + * @return none + */ +void CAN_FIFORelease(CAN_TypeDef* CANx, uint8_t FIFONumber) +{ + if (FIFONumber == CAN_FIFO0) + { + CANx->RFIFO0 |= CAN_RFIFO0_RFOM0; + } + else + { + CANx->RFIFO1 |= CAN_RFIFO1_RFOM1; + } +} + +/********************************************************************* + * @fn CAN_MessagePending + * + * @brief Returns the number of pending messages. + * + * @param CANx - where x can be 1 to select the CAN peripheral. + * FIFONumber - Receive FIFO number. + * CAN_FIFO0. + * CAN_FIFO1. + * + * @return message_pending: which is the number of pending message. + */ +uint8_t CAN_MessagePending(CAN_TypeDef* CANx, uint8_t FIFONumber) +{ + uint8_t message_pending=0; + + if (FIFONumber == CAN_FIFO0) + { + message_pending = (uint8_t)(CANx->RFIFO0&(uint32_t)0x03); + } + else if (FIFONumber == CAN_FIFO1) + { + message_pending = (uint8_t)(CANx->RFIFO1&(uint32_t)0x03); + } + else + { + message_pending = 0; + } + + return message_pending; +} + +/********************************************************************* + * @fn CAN_OperatingModeRequest + * + * @brief Select the CAN Operation mode. + * + * @param CANx - where x can be 1 to select the CAN peripheral. + * CAN_OperatingMode - CAN Operating Mode. + * CAN_OperatingMode_Initialization. + * CAN_OperatingMode_Normal. + * CAN_OperatingMode_Sleep. + * + * @return status - + * CAN_ModeStatus_Failed - CAN failed entering the specific mode. + * CAN_ModeStatus_Success - CAN Succeed entering the specific mode. + */ +uint8_t CAN_OperatingModeRequest(CAN_TypeDef* CANx, uint8_t CAN_OperatingMode) +{ + uint8_t status = CAN_ModeStatus_Failed; + uint32_t timeout = INAK_TIMEOUT; + + if (CAN_OperatingMode == CAN_OperatingMode_Initialization) + { + CANx->CTLR = (uint32_t)((CANx->CTLR & (uint32_t)(~(uint32_t)CAN_CTLR_SLEEP)) | CAN_CTLR_INRQ); + + while (((CANx->STATR & CAN_MODE_MASK) != CAN_STATR_INAK) && (timeout != 0)) + { + timeout--; + } + if ((CANx->STATR & CAN_MODE_MASK) != CAN_STATR_INAK) + { + status = CAN_ModeStatus_Failed; + } + else + { + status = CAN_ModeStatus_Success; + } + } + else if (CAN_OperatingMode == CAN_OperatingMode_Normal) + { + CANx->CTLR &= (uint32_t)(~(CAN_CTLR_SLEEP|CAN_CTLR_INRQ)); + + while (((CANx->STATR & CAN_MODE_MASK) != 0) && (timeout!=0)) + { + timeout--; + } + if ((CANx->STATR & CAN_MODE_MASK) != 0) + { + status = CAN_ModeStatus_Failed; + } + else + { + status = CAN_ModeStatus_Success; + } + } + else if (CAN_OperatingMode == CAN_OperatingMode_Sleep) + { + CANx->CTLR = (uint32_t)((CANx->CTLR & (uint32_t)(~(uint32_t)CAN_CTLR_INRQ)) | CAN_CTLR_SLEEP); + + while (((CANx->STATR & CAN_MODE_MASK) != CAN_STATR_SLAK) && (timeout!=0)) + { + timeout--; + } + if ((CANx->STATR & CAN_MODE_MASK) != CAN_STATR_SLAK) + { + status = CAN_ModeStatus_Failed; + } + else + { + status = CAN_ModeStatus_Success; + } + } + else + { + status = CAN_ModeStatus_Failed; + } + + return (uint8_t) status; +} + +/********************************************************************* + * @fn CAN_Sleep + * + * @brief Enters the low power mode. + * + * @param CANx - where x can be 1 to select the CAN peripheral. + * + * @return sleepstatus - + * CAN_Sleep_Ok. + * CAN_Sleep_Failed. + */ +uint8_t CAN_Sleep(CAN_TypeDef* CANx) +{ + uint8_t sleepstatus = CAN_Sleep_Failed; + + CANx->CTLR = (((CANx->CTLR) & (uint32_t)(~(uint32_t)CAN_CTLR_INRQ)) | CAN_CTLR_SLEEP); + + if ((CANx->STATR & (CAN_STATR_SLAK|CAN_STATR_INAK)) == CAN_STATR_SLAK) + { + sleepstatus = CAN_Sleep_Ok; + } + + return (uint8_t)sleepstatus; +} + +/********************************************************************* + * @fn CAN_WakeUp + * + * @brief Wakes the CAN up. + * + * @param CANx - where x can be 1 to select the CAN peripheral. + * + * @return wakeupstatus - + * CAN_WakeUp_Ok. + * CAN_WakeUp_Failed. + */ +uint8_t CAN_WakeUp(CAN_TypeDef* CANx) +{ + uint32_t wait_slak = SLAK_TIMEOUT; + uint8_t wakeupstatus = CAN_WakeUp_Failed; + + CANx->CTLR &= ~(uint32_t)CAN_CTLR_SLEEP; + + while(((CANx->STATR & CAN_STATR_SLAK) == CAN_STATR_SLAK)&&(wait_slak!=0x00)) + { + wait_slak--; + } + if((CANx->STATR & CAN_STATR_SLAK) != CAN_STATR_SLAK) + { + wakeupstatus = CAN_WakeUp_Ok; + } + + return (uint8_t)wakeupstatus; +} + +/********************************************************************* + * @fn CAN_GetLastErrorCode + * + * @brief Returns the CANx's last error code (LEC). + * + * @param CANx - where x can be 1 to select the CAN peripheral. + * + * @return errorcode - specifies the Error code. + * CAN_ErrorCode_NoErr - No Error. + * CAN_ErrorCode_StuffErr - Stuff Error. + * CAN_ErrorCode_FormErr - Form Error. + * CAN_ErrorCode_ACKErr - Acknowledgment Error. + * CAN_ErrorCode_BitRecessiveErr - Bit Recessive Error. + * CAN_ErrorCode_BitDominantErr - Bit Dominant Error. + * CAN_ErrorCode_CRCErr - CRC Error. + * CAN_ErrorCode_SoftwareSetErr - Software Set Error. + */ +uint8_t CAN_GetLastErrorCode(CAN_TypeDef* CANx) +{ + uint8_t errorcode=0; + + errorcode = (((uint8_t)CANx->ERRSR) & (uint8_t)CAN_ERRSR_LEC); + + return errorcode; +} + +/********************************************************************* + * @fn CAN_GetReceiveErrorCounter + * + * @brief Returns the CANx Receive Error Counter (REC). + * + * @param CANx - where x can be 1 to select the CAN peripheral. + * Note- + * In case of an error during reception, this counter is incremented + * by 1 or by 8 depending on the error condition as defined by the CAN + * standard. After every successful reception, the counter is + * decremented by 1 or reset to 120 if its value was higher than 128. + * When the counter value exceeds 127, the CAN controller enters the + * error passive state. + * @return counter - CAN Receive Error Counter. + */ +uint8_t CAN_GetReceiveErrorCounter(CAN_TypeDef* CANx) +{ + uint8_t counter=0; + + counter = (uint8_t)((CANx->ERRSR & CAN_ERRSR_REC)>> 24); + + return counter; +} + +/********************************************************************* + * @fn CAN_GetLSBTransmitErrorCounter + * + * @brief Returns the LSB of the 9-bit CANx Transmit Error Counter(TEC). + * + * @param CANx - where x can be 1 to select the CAN peripheral. + * + * @return counter - LSB of the 9-bit CAN Transmit Error Counter. + */ +uint8_t CAN_GetLSBTransmitErrorCounter(CAN_TypeDef* CANx) +{ + uint8_t counter=0; + + counter = (uint8_t)((CANx->ERRSR & CAN_ERRSR_TEC)>> 16); + + return counter; +} + +/********************************************************************* + * @fn CAN_ITConfig + * + * @brief Enables or disables the specified CANx interrupts. + * + * @param CANx - where x can be 1 to select the CAN peripheral. + * CAN_IT - specifies the CAN interrupt sources to be enabled or disabled. + * CAN_IT_TME. + * CAN_IT_FMP0. + * CAN_IT_FF0. + * CAN_IT_FOV0. + * CAN_IT_FMP1. + * CAN_IT_FF1. + * CAN_IT_FOV1. + * CAN_IT_EWG. + * CAN_IT_EPV. + * CAN_IT_LEC. + * CAN_IT_ERR. + * CAN_IT_WKU. + * CAN_IT_SLK. + * NewState - ENABLE or DISABLE. + * + * @return counter - LSB of the 9-bit CAN Transmit Error Counter. + */ +void CAN_ITConfig(CAN_TypeDef* CANx, uint32_t CAN_IT, FunctionalState NewState) +{ + if (NewState != DISABLE) + { + CANx->INTENR |= CAN_IT; + } + else + { + CANx->INTENR &= ~CAN_IT; + } +} + +/********************************************************************* + * @fn CAN_GetFlagStatus + * + * @brief Checks whether the specified CAN flag is set or not. + * + * @param CANx - where x can be 1 to select the CAN peripheral. + * CAN_FLAG - specifies the flag to check. + * CAN_FLAG_EWG. + * CAN_FLAG_EPV. + * CAN_FLAG_BOF. + * CAN_FLAG_RQCP0. + * CAN_FLAG_RQCP1. + * CAN_FLAG_RQCP2. + * CAN_FLAG_FMP1. + * CAN_FLAG_FF1. + * CAN_FLAG_FOV1. + * CAN_FLAG_FMP0. + * CAN_FLAG_FF0. + * CAN_FLAG_FOV0. + * CAN_FLAG_WKU. + * CAN_FLAG_SLAK. + * CAN_FLAG_LEC. + * NewState - ENABLE or DISABLE. + * + * @return FlagStatus - SET or RESET. + */ +FlagStatus CAN_GetFlagStatus(CAN_TypeDef* CANx, uint32_t CAN_FLAG) +{ + FlagStatus bitstatus = RESET; + + if((CAN_FLAG & CAN_FLAGS_ERRSR) != (uint32_t)RESET) + { + if ((CANx->ERRSR & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + } + else if((CAN_FLAG & CAN_FLAGS_STATR) != (uint32_t)RESET) + { + if ((CANx->STATR & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + } + else if((CAN_FLAG & CAN_FLAGS_TSTATR) != (uint32_t)RESET) + { + if ((CANx->TSTATR & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + } + else if((CAN_FLAG & CAN_FLAGS_RFIFO0) != (uint32_t)RESET) + { + if ((CANx->RFIFO0 & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + } + else + { + if ((uint32_t)(CANx->RFIFO1 & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + } + + return bitstatus; +} + +/********************************************************************* + * @fn CAN_ClearFlag + * + * @brief Clears the CAN's pending flags. + * + * @param CANx - where x can be 1 to select the CAN peripheral. + * CAN_FLAG - specifies the flag to clear. + * CAN_FLAG_RQCP0. + * CAN_FLAG_RQCP1. + * CAN_FLAG_RQCP2. + * CAN_FLAG_FF1. + * CAN_FLAG_FOV1. + * CAN_FLAG_FF0. + * CAN_FLAG_FOV0. + * CAN_FLAG_WKU. + * CAN_FLAG_SLAK. + * CAN_FLAG_LEC. + * + * @return none + */ +void CAN_ClearFlag(CAN_TypeDef* CANx, uint32_t CAN_FLAG) +{ + uint32_t flagtmp=0; + + if (CAN_FLAG == CAN_FLAG_LEC) + { + CANx->ERRSR = (uint32_t)RESET; + } + else + { + flagtmp = CAN_FLAG & 0x000FFFFF; + + if ((CAN_FLAG & CAN_FLAGS_RFIFO0)!=(uint32_t)RESET) + { + CANx->RFIFO0 = (uint32_t)(flagtmp); + } + else if ((CAN_FLAG & CAN_FLAGS_RFIFO1)!=(uint32_t)RESET) + { + CANx->RFIFO1 = (uint32_t)(flagtmp); + } + else if ((CAN_FLAG & CAN_FLAGS_TSTATR)!=(uint32_t)RESET) + { + CANx->TSTATR = (uint32_t)(flagtmp); + } + else + { + CANx->STATR = (uint32_t)(flagtmp); + } + } +} + +/********************************************************************* + * @fn CAN_GetITStatus + * + * @brief Checks whether the specified CANx interrupt has occurred or not. + * + * @param CANx - where x can be 1 to select the CAN peripheral. + * CAN_IT - specifies the CAN interrupt source to check. + * CAN_IT_TME. + * CAN_IT_FMP0. + * CAN_IT_FF0. + * CAN_IT_FOV0. + * CAN_IT_FMP1. + * CAN_IT_FF1. + * CAN_IT_FOV1. + * CAN_IT_WKU. + * CAN_IT_SLK. + * CAN_IT_EWG. + * CAN_IT_EPV. + * CAN_IT_BOF. + * CAN_IT_LEC. + * CAN_IT_ERR. + * + * @return ITStatus - SET or RESET. + */ +ITStatus CAN_GetITStatus(CAN_TypeDef* CANx, uint32_t CAN_IT) +{ + ITStatus itstatus = RESET; + + if((CANx->INTENR & CAN_IT) != RESET) + { + switch (CAN_IT) + { + case CAN_IT_TME: + itstatus = CheckITStatus(CANx->TSTATR, CAN_TSTATR_RQCP0|CAN_TSTATR_RQCP1|CAN_TSTATR_RQCP2); + break; + + case CAN_IT_FMP0: + itstatus = CheckITStatus(CANx->RFIFO0, CAN_RFIFO0_FMP0); + break; + + case CAN_IT_FF0: + itstatus = CheckITStatus(CANx->RFIFO0, CAN_RFIFO0_FULL0); + break; + + case CAN_IT_FOV0: + itstatus = CheckITStatus(CANx->RFIFO0, CAN_RFIFO0_FOVR0); + break; + + case CAN_IT_FMP1: + itstatus = CheckITStatus(CANx->RFIFO1, CAN_RFIFO1_FMP1); + break; + + case CAN_IT_FF1: + itstatus = CheckITStatus(CANx->RFIFO1, CAN_RFIFO1_FULL1); + break; + + case CAN_IT_FOV1: + itstatus = CheckITStatus(CANx->RFIFO1, CAN_RFIFO1_FOVR1); + break; + + case CAN_IT_WKU: + itstatus = CheckITStatus(CANx->STATR, CAN_STATR_WKUI); + break; + + case CAN_IT_SLK: + itstatus = CheckITStatus(CANx->STATR, CAN_STATR_SLAKI); + break; + + case CAN_IT_EWG: + itstatus = CheckITStatus(CANx->ERRSR, CAN_ERRSR_EWGF); + break; + + case CAN_IT_EPV: + itstatus = CheckITStatus(CANx->ERRSR, CAN_ERRSR_EPVF); + break; + + case CAN_IT_BOF: + itstatus = CheckITStatus(CANx->ERRSR, CAN_ERRSR_BOFF); + break; + + case CAN_IT_LEC: + itstatus = CheckITStatus(CANx->ERRSR, CAN_ERRSR_LEC); + break; + + case CAN_IT_ERR: + itstatus = CheckITStatus(CANx->STATR, CAN_STATR_ERRI); + break; + + default : + itstatus = RESET; + break; + } + } + else + { + itstatus = RESET; + } + + return itstatus; +} + +/********************************************************************* + * @fn CAN_ClearITPendingBit + * + * @brief Clears the CANx's interrupt pending bits. + * + * @param CANx - where x can be 1 to select the CAN peripheral. + * CAN_IT - specifies the interrupt pending bit to clear. + * CAN_IT_TME. + * CAN_IT_FF0. + * CAN_IT_FOV0. + * CAN_IT_FF1. + * CAN_IT_FOV1. + * CAN_IT_WKU. + * CAN_IT_SLK. + * CAN_IT_EWG. + * CAN_IT_EPV. + * CAN_IT_BOF. + * CAN_IT_LEC. + * CAN_IT_ERR. + * + * @return none + */ +void CAN_ClearITPendingBit(CAN_TypeDef* CANx, uint32_t CAN_IT) +{ + switch (CAN_IT) + { + case CAN_IT_TME: + CANx->TSTATR = CAN_TSTATR_RQCP0|CAN_TSTATR_RQCP1|CAN_TSTATR_RQCP2; + break; + + case CAN_IT_FF0: + CANx->RFIFO0 = CAN_RFIFO0_FULL0; + break; + + case CAN_IT_FOV0: + CANx->RFIFO0 = CAN_RFIFO0_FOVR0; + break; + + case CAN_IT_FF1: + CANx->RFIFO1 = CAN_RFIFO1_FULL1; + break; + + case CAN_IT_FOV1: + CANx->RFIFO1 = CAN_RFIFO1_FOVR1; + break; + + case CAN_IT_WKU: + CANx->STATR = CAN_STATR_WKUI; + break; + + case CAN_IT_SLK: + CANx->STATR = CAN_STATR_SLAKI; + break; + + case CAN_IT_EWG: + CANx->STATR = CAN_STATR_ERRI; + break; + + case CAN_IT_EPV: + CANx->STATR = CAN_STATR_ERRI; + break; + + case CAN_IT_BOF: + CANx->STATR = CAN_STATR_ERRI; + break; + + case CAN_IT_LEC: + CANx->ERRSR = RESET; + CANx->STATR = CAN_STATR_ERRI; + break; + + case CAN_IT_ERR: + CANx->ERRSR = RESET; + CANx->STATR = CAN_STATR_ERRI; + break; + + default : + break; + } +} + +/********************************************************************* + * @fn CheckITStatus + * + * @brief Checks whether the CAN interrupt has occurred or not. + * + * @param CAN_Reg - specifies the CAN interrupt register to check + * It_Bit - specifies the interrupt source bit to check. + * + * @return ITStatus - SET or RESET. + */ +static ITStatus CheckITStatus(uint32_t CAN_Reg, uint32_t It_Bit) +{ + ITStatus pendingbitstatus = RESET; + + if ((CAN_Reg & It_Bit) != (uint32_t)RESET) + { + pendingbitstatus = SET; + } + else + { + pendingbitstatus = RESET; + } + + return pendingbitstatus; +} + +/********************************************************************* + * @fn CAN_BS1_ModeConfig + * + * @brief Configures the CAN the number of time quanta in Bit and mode. + * + * @param CANx - where x can be 1 to select the CAN peripheral. + * CAN_BS1_Mode - CAN BS1 Mode + * CAN_BS1_4bit - 4bit mode + * CAN_BS1_tq = TS1[3:0];(CANx->BTIMR) + * This parameter must range from 0x00 to 0x0F. + * CAN_BS1_6bit - 6bit mode + * CAN_BS1_tq = (TS1[1:0] << 4) + BTR_TS1_T[3:0];(CANx->BTIMR) + * This parameter must range from 0x00 to 0x3F. + * + * @return none + */ +void CAN_BS1_ModeConfig(CAN_TypeDef* CANx, uint32_t CAN_BS1_Mode, uint8_t CAN_BS1_tq) +{ + CANx->CANFD_CR &= ~(CAN_BS1_6bit); + CANx->BTIMR &= ~(0x000FF000); + + if(CAN_BS1_Mode == CAN_BS1_6bit) + { + CANx->CANFD_CR |= CAN_BS1_6bit; + CANx->BTIMR |= (CAN_BS1_tq << 16); + } + else if(CAN_BS1_Mode == CAN_BS1_4bit) + { + CANx->BTIMR |= (CAN_BS1_tq << 12); + } +} + +/********************************************************************* + * @fn CAN_BusOff_ErrCntConfig + * + * @brief Configures the CAN the number of err count bus off. + * + * @param CANx - where x can be 1 to select the CAN peripheral. + * BusOff_ErrCnt - Err count bus off. + * This parameter must range from 0x00 to 0xFF. + * + * @return none + */ +void CAN_BusOff_ErrCntConfig(CAN_TypeDef *CANx, uint8_t BusOff_ErrCnt) +{ + CANx->TERR_CNT &= ~(0x000000FF); + CANx->TERR_CNT |= (uint32_t)BusOff_ErrCnt; +} + +/********************************************************************* + * @fn CANFD_Restrict_ModeCmd + * + * @brief Enables or disables the CANFD restrict mode. + * + * @param CANx - where x can be 1 to select the CANFD peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void CANFD_Restrict_ModeCmd(CAN_TypeDef *CANx, FunctionalState NewState) +{ + + if(NewState) + { + CANx->CANFD_CR |= (1<<9); + } + else + { + CANx->CANFD_CR &= ~(1<<9); + } +} + +/********************************************************************* + * @fn CANFD_Init + * + * @brief Initializes the CAN peripheral according to the specified + * parameters in the CANFD_InitStruct. + * + * @param CANx - where x can be 1 to select the CAN peripheral. + * CANFD_InitStruct - pointer to a CANFD_InitTypeDef structure that + * contains the configuration information for the CAN peripheral. + * + * @return InitStatus - CAN InitStatus state. +* CAN_InitStatus_Failed. +* CAN_InitStatus_Success. + */ +uint8_t CANFD_Init(CAN_TypeDef* CANx, CANFD_InitTypeDef* CANFD_InitStruct) +{ + uint8_t InitStatus = CAN_InitStatus_Failed; + uint32_t wait_ack = 0x00000000; + + CANx->CANFD_CR |= 1; + + CANx->CTLR &= (~(uint32_t)CAN_CTLR_SLEEP); + CANx->CTLR |= CAN_CTLR_INRQ ; + + while (((CANx->STATR & CAN_STATR_INAK) != CAN_STATR_INAK) && (wait_ack != INAK_TIMEOUT)) + { + wait_ack++; + } + + if ((CANx->STATR & CAN_STATR_INAK) != CAN_STATR_INAK) + { + InitStatus = CAN_InitStatus_Failed; + } + else + { + if (CANFD_InitStruct->CANFD_TTCM == ENABLE) + { + CANx->CTLR |= CAN_CTLR_TTCM; + } + else + { + CANx->CTLR &= ~(uint32_t)CAN_CTLR_TTCM; + } + + if (CANFD_InitStruct->CANFD_ABOM == ENABLE) + { + CANx->CTLR |= CAN_CTLR_ABOM; + } + else + { + CANx->CTLR &= ~(uint32_t)CAN_CTLR_ABOM; + } + + if (CANFD_InitStruct->CANFD_AWUM == ENABLE) + { + CANx->CTLR |= CAN_CTLR_AWUM; + } + else + { + CANx->CTLR &= ~(uint32_t)CAN_CTLR_AWUM; + } + + if (CANFD_InitStruct->CANFD_NART == ENABLE) + { + CANx->CTLR |= CAN_CTLR_NART; + } + else + { + CANx->CTLR &= ~(uint32_t)CAN_CTLR_NART; + } + + if (CANFD_InitStruct->CANFD_TXFP == ENABLE) + { + CANx->CTLR |= CAN_CTLR_TXFP; + } + else + { + CANx->CTLR &= ~(uint32_t)CAN_CTLR_TXFP; + } + + if (CANFD_InitStruct->CANFD_RES_Error == ENABLE) + { + CANx->CANFD_CR |= (1<<7); + } + else + { + CANx->CANFD_CR &= ~(1<<7); + } + + if (CANFD_InitStruct->CANFD_BRS_TXM0 == ENABLE) + { + CANx->CANFD_CR |= (1<<1); + } + else + { + CANx->CANFD_CR &= ~(1<<1); + } + + if (CANFD_InitStruct->CANFD_BRS_TXM1 == ENABLE) + { + CANx->CANFD_CR |= (1<<2); + } + else + { + CANx->CANFD_CR &= ~(1<<2); + } + + if (CANFD_InitStruct->CANFD_BRS_TXM2 == ENABLE) + { + CANx->CANFD_CR |= (1<<3); + } + else + { + CANx->CANFD_CR &= ~(1<<3); + } + + if (CANFD_InitStruct->CANFD_ESI_Auto_TXM0 == ENABLE) + { + CANx->CANFD_CR |= (1<<4); + } + else + { + CANx->CANFD_CR &= ~(1<<4); + } + + if (CANFD_InitStruct->CANFD_ESI_Auto_TXM1 == ENABLE) + { + CANx->CANFD_CR |= (1<<5); + } + else + { + CANx->CANFD_CR &= ~(1<<5); + } + + if (CANFD_InitStruct->CANFD_ESI_Auto_TXM2 == ENABLE) + { + CANx->CANFD_CR |= (1<<6); + } + else + { + CANx->CANFD_CR &= ~(1<<6); + } + + CANx->CANFD_BTR &= ~(0x009F1FFF); + CANx->CANFD_TDCT &= ~(0x00003F3F); + + CANx->CANFD_TDCT = (uint32_t)((uint32_t)CANFD_InitStruct->CANFD_TDC_FILTER << 8) | \ + ((uint32_t)CANFD_InitStruct->CANFD_TDC0); + + CANx->CANFD_BTR = (uint32_t)((uint32_t)CANFD_InitStruct->CANFD_TDCE << 23) | \ + (((uint32_t)CANFD_InitStruct->CANFD_Prescaler-1) << 16) | \ + ((uint32_t)CANFD_InitStruct->CANFD_BS1 << 8) | \ + ((uint32_t)CANFD_InitStruct->CANFD_BS2 << 4) | \ + ((uint32_t)CANFD_InitStruct->CANFD_SJW); + + CANx->CTLR &= ~(uint32_t)CAN_CTLR_INRQ; + wait_ack = 0; + + while (((CANx->STATR & CAN_STATR_INAK) == CAN_STATR_INAK) && (wait_ack != INAK_TIMEOUT)) + { + wait_ack++; + } + + if ((CANx->STATR & CAN_STATR_INAK) == CAN_STATR_INAK) + { + InitStatus = CAN_InitStatus_Failed; + } + else + { + InitStatus = CAN_InitStatus_Success ; + } + } + + return InitStatus; +} + +/********************************************************************* + * @fn CANFD_StructInit + * + * @brief Fills each CANFD_InitStruct member with its default value. + * + * @param CANFD_InitStruct - pointer to a CANFD_InitTypeDef structure which + * will be initialized. + * + * @return none + */ +void CANFD_StructInit(CANFD_InitTypeDef* CANFD_InitStruct) +{ + CANFD_InitStruct->CANFD_TTCM = DISABLE; + CANFD_InitStruct->CANFD_ABOM = DISABLE; + CANFD_InitStruct->CANFD_AWUM = DISABLE; + CANFD_InitStruct->CANFD_NART = DISABLE; + CANFD_InitStruct->CANFD_TXFP = DISABLE; + + CANFD_InitStruct->CANFD_RES_Error = DISABLE; + CANFD_InitStruct->CANFD_ESI_Auto_TXM0 = DISABLE; + CANFD_InitStruct->CANFD_ESI_Auto_TXM1 = DISABLE; + CANFD_InitStruct->CANFD_ESI_Auto_TXM2 = DISABLE; + CANFD_InitStruct->CANFD_BRS_TXM0 = DISABLE; + CANFD_InitStruct->CANFD_BRS_TXM1 = DISABLE; + CANFD_InitStruct->CANFD_BRS_TXM2 = DISABLE; + + CANFD_InitStruct->CANFD_TDC_FILTER = 0; + CANFD_InitStruct->CANFD_TDC0 = 2; + CANFD_InitStruct->CANFD_TDCE = ENABLE; + + CANFD_InitStruct->CANFD_Mode = CAN_Mode_Normal; + CANFD_InitStruct->CANFD_SJW = CANFD_SJW_8tq; + CANFD_InitStruct->CANFD_BS1 = CANFD_BS1_7tq; + CANFD_InitStruct->CANFD_BS2 = CANFD_BS2_4tq; + CANFD_InitStruct->CANFD_Prescaler = 1; +} + +/********************************************************************* + * @fn CANFD_Transmit + * + * @brief Initiates the transmission of a message for CANFD. + * + * @param CANx - where x can be 1 to select the CAN peripheral. + * TxMessage - pointer to a structure which contains CAN Id, CAN + * DLC and CAN data. + * + * @return transmit_mailbox - The number of the mailbox that is used for + * transmission or CAN_TxStatus_NoMailBox if there is no empty mailbox. + */ +uint8_t CANFD_Transmit(CAN_TypeDef* CANx, CanFDTxMsg* TxMessage) +{ + uint8_t transmit_mailbox = 0; + + CANx->CANFD_CR |= (1); + + if ((CANx->TSTATR&CAN_TSTATR_TME0) == CAN_TSTATR_TME0) + { + transmit_mailbox = 0; + } + else if ((CANx->TSTATR&CAN_TSTATR_TME1) == CAN_TSTATR_TME1) + { + transmit_mailbox = 1; + } + else if ((CANx->TSTATR&CAN_TSTATR_TME2) == CAN_TSTATR_TME2) + { + transmit_mailbox = 2; + } + else + { + transmit_mailbox = CAN_TxStatus_NoMailBox; + } + + if (transmit_mailbox != CAN_TxStatus_NoMailBox) + { + CANx->sTxMailBox[transmit_mailbox].TXMIR &= TMIDxR_TXRQ; + if (TxMessage->IDE == CAN_Id_Standard) + { + CANx->sTxMailBox[transmit_mailbox].TXMIR |= ((TxMessage->StdId << 21) | \ + TxMessage->RTR); + } + else + { + CANx->sTxMailBox[transmit_mailbox].TXMIR |= ((TxMessage->ExtId << 3) | \ + TxMessage->IDE | \ + TxMessage->RTR); + } + + TxMessage->DLC &= (uint8_t)0x0000000F; + CANx->sTxMailBox[transmit_mailbox].TXMDTR &= (uint32_t)0xFFFFFFF0; + CANx->sTxMailBox[transmit_mailbox].TXMDTR |= TxMessage->DLC; + CANx->CANFD_DMA_T[transmit_mailbox] = (uint32_t)TxMessage->Data; + CANx->sTxMailBox[transmit_mailbox].TXMIR |= TMIDxR_TXRQ; + } + + return transmit_mailbox; +} + +/********************************************************************* + * @fn CANFD_Receive + * + * @brief Receives a message. + * + * @param CANx - where x can be 1 to select the CAN peripheral. + * FIFONumber - Receive FIFO number. + * CAN_FIFO0. + * CAN_FIFO1. + * RxMessage - pointer to a structure receive message which contains + * CAN Id, CAN DLC, CAN datas and FMI number. + * + * @return ErrorStatus - NoREADY or READY. + */ +ErrorStatus CANFD_Receive(CAN_TypeDef* CANx, uint8_t FIFONumber, CanFDRxMsg* RxMessage) +{ + ErrorStatus sta = NoREADY; + uint8_t len, i; + uint32_t adr; + + if((CANx->sFIFOMailBox[FIFONumber].RXMIR & 1) == 0) return sta; + + RxMessage->IDE = (uint8_t)0x04 & CANx->sFIFOMailBox[FIFONumber].RXMIR; + + if (RxMessage->IDE == CAN_Id_Standard) + { + RxMessage->StdId = (uint32_t)0x000007FF & (CANx->sFIFOMailBox[FIFONumber].RXMIR >> 21); + } + else + { + RxMessage->ExtId = (uint32_t)0x1FFFFFFF & (CANx->sFIFOMailBox[FIFONumber].RXMIR >> 3); + } + + RxMessage->RTR = (uint8_t)0x02 & CANx->sFIFOMailBox[FIFONumber].RXMIR; + + len = (uint8_t)0x0F & CANx->sFIFOMailBox[FIFONumber].RXMDTR; + + if(len <= 8) + { + RxMessage->DLC = len; + } + else if(len <= 12) + { + RxMessage->DLC = (len - 6) * 4; + } + else if(len <= 15) + { + RxMessage->DLC = (len - 11) * 16; + } + + RxMessage->FMI = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RXMDTR >> 8); + RxMessage->BRS = (uint8_t)0x01 & (CANx->sFIFOMailBox[FIFONumber].RXMDTR >> 4); + RxMessage->ESI = (uint8_t)0x01 & (CANx->sFIFOMailBox[FIFONumber].RXMDTR >> 5); + RxMessage->RES = (uint8_t)0x01 & (CANx->sFIFOMailBox[FIFONumber].RXMDTR >> 6); + + adr = CANx->CANFD_DMA_R[FIFONumber] + 0x20000000; + + for(i=0; iDLC; i++) + { + RxMessage->Data[i] = *((uint8_t*)adr++); + } + + if (FIFONumber == CAN_FIFO0) + { + CANx->RFIFO0 |= CAN_RFIFO0_RFOM0; + } + else + { + CANx->RFIFO1 |= CAN_RFIFO1_RFOM1; + } + + sta = READY; + + return sta; +} + + +/********************************************************************* + * @fn CANFD_GetTransmitDelayOffsetVal + * + * @brief Returns the CANx Transmit Delay Offset Value. + * + * @param CANx - where x can be 1 to select the CAN peripheral. + * + * @return val - CAN Transmit Delay Offset Value. + */ +uint8_t CANFD_GetTransmitDelayOffsetVal(CAN_TypeDef *CANx) +{ + uint8_t val=0; + + val = (uint8_t)((CANx->CANFD_PSR & 0x00FF0000)>> 16); + + return val; +} + +/********************************************************************* + * @fn CANFD_TransmitMailbox_DMAAdr + * + * @brief Set Transmit Mailbox DMA address. + * + * @param CANx - where x can be 1 to select the CAN peripheral. + * MailboxNumber - Transmit Mailbox. + * CAN_Transmit_Mailbox0. + * CAN_Transmit_Mailbox1. + * CAN_Transmit_Mailbox2. + * address - DMA address. + * + * @return none. + */ +void CANFD_TransmitMailbox_DMAAdr(CAN_TypeDef *CANx, uint8_t MailboxNumber, uint32_t Address) +{ + CANx->CANFD_DMA_T[MailboxNumber] = Address; +} + +/********************************************************************* + * @fn CANFD_ReceiveFIFO_DMAAdr + * + * @brief Set receives FIFO DMA address. + * + * @param CANx - where x can be 1 to select the CAN peripheral. + * FIFONumber - Receive FIFO number. + * CAN_FIFO0. + * CAN_FIFO1. + * address - DMA address. + * + * @return none. + */ +void CANFD_ReceiveFIFO_DMAAdr(CAN_TypeDef *CANx, uint8_t FIFONumber, uint32_t Address) +{ + CANx->CANFD_DMA_R[FIFONumber] = Address; +} diff --git a/ZDBMS/BMS_MC/Peripheral/src/ch32l103_crc.c b/ZDBMS/BMS_MC/Peripheral/src/ch32l103_crc.c new file mode 100644 index 0000000..d2eebe6 --- /dev/null +++ b/ZDBMS/BMS_MC/Peripheral/src/ch32l103_crc.c @@ -0,0 +1,99 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32l103_crc.c + * Author : WCH + * Version : V1.0.0 + * Date : 2023/07/08 + * Description : This file provides all the CRC firmware functions. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#include "ch32l103_crc.h" + +/********************************************************************* + * @fn CRC_ResetDR + * + * @brief Resets the CRC Data register (DR). + * + * @return none + */ +void CRC_ResetDR(void) +{ + CRC->CTLR = CRC_CTLR_RESET; +} + +/********************************************************************* + * @fn CRC_CalcCRC + * + * @brief Computes the 32-bit CRC of a given data word(32-bit). + * + * @param Data - data word(32-bit) to compute its CRC. + * + * @return 32-bit CRC. + */ +uint32_t CRC_CalcCRC(uint32_t Data) +{ + CRC->DATAR = Data; + + return (CRC->DATAR); +} + +/********************************************************************* + * @fn CRC_CalcBlockCRC + * + * @brief Computes the 32-bit CRC of a given buffer of data word(32-bit). + * + * @param pBuffer - pointer to the buffer containing the data to be computed. + * BufferLength - length of the buffer to be computed. + * + * @return 32-bit CRC. + */ +uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength) +{ + uint32_t index = 0; + + for(index = 0; index < BufferLength; index++){ + CRC->DATAR = pBuffer[index]; + } + + return (CRC->DATAR); +} + +/********************************************************************* + * @fn CRC_GetCRC + * + * @brief Returns the current CRC value. + * + * @return 32-bit CRC. + */ +uint32_t CRC_GetCRC(void) +{ + return (CRC->DATAR); +} + +/********************************************************************* + * @fn CRC_SetIDRegister + * + * @brief Stores a 8-bit data in the Independent Data(ID) register. + * + * @param IDValue - 8-bit value to be stored in the ID register. + * + * @return none + */ +void CRC_SetIDRegister(uint8_t IDValue) +{ + CRC->IDATAR = IDValue; +} + +/********************************************************************* + * @fn CRC_GetIDRegister + * + * @brief Returns the 8-bit data stored in the Independent Data(ID) register. + * + * @return 8-bit value of the ID register. + */ +uint8_t CRC_GetIDRegister(void) +{ + return (CRC->IDATAR); +} diff --git a/ZDBMS/BMS_MC/Peripheral/src/ch32l103_dbgmcu.c b/ZDBMS/BMS_MC/Peripheral/src/ch32l103_dbgmcu.c new file mode 100644 index 0000000..44ec56c --- /dev/null +++ b/ZDBMS/BMS_MC/Peripheral/src/ch32l103_dbgmcu.c @@ -0,0 +1,126 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32l103_dbgmcu.c + * Author : WCH + * Version : V1.0.0 + * Date : 2024/05/06 + * Description : This file provides all the DBGMCU firmware functions. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#include "ch32l103_dbgmcu.h" + +#define IDCODE_DEVID_MASK ((uint32_t)0x0000FFFF) + + +/********************************************************************* + * @fn DBGMCU_GetREVID + * + * @brief Returns the device revision identifier. + * + * @return Revision identifier. + */ +uint32_t DBGMCU_GetREVID(void) +{ + return (CHIPID >> 16); +} + +/********************************************************************* + * @fn DBGMCU_GetDEVID + * + * @brief Returns the device identifier. + * + * @return Device identifier. + */ +uint32_t DBGMCU_GetDEVID(void) +{ + return (CHIPID & IDCODE_DEVID_MASK); +} + +/********************************************************************* + * @fn __get_DEBUG_CR + * + * @brief Return the DEBUGE Control Register + * + * @return DEBUGE Control value + */ +uint32_t __get_DEBUG_CR(void) +{ + uint32_t result; + + __asm volatile("csrr %0,""0x7C0" : "=r"(result)); + return (result); +} + +/********************************************************************* + * @fn __set_DEBUG_CR + * + * @brief Set the DEBUGE Control Register + * + * @param value - set DEBUGE Control value + * + * @return none + */ +void __set_DEBUG_CR(uint32_t value) +{ + __asm volatile("csrw 0x7C0, %0" : : "r"(value)); +} + + +/********************************************************************* + * @fn DBGMCU_Config + * + * @brief Configures the specified peripheral and low power mode behavior + * when the MCU under Debug mode. + * + * @param DBGMCU_Periph - specifies the peripheral and low power mode. + * DBGMCU_SLEEP - Debug sleep stopped when Core is halted + * DBGMCU_STOP - Debug stop stopped when Core is halted + * DBGMCU_STANDBY - Debug standby stopped when Core is halted + * DBGMCU_IWDG_STOP - Debug IWDG stopped when Core is halted + * DBGMCU_WWDG_STOP - Debug WWDG stopped when Core is halted + * DBGMCU_I2C1_SMBUS_TIMEOUT - Debug I2C1 SMBUS time out when Core is halted + * DBGMCU_I2C2_SMBUS_TIMEOUT - Debug I2C2 SMBUS time out when Core is halted + * DBGMCU_TIM1_STOP - TIM1 counter stopped when Core is halted + * DBGMCU_TIM2_STOP - TIM2 counter stopped when Core is halted + * DBGMCU_TIM3_STOP - TIM3 counter stopped when Core is halted + * DBGMCU_TIM4_STOP - TIM4 counter stopped when Core is halted + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState) +{ + uint32_t val; + + if(NewState != DISABLE) + { + __set_DEBUG_CR(DBGMCU_Periph); + } + else + { + val = __get_DEBUG_CR(); + val &= ~(uint32_t)DBGMCU_Periph; + __set_DEBUG_CR(val); + } +} + +/********************************************************************* + * @fn DBGMCU_GetCHIPID + * + * @brief Returns the CHIP identifier. + * + * @return Device identifier. + * ChipID List- + * CH32L103C8T6-0x103107x0 + * CH32L103F8P6-0x103A07x0 + * CH32L103G8R6-0x103B07x0 + * CH32L103K8U6-0x103207x0 + * CH32L103F8U6-0x103D07x0 + * + */ +uint32_t DBGMCU_GetCHIPID( void ) +{ + return( CHIPID ); +} diff --git a/ZDBMS/BMS_MC/Peripheral/src/ch32l103_dma.c b/ZDBMS/BMS_MC/Peripheral/src/ch32l103_dma.c new file mode 100644 index 0000000..53feb25 --- /dev/null +++ b/ZDBMS/BMS_MC/Peripheral/src/ch32l103_dma.c @@ -0,0 +1,432 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32l103_dma.c + * Author : WCH + * Version : V1.0.0 + * Date : 2023/07/08 + * Description : This file provides all the DMA firmware functions. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#include "ch32l103_dma.h" +#include "ch32l103_rcc.h" + +/* DMA1 Channelx interrupt pending bit masks */ +#define DMA1_Channel1_IT_Mask ((uint32_t)(DMA_GIF1 | DMA_TCIF1 | DMA_HTIF1 | DMA_TEIF1)) +#define DMA1_Channel2_IT_Mask ((uint32_t)(DMA_GIF2 | DMA_TCIF2 | DMA_HTIF2 | DMA_TEIF2)) +#define DMA1_Channel3_IT_Mask ((uint32_t)(DMA_GIF3 | DMA_TCIF3 | DMA_HTIF3 | DMA_TEIF3)) +#define DMA1_Channel4_IT_Mask ((uint32_t)(DMA_GIF4 | DMA_TCIF4 | DMA_HTIF4 | DMA_TEIF4)) +#define DMA1_Channel5_IT_Mask ((uint32_t)(DMA_GIF5 | DMA_TCIF5 | DMA_HTIF5 | DMA_TEIF5)) +#define DMA1_Channel6_IT_Mask ((uint32_t)(DMA_GIF6 | DMA_TCIF6 | DMA_HTIF6 | DMA_TEIF6)) +#define DMA1_Channel7_IT_Mask ((uint32_t)(DMA_GIF7 | DMA_TCIF7 | DMA_HTIF7 | DMA_TEIF7)) +#define DMA1_Channel8_IT_Mask ((uint32_t)(DMA_GIF8 | DMA_TCIF8 | DMA_HTIF8 | DMA_TEIF8)) + +/* DMA registers Masks */ +#define CFGR_CLEAR_Mask ((uint32_t)0xFFFF800F) + +/********************************************************************* + * @fn DMA_DeInit + * + * @brief Deinitializes the DMAy Channelx registers to their default + * reset values. + * + * @param DMAy_Channelx - here y can be 1 to select the DMA and x can be + * 1 to 8 for DMA1 to select the DMA Channel. + * + * @return none + */ +void DMA_DeInit(DMA_Channel_TypeDef *DMAy_Channelx) +{ + DMAy_Channelx->CFGR &= (uint16_t)(~DMA_CFGR1_EN); + DMAy_Channelx->CFGR = 0; + DMAy_Channelx->CNTR = 0; + DMAy_Channelx->PADDR = 0; + DMAy_Channelx->MADDR = 0; + if(DMAy_Channelx == DMA1_Channel1) + { + DMA1->INTFCR |= DMA1_Channel1_IT_Mask; + } + else if(DMAy_Channelx == DMA1_Channel2) + { + DMA1->INTFCR |= DMA1_Channel2_IT_Mask; + } + else if(DMAy_Channelx == DMA1_Channel3) + { + DMA1->INTFCR |= DMA1_Channel3_IT_Mask; + } + else if(DMAy_Channelx == DMA1_Channel4) + { + DMA1->INTFCR |= DMA1_Channel4_IT_Mask; + } + else if(DMAy_Channelx == DMA1_Channel5) + { + DMA1->INTFCR |= DMA1_Channel5_IT_Mask; + } + else if(DMAy_Channelx == DMA1_Channel6) + { + DMA1->INTFCR |= DMA1_Channel6_IT_Mask; + } + else if(DMAy_Channelx == DMA1_Channel7) + { + DMA1->INTFCR |= DMA1_Channel7_IT_Mask; + } + else if(DMAy_Channelx == DMA1_Channel8) + { + DMA1->INTFCR |= DMA1_Channel8_IT_Mask; + } +} + +/********************************************************************* + * @fn DMA_Init + * + * @brief Initializes the DMAy Channelx according to the specified + * parameters in the DMA_InitStruct. + * + * @param DMAy_Channelx - here y can be 1 to select the DMA and x can be + * 1 to 8 for DMA1 to select the DMA Channel. + * DMA_InitStruct - pointer to a DMA_InitTypeDef structure that contains + * contains the configuration information for the specified DMA Channel. + * + * @return none + */ +void DMA_Init(DMA_Channel_TypeDef *DMAy_Channelx, DMA_InitTypeDef *DMA_InitStruct) +{ + uint32_t tmpreg = 0; + + tmpreg = DMAy_Channelx->CFGR; + tmpreg &= CFGR_CLEAR_Mask; + tmpreg |= DMA_InitStruct->DMA_DIR | DMA_InitStruct->DMA_Mode | + DMA_InitStruct->DMA_PeripheralInc | DMA_InitStruct->DMA_MemoryInc | + DMA_InitStruct->DMA_PeripheralDataSize | DMA_InitStruct->DMA_MemoryDataSize | + DMA_InitStruct->DMA_Priority | DMA_InitStruct->DMA_M2M; + + DMAy_Channelx->CFGR = tmpreg; + DMAy_Channelx->CNTR = DMA_InitStruct->DMA_BufferSize; + DMAy_Channelx->PADDR = DMA_InitStruct->DMA_PeripheralBaseAddr; + DMAy_Channelx->MADDR = DMA_InitStruct->DMA_MemoryBaseAddr; +} + +/********************************************************************* + * @fn DMA_StructInit + * + * @brief Fills each DMA_InitStruct member with its default value. + * + * @param DMAy_Channelx - here y can be 1 to select the DMA and x can be + * 1 to 8 for DMA1 to select the DMA Channel. + * DMA_InitStruct - pointer to a DMA_InitTypeDef structure that contains + * contains the configuration information for the specified DMA Channel. + * + * @return none + */ +void DMA_StructInit(DMA_InitTypeDef *DMA_InitStruct) +{ + DMA_InitStruct->DMA_PeripheralBaseAddr = 0; + DMA_InitStruct->DMA_MemoryBaseAddr = 0; + DMA_InitStruct->DMA_DIR = DMA_DIR_PeripheralSRC; + DMA_InitStruct->DMA_BufferSize = 0; + DMA_InitStruct->DMA_PeripheralInc = DMA_PeripheralInc_Disable; + DMA_InitStruct->DMA_MemoryInc = DMA_MemoryInc_Disable; + DMA_InitStruct->DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte; + DMA_InitStruct->DMA_MemoryDataSize = DMA_MemoryDataSize_Byte; + DMA_InitStruct->DMA_Mode = DMA_Mode_Normal; + DMA_InitStruct->DMA_Priority = DMA_Priority_Low; + DMA_InitStruct->DMA_M2M = DMA_M2M_Disable; +} + +/********************************************************************* + * @fn DMA_Cmd + * + * @brief Enables or disables the specified DMAy Channelx. + * + * @param DMAy_Channelx - here y can be 1 to select the DMA and x can be + * 1 to 8 for DMA1 to select the DMA Channel. + * NewState - new state of the DMAy Channelx(ENABLE or DISABLE). + * + * @return none + */ +void DMA_Cmd(DMA_Channel_TypeDef *DMAy_Channelx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + DMAy_Channelx->CFGR |= DMA_CFGR1_EN; + } + else + { + DMAy_Channelx->CFGR &= (uint16_t)(~DMA_CFGR1_EN); + } +} + +/********************************************************************* + * @fn DMA_ITConfig + * + * @brief Enables or disables the specified DMAy Channelx interrupts. + * + * @param DMAy_Channelx - here y can be 1 to select the DMA and x can be + * 1 to 8 for DMA1 to select the DMA Channel. + * DMA_IT - specifies the DMA interrupts sources to be enabled + * or disabled. + * DMA_IT_TC - Transfer complete interrupt mask + * DMA_IT_HT - Half transfer interrupt mask + * DMA_IT_TE - Transfer error interrupt mask + * NewState - new state of the DMAy Channelx(ENABLE or DISABLE). + * + * @return none + */ +void DMA_ITConfig(DMA_Channel_TypeDef *DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + DMAy_Channelx->CFGR |= DMA_IT; + } + else + { + DMAy_Channelx->CFGR &= ~DMA_IT; + } +} + +/********************************************************************* + * @fn DMA_SetCurrDataCounter + * + * @brief Sets the number of data units in the current DMAy Channelx transfer. + * + * @param DMAy_Channelx - here y can be 1 to select the DMA and x can be + * 1 to 8 for DMA1 to select the DMA Channel. + * DataNumber - The number of data units in the current DMAy Channelx + * transfer. + * + * @return none + */ +void DMA_SetCurrDataCounter(DMA_Channel_TypeDef *DMAy_Channelx, uint16_t DataNumber) +{ + DMAy_Channelx->CNTR = DataNumber; +} + +/********************************************************************* + * @fn DMA_GetCurrDataCounter + * + * @brief Returns the number of remaining data units in the current + * DMAy Channelx transfer. + * + * @param DMAy_Channelx - here y can be 1 to select the DMA and x can be + * 1 to 8 for DMA1 to select the DMA Channel. + * + * @return DataNumber - The number of remaining data units in the current + * DMAy Channelx transfer. + */ +uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef *DMAy_Channelx) +{ + return ((uint16_t)(DMAy_Channelx->CNTR)); +} + +/********************************************************************* + * @fn DMA_GetFlagStatus + * + * @brief Checks whether the specified DMAy Channelx flag is set or not. + * + * @param DMAy_FLAG - specifies the flag to check. + * DMA1_FLAG_GL1 - DMA1 Channel1 global flag. + * DMA1_FLAG_TC1 - DMA1 Channel1 transfer complete flag. + * DMA1_FLAG_HT1 - DMA1 Channel1 half transfer flag. + * DMA1_FLAG_TE1 - DMA1 Channel1 transfer error flag. + * DMA1_FLAG_GL2 - DMA1 Channel2 global flag. + * DMA1_FLAG_TC2 - DMA1 Channel2 transfer complete flag. + * DMA1_FLAG_HT2 - DMA1 Channel2 half transfer flag. + * DMA1_FLAG_TE2 - DMA1 Channel2 transfer error flag. + * DMA1_FLAG_GL3 - DMA1 Channel3 global flag. + * DMA1_FLAG_TC3 - DMA1 Channel3 transfer complete flag. + * DMA1_FLAG_HT3 - DMA1 Channel3 half transfer flag. + * DMA1_FLAG_TE3 - DMA1 Channel3 transfer error flag. + * DMA1_FLAG_GL4 - DMA1 Channel4 global flag. + * DMA1_FLAG_TC4 - DMA1 Channel4 transfer complete flag. + * DMA1_FLAG_HT4 - DMA1 Channel4 half transfer flag. + * DMA1_FLAG_TE4 - DMA1 Channel4 transfer error flag. + * DMA1_FLAG_GL5 - DMA1 Channel5 global flag. + * DMA1_FLAG_TC5 - DMA1 Channel5 transfer complete flag. + * DMA1_FLAG_HT5 - DMA1 Channel5 half transfer flag. + * DMA1_FLAG_TE5 - DMA1 Channel5 transfer error flag. + * DMA1_FLAG_GL6 - DMA1 Channel6 global flag. + * DMA1_FLAG_TC6 - DMA1 Channel6 transfer complete flag. + * DMA1_FLAG_HT6 - DMA1 Channel6 half transfer flag. + * DMA1_FLAG_TE6 - DMA1 Channel6 transfer error flag. + * DMA1_FLAG_GL7 - DMA1 Channel7 global flag. + * DMA1_FLAG_TC7 - DMA1 Channel7 transfer complete flag. + * DMA1_FLAG_HT7 - DMA1 Channel7 half transfer flag. + * DMA1_FLAG_TE7 - DMA1 Channel7 transfer error flag. + * DMA1_FLAG_GL8 - DMA1 Channel8 global flag. + * DMA1_FLAG_TC8 - DMA1 Channel8 transfer complete flag. + * DMA1_FLAG_HT8 - DMA1 Channel8 half transfer flag. + * DMA1_FLAG_TE8 - DMA1 Channel8 transfer error flag. + * + * @return The new state of DMAy_FLAG (SET or RESET). + */ +FlagStatus DMA_GetFlagStatus(uint32_t DMAy_FLAG) +{ + FlagStatus bitstatus = RESET; + uint32_t tmpreg = 0; + + tmpreg = DMA1->INTFR; + + if((tmpreg & DMAy_FLAG) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn DMA_ClearFlag + * + * @brief Clears the DMAy Channelx's pending flags. + * + * @param DMAy_FLAG - specifies the flag to check. + * DMA1_FLAG_GL1 - DMA1 Channel1 global flag. + * DMA1_FLAG_TC1 - DMA1 Channel1 transfer complete flag. + * DMA1_FLAG_HT1 - DMA1 Channel1 half transfer flag. + * DMA1_FLAG_TE1 - DMA1 Channel1 transfer error flag. + * DMA1_FLAG_GL2 - DMA1 Channel2 global flag. + * DMA1_FLAG_TC2 - DMA1 Channel2 transfer complete flag. + * DMA1_FLAG_HT2 - DMA1 Channel2 half transfer flag. + * DMA1_FLAG_TE2 - DMA1 Channel2 transfer error flag. + * DMA1_FLAG_GL3 - DMA1 Channel3 global flag. + * DMA1_FLAG_TC3 - DMA1 Channel3 transfer complete flag. + * DMA1_FLAG_HT3 - DMA1 Channel3 half transfer flag. + * DMA1_FLAG_TE3 - DMA1 Channel3 transfer error flag. + * DMA1_FLAG_GL4 - DMA1 Channel4 global flag. + * DMA1_FLAG_TC4 - DMA1 Channel4 transfer complete flag. + * DMA1_FLAG_HT4 - DMA1 Channel4 half transfer flag. + * DMA1_FLAG_TE4 - DMA1 Channel4 transfer error flag. + * DMA1_FLAG_GL5 - DMA1 Channel5 global flag. + * DMA1_FLAG_TC5 - DMA1 Channel5 transfer complete flag. + * DMA1_FLAG_HT5 - DMA1 Channel5 half transfer flag. + * DMA1_FLAG_TE5 - DMA1 Channel5 transfer error flag. + * DMA1_FLAG_GL6 - DMA1 Channel6 global flag. + * DMA1_FLAG_TC6 - DMA1 Channel6 transfer complete flag. + * DMA1_FLAG_HT6 - DMA1 Channel6 half transfer flag. + * DMA1_FLAG_TE6 - DMA1 Channel6 transfer error flag. + * DMA1_FLAG_GL7 - DMA1 Channel7 global flag. + * DMA1_FLAG_TC7 - DMA1 Channel7 transfer complete flag. + * DMA1_FLAG_HT7 - DMA1 Channel7 half transfer flag. + * DMA1_FLAG_TE7 - DMA1 Channel7 transfer error flag. + * DMA1_FLAG_GL8 - DMA1 Channel8 global flag. + * DMA1_FLAG_TC8 - DMA1 Channel8 transfer complete flag. + * DMA1_FLAG_HT8 - DMA1 Channel8 half transfer flag. + * DMA1_FLAG_TE8 - DMA1 Channel8 transfer error flag. + * + * @return none + */ +void DMA_ClearFlag(uint32_t DMAy_FLAG) +{ + DMA1->INTFCR = DMAy_FLAG; +} + +/********************************************************************* + * @fn DMA_GetITStatus + * + * @brief Checks whether the specified DMAy Channelx interrupt has + * occurred or not. + * + * @param DMAy_IT - specifies the DMAy interrupt source to check. + * DMA1_IT_GL1 - DMA1 Channel1 global flag. + * DMA1_IT_TC1 - DMA1 Channel1 transfer complete flag. + * DMA1_IT_HT1 - DMA1 Channel1 half transfer flag. + * DMA1_IT_TE1 - DMA1 Channel1 transfer error flag. + * DMA1_IT_GL2 - DMA1 Channel2 global flag. + * DMA1_IT_TC2 - DMA1 Channel2 transfer complete flag. + * DMA1_IT_HT2 - DMA1 Channel2 half transfer flag. + * DMA1_IT_TE2 - DMA1 Channel2 transfer error flag. + * DMA1_IT_GL3 - DMA1 Channel3 global flag. + * DMA1_IT_TC3 - DMA1 Channel3 transfer complete flag. + * DMA1_IT_HT3 - DMA1 Channel3 half transfer flag. + * DMA1_IT_TE3 - DMA1 Channel3 transfer error flag. + * DMA1_IT_GL4 - DMA1 Channel4 global flag. + * DMA1_IT_TC4 - DMA1 Channel4 transfer complete flag. + * DMA1_IT_HT4 - DMA1 Channel4 half transfer flag. + * DMA1_IT_TE4 - DMA1 Channel4 transfer error flag. + * DMA1_IT_GL5 - DMA1 Channel5 global flag. + * DMA1_IT_TC5 - DMA1 Channel5 transfer complete flag. + * DMA1_IT_HT5 - DMA1 Channel5 half transfer flag. + * DMA1_IT_TE5 - DMA1 Channel5 transfer error flag. + * DMA1_IT_GL6 - DMA1 Channel6 global flag. + * DMA1_IT_TC6 - DMA1 Channel6 transfer complete flag. + * DMA1_IT_HT6 - DMA1 Channel6 half transfer flag. + * DMA1_IT_TE6 - DMA1 Channel6 transfer error flag. + * DMA1_IT_GL7 - DMA1 Channel7 global flag. + * DMA1_IT_TC7 - DMA1 Channel7 transfer complete flag. + * DMA1_IT_HT7 - DMA1 Channel7 half transfer flag. + * DMA1_IT_TE7 - DMA1 Channel7 transfer error flag. + * DMA1_IT_GL8 - DMA1 Channel8 global flag. + * DMA1_IT_TC8 - DMA1 Channel8 transfer complete flag. + * DMA1_IT_HT8 - DMA1 Channel8 half transfer flag. + * DMA1_IT_TE8 - DMA1 Channel8 transfer error flag. + * + * @return The new state of DMAy_IT (SET or RESET). + */ +ITStatus DMA_GetITStatus(uint32_t DMAy_IT) +{ + ITStatus bitstatus = RESET; + uint32_t tmpreg = 0; + + tmpreg = DMA1->INTFR; + + if((tmpreg & DMAy_IT) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/********************************************************************* + * @fn DMA_ClearITPendingBit + * + * @brief Clears the DMAy Channelx's interrupt pending bits. + * + * @param DMAy_IT - specifies the DMAy interrupt source to check. + * DMA1_IT_GL1 - DMA1 Channel1 global flag. + * DMA1_IT_TC1 - DMA1 Channel1 transfer complete flag. + * DMA1_IT_HT1 - DMA1 Channel1 half transfer flag. + * DMA1_IT_TE1 - DMA1 Channel1 transfer error flag. + * DMA1_IT_GL2 - DMA1 Channel2 global flag. + * DMA1_IT_TC2 - DMA1 Channel2 transfer complete flag. + * DMA1_IT_HT2 - DMA1 Channel2 half transfer flag. + * DMA1_IT_TE2 - DMA1 Channel2 transfer error flag. + * DMA1_IT_GL3 - DMA1 Channel3 global flag. + * DMA1_IT_TC3 - DMA1 Channel3 transfer complete flag. + * DMA1_IT_HT3 - DMA1 Channel3 half transfer flag. + * DMA1_IT_TE3 - DMA1 Channel3 transfer error flag. + * DMA1_IT_GL4 - DMA1 Channel4 global flag. + * DMA1_IT_TC4 - DMA1 Channel4 transfer complete flag. + * DMA1_IT_HT4 - DMA1 Channel4 half transfer flag. + * DMA1_IT_TE4 - DMA1 Channel4 transfer error flag. + * DMA1_IT_GL5 - DMA1 Channel5 global flag. + * DMA1_IT_TC5 - DMA1 Channel5 transfer complete flag. + * DMA1_IT_HT5 - DMA1 Channel5 half transfer flag. + * DMA1_IT_TE5 - DMA1 Channel5 transfer error flag. + * DMA1_IT_GL6 - DMA1 Channel6 global flag. + * DMA1_IT_TC6 - DMA1 Channel6 transfer complete flag. + * DMA1_IT_HT6 - DMA1 Channel6 half transfer flag. + * DMA1_IT_TE6 - DMA1 Channel6 transfer error flag. + * DMA1_IT_GL7 - DMA1 Channel7 global flag. + * DMA1_IT_TC7 - DMA1 Channel7 transfer complete flag. + * DMA1_IT_HT7 - DMA1 Channel7 half transfer flag. + * DMA1_IT_TE7 - DMA1 Channel7 transfer error flag. + * DMA1_IT_GL8 - DMA1 Channel8 global flag. + * DMA1_IT_TC8 - DMA1 Channel8 transfer complete flag. + * DMA1_IT_HT8 - DMA1 Channel8 half transfer flag. + * DMA1_IT_TE8 - DMA1 Channel8 transfer error flag. + * + * @return none + */ +void DMA_ClearITPendingBit(uint32_t DMAy_IT) +{ + DMA1->INTFCR = DMAy_IT; +} diff --git a/ZDBMS/BMS_MC/Peripheral/src/ch32l103_exti.c b/ZDBMS/BMS_MC/Peripheral/src/ch32l103_exti.c new file mode 100644 index 0000000..5cdc822 --- /dev/null +++ b/ZDBMS/BMS_MC/Peripheral/src/ch32l103_exti.c @@ -0,0 +1,182 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32l103_exti.c + * Author : WCH + * Version : V1.0.0 + * Date : 2023/07/08 + * Description : This file provides all the EXTI firmware functions. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#include "ch32l103_exti.h" + +/* No interrupt selected */ +#define EXTI_LINENONE ((uint32_t)0x000000) + +/********************************************************************* + * @fn EXTI_DeInit + * + * @brief Deinitializes the EXTI peripheral registers to their default + * reset values. + * + * @return none. + */ +void EXTI_DeInit(void) +{ + EXTI->INTENR = 0x00000000; + EXTI->EVENR = 0x00000000; + EXTI->RTENR = 0x00000000; + EXTI->FTENR = 0x00000000; + EXTI->INTFR = 0x007FFFFF; +} + +/********************************************************************* + * @fn EXTI_Init + * + * @brief Initializes the EXTI peripheral according to the specified + * parameters in the EXTI_InitStruct. + * + * @param EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure + * + * @return none. + */ +void EXTI_Init(EXTI_InitTypeDef *EXTI_InitStruct) +{ + uint32_t tmp = 0; + + tmp = (uint32_t)EXTI_BASE; + if(EXTI_InitStruct->EXTI_LineCmd != DISABLE) + { + EXTI->INTENR &= ~EXTI_InitStruct->EXTI_Line; + EXTI->EVENR &= ~EXTI_InitStruct->EXTI_Line; + tmp += EXTI_InitStruct->EXTI_Mode; + *(__IO uint32_t *)tmp |= EXTI_InitStruct->EXTI_Line; + EXTI->RTENR &= ~EXTI_InitStruct->EXTI_Line; + EXTI->FTENR &= ~EXTI_InitStruct->EXTI_Line; + if(EXTI_InitStruct->EXTI_Trigger == EXTI_Trigger_Rising_Falling) + { + EXTI->RTENR |= EXTI_InitStruct->EXTI_Line; + EXTI->FTENR |= EXTI_InitStruct->EXTI_Line; + } + else + { + tmp = (uint32_t)EXTI_BASE; + tmp += EXTI_InitStruct->EXTI_Trigger; + *(__IO uint32_t *)tmp |= EXTI_InitStruct->EXTI_Line; + } + } + else + { + tmp += EXTI_InitStruct->EXTI_Mode; + *(__IO uint32_t *)tmp &= ~EXTI_InitStruct->EXTI_Line; + } +} + +/********************************************************************* + * @fn EXTI_StructInit + * + * @brief Fills each EXTI_InitStruct member with its reset value. + * + * @param EXTI_InitStruct - pointer to a EXTI_InitTypeDef structure + * + * @return none. + */ +void EXTI_StructInit(EXTI_InitTypeDef *EXTI_InitStruct) +{ + EXTI_InitStruct->EXTI_Line = EXTI_LINENONE; + EXTI_InitStruct->EXTI_Mode = EXTI_Mode_Interrupt; + EXTI_InitStruct->EXTI_Trigger = EXTI_Trigger_Falling; + EXTI_InitStruct->EXTI_LineCmd = DISABLE; +} + +/********************************************************************* + * @fn EXTI_GenerateSWInterrupt + * + * @brief Generates a Software interrupt. + * + * @param EXTI_Line - specifies the EXTI lines to be enabled or disabled. + * + * @return none. + */ +void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line) +{ + EXTI->SWIEVR |= EXTI_Line; +} + +/********************************************************************* + * @fn EXTI_GetFlagStatus + * + * @brief Checks whether the specified EXTI line flag is set or not. + * + * @param EXTI_Line - specifies the EXTI lines to be enabled or disabled. + * + * @return The new state of EXTI_Line (SET or RESET). + */ +FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line) +{ + FlagStatus bitstatus = RESET; + if((EXTI->INTFR & EXTI_Line) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/********************************************************************* + * @fn EXTI_ClearFlag + * + * @brief Clears the EXTI's line pending flags. + * + * @param EXTI_Line - specifies the EXTI lines to be enabled or disabled. + * + * @return None + */ +void EXTI_ClearFlag(uint32_t EXTI_Line) +{ + EXTI->INTFR = EXTI_Line; +} + +/********************************************************************* + * @fn EXTI_GetITStatus + * + * @brief Checks whether the specified EXTI line is asserted or not. + * + * @param EXTI_Line - specifies the EXTI lines to be enabled or disabled. + * + * @return The new state of EXTI_Line (SET or RESET). + */ +ITStatus EXTI_GetITStatus(uint32_t EXTI_Line) +{ + ITStatus bitstatus = RESET; + uint32_t enablestatus = 0; + + enablestatus = EXTI->INTENR & EXTI_Line; + if(((EXTI->INTFR & EXTI_Line) != (uint32_t)RESET) && (enablestatus != (uint32_t)RESET)) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/********************************************************************* + * @fn EXTI_ClearITPendingBit + * + * @brief Clears the EXTI's line pending bits. + * + * @param EXTI_Line - specifies the EXTI lines to be enabled or disabled. + * + * @return none + */ +void EXTI_ClearITPendingBit(uint32_t EXTI_Line) +{ + EXTI->INTFR = EXTI_Line; +} diff --git a/ZDBMS/BMS_MC/Peripheral/src/ch32l103_flash.c b/ZDBMS/BMS_MC/Peripheral/src/ch32l103_flash.c new file mode 100644 index 0000000..7da1107 --- /dev/null +++ b/ZDBMS/BMS_MC/Peripheral/src/ch32l103_flash.c @@ -0,0 +1,1009 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32l103_flash.c + * Author : WCH + * Version : V1.0.1 + * Date : 2024/12/11 + * Description : This file provides all the FLASH firmware functions. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#include "ch32l103_flash.h" + +/* Flash Access Control Register bits */ +#define ACR_LATENCY_Mask ((uint32_t)0xFFFFFFFC) + +/* Flash Control Register bits */ +#define CR_PER_Set ((uint32_t)0x00000002) +#define CR_PER_Reset ((uint32_t)0xFFFFFFFD) +#define CR_MER_Set ((uint32_t)0x00000004) +#define CR_MER_Reset ((uint32_t)0xFFFFFFFB) +#define CR_OPTER_Set ((uint32_t)0x00000020) +#define CR_OPTER_Reset ((uint32_t)0xFFFFFFDF) +#define CR_STRT_Set ((uint32_t)0x00000040) +#define CR_LOCK_Set ((uint32_t)0x00000080) +#define CR_FLOCK_Set ((uint32_t)0x00008000) +#define CR_PAGE_PG ((uint32_t)0x00010000) +#define CR_PAGE_ER ((uint32_t)0x00020000) +#define CR_PAGE_ER_Reset ((uint32_t)0xFFFDFFFF) +#define CR_BUF_LOAD ((uint32_t)0x00040000) +#define CR_BUF_RST ((uint32_t)0x00080000) +#define CR_BER32 ((uint32_t)0x00800000) + +/* FLASH Status Register bits */ +#define SR_BSY ((uint32_t)0x00000001) +#define SR_WRPRTERR ((uint32_t)0x00000010) +#define SR_EOP ((uint32_t)0x00000020) + +/* FLASH Mask */ +#define RDPRT_Mask ((uint32_t)0x00000002) +#define WRP0_Mask ((uint32_t)0x000000FF) +#define WRP1_Mask ((uint32_t)0x0000FF00) +#define WRP2_Mask ((uint32_t)0x00FF0000) +#define WRP3_Mask ((uint32_t)0xFF000000) + +/* FLASH Keys */ +#define RDP_Key ((uint16_t)0x00A5) +#define FLASH_KEY1 ((uint32_t)0x45670123) +#define FLASH_KEY2 ((uint32_t)0xCDEF89AB) + +/* Delay definition */ +#define EraseTimeout ((uint32_t)0x000B0000) +#define ProgramTimeout ((uint32_t)0x00005000) + +/* Flash Program Valid Address */ +#define ValidAddrStart (FLASH_BASE) +#define ValidAddrEnd (FLASH_BASE + 0x10000) + +/* FLASH Size */ +#define Size_256B 0x100 +#define Size_1KB 0x400 +#define Size_32KB 0x8000 + +/******************************************************************************** + * @fn FLASH_SetLatency + * + * @brief Sets the code latency value. + * + * @param FLASH_Latency - specifies the FLASH Latency mode. + * FLASH_Latency_0 - FLASH Latency mode 0 + * FLASH_Latency_1 - FLASH Latency mode 1 + * FLASH_Latency_2 - FLASH Latency mode 2 + * + * @return None + */ +void FLASH_SetLatency(uint32_t FLASH_Latency) +{ + uint32_t tmpreg = 0; + + tmpreg = FLASH->ACTLR; + tmpreg &= ACR_LATENCY_Mask; + tmpreg |= FLASH_Latency; + FLASH->ACTLR = tmpreg; +} + +/******************************************************************************** + * @fn FLASH_Unlock + * + * @brief Unlocks the FLASH Program Erase Controller. + * + * @return None + */ +void FLASH_Unlock(void) +{ + /* Authorize the FPEC of Bank1 Access */ + FLASH->KEYR = FLASH_KEY1; + FLASH->KEYR = FLASH_KEY2; +} + +/******************************************************************************** + * @fn FLASH_Lock + * + * @brief Locks the FLASH Program Erase Controller. + * + * @return None + */ +void FLASH_Lock(void) +{ + FLASH->CTLR |= CR_LOCK_Set; +} + +/******************************************************************************** + * @fn FLASH_ErasePage + * + * @brief Erases a specified FLASH page(1KB). + * + * @param Page_Address - The page address to be erased. + * + * @return FLASH Status - FLASH_BUSY, FLASH_ERROR_PG, + * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. + */ +FLASH_Status FLASH_ErasePage(uint32_t Page_Address) +{ + FLASH_Status status = FLASH_COMPLETE; + + status = FLASH_WaitForLastOperation(EraseTimeout); + + if(status == FLASH_COMPLETE) + { + FLASH->CTLR &= (CR_OPTER_Reset & CR_PAGE_ER_Reset); + FLASH->CTLR |= CR_PER_Set; + FLASH->ADDR = Page_Address; + FLASH->CTLR |= CR_STRT_Set; + + status = FLASH_WaitForLastOperation(EraseTimeout); + + FLASH->CTLR &= CR_PER_Reset; + } + + return status; +} + +/******************************************************************************** + * @fn FLASH_EraseAllPages + * + * @brief Erases all FLASH pages. + * + * @return FLASH Status - FLASH_BUSY, FLASH_ERROR_PG, + * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. + */ +FLASH_Status FLASH_EraseAllPages(void) +{ + FLASH_Status status = FLASH_COMPLETE; + + status = FLASH_WaitForLastOperation(EraseTimeout); + if(status == FLASH_COMPLETE) + { + FLASH->CTLR &= (CR_OPTER_Reset & CR_PAGE_ER_Reset); + FLASH->CTLR |= CR_MER_Set; + FLASH->CTLR |= CR_STRT_Set; + + status = FLASH_WaitForLastOperation(EraseTimeout); + + FLASH->CTLR &= CR_MER_Reset; + } + + return status; +} + +/******************************************************************************** + * @fn FLASH_EraseOptionBytes + * + * @brief Erases the FLASH option bytes. + * + * @return FLASH Status - FLASH_BUSY, FLASH_ERROR_PG, + * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. + */ +FLASH_Status FLASH_EraseOptionBytes(void) +{ + FLASH_Status status = FLASH_COMPLETE; + + status = FLASH_WaitForLastOperation(EraseTimeout); + if(status == FLASH_COMPLETE) + { + FLASH_Unlock(); + + FLASH->OBKEYR = FLASH_KEY1; + FLASH->OBKEYR = FLASH_KEY2; + + FLASH->CTLR &= (CR_OPTER_Reset & CR_PAGE_ER_Reset); + FLASH->CTLR |= CR_OPTER_Set; + FLASH->CTLR |= CR_STRT_Set; + status = FLASH_WaitForLastOperation(EraseTimeout); + + FLASH->CTLR &= CR_OPTER_Reset; + + FLASH_Lock(); + } + return status; +} + +/********************************************************************* + * @fn FLASH_OptionBytePR + * + * @brief Programs option bytes. + * + * @param pbuf - data. + * + * @return none + */ +void FLASH_OptionBytePR(u32* pbuf) +{ + uint8_t i; + + FLASH_EraseOptionBytes(); + FLASH_Unlock_Fast(); + FLASH_BufReset(); + + for(i=0; i<4; i++) + { + FLASH_BufLoad((OB_BASE + 4*i), *pbuf++); + } + + FLASH_ProgramPage_Fast(OB_BASE); + FLASH_Lock_Fast(); +} + +/********************************************************************* + * @fn FLASH_EnableWriteProtection + * + * @brief Write protects the desired sectors + * + * @param FLASH_Sectors - specifies the address of the pages to be write protected. + * + * @return FLASH Status - FLASH_BUSY, FLASH_ERROR_PG, + * FLASH_ERROR_WRP, FLASH_COMPLETE , FLASH_TIMEOUT or FLASH_RDP. + */ +FLASH_Status FLASH_EnableWriteProtection(uint32_t FLASH_Pages) +{ + uint8_t WRP0_Data = 0xFF, WRP1_Data = 0xFF, WRP2_Data = 0xFF, WRP3_Data = 0xFF; + uint32_t buf[4]; + uint8_t i; + FLASH_Status status = FLASH_COMPLETE; + + if((FLASH->OBR & RDPRT_Mask) != (uint32_t)RESET) + { + status = FLASH_RDP; + } + else{ + FLASH_Pages = (uint32_t)(~FLASH_Pages); + WRP0_Data = (uint8_t)(FLASH_Pages & WRP0_Mask); + WRP1_Data = (uint8_t)((FLASH_Pages & WRP1_Mask) >> 8); + WRP2_Data = (uint8_t)((FLASH_Pages & WRP2_Mask) >> 16); + WRP3_Data = (uint8_t)((FLASH_Pages & WRP3_Mask) >> 24); + + status = FLASH_WaitForLastOperation(ProgramTimeout); + + if(status == FLASH_COMPLETE) + { + for(i=0; i<4; i++){ + buf[i] = *(uint32_t*)(OB_BASE + 4*i); + } + + buf[2] = ((uint32_t)(((uint32_t)(WRP0_Data) & 0x00FF) + (((uint32_t)(~WRP0_Data) & 0x00FF) << 8) \ + + (((uint32_t)(WRP1_Data) & 0x00FF) << 16) + (((uint32_t)(~WRP1_Data) & 0x00FF) << 24))); + buf[3] = ((uint32_t)(((uint32_t)(WRP2_Data) & 0x00FF) + (((uint32_t)(~WRP2_Data) & 0x00FF) << 8) \ + + (((uint32_t)(WRP3_Data) & 0x00FF) << 16) + (((uint32_t)(~WRP3_Data) & 0x00FF) << 24))); + + FLASH_OptionBytePR(buf); + } + } + + return status; +} + +/********************************************************************* + * @fn FLASH_EnableReadOutProtection + * + * @brief Enables the read out protection. + * + * @param Newstate - new state of the ReadOut Protection(ENABLE or DISABLE). + * + * @return FLASH Status - FLASH_BUSY, FLASH_ERROR_PG, + * FLASH_ERROR_WRP, FLASH_COMPLETE, FLASH_TIMEOUT or FLASH_RDP. + */ +FLASH_Status FLASH_EnableReadOutProtection(void) +{ + FLASH_Status status = FLASH_COMPLETE; + uint32_t buf[4]; + uint8_t i; + + if((FLASH->OBR & RDPRT_Mask) != (uint32_t)RESET) + { + status = FLASH_RDP; + } + else{ + status = FLASH_WaitForLastOperation(EraseTimeout); + if(status == FLASH_COMPLETE) + { + for(i=0; i<4; i++){ + buf[i] = *(uint32_t*)(OB_BASE + 4*i); + } + + buf[0] = 0x000000FF + (buf[0] & 0xFFFF0000); + FLASH_OptionBytePR(buf); + } + } + + return status; +} + +/********************************************************************* + * @fn FLASH_UserOptionByteConfig + * + * @brief Programs the FLASH User Option Byte - IWDG_SW / RST_STOP / RST_STDBY/CAN_BusOff_MODE. + * + * @param OB_IWDG - Selects the IWDG mode. + * OB_IWDG_SW - Software IWDG selected + * OB_IWDG_HW - Hardware IWDG selected + * OB_STOP - Reset event when entering STOP mode. + * OB_STOP_NoRST - No reset generated when entering in STOP + * OB_STOP_RST - Reset generated when entering in STOP + * OB_STDBY - Reset event when entering Standby mode. + * OB_STDBY_NoRST - No reset generated when entering in STANDBY + * OB_STDBY_RST - Reset generated when entering in STANDBY + * OB_CAN - Set CAN bus off recovery time. + * OB_CAN_BusOff_MODE1 - Faster recovery time from Bus off. + * OB_CAN_BusOff_MODE2 - Normal recovery time from bus off. + * + * @return FLASH Status - FLASH_BUSY, FLASH_ERROR_PG, + * FLASH_ERROR_WRP, FLASH_COMPLETE , FLASH_TIMEOUT or FLASH_RDP. + */ +FLASH_Status FLASH_UserOptionByteConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY, uint8_t OB_CAN) +{ + FLASH_Status status = FLASH_COMPLETE; + uint8_t UserByte; + uint32_t buf[4]; + uint8_t i; + + if((FLASH->OBR & RDPRT_Mask) != (uint32_t)RESET) + { + status = FLASH_RDP; + } + else{ + UserByte = OB_IWDG | (uint8_t)(OB_STOP | (uint8_t)(OB_STDBY | (uint8_t)(OB_CAN | (uint8_t)0xD8))); + + for(i=0; i<4; i++){ + buf[i] = *(uint32_t*)(OB_BASE + 4*i); + } + buf[0] = ((uint32_t)((((uint32_t)(UserByte) & 0x00FF) << 16) + (((uint32_t)(~UserByte) & 0x00FF) << 24))) + 0x00005AA5; + + FLASH_OptionBytePR(buf); + } + + return status; +} + +/********************************************************************* + * @fn FLASH_GetUserOptionByte + * + * @brief Returns the FLASH User Option Bytes values. + * + * @return The FLASH User Option Bytes values:IWDG_SW(Bit0), RST_STOP(Bit1), + * RST_STDBY(Bit2) ,CAN_BusOff_MODE(bit7) ,DATA0(bit[15:8]) and + * DATA1(bit[23:16]). + */ +uint32_t FLASH_GetUserOptionByte(void) +{ + return (uint32_t)(FLASH->OBR >> 2); +} + +/********************************************************************* + * @fn FLASH_GetWriteProtectionOptionByte + * + * @brief Returns the FLASH Write Protection Option Bytes Register value. + * + * @return The FLASH Write Protection Option Bytes Register value. + */ +uint32_t FLASH_GetWriteProtectionOptionByte(void) +{ + return (uint32_t)(FLASH->WPR); +} + +/********************************************************************* + * @fn FLASH_GetReadOutProtectionStatus + * + * @brief Checks whether the FLASH Read Out Protection Status is set or not. + * + * @return FLASH ReadOut Protection Status(SET or RESET) + */ +FlagStatus FLASH_GetReadOutProtectionStatus(void) +{ + FlagStatus readoutstatus = RESET; + if((FLASH->OBR & RDPRT_Mask) != (uint32_t)RESET) + { + readoutstatus = SET; + } + else + { + readoutstatus = RESET; + } + return readoutstatus; +} + +/********************************************************************* + * @fn FLASH_ITConfig + * + * @brief Enables or disables the specified FLASH interrupts. + * + * @param FLASH_IT - specifies the FLASH interrupt sources to be enabled or disabled. + * FLASH_IT_ERROR - FLASH Error Interrupt + * FLASH_IT_EOP - FLASH end of operation Interrupt + * NewState - new state of the specified Flash interrupts(ENABLE or DISABLE). + * + * @return FLASH Prefetch Buffer Status (SET or RESET). + */ +void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + FLASH->CTLR |= FLASH_IT; + } + else + { + FLASH->CTLR &= ~(uint32_t)FLASH_IT; + } +} + +/********************************************************************* + * @fn FLASH_GetFlagStatus + * + * @brief Checks whether the specified FLASH flag is set or not. + * + * @param FLASH_FLAG - specifies the FLASH flag to check. + * FLASH_FLAG_BSY - FLASH Busy flag + * FLASH_FLAG_WRPRTERR - FLASH Write protected error flag + * FLASH_FLAG_EOP - FLASH End of Operation flag + * FLASH_FLAG_WAKE_UP - FLASH Wake up of Operation flag + * FLASH_FLAG_OPTERR - FLASH Option Byte error flag + * + * @return The new state of FLASH_FLAG (SET or RESET). + */ +FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG) +{ + FlagStatus bitstatus = RESET; + + if(FLASH_FLAG == FLASH_FLAG_OPTERR) + { + if((FLASH->OBR & FLASH_FLAG_OPTERR) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + } + else + { + if((FLASH->STATR & FLASH_FLAG) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + } + return bitstatus; +} + +/********************************************************************* + * @fn FLASH_ClearFlag + * + * @brief Clears the FLASH's pending flags. + * + * @param FLASH_FLAG - specifies the FLASH flags to clear. + * FLASH_FLAG_WRPRTERR - FLASH Write protected error flag + * FLASH_FLAG_EOP - FLASH End of Operation flag + * + * @return none + */ +void FLASH_ClearFlag(uint32_t FLASH_FLAG) +{ + FLASH->STATR = FLASH_FLAG; +} + +/********************************************************************* + * @fn FLASH_GetStatus + * + * @brief Returns the FLASH Status. + * + * @return FLASH Status - FLASH_BUSY, FLASH_ERROR_PG, + * FLASH_ERROR_WRP or FLASH_COMPLETE. + */ +FLASH_Status FLASH_GetStatus(void) +{ + FLASH_Status flashstatus = FLASH_COMPLETE; + + if((FLASH->STATR & FLASH_FLAG_BSY) == FLASH_FLAG_BSY) + { + flashstatus = FLASH_BUSY; + } + else + { + if((FLASH->STATR & FLASH_FLAG_WRPRTERR) != 0) + { + flashstatus = FLASH_ERROR_WRP; + } + else + { + flashstatus = FLASH_COMPLETE; + } + } + return flashstatus; +} + +/********************************************************************* + * @fn FLASH_GetBank1Status + * + * @brief Returns the FLASH Bank1 Status. + * + * @return FLASH Status - FLASH_BUSY, FLASH_ERROR_PG, + * FLASH_ERROR_WRP or FLASH_COMPLETE. + */ +FLASH_Status FLASH_GetBank1Status(void) +{ + FLASH_Status flashstatus = FLASH_COMPLETE; + + if((FLASH->STATR & FLASH_FLAG_BANK1_BSY) == FLASH_FLAG_BSY) + { + flashstatus = FLASH_BUSY; + } + else + { + if((FLASH->STATR & FLASH_FLAG_BANK1_WRPRTERR) != 0) + { + flashstatus = FLASH_ERROR_WRP; + } + else + { + flashstatus = FLASH_COMPLETE; + } + } + return flashstatus; +} + +/********************************************************************* + * @fn FLASH_WaitForLastOperation + * + * @brief Waits for a Flash operation to complete or a TIMEOUT to occur. + * + * @param Timeout - FLASH programming Timeout + * + * @return FLASH Status - FLASH_BUSY, FLASH_ERROR_PG, + * FLASH_ERROR_WRP or FLASH_COMPLETE. + */ +FLASH_Status FLASH_WaitForLastOperation(uint32_t Timeout) +{ + FLASH_Status status = FLASH_COMPLETE; + + status = FLASH_GetBank1Status(); + while((status == FLASH_BUSY) && (Timeout != 0x00)) + { + status = FLASH_GetBank1Status(); + Timeout--; + } + if(Timeout == 0x00) + { + status = FLASH_TIMEOUT; + } + return status; +} + +/********************************************************************* + * @fn FLASH_WaitForLastBank1Operation + * + * @brief Waits for a Flash operation on Bank1 to complete or a TIMEOUT to occur. + * + * @param Timeout - FLASH programming Timeout + * + * @return FLASH Status - FLASH_BUSY, FLASH_ERROR_PG, + * FLASH_ERROR_WRP or FLASH_COMPLETE. + */ +FLASH_Status FLASH_WaitForLastBank1Operation(uint32_t Timeout) +{ + FLASH_Status status = FLASH_COMPLETE; + + status = FLASH_GetBank1Status(); + while((status == FLASH_FLAG_BANK1_BSY) && (Timeout != 0x00)) + { + status = FLASH_GetBank1Status(); + Timeout--; + } + if(Timeout == 0x00) + { + status = FLASH_TIMEOUT; + } + return status; +} + +/********************************************************************* + * @fn FLASH_Unlock_Fast + * + * @brief Unlocks the Fast Program Erase Mode. + * + * @return none + */ +void FLASH_Unlock_Fast(void) +{ + /* Authorize the FPEC of Bank1 Access */ + FLASH->KEYR = FLASH_KEY1; + FLASH->KEYR = FLASH_KEY2; + + /* Fast program mode unlock */ + FLASH->MODEKEYR = FLASH_KEY1; + FLASH->MODEKEYR = FLASH_KEY2; +} + +/********************************************************************* + * @fn FLASH_Lock_Fast + * + * @brief Locks the Fast Program Erase Mode. + * + * @return none + */ +void FLASH_Lock_Fast(void) +{ + FLASH->CTLR |= CR_FLOCK_Set; +} + +/********************************************************************* + * @fn FLASH_BufReset + * + * @brief Flash Buffer reset. + * + * @return none + */ +void FLASH_BufReset(void) +{ + FLASH->CTLR &= (CR_OPTER_Reset & CR_PAGE_ER_Reset); + + FLASH->CTLR |= CR_PAGE_PG; + FLASH->CTLR |= CR_BUF_RST; + while(FLASH->STATR & SR_BSY) + ; + FLASH->CTLR &= ~CR_PAGE_PG; +} + +/********************************************************************* + * @fn FLASH_BufLoad + * + * @brief Flash Buffer load(4Byte). + * + * @param Address - specifies the address to be programmed. + * Data0 - specifies the data0 to be programmed. + * + * @return none + */ +void FLASH_BufLoad(uint32_t Address, uint32_t Data0) +{ + FLASH->CTLR &= (CR_OPTER_Reset & CR_PAGE_ER_Reset); + + FLASH->CTLR |= CR_PAGE_PG; + *(__IO uint32_t *)(Address) = Data0; + FLASH->CTLR |= CR_BUF_LOAD; + while(FLASH->STATR & SR_BSY) + ; + FLASH->CTLR &= ~CR_PAGE_PG; +} + +/********************************************************************* + * @fn FLASH_ErasePage_Fast + * + * @brief Erases a specified FLASH page (1page = 256Byte). + * + * @param Page_Address - The page address to be erased. + * + * @return none + */ +void FLASH_ErasePage_Fast(uint32_t Page_Address) +{ + FLASH->CTLR &= (CR_OPTER_Reset & CR_PAGE_ER_Reset); + + FLASH->CTLR |= CR_PAGE_ER; + FLASH->ADDR = Page_Address; + FLASH->CTLR |= CR_STRT_Set; + while(FLASH->STATR & SR_BSY) + ; + FLASH->CTLR &= ~CR_PAGE_ER; +} + +/********************************************************************* + * @fn FLASH_EraseBlock_32K_Fast + * + * @brief Erases a specified FLASH Block (1Block = 32KByte). + * + * @param Block_Address - The block address to be erased. + * + * @return none + */ +void FLASH_EraseBlock_32K_Fast(uint32_t Block_Address) +{ + FLASH->CTLR &= (CR_OPTER_Reset & CR_PAGE_ER_Reset); + + Block_Address &= 0xFFFF8000; + + FLASH->CTLR |= CR_BER32; + FLASH->ADDR = Block_Address; + FLASH->CTLR |= CR_STRT_Set; + while(FLASH->STATR & SR_BSY) + ; + FLASH->CTLR &= ~CR_BER32; +} + +/********************************************************************* + * @fn FLASH_ProgramPage_Fast + * + * @brief Program a specified FLASH page (1page = 256Byte). + * + * @param Page_Address - The page address to be programed. + * + * @return none + */ +void FLASH_ProgramPage_Fast(uint32_t Page_Address) +{ + FLASH->CTLR &= (CR_OPTER_Reset & CR_PAGE_ER_Reset); + + FLASH->CTLR |= CR_PAGE_PG; + FLASH->ADDR = Page_Address; + FLASH->CTLR |= CR_STRT_Set; + while(FLASH->STATR & SR_BSY) + ; + FLASH->CTLR &= ~CR_PAGE_PG; +} + +/********************************************************************* + * @fn ROM_ERASE + * + * @brief Select erases a specified FLASH . + * + * @param StartAddr - Erases Flash start address(StartAddr%256 == 0). + * Cnt - Erases count. + * Erase_Size - Erases size select.The returned value can be: + * Size_32KB, Size_1KB, Size_256B. + * + * @return none. + */ +static void ROM_ERASE(uint32_t StartAddr, uint32_t Cnt, uint32_t Erase_Size) +{ + FLASH->CTLR &= (CR_OPTER_Reset & CR_PAGE_ER_Reset); + + do{ + if(Erase_Size == Size_32KB) + { + FLASH->CTLR |= CR_BER32; + } + else if(Erase_Size == Size_1KB) + { + FLASH->CTLR |= CR_PER_Set; + } + else if(Erase_Size == Size_256B) + { + FLASH->CTLR |= CR_PAGE_ER; + } + + FLASH->ADDR = StartAddr; + FLASH->CTLR |= CR_STRT_Set; + while(FLASH->STATR & SR_BSY) + ; + + if(Erase_Size == Size_32KB) + { + FLASH->CTLR &= ~CR_BER32; + StartAddr += Size_32KB; + } + else if(Erase_Size == Size_1KB) + { + FLASH->CTLR &= ~CR_PER_Set; + StartAddr += Size_1KB; + } + else if(Erase_Size == Size_256B) + { + FLASH->CTLR &= ~CR_PAGE_ER; + StartAddr += Size_256B; + } + }while(--Cnt); +} + +/********************************************************************* + * @fn FLASH_ROM_ERASE + * + * @brief Erases a specified FLASH . + * + * @param StartAddr - Erases Flash start address(StartAddr%256 == 0). + * Length - Erases Flash start Length(Length%256 == 0). + * + * @return FLASH Status - The returned value can be: FLASH_ADR_RANGE_ERROR, + * FLASH_ALIGN_ERROR, FLASH_OP_RANGE_ERROR or FLASH_COMPLETE. + */ +FLASH_Status FLASH_ROM_ERASE(uint32_t StartAddr, uint32_t Length) +{ + uint32_t Addr0 = 0, Addr1 = 0, Length0 = 0, Length1 = 0; + + FLASH_Status status = FLASH_COMPLETE; + + if((StartAddr < ValidAddrStart) || (StartAddr >= ValidAddrEnd)) + { + return FLASH_ADR_RANGE_ERROR; + } + + if((StartAddr + Length) > ValidAddrEnd) + { + return FLASH_OP_RANGE_ERROR; + } + + if((StartAddr & (Size_256B-1)) || (Length & (Size_256B-1)) || (Length == 0)) + { + return FLASH_ALIGN_ERROR; + } + + /* Authorize the FPEC of Bank1 Access */ + FLASH->KEYR = FLASH_KEY1; + FLASH->KEYR = FLASH_KEY2; + + /* Fast mode unlock */ + FLASH->MODEKEYR = FLASH_KEY1; + FLASH->MODEKEYR = FLASH_KEY2; + + Addr0 = StartAddr; + + if(Length >= Size_32KB) + { + Length0 = Size_32KB - (Addr0 & (Size_32KB - 1)); + Addr1 = StartAddr + Length0; + Length1 = Length - Length0; + } + else if(Length >= Size_1KB) + { + Length0 = Size_1KB - (Addr0 & (Size_1KB - 1)); + Addr1 = StartAddr + Length0; + Length1 = Length - Length0; + } + else if(Length >= Size_256B) + { + Length0 = Length; + } + + /* Erase 32KB */ + if(Length0 >= Size_32KB)//front + { + Length = Length0; + if(Addr0 & (Size_32KB - 1)) + { + Length0 = Size_32KB - (Addr0 & (Size_32KB - 1)); + } + else + { + Length0 = 0; + } + + ROM_ERASE((Addr0 + Length0), ((Length - Length0) >> 15), Size_32KB); + } + + if(Length1 >= Size_32KB)//back + { + StartAddr = Addr1; + Length = Length1; + + if((Addr1 + Length1) & (Size_32KB - 1)) + { + Addr1 = ((StartAddr + Length1) & (~(Size_32KB - 1))); + Length1 = (StartAddr + Length1) & (Size_32KB - 1); + } + else + { + Length1 = 0; + } + + ROM_ERASE(StartAddr, ((Length - Length1) >> 15), Size_32KB); + } + + /* Erase 1KB */ + if(Length0 >= Size_1KB) //front + { + Length = Length0; + if(Addr0 & (Size_1KB - 1)) + { + Length0 = Size_1KB - (Addr0 & (Size_1KB - 1)); + } + else + { + Length0 = 0; + } + + ROM_ERASE((Addr0 + Length0), ((Length - Length0) >> 10), Size_1KB); + } + + if(Length1 >= Size_1KB) //back + { + StartAddr = Addr1; + Length = Length1; + + if((Addr1 + Length1) & (Size_1KB - 1)) + { + Addr1 = ((StartAddr + Length1) & (~(Size_1KB - 1))); + Length1 = (StartAddr + Length1) & (Size_1KB - 1); + } + else + { + Length1 = 0; + } + + ROM_ERASE(StartAddr, ((Length - Length1) >> 10), Size_1KB); + } + + /* Erase 256B */ + if(Length0)//front + { + ROM_ERASE(Addr0, (Length0 >> 8), Size_256B); + } + + if(Length1)//back + { + ROM_ERASE(Addr1, (Length1 >> 8), Size_256B); + } + + FLASH->CTLR |= CR_FLOCK_Set; + FLASH->CTLR |= CR_LOCK_Set; + + return status; +} + +/********************************************************************* + * @fn FLASH_ROM_WRITE + * + * @brief Writes a specified FLASH . + * + * @param StartAddr - Writes Flash start address(StartAddr%256 == 0). + * Length - Writes Flash start Length(Length%256 == 0). + * pbuf - Writes Flash value buffer. + * + * @return FLASH Status - The returned value can be: FLASH_ADR_RANGE_ERROR, + * FLASH_ALIGN_ERROR, FLASH_OP_RANGE_ERROR or FLASH_COMPLETE. + */ +FLASH_Status FLASH_ROM_WRITE(uint32_t StartAddr, uint32_t *pbuf, uint32_t Length) +{ + uint32_t i, adr; + uint8_t size; + + FLASH_Status status = FLASH_COMPLETE; + + if((StartAddr < ValidAddrStart) || (StartAddr >= ValidAddrEnd)) + { + return FLASH_ADR_RANGE_ERROR; + } + + if((StartAddr + Length) > ValidAddrEnd) + { + return FLASH_OP_RANGE_ERROR; + } + + if((StartAddr & (Size_256B-1)) || (Length & (Size_256B-1)) || (Length == 0)) + { + return FLASH_ALIGN_ERROR; + } + adr = StartAddr; + i = Length >> 8; + + /* Authorize the FPEC of Bank1 Access */ + FLASH->KEYR = FLASH_KEY1; + FLASH->KEYR = FLASH_KEY2; + + /* Fast program mode unlock */ + FLASH->MODEKEYR = FLASH_KEY1; + FLASH->MODEKEYR = FLASH_KEY2; + + FLASH->CTLR &= (CR_OPTER_Reset & CR_PAGE_ER_Reset); + + do{ + FLASH->CTLR |= CR_PAGE_PG; + FLASH->CTLR |= CR_BUF_RST; + while(FLASH->STATR & SR_BSY) + ; + size = 64; + while(size) + { + *(uint32_t *)StartAddr = *(uint32_t *)pbuf; + FLASH->CTLR |= CR_BUF_LOAD; + while(FLASH->STATR & SR_BSY) + ; + StartAddr += 4; + pbuf += 1; + size -= 1; + } + + FLASH->ADDR = adr; + FLASH->CTLR |= CR_STRT_Set; + while(FLASH->STATR & SR_BSY) + ; + FLASH->CTLR &= ~CR_PAGE_PG; + adr += 256; + }while(--i); + + FLASH->CTLR |= CR_FLOCK_Set; + FLASH->CTLR |= CR_LOCK_Set; + + return status; +} diff --git a/ZDBMS/BMS_MC/Peripheral/src/ch32l103_gpio.c b/ZDBMS/BMS_MC/Peripheral/src/ch32l103_gpio.c new file mode 100644 index 0000000..5745833 --- /dev/null +++ b/ZDBMS/BMS_MC/Peripheral/src/ch32l103_gpio.c @@ -0,0 +1,696 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32l103_gpio.c + * Author : WCH + * Version : V1.0.0 + * Date : 2024/11/06 + * Description : This file provides all the GPIO firmware functions. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#include "ch32l103_gpio.h" +#include "ch32l103_rcc.h" + +/* MASK */ +#define ECR_PORTPINCONFIG_MASK ((uint16_t)0xFF80) +#define LSB_MASK ((uint16_t)0xFFFF) +#define DBGAFR_POSITION_MASK ((uint32_t)0x000F0000) +#define DBGAFR_SWJCFG_MASK ((uint32_t)0xF8FFFFFF) +#define DBGAFR_LOCATION_MASK ((uint32_t)0x00200000) +#define DBGAFR_NUMBITS_MASK ((uint32_t)0x00100000) +#define REMAP_MASK ((uint32_t)0xC0000000) +#define REMAP_NUM_MASK ((uint32_t)0x38000000) + +uint32_t OPA_Trim = 0; +uint16_t ADC_Trim = 0; +uint32_t TS_Val = 0; +uint32_t CHIPID = 0; +uint16_t USBPD_CFG = 0; +/********************************************************************* + * @fn GPIO_DeInit + * + * @brief Deinitializes the GPIOx peripheral registers to their default + * reset values. + * + * @param GPIOx - where x can be (A..D) to select the GPIO peripheral. + * + * @return none + */ +void GPIO_DeInit(GPIO_TypeDef *GPIOx) +{ + if(GPIOx == GPIOA) + { + RCC_PB2PeriphResetCmd(RCC_PB2Periph_GPIOA, ENABLE); + RCC_PB2PeriphResetCmd(RCC_PB2Periph_GPIOA, DISABLE); + } + else if(GPIOx == GPIOB) + { + RCC_PB2PeriphResetCmd(RCC_PB2Periph_GPIOB, ENABLE); + RCC_PB2PeriphResetCmd(RCC_PB2Periph_GPIOB, DISABLE); + } + else if(GPIOx == GPIOC) + { + RCC_PB2PeriphResetCmd(RCC_PB2Periph_GPIOC, ENABLE); + RCC_PB2PeriphResetCmd(RCC_PB2Periph_GPIOC, DISABLE); + } + else if(GPIOx == GPIOD) + { + RCC_PB2PeriphResetCmd(RCC_PB2Periph_GPIOD, ENABLE); + RCC_PB2PeriphResetCmd(RCC_PB2Periph_GPIOD, DISABLE); + } +} + +/********************************************************************* + * @fn GPIO_AFIODeInit + * + * @brief Deinitializes the Alternate Functions (remap, event control + * and EXTI configuration) registers to their default reset values. + * + * @return none + */ +void GPIO_AFIODeInit(void) +{ + RCC_PB2PeriphResetCmd(RCC_PB2Periph_AFIO, ENABLE); + RCC_PB2PeriphResetCmd(RCC_PB2Periph_AFIO, DISABLE); +} + +/********************************************************************* + * @fn GPIO_Init + * + * @brief GPIOx - where x can be (A..D) to select the GPIO peripheral. + * + * @param GPIO_InitStruct - pointer to a GPIO_InitTypeDef structure that + * contains the configuration information for the specified GPIO peripheral. + * + * @return none + */ +void GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_InitStruct) +{ + uint32_t currentmode = 0x00, currentpin = 0x00, pinpos = 0x00, pos = 0x00; + uint32_t tmpreg = 0x00, pinmask = 0x00; + + currentmode = ((uint32_t)GPIO_InitStruct->GPIO_Mode) & ((uint32_t)0x0F); + + if((((uint32_t)GPIO_InitStruct->GPIO_Mode) & ((uint32_t)0x10)) != 0x00) + { + currentmode |= (uint32_t)GPIO_InitStruct->GPIO_Speed; + } + + if(((uint32_t)GPIO_InitStruct->GPIO_Pin & ((uint32_t)0x00FF)) != 0x00) + { + tmpreg = GPIOx->CFGLR; + + for(pinpos = 0x00; pinpos < 0x08; pinpos++) + { + pos = ((uint32_t)0x01) << pinpos; + currentpin = (GPIO_InitStruct->GPIO_Pin) & pos; + + if(currentpin == pos) + { + pos = pinpos << 2; + pinmask = ((uint32_t)0x0F) << pos; + tmpreg &= ~pinmask; + tmpreg |= (currentmode << pos); + + if(GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPD) + { + GPIOx->BCR = (((uint32_t)0x01) << pinpos); + } + else + { + if(GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPU) + { + GPIOx->BSHR = (((uint32_t)0x01) << pinpos); + } + } + } + } + GPIOx->CFGLR = tmpreg; + } + + if(GPIO_InitStruct->GPIO_Pin > 0x00FF) + { + tmpreg = GPIOx->CFGHR; + + for(pinpos = 0x00; pinpos < 0x08; pinpos++) + { + pos = (((uint32_t)0x01) << (pinpos + 0x08)); + currentpin = ((GPIO_InitStruct->GPIO_Pin) & pos); + + if(currentpin == pos) + { + pos = pinpos << 2; + pinmask = ((uint32_t)0x0F) << pos; + tmpreg &= ~pinmask; + tmpreg |= (currentmode << pos); + + if(GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPD) + { + GPIOx->BCR = (((uint32_t)0x01) << (pinpos + 0x08)); + } + + if(GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPU) + { + GPIOx->BSHR = (((uint32_t)0x01) << (pinpos + 0x08)); + } + } + } + GPIOx->CFGHR = tmpreg; + } +} + +/********************************************************************* + * @fn GPIO_StructInit + * + * @brief Fills each GPIO_InitStruct member with its default + * + * @param GPIO_InitStruct - pointer to a GPIO_InitTypeDef structure + * which will be initialized. + * + * @return none + */ +void GPIO_StructInit(GPIO_InitTypeDef *GPIO_InitStruct) +{ + GPIO_InitStruct->GPIO_Pin = GPIO_Pin_All; + GPIO_InitStruct->GPIO_Speed = GPIO_Speed_2MHz; + GPIO_InitStruct->GPIO_Mode = GPIO_Mode_IN_FLOATING; +} + +/********************************************************************* + * @fn GPIO_ReadInputDataBit + * + * @brief GPIOx - where x can be (A..D) to select the GPIO peripheral. + * + * @param GPIO_Pin - specifies the port bit to read. + * This parameter can be GPIO_Pin_x where x can be (0..15). + * + * @return The input port pin value. + */ +uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) +{ + uint8_t bitstatus = 0x00; + + if((GPIOx->INDR & GPIO_Pin) != (uint32_t)Bit_RESET) + { + bitstatus = (uint8_t)Bit_SET; + } + else + { + bitstatus = (uint8_t)Bit_RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn GPIO_ReadInputData + * + * @brief Reads the specified GPIO input data port. + * + * @param GPIOx - where x can be (A..D) to select the GPIO peripheral. + * + * @return The output port pin value. + */ +uint16_t GPIO_ReadInputData(GPIO_TypeDef *GPIOx) +{ + uint16_t val; + + val = ( uint16_t )GPIOx->INDR; + + return ( val ); +} + +/********************************************************************* + * @fn GPIO_ReadOutputDataBit + * + * @brief Reads the specified output data port bit. + * + * @param GPIOx - where x can be (A..D) to select the GPIO peripheral. + * GPIO_Pin - specifies the port bit to read. + * This parameter can be GPIO_Pin_x where x can be (0..15). + * + * @return none + */ +uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) +{ + uint8_t bitstatus = 0x00; + + if((GPIOx->OUTDR & GPIO_Pin) != (uint32_t)Bit_RESET) + { + bitstatus = (uint8_t)Bit_SET; + } + else + { + bitstatus = (uint8_t)Bit_RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn GPIO_ReadOutputData + * + * @brief Reads the specified GPIO output data port. + * + * @param GPIOx - where x can be (A..D) to select the GPIO peripheral. + * + * @return GPIO output port pin value. + */ +uint16_t GPIO_ReadOutputData(GPIO_TypeDef *GPIOx) +{ + uint16_t val; + + val = ( uint16_t )GPIOx->OUTDR; + + return ( val ); +} + +/********************************************************************* + * @fn GPIO_SetBits + * + * @brief Sets the selected data port bits. + * + * @param GPIOx - where x can be (A..D) to select the GPIO peripheral. + * GPIO_Pin - specifies the port bits to be written. + * This parameter can be any combination of GPIO_Pin_x where x can be (0..15). + * + * @return none + */ +void GPIO_SetBits(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) +{ + GPIOx->BSHR = GPIO_Pin; +} + +/********************************************************************* + * @fn GPIO_ResetBits + * + * @brief Clears the selected data port bits. + * + * @param GPIOx - where x can be (A..D) to select the GPIO peripheral. + * GPIO_Pin - specifies the port bits to be written. + * This parameter can be any combination of GPIO_Pin_x where x can be (0..15). + * + * @return none + */ +void GPIO_ResetBits(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) +{ + GPIOx->BCR = GPIO_Pin; +} + +/********************************************************************* + * @fn GPIO_WriteBit + * + * @brief Sets or clears the selected data port bit. + * + * @param GPIO_Pin - specifies the port bit to be written. + * This parameter can be one of GPIO_Pin_x where x can be (0..15). + * BitVal - specifies the value to be written to the selected bit. + * Bit_RESET - to clear the port pin. + * Bit_SET - to set the port pin. + * + * @return none + */ +void GPIO_WriteBit(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, BitAction BitVal) +{ + if(BitVal != Bit_RESET) + { + GPIOx->BSHR = GPIO_Pin; + } + else + { + GPIOx->BCR = GPIO_Pin; + } +} + +/********************************************************************* + * @fn GPIO_Write + * + * @brief Writes data to the specified GPIO data port. + * + * @param GPIOx - where x can be (A..D) to select the GPIO peripheral. + * PortVal - specifies the value to be written to the port output data register. + * + * @return none + */ +void GPIO_Write(GPIO_TypeDef *GPIOx, uint16_t PortVal) +{ + GPIOx->OUTDR = PortVal; +} + +/********************************************************************* + * @fn GPIO_PinLockConfig + * + * @brief Locks GPIO Pins configuration registers. + * + * @param GPIOx - where x can be (A..D) to select the GPIO peripheral. + * GPIO_Pin - specifies the port bit to be written. + * This parameter can be any combination of GPIO_Pin_x where x can be (0..15). + * + * @return none + */ +void GPIO_PinLockConfig(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) +{ + uint32_t tmp = 0x00010000; + + tmp |= GPIO_Pin; + GPIOx->LCKR = tmp; + GPIOx->LCKR = GPIO_Pin; + GPIOx->LCKR = tmp; + tmp = GPIOx->LCKR; + tmp = GPIOx->LCKR; +} + +/********************************************************************* + * @fn GPIO_EventOutputConfig + * + * @brief Selects the GPIO pin used as Event output. + * + * @param GPIO_PortSource - selects the GPIO port to be used as source + * for Event output. + * This parameter can be GPIO_PortSourceGPIOx where x can be (A..D). + * GPIO_PinSource - specifies the pin for the Event output. + * This parameter can be GPIO_PinSourcex where x can be (0..15). + * + * @return none + */ +void GPIO_EventOutputConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource) +{ + uint32_t tmpreg = 0x00; + + tmpreg = AFIO->ECR; + tmpreg &= ECR_PORTPINCONFIG_MASK; + tmpreg |= (uint32_t)GPIO_PortSource << 0x04; + tmpreg |= GPIO_PinSource; + AFIO->ECR = tmpreg; +} + +/********************************************************************* + * @fn GPIO_EventOutputCmd + * + * @brief Enables or disables the Event Output. + * + * @param NewState - ENABLE or DISABLE. + * + * @return none + */ +void GPIO_EventOutputCmd(FunctionalState NewState) +{ + if(NewState) + { + AFIO->ECR |= (1 << 7); + } + else + { + AFIO->ECR &= ~(1 << 7); + } +} + +/********************************************************************* + * @fn GPIO_PinRemapConfig + * + * @brief Changes the mapping of the specified pin. + * + * @param GPIO_Remap - selects the pin to remap. + * GPIO_PartialRemap1_SPI1 - SPI1 Partial1 Alternate Function mapping + * GPIO_PartialRemap2_SPI1 - SPI1 Partial2 Alternate Function mapping + * GPIO_FullRemap_SPI1 - SPI1 Full Alternate Function mapping + * GPIO_PartialRemap1_I2C1 - I2C1 Partial1 Alternate Function mapping + * GPIO_FullRemap_I2C1 - I2C1 Full Alternate Function mapping + * GPIO_PartialRemap1_USART1 - USART1 Partial1 Alternate Function mapping + * GPIO_PartialRemap2_USART1 - USART1 Partial2 Alternate Function mapping + * GPIO_PartialRemap3_USART1 - USART1 Partial3 Alternate Function mapping + * GPIO_PartialRemap4_USART1 - USART1 Partial4 Alternate Function mapping + * GPIO_FullRemap_USART1 - USART1 Full Alternate Function mapping + * GPIO_PartialRemap1_USART2 - USART2 Partial1 Alternate Function mapping + * GPIO_PartialRemap2_USART2 - USART2 Partial2 Alternate Function mapping + * GPIO_FullRemap_USART2 - USART2 Full Alternate Function mapping + * GPIO_PartialRemap1_TIM1 - TIM1 Partial1 Alternate Function mapping + * GPIO_PartialRemap2_TIM1 - TIM1 Partial2 Alternate Function mapping + * GPIO_PartialRemap3_TIM1 - TIM1 Partial3 Alternate Function mapping + * GPIO_PartialRemap4_TIM1 - TIM1 Partial4 Alternate Function mapping + * GPIO_PartialRemap5_TIM1 - TIM1 Partial5 Alternate Function mapping + * GPIO_FullRemap_TIM1 - TIM1 Full Alternate Function mapping + * GPIO_PartialRemap1_TIM2 - TIM2 Partial1 Alternate Function mapping + * GPIO_PartialRemap2_TIM2 - TIM2 Partial2 Alternate Function mapping + * GPIO_PartialRemap3_TIM2 - TIM2 Partial3 Alternate Function mapping + * GPIO_PartialRemap4_TIM2 - TIM2 Partial4 Alternate Function mapping + * GPIO_PartialRemap5_TIM2 - TIM2 Partial5 Alternate Function mapping + * GPIO_FullRemap_TIM2 - TIM2 Full Alternate Function mapping + * GPIO_PartialRemap_USART3 - USART3 Partial Alternate Function mapping + * GPIO_FullRemap_USART3 - USART3 Full Alternate Function mapping + * GPIO_Remap_TIM3 - TIM3 Alternate Function mapping + * GPIO_Remap_TIM4 - TIM4 Alternate Function mapping + * GPIO_Remap1_CAN1 - CAN1 Alternate Function mapping + * GPIO_Remap2_CAN1 - CAN1 Alternate Function mapping + * GPIO_Remap_PD01 - PD01 Alternate Function mapping + * GPIO_Remap_SWJ_Disable - Full SDI Disabled (SDI) + * GPIO_Remap_USART4 - USART4 Alternate Function mapping + * GPIO_Remap_LPTIM - LPTIM Alternate Function mapping + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void GPIO_PinRemapConfig(uint32_t GPIO_Remap, FunctionalState NewState) +{ + uint32_t tmp = 0x00, tmp1 = 0x00, tmpreg1 = 0x00, tmpreg2 = 0x00, tmpmask = 0x00; + + if((GPIO_Remap & 0xC0000000) == 0xC0000000) /* PCFR1 + PCFR2 */ + { + tmpreg1 = AFIO->PCFR1; + tmpreg2 = AFIO->PCFR2; + + /* Clear bit */ + tmp1 = ((GPIO_Remap & REMAP_NUM_MASK) >> 27); + + if(tmp1 == 0) + { + tmpreg1 &= ~(1<<0); + tmpreg2 &= ~(1<<24); + } + else if(tmp1 == 1) + { + tmpreg1 &= ~(1<<1); + tmpreg2 &= ~(1<<23); + } + else if(tmp1 == 2) + { + tmpreg1 &= ~(1<<2); + tmpreg2 &= ~(3<<19); + } + else if(tmp1 == 3) + { + tmpreg1 &= ~(1<<3); + tmpreg2 &= ~(1<<18); + } + else if(tmp1 == 4) + { + tmpreg1 &= ~(3<<6); + tmpreg2 &= ~(1<<22); + } + else if(tmp1 == 5) + { + tmpreg1 &= ~(3<<8); + tmpreg2 &= ~(1<<21); + } + + /* Set bit */ + if(NewState != DISABLE) + { + tmpreg1 |= (GPIO_Remap & 0x0000FFFF); + tmpreg2 |= (GPIO_Remap & 0x01FF0000); + } + + tmpreg1 |= ~DBGAFR_SWJCFG_MASK; + + AFIO->PCFR1 = tmpreg1; + AFIO->PCFR2 = tmpreg2; + } + else if((GPIO_Remap & 0xC0000000) == 0x40000000) /* PCFR2 */ + { + tmpreg2 = AFIO->PCFR2; + + /* Clear bit */ + tmp1 = ((GPIO_Remap & (~REMAP_MASK)) << 0x10); + tmpreg2 &= ~tmp1; + + /* Set bit */ + if(NewState != DISABLE) + { + tmpreg2 |= tmp1; + } + + AFIO->PCFR2 = tmpreg2; + } + else if((GPIO_Remap & 0xC0000000) == 0x00000000) /* PCFR1 */ + { + tmpreg1 = AFIO->PCFR1; + + /* Clear bit */ + tmpmask = (GPIO_Remap & DBGAFR_POSITION_MASK) >> 0x10; + tmp = GPIO_Remap & LSB_MASK; + + if((GPIO_Remap & (DBGAFR_LOCATION_MASK | DBGAFR_NUMBITS_MASK)) == (DBGAFR_LOCATION_MASK | DBGAFR_NUMBITS_MASK)) /* [26:24] 3bit SW_CFG */ + { + tmpreg1 &= DBGAFR_SWJCFG_MASK; + AFIO->PCFR1 &= DBGAFR_SWJCFG_MASK; + } + else if((GPIO_Remap & DBGAFR_NUMBITS_MASK) == DBGAFR_NUMBITS_MASK) /* [15:0] 2bit */ + { + tmp1 = ((uint32_t)0x03) << tmpmask; + tmpreg1 &= ~tmp1; + tmpreg1 |= ~DBGAFR_SWJCFG_MASK; + } + else /* [31:0] 1bit */ + { + tmpreg1 &= ~(tmp << ((GPIO_Remap >> 0x15) * 0x10)); + tmpreg1 |= ~DBGAFR_SWJCFG_MASK; + } + + /* Set bit */ + if(NewState != DISABLE) + { + tmpreg1 |= (tmp << (((GPIO_Remap & 0x7FFFFFFF )>> 0x15) * 0x10)); + } + + AFIO->PCFR1 = tmpreg1; + } +} + +/********************************************************************* + * @fn GPIO_EXTILineConfig + * + * @brief Selects the GPIO pin used as EXTI Line. + * + * @param GPIO_PortSource - selects the GPIO port to be used as source for EXTI lines. + * This parameter can be GPIO_PortSourceGPIOx where x can be (A..D). + * GPIO_PinSource - specifies the EXTI line to be configured. + * This parameter can be GPIO_PinSourcex where x can be (0..15). + * + * @return none + */ +void GPIO_EXTILineConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource) +{ + uint32_t tmp = 0x00; + + tmp = ((uint32_t)0x0F) << (0x04 * (GPIO_PinSource & (uint8_t)0x03)); + AFIO->EXTICR[GPIO_PinSource >> 0x02] &= ~tmp; + AFIO->EXTICR[GPIO_PinSource >> 0x02] |= (((uint32_t)GPIO_PortSource) << (0x04 * (GPIO_PinSource & (uint8_t)0x03))); +} + +/********************************************************************* + * @fn GPIO_IPD_Unused + * + * @brief Configure unused GPIO as input pull-down. + * + * @param none + * + * @return none + */ +void GPIO_IPD_Unused(void) +{ + GPIO_InitTypeDef GPIO_InitStructure = {0}; + uint32_t chip = 0; + + OPA_Trim = (((*(uint32_t *)OPA_TRIM_BASE & 0x0000001F) << 25) | (((*(uint32_t *)OPA_TRIM_BASE & 0x00008000)^0x00008000) << 9)) \ + | (((*(uint32_t *)OPA_TRIM_BASE & 0x001F0000) << 1) | (((*(uint32_t *)OPA_TRIM_BASE & 0x80000000)^0x80000000) >> 15)); + ADC_Trim = (*(uint16_t *)ADC_TRIM_BASE); + TS_Val = (*(uint32_t *)TS_BASE); + CHIPID = (*(uint32_t *)CHIPID_BASE); + USBPD_CFG = (*(uint16_t *)USBPD_CFG_BASE); + + RCC_PB2PeriphClockCmd(RCC_PB2Periph_GPIOA | RCC_PB2Periph_GPIOB | RCC_PB2Periph_GPIOC |RCC_PB2Periph_GPIOD |RCC_PB2Periph_AFIO,ENABLE); + chip = *( uint32_t * )CHIPID_BASE & (~0x000000F0); + switch(chip) + { + case 0x10320700: //CH32L103K8U6 + { + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_10\ + |GPIO_Pin_11|GPIO_Pin_12\ + |GPIO_Pin_13|GPIO_Pin_14; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; + GPIO_Init(GPIOB, &GPIO_InitStructure); + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_13; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; + GPIO_Init(GPIOC, &GPIO_InitStructure); + break; + } + case 0x103D0700: //CH32L103F8U6 + { + GPIO_PinRemapConfig(GPIO_Remap_PD01, ENABLE); + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_15; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; + GPIO_Init(GPIOA, &GPIO_InitStructure); + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_3\ + |GPIO_Pin_4|GPIO_Pin_5\ + |GPIO_Pin_8|GPIO_Pin_9\ + |GPIO_Pin_12; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; + GPIO_Init(GPIOB, &GPIO_InitStructure); + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPD; + GPIO_Init(GPIOB, &GPIO_InitStructure); + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_13|GPIO_Pin_14\ + |GPIO_Pin_15; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; + GPIO_Init(GPIOC, &GPIO_InitStructure); + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_1; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; + GPIO_Init(GPIOD, &GPIO_InitStructure); + break; + } + case 0x103B0700: //CH32L103G8R6 + { + GPIO_PinRemapConfig(GPIO_Remap_PD01, ENABLE); + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_15; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; + GPIO_Init(GPIOA, &GPIO_InitStructure); + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_4|GPIO_Pin_9; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; + GPIO_Init(GPIOB, &GPIO_InitStructure); + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPD; + GPIO_Init(GPIOB, &GPIO_InitStructure); + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_13|GPIO_Pin_14\ + |GPIO_Pin_15; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; + GPIO_Init(GPIOC, &GPIO_InitStructure); + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_1; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; + GPIO_Init(GPIOD, &GPIO_InitStructure); + break; + } + case 0x103A0700: //CH32L103F8P6 + { + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_8|GPIO_Pin_9\ + |GPIO_Pin_10|GPIO_Pin_15; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; + GPIO_Init(GPIOA, &GPIO_InitStructure); + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_3\ + |GPIO_Pin_4|GPIO_Pin_5\ + |GPIO_Pin_9|GPIO_Pin_10\ + |GPIO_Pin_11|GPIO_Pin_12\ + |GPIO_Pin_13|GPIO_Pin_14\ + |GPIO_Pin_15; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; + GPIO_Init(GPIOB, &GPIO_InitStructure); + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPD; + GPIO_Init(GPIOB, &GPIO_InitStructure); + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_13|GPIO_Pin_14\ + |GPIO_Pin_15; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; + GPIO_Init(GPIOC, &GPIO_InitStructure); + break; + } + case 0x10310700: //CH32L103C8T6 + { + break; + } + default: + { + break; + } + + } +} diff --git a/ZDBMS/BMS_MC/Peripheral/src/ch32l103_i2c.c b/ZDBMS/BMS_MC/Peripheral/src/ch32l103_i2c.c new file mode 100644 index 0000000..238badd --- /dev/null +++ b/ZDBMS/BMS_MC/Peripheral/src/ch32l103_i2c.c @@ -0,0 +1,1013 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32l103_i2c.c + * Author : WCH + * Version : V1.0.0 + * Date : 2024/01/19 + * Description : This file provides all the I2C firmware functions. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#include "ch32l103_i2c.h" +#include "ch32l103_rcc.h" + +/* I2C SPE mask */ +#define CTLR1_PE_Set ((uint16_t)0x0001) +#define CTLR1_PE_Reset ((uint16_t)0xFFFE) + +/* I2C START mask */ +#define CTLR1_START_Set ((uint16_t)0x0100) +#define CTLR1_START_Reset ((uint16_t)0xFEFF) + +/* I2C STOP mask */ +#define CTLR1_STOP_Set ((uint16_t)0x0200) +#define CTLR1_STOP_Reset ((uint16_t)0xFDFF) + +/* I2C ACK mask */ +#define CTLR1_ACK_Set ((uint16_t)0x0400) +#define CTLR1_ACK_Reset ((uint16_t)0xFBFF) + +/* I2C ENGC mask */ +#define CTLR1_ENGC_Set ((uint16_t)0x0040) +#define CTLR1_ENGC_Reset ((uint16_t)0xFFBF) + +/* I2C SWRST mask */ +#define CTLR1_SWRST_Set ((uint16_t)0x8000) +#define CTLR1_SWRST_Reset ((uint16_t)0x7FFF) + +/* I2C PEC mask */ +#define CTLR1_PEC_Set ((uint16_t)0x1000) +#define CTLR1_PEC_Reset ((uint16_t)0xEFFF) + +/* I2C ENPEC mask */ +#define CTLR1_ENPEC_Set ((uint16_t)0x0020) +#define CTLR1_ENPEC_Reset ((uint16_t)0xFFDF) + +/* I2C ENARP mask */ +#define CTLR1_ENARP_Set ((uint16_t)0x0010) +#define CTLR1_ENARP_Reset ((uint16_t)0xFFEF) + +/* I2C NOSTRETCH mask */ +#define CTLR1_NOSTRETCH_Set ((uint16_t)0x0080) +#define CTLR1_NOSTRETCH_Reset ((uint16_t)0xFF7F) + +/* I2C registers Masks */ +#define CTLR1_CLEAR_Mask ((uint16_t)0xFBF5) + +/* I2C DMAEN mask */ +#define CTLR2_DMAEN_Set ((uint16_t)0x0800) +#define CTLR2_DMAEN_Reset ((uint16_t)0xF7FF) + +/* I2C LAST mask */ +#define CTLR2_LAST_Set ((uint16_t)0x1000) +#define CTLR2_LAST_Reset ((uint16_t)0xEFFF) + +/* I2C FREQ mask */ +#define CTLR2_FREQ_Reset ((uint16_t)0xFFC0) + +/* I2C ADD0 mask */ +#define OADDR1_ADD0_Set ((uint16_t)0x0001) +#define OADDR1_ADD0_Reset ((uint16_t)0xFFFE) + +/* I2C ENDUAL mask */ +#define OADDR2_ENDUAL_Set ((uint16_t)0x0001) +#define OADDR2_ENDUAL_Reset ((uint16_t)0xFFFE) + +/* I2C ADD2 mask */ +#define OADDR2_ADD2_Reset ((uint16_t)0xFF01) + +/* I2C F/S mask */ +#define CKCFGR_FS_Set ((uint16_t)0x8000) + +/* I2C CCR mask */ +#define CKCFGR_CCR_Set ((uint16_t)0x0FFF) + +/* I2C FLAG mask */ +#define FLAG_Mask ((uint32_t)0x00FFFFFF) + +/* I2C Interrupt Enable mask */ +#define ITEN_Mask ((uint32_t)0x07000000) + +/********************************************************************* + * @fn I2C_DeInit + * + * @brief Deinitializes the I2Cx peripheral registers to their default + * reset values. + * + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * + * @return none + */ +void I2C_DeInit(I2C_TypeDef *I2Cx) +{ + if(I2Cx == I2C1) + { + RCC_PB1PeriphResetCmd(RCC_PB1Periph_I2C1, ENABLE); + RCC_PB1PeriphResetCmd(RCC_PB1Periph_I2C1, DISABLE); + } + else + { + RCC_PB1PeriphResetCmd(RCC_PB1Periph_I2C2, ENABLE); + RCC_PB1PeriphResetCmd(RCC_PB1Periph_I2C2, DISABLE); + } +} + +/********************************************************************* + * @fn I2C_Init + * + * @brief Initializes the I2Cx peripheral according to the specified + * parameters in the I2C_InitStruct. + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * I2C_InitStruct - pointer to a I2C_InitTypeDef structure that + * contains the configuration information for the specified I2C peripheral. + * + * @return none + */ +void I2C_Init(I2C_TypeDef *I2Cx, I2C_InitTypeDef *I2C_InitStruct) +{ + uint16_t tmpreg = 0, freqrange = 0; + uint16_t result = 0x04; + uint32_t pclk1 = 8000000; + + RCC_ClocksTypeDef rcc_clocks; + + tmpreg = I2Cx->CTLR2; + tmpreg &= CTLR2_FREQ_Reset; + RCC_GetClocksFreq(&rcc_clocks); + pclk1 = rcc_clocks.PCLK1_Frequency; + freqrange = (uint16_t)(pclk1 / 1000000); + if(freqrange > 60){ + freqrange =60; + } + tmpreg |= freqrange; + I2Cx->CTLR2 = tmpreg; + + I2Cx->CTLR1 &= CTLR1_PE_Reset; + tmpreg = 0; + + if(I2C_InitStruct->I2C_ClockSpeed <= 100000) + { + result = (uint16_t)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed << 1)); + + if(result < 0x04) + { + result = 0x04; + } + + tmpreg |= result; + I2Cx->RTR = freqrange + 1; + } + else + { + if(I2C_InitStruct->I2C_DutyCycle == I2C_DutyCycle_2) + { + result = (uint16_t)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed * 3)); + } + else + { + result = (uint16_t)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed * 25)); + result |= I2C_DutyCycle_16_9; + } + + if((result & CKCFGR_CCR_Set) == 0) + { + result |= (uint16_t)0x0001; + } + + tmpreg |= (uint16_t)(result | CKCFGR_FS_Set); + I2Cx->RTR = (uint16_t)(((freqrange * (uint16_t)300) / (uint16_t)1000) + (uint16_t)1); + } + + I2Cx->CKCFGR = tmpreg; + I2Cx->CTLR1 |= CTLR1_PE_Set; + + tmpreg = I2Cx->CTLR1; + tmpreg &= CTLR1_CLEAR_Mask; + tmpreg |= (uint16_t)((uint32_t)I2C_InitStruct->I2C_Mode | I2C_InitStruct->I2C_Ack); + I2Cx->CTLR1 = tmpreg; + + I2Cx->OADDR1 = (I2C_InitStruct->I2C_AcknowledgedAddress | I2C_InitStruct->I2C_OwnAddress1); +} + +/********************************************************************* + * @fn I2C_StructInit + * + * @brief Fills each I2C_InitStruct member with its default value. + * + * @param I2C_InitStruct - pointer to an I2C_InitTypeDef structure which + * will be initialized. + * + * @return none + */ +void I2C_StructInit(I2C_InitTypeDef *I2C_InitStruct) +{ + I2C_InitStruct->I2C_ClockSpeed = 5000; + I2C_InitStruct->I2C_Mode = I2C_Mode_I2C; + I2C_InitStruct->I2C_DutyCycle = I2C_DutyCycle_2; + I2C_InitStruct->I2C_OwnAddress1 = 0; + I2C_InitStruct->I2C_Ack = I2C_Ack_Disable; + I2C_InitStruct->I2C_AcknowledgedAddress = I2C_AcknowledgedAddress_7bit; +} + +/********************************************************************* + * @fn I2C_Cmd + * + * @brief Enables or disables the specified I2C peripheral. + * + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void I2C_Cmd(I2C_TypeDef *I2Cx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + I2Cx->CTLR1 |= CTLR1_PE_Set; + } + else + { + I2Cx->CTLR1 &= CTLR1_PE_Reset; + } +} + +/********************************************************************* + * @fn I2C_DMACmd + * + * @brief Enables or disables the specified I2C DMA requests. + * + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void I2C_DMACmd(I2C_TypeDef *I2Cx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + I2Cx->CTLR2 |= CTLR2_DMAEN_Set; + } + else + { + I2Cx->CTLR2 &= CTLR2_DMAEN_Reset; + } +} + +/********************************************************************* + * @fn I2C_DMALastTransferCmd + * + * @brief Specifies if the next DMA transfer will be the last one. + * + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void I2C_DMALastTransferCmd(I2C_TypeDef *I2Cx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + I2Cx->CTLR2 |= CTLR2_LAST_Set; + } + else + { + I2Cx->CTLR2 &= CTLR2_LAST_Reset; + } +} + +/********************************************************************* + * @fn I2C_GenerateSTART + * + * @brief Generates I2Cx communication START condition. + * + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void I2C_GenerateSTART(I2C_TypeDef *I2Cx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + I2Cx->CTLR1 |= CTLR1_START_Set; + } + else + { + I2Cx->CTLR1 &= CTLR1_START_Reset; + } +} + +/********************************************************************* + * @fn I2C_GenerateSTOP + * + * @brief Generates I2Cx communication STOP condition. + * + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void I2C_GenerateSTOP(I2C_TypeDef *I2Cx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + I2Cx->CTLR1 |= CTLR1_STOP_Set; + } + else + { + I2Cx->CTLR1 &= CTLR1_STOP_Reset; + } +} + +/********************************************************************* + * @fn I2C_AcknowledgeConfig + * + * @brief Enables or disables the specified I2C acknowledge feature. + * + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void I2C_AcknowledgeConfig(I2C_TypeDef *I2Cx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + I2Cx->CTLR1 |= CTLR1_ACK_Set; + } + else + { + I2Cx->CTLR1 &= CTLR1_ACK_Reset; + } +} + +/********************************************************************* + * @fn I2C_OwnAddress2Config + * + * @brief Configures the specified I2C own address2. + * + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * Address - specifies the 7bit I2C own address2. + * + * @return none + */ +void I2C_OwnAddress2Config(I2C_TypeDef *I2Cx, uint8_t Address) +{ + uint16_t tmpreg = 0; + + tmpreg = I2Cx->OADDR2; + tmpreg &= OADDR2_ADD2_Reset; + tmpreg |= (uint16_t)((uint16_t)Address & (uint16_t)0x00FE); + I2Cx->OADDR2 = tmpreg; +} + +/********************************************************************* + * @fn I2C_DualAddressCmd + * + * @brief Enables or disables the specified I2C dual addressing mode. + * + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void I2C_DualAddressCmd(I2C_TypeDef *I2Cx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + I2Cx->OADDR2 |= OADDR2_ENDUAL_Set; + } + else + { + I2Cx->OADDR2 &= OADDR2_ENDUAL_Reset; + } +} + +/********************************************************************* + * @fn I2C_GeneralCallCmd + * + * @brief Enables or disables the specified I2C general call feature. + * + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void I2C_GeneralCallCmd(I2C_TypeDef *I2Cx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + I2Cx->CTLR1 |= CTLR1_ENGC_Set; + } + else + { + I2Cx->CTLR1 &= CTLR1_ENGC_Reset; + } +} + +/********************************************************************* + * @fn I2C_ITConfig + * + * @brief Enables or disables the specified I2C interrupts. + * + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * I2C_IT - specifies the I2C interrupts sources to be enabled or disabled. + * I2C_IT_BUF - Buffer interrupt mask. + * I2C_IT_EVT - Event interrupt mask. + * I2C_IT_ERR - Error interrupt mask. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void I2C_ITConfig(I2C_TypeDef *I2Cx, uint16_t I2C_IT, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + I2Cx->CTLR2 |= I2C_IT; + } + else + { + I2Cx->CTLR2 &= (uint16_t)~I2C_IT; + } +} + +/********************************************************************* + * @fn I2C_SendData + * + * @brief Sends a data byte through the I2Cx peripheral. + * + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * Data - Byte to be transmitted. + * + * @return none + */ +void I2C_SendData(I2C_TypeDef *I2Cx, uint8_t Data) +{ + I2Cx->DATAR = Data; +} + +/********************************************************************* + * @fn I2C_ReceiveData + * + * @brief Returns the most recent received data by the I2Cx peripheral. + * + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * + * @return The value of the received data. + */ +uint8_t I2C_ReceiveData(I2C_TypeDef *I2Cx) +{ + return (uint8_t)I2Cx->DATAR; +} + +/********************************************************************* + * @fn I2C_Send7bitAddress + * + * @brief Transmits the address byte to select the slave device. + * + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * Address - specifies the slave address which will be transmitted. + * I2C_Direction - specifies whether the I2C device will be a + * Transmitter or a Receiver. + * I2C_Direction_Transmitter - Transmitter mode. + * I2C_Direction_Receiver - Receiver mode. + * + * @return none + */ +void I2C_Send7bitAddress(I2C_TypeDef *I2Cx, uint8_t Address, uint8_t I2C_Direction) +{ + if(I2C_Direction != I2C_Direction_Transmitter) + { + Address |= OADDR1_ADD0_Set; + } + else + { + Address &= OADDR1_ADD0_Reset; + } + + I2Cx->DATAR = Address; +} + +/********************************************************************* + * @fn I2C_ReadRegister + * + * @brief Reads the specified I2C register and returns its value. + * + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * I2C_Register - specifies the register to read. + * I2C_Register_CTLR1. + * I2C_Register_CTLR2. + * I2C_Register_OADDR1. + * I2C_Register_OADDR2. + * I2C_Register_DATAR. + * I2C_Register_STAR1. + * I2C_Register_STAR2. + * I2C_Register_CKCFGR. + * I2C_Register_RTR. + * + * @return none + */ +uint16_t I2C_ReadRegister(I2C_TypeDef *I2Cx, uint8_t I2C_Register) +{ + __IO uint32_t tmp = 0; + + tmp = (uint32_t)I2Cx; + tmp += I2C_Register; + + return (*(__IO uint16_t *)tmp); +} + +/********************************************************************* + * @fn I2C_SoftwareResetCmd + * + * @brief Enables or disables the specified I2C software reset. + * + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void I2C_SoftwareResetCmd(I2C_TypeDef *I2Cx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + I2Cx->CTLR1 |= CTLR1_SWRST_Set; + } + else + { + I2Cx->CTLR1 &= CTLR1_SWRST_Reset; + } +} + +/********************************************************************* + * @fn I2C_NACKPositionConfig + * + * @brief Selects the specified I2C NACK position in master receiver mode. + * + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * I2C_NACKPosition - specifies the NACK position. + * I2C_NACKPosition_Next - indicates that the next byte will be + * the last received byte. + * I2C_NACKPosition_Current - indicates that current byte is the + * last received byte. + * Note- + * This function configures the same bit (POS) as I2C_PECPositionConfig() + * but is intended to be used in I2C mode while I2C_PECPositionConfig() + * is intended to used in SMBUS mode. + * + * @return none + */ +void I2C_NACKPositionConfig(I2C_TypeDef *I2Cx, uint16_t I2C_NACKPosition) +{ + if(I2C_NACKPosition == I2C_NACKPosition_Next) + { + I2Cx->CTLR1 |= I2C_NACKPosition_Next; + } + else + { + I2Cx->CTLR1 &= I2C_NACKPosition_Current; + } +} + +/********************************************************************* + * @fn I2C_SMBusAlertConfig + * + * @brief Drives the SMBusAlert pin high or low for the specified I2C. + * + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * I2C_SMBusAlert - specifies SMBAlert pin level. + * I2C_SMBusAlert_Low - SMBAlert pin driven low. + * I2C_SMBusAlert_High - SMBAlert pin driven high. + * + * @return none + */ +void I2C_SMBusAlertConfig(I2C_TypeDef *I2Cx, uint16_t I2C_SMBusAlert) +{ + if(I2C_SMBusAlert == I2C_SMBusAlert_Low) + { + I2Cx->CTLR1 |= I2C_SMBusAlert_Low; + } + else + { + I2Cx->CTLR1 &= I2C_SMBusAlert_High; + } +} + +/********************************************************************* + * @fn I2C_TransmitPEC + * + * @brief Enables or disables the specified I2C PEC transfer. + * + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void I2C_TransmitPEC(I2C_TypeDef *I2Cx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + I2Cx->CTLR1 |= CTLR1_PEC_Set; + } + else + { + I2Cx->CTLR1 &= CTLR1_PEC_Reset; + } +} + +/********************************************************************* + * @fn I2C_PECPositionConfig + * + * @brief Selects the specified I2C PEC position. + * + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * I2C_PECPosition - specifies the PEC position. + * I2C_PECPosition_Next - indicates that the next byte is PEC. + * I2C_PECPosition_Current - indicates that current byte is PEC. + * + * @return none + */ +void I2C_PECPositionConfig(I2C_TypeDef *I2Cx, uint16_t I2C_PECPosition) +{ + if(I2C_PECPosition == I2C_PECPosition_Next) + { + I2Cx->CTLR1 |= I2C_PECPosition_Next; + } + else + { + I2Cx->CTLR1 &= I2C_PECPosition_Current; + } +} + +/********************************************************************* + * @fn I2C_CalculatePEC + * + * @brief Enables or disables the PEC value calculation of the transferred bytes. + * + * @param I2Cx- where x can be 1 or 2 to select the I2C peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void I2C_CalculatePEC(I2C_TypeDef *I2Cx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + I2Cx->CTLR1 |= CTLR1_ENPEC_Set; + } + else + { + I2Cx->CTLR1 &= CTLR1_ENPEC_Reset; + } +} + +/********************************************************************* + * @fn I2C_GetPEC + * + * @brief Returns the PEC value for the specified I2C. + * + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * + * @return The PEC value. + */ +uint8_t I2C_GetPEC(I2C_TypeDef *I2Cx) +{ + return ((I2Cx->STAR2) >> 8); +} + +/********************************************************************* + * @fn I2C_ARPCmd + * + * @brief Enables or disables the specified I2C ARP. + * + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * NewState - ENABLE or DISABLE. + * + * @return The PEC value. + */ +void I2C_ARPCmd(I2C_TypeDef *I2Cx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + I2Cx->CTLR1 |= CTLR1_ENARP_Set; + } + else + { + I2Cx->CTLR1 &= CTLR1_ENARP_Reset; + } +} + +/********************************************************************* + * @fn I2C_StretchClockCmd + * + * @brief Enables or disables the specified I2C Clock stretching. + * + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void I2C_StretchClockCmd(I2C_TypeDef *I2Cx, FunctionalState NewState) +{ + if(NewState == DISABLE) + { + I2Cx->CTLR1 |= CTLR1_NOSTRETCH_Set; + } + else + { + I2Cx->CTLR1 &= CTLR1_NOSTRETCH_Reset; + } +} + +/********************************************************************* + * @fn I2C_FastModeDutyCycleConfig + * + * @brief Selects the specified I2C fast mode duty cycle. + * + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * I2C_DutyCycle - specifies the fast mode duty cycle. + * I2C_DutyCycle_2 - I2C fast mode Tlow/Thigh = 2. + * I2C_DutyCycle_16_9 - I2C fast mode Tlow/Thigh = 16/9. + * + * @return none + */ +void I2C_FastModeDutyCycleConfig(I2C_TypeDef *I2Cx, uint16_t I2C_DutyCycle) +{ + if(I2C_DutyCycle != I2C_DutyCycle_16_9) + { + I2Cx->CKCFGR &= I2C_DutyCycle_2; + } + else + { + I2Cx->CKCFGR |= I2C_DutyCycle_16_9; + } +} + +/********************************************************************* + * @fn I2C_CheckEvent + * + * @brief Checks whether the last I2Cx Event is equal to the one passed + * as parameter. + * + * @param I2Cx- where x can be 1 or 2 to select the I2C peripheral. + * I2C_EVENT: specifies the event to be checked. + * I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED - EVT1. + * I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED - EVT1. + * I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED - EVT1. + * I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED - EVT1. + * I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED - EVT1. + * I2C_EVENT_SLAVE_BYTE_RECEIVED - EVT2. + * (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_DUALF) - EVT2. + * (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_GENCALL) - EVT2. + * I2C_EVENT_SLAVE_BYTE_TRANSMITTED - EVT3. + * (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_DUALF) - EVT3. + * (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_GENCALL) - EVT3. + * I2C_EVENT_SLAVE_ACK_FAILURE - EVT3_2. + * I2C_EVENT_SLAVE_STOP_DETECTED - EVT4. + * I2C_EVENT_MASTER_MODE_SELECT - EVT5. + * I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED - EVT6. + * I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED - EVT6. + * I2C_EVENT_MASTER_BYTE_RECEIVED - EVT7. + * I2C_EVENT_MASTER_BYTE_TRANSMITTING - EVT8. + * I2C_EVENT_MASTER_BYTE_TRANSMITTED - EVT8_2. + * I2C_EVENT_MASTER_MODE_ADDRESS10 - EVT9. + * + * @return ErrorStatus - READY or NoREADY. + */ +ErrorStatus I2C_CheckEvent(I2C_TypeDef *I2Cx, uint32_t I2C_EVENT) +{ + uint32_t lastevent = 0; + uint32_t flag1 = 0, flag2 = 0; + ErrorStatus status = NoREADY; + + flag1 = I2Cx->STAR1; + flag2 = I2Cx->STAR2; + flag2 = flag2 << 16; + + lastevent = (flag1 | flag2) & FLAG_Mask; + + if((lastevent & I2C_EVENT) == I2C_EVENT) + { + status = READY; + } + else + { + status = NoREADY; + } + + return status; +} + +/********************************************************************* + * @fn I2C_GetLastEvent + * + * @brief Returns the last I2Cx Event. + * + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * + * @return none + */ +uint32_t I2C_GetLastEvent(I2C_TypeDef *I2Cx) +{ + uint32_t lastevent = 0; + uint32_t flag1 = 0, flag2 = 0; + + flag1 = I2Cx->STAR1; + flag2 = I2Cx->STAR2; + flag2 = flag2 << 16; + lastevent = (flag1 | flag2) & FLAG_Mask; + + return lastevent; +} + +/********************************************************************* + * @fn I2C_GetFlagStatus + * + * @brief Checks whether the last I2Cx Event is equal to the one passed + * as parameter. + * + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * I2C_FLAG - specifies the flag to check. + * I2C_FLAG_DUALF - Dual flag (Slave mode). + * I2C_FLAG_SMBHOST - SMBus host header (Slave mode). + * I2C_FLAG_SMBDEFAULT - SMBus default header (Slave mode). + * I2C_FLAG_GENCALL - General call header flag (Slave mode). + * I2C_FLAG_TRA - Transmitter/Receiver flag. + * I2C_FLAG_BUSY - Bus busy flag. + * I2C_FLAG_MSL - Master/Slave flag. + * I2C_FLAG_SMBALERT - SMBus Alert flag. + * I2C_FLAG_TIMEOUT - Timeout or Tlow error flag. + * I2C_FLAG_PECERR - PEC error in reception flag. + * I2C_FLAG_OVR - Overrun/Underrun flag (Slave mode). + * I2C_FLAG_AF - Acknowledge failure flag. + * I2C_FLAG_ARLO - Arbitration lost flag (Master mode). + * I2C_FLAG_BERR - Bus error flag. + * I2C_FLAG_TXE - Data register empty flag (Transmitter). + * I2C_FLAG_RXNE- Data register not empty (Receiver) flag. + * I2C_FLAG_STOPF - Stop detection flag (Slave mode). + * I2C_FLAG_ADD10 - 10-bit header sent flag (Master mode). + * I2C_FLAG_BTF - Byte transfer finished flag. + * I2C_FLAG_ADDR - Address sent flag (Master mode) "ADSL" + * Address matched flag (Slave mode)"ENDA". + * I2C_FLAG_SB - Start bit flag (Master mode). + * + * @return FlagStatus - SET or RESET. + */ +FlagStatus I2C_GetFlagStatus(I2C_TypeDef *I2Cx, uint32_t I2C_FLAG) +{ + FlagStatus bitstatus = RESET; + __IO uint32_t i2creg = 0, i2cxbase = 0; + + i2cxbase = (uint32_t)I2Cx; + i2creg = I2C_FLAG >> 28; + I2C_FLAG &= FLAG_Mask; + + if(i2creg != 0) + { + i2cxbase += 0x14; + } + else + { + I2C_FLAG = (uint32_t)(I2C_FLAG >> 16); + i2cxbase += 0x18; + } + + if(((*(__IO uint32_t *)i2cxbase) & I2C_FLAG) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn I2C_ClearFlag + * + * @brief Clears the I2Cx's pending flags. + * + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * I2C_FLAG - specifies the flag to clear. + * I2C_FLAG_SMBALERT - SMBus Alert flag. + * I2C_FLAG_TIMEOUT - Timeout or Tlow error flag. + * I2C_FLAG_PECERR - PEC error in reception flag. + * I2C_FLAG_OVR - Overrun/Underrun flag (Slave mode). + * I2C_FLAG_AF - Acknowledge failure flag. + * I2C_FLAG_ARLO - Arbitration lost flag (Master mode). + * I2C_FLAG_BERR - Bus error flag. + * Note- + * - STOPF (STOP detection) is cleared by software sequence: a read operation + * to I2C_STAR1 register (I2C_GetFlagStatus()) followed by a write operation + * to I2C_CTLR1 register (I2C_Cmd() to re-enable the I2C peripheral). + * - ADD10 (10-bit header sent) is cleared by software sequence: a read + * operation to I2C_SATR1 (I2C_GetFlagStatus()) followed by writing the + * second byte of the address in DATAR register. + * - BTF (Byte Transfer Finished) is cleared by software sequence: a read + * operation to I2C_SATR1 register (I2C_GetFlagStatus()) followed by a + * read/write to I2C_DATAR register (I2C_SendData()). + * - ADDR (Address sent) is cleared by software sequence: a read operation to + * I2C_SATR1 register (I2C_GetFlagStatus()) followed by a read operation to + * I2C_SATR2 register ((void)(I2Cx->STAR2)). + * - SB (Start Bit) is cleared software sequence: a read operation to I2C_STAR1 + * register (I2C_GetFlagStatus()) followed by a write operation to I2C_DATAR + * register (I2C_SendData()). + * + * @return none + */ +void I2C_ClearFlag(I2C_TypeDef *I2Cx, uint32_t I2C_FLAG) +{ + uint32_t flagpos = 0; + + flagpos = I2C_FLAG & FLAG_Mask; + I2Cx->STAR1 = (uint16_t)~flagpos; +} + +/********************************************************************* + * @fn I2C_GetITStatus + * + * @brief Checks whether the specified I2C interrupt has occurred or not. + * + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * II2C_IT - specifies the interrupt source to check. + * I2C_IT_SMBALERT - SMBus Alert flag. + * I2C_IT_TIMEOUT - Timeout or Tlow error flag. + * I2C_IT_PECERR - PEC error in reception flag. + * I2C_IT_OVR - Overrun/Underrun flag (Slave mode). + * I2C_IT_AF - Acknowledge failure flag. + * I2C_IT_ARLO - Arbitration lost flag (Master mode). + * I2C_IT_BERR - Bus error flag. + * I2C_IT_TXE - Data register empty flag (Transmitter). + * I2C_IT_RXNE - Data register not empty (Receiver) flag. + * I2C_IT_STOPF - Stop detection flag (Slave mode). + * I2C_IT_ADD10 - 10-bit header sent flag (Master mode). + * I2C_IT_BTF - Byte transfer finished flag. + * I2C_IT_ADDR - Address sent flag (Master mode) "ADSL" Address matched + * flag (Slave mode)"ENDAD". + * I2C_IT_SB - Start bit flag (Master mode). + * + * @return none + */ +ITStatus I2C_GetITStatus(I2C_TypeDef *I2Cx, uint32_t I2C_IT) +{ + ITStatus bitstatus = RESET; + uint32_t enablestatus = 0; + + enablestatus = (uint32_t)(((I2C_IT & ITEN_Mask) >> 16) & (I2Cx->CTLR2)); + I2C_IT &= FLAG_Mask; + + if(((I2Cx->STAR1 & I2C_IT) != (uint32_t)RESET) && enablestatus) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn I2C_ClearITPendingBit + * + * @brief Clears the I2Cx interrupt pending bits. + * + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * I2C_IT - specifies the interrupt pending bit to clear. + * I2C_IT_SMBALERT - SMBus Alert interrupt. + * I2C_IT_TIMEOUT - Timeout or Tlow error interrupt. + * I2C_IT_PECERR - PEC error in reception interrupt. + * I2C_IT_OVR - Overrun/Underrun interrupt (Slave mode). + * I2C_IT_AF - Acknowledge failure interrupt. + * I2C_IT_ARLO - Arbitration lost interrupt (Master mode). + * I2C_IT_BERR - Bus error interrupt. + * Note- + * - STOPF (STOP detection) is cleared by software sequence: a read operation + * to I2C_STAR1 register (I2C_GetITStatus()) followed by a write operation to + * I2C_CTLR1 register (I2C_Cmd() to re-enable the I2C peripheral). + * - ADD10 (10-bit header sent) is cleared by software sequence: a read + * operation to I2C_STAR1 (I2C_GetITStatus()) followed by writing the second + * byte of the address in I2C_DATAR register. + * - BTF (Byte Transfer Finished) is cleared by software sequence: a read + * operation to I2C_STAR1 register (I2C_GetITStatus()) followed by a + * read/write to I2C_DATAR register (I2C_SendData()). + * - ADDR (Address sent) is cleared by software sequence: a read operation to + * I2C_STAR1 register (I2C_GetITStatus()) followed by a read operation to + * I2C_STAR2 register ((void)(I2Cx->STAR2)). + * - SB (Start Bit) is cleared by software sequence: a read operation to + * I2C_STAR1 register (I2C_GetITStatus()) followed by a write operation to + * I2C_DATAR register (I2C_SendData()). + * + * @return none + */ +void I2C_ClearITPendingBit(I2C_TypeDef *I2Cx, uint32_t I2C_IT) +{ + uint32_t flagpos = 0; + + flagpos = I2C_IT & FLAG_Mask; + I2Cx->STAR1 = (uint16_t)~flagpos; +} diff --git a/ZDBMS/BMS_MC/Peripheral/src/ch32l103_iwdg.c b/ZDBMS/BMS_MC/Peripheral/src/ch32l103_iwdg.c new file mode 100644 index 0000000..4779397 --- /dev/null +++ b/ZDBMS/BMS_MC/Peripheral/src/ch32l103_iwdg.c @@ -0,0 +1,123 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32l103_iwdg.c + * Author : WCH + * Version : V1.0.0 + * Date : 2024/03/26 + * Description : This file provides all the IWDG firmware functions. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#include "ch32l103_iwdg.h" + +/* CTLR register bit mask */ +#define CTLR_KEY_Reload ((uint16_t)0xAAAA) +#define CTLR_KEY_Enable ((uint16_t)0xCCCC) + +/********************************************************************* + * @fn IWDG_WriteAccessCmd + * + * @brief Enables or disables write access to IWDG_PSCR and IWDG_RLDR registers. + * + * @param WDG_WriteAccess - new state of write access to IWDG_PSCR and + * IWDG_RLDR registers. + * IWDG_WriteAccess_Enable - Enable write access to IWDG_PSCR and + * IWDG_RLDR registers. + * IWDG_WriteAccess_Disable - Disable write access to IWDG_PSCR + * and IWDG_RLDR registers. + * + * @return none + */ +void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess) +{ + IWDG->CTLR = IWDG_WriteAccess; +} + +/********************************************************************* + * @fn IWDG_SetPrescaler + * + * @brief Sets IWDG Prescaler value. + * + * @param IWDG_Prescaler - specifies the IWDG Prescaler value. + * IWDG_Prescaler_4 - IWDG prescaler set to 4. + * IWDG_Prescaler_8 - IWDG prescaler set to 8. + * IWDG_Prescaler_16 - IWDG prescaler set to 16. + * IWDG_Prescaler_32 - IWDG prescaler set to 32. + * IWDG_Prescaler_64 - IWDG prescaler set to 64. + * IWDG_Prescaler_128 - IWDG prescaler set to 128. + * IWDG_Prescaler_256 - IWDG prescaler set to 256. + * + * @return none + */ +void IWDG_SetPrescaler(uint8_t IWDG_Prescaler) +{ + IWDG->PSCR = IWDG_Prescaler; +} + +/********************************************************************* + * @fn IWDG_SetReload + * + * @brief Sets IWDG Reload value. + * + * @param Reload - specifies the IWDG Reload value. + * This parameter must be a number between 0 and 0x0FFF. + * + * @return none + */ +void IWDG_SetReload(uint16_t Reload) +{ + IWDG->RLDR = Reload; +} + +/********************************************************************* + * @fn IWDG_ReloadCounter + * + * @brief Reloads IWDG counter with value defined in the reload register. + * + * @return none + */ +void IWDG_ReloadCounter(void) +{ + IWDG->CTLR = CTLR_KEY_Reload; +} + +/********************************************************************* + * @fn IWDG_Enable + * + * @brief Enables IWDG (write access to IWDG_PSCR and IWDG_RLDR registers disabled). + * + * @return none + */ +void IWDG_Enable(void) +{ + IWDG->CTLR = CTLR_KEY_Enable; + while((RCC->RSTSCKR & 0x2) == RESET); +} + +/********************************************************************* + * @fn IWDG_GetFlagStatus + * + * @brief Checks whether the specified IWDG flag is set or not. + * + * @param IWDG_FLAG - specifies the flag to check. + * IWDG_FLAG_PVU - Prescaler Value Update on going. + * IWDG_FLAG_RVU - Reload Value Update on going. + * + * @return none + */ +FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG) +{ + FlagStatus bitstatus = RESET; + + if((IWDG->STATR & IWDG_FLAG) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} diff --git a/ZDBMS/BMS_MC/Peripheral/src/ch32l103_lptim.c b/ZDBMS/BMS_MC/Peripheral/src/ch32l103_lptim.c new file mode 100644 index 0000000..27597a7 --- /dev/null +++ b/ZDBMS/BMS_MC/Peripheral/src/ch32l103_lptim.c @@ -0,0 +1,363 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32l103_lptim.c + * Author : WCH + * Version : V1.0.0 + * Date : 2024/08/29 + * Description : This file provides all the TIM firmware functions. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#include "ch32l103_lptim.h" +#include "ch32l103_rcc.h" + + +/********************************************************************* + * @fn LPTIM_DeInit + * + * @brief Deinitializes the LPTIM peripheral registers to their default + * reset values. + * + * @param none + * + * @return none + */ +void LPTIM_DeInit(void) +{ + RCC_PB1PeriphResetCmd(RCC_PB1Periph_LPTIM, ENABLE); + RCC_PB1PeriphResetCmd(RCC_PB1Periph_LPTIM, DISABLE); +} + +/********************************************************************* + * @fn LPTIM_TimeBaseInit + * + * @brief Initializes the LPTIM Time Base Unit peripheral according to + * the specified parameters in the LPTIM_TimeBaseInitStruct. + * + * @param LPTIM_TimeBaseInitStruct - pointer to a LPTIM_TimeBaseInitTypeDef + * structure. + * + * @return none + */ +void LPTIM_TimeBaseInit(LPTIM_TimeBaseInitTypeDef *LPTIM_TimeBaseInitStruct) +{ + uint32_t temp1 = 0, temp2 = 0; + + temp2 = (LPTIM->CR & 0x00000001); + + if(LPTIM_TimeBaseInitStruct->LPTIM_Encoder == ENABLE) + { + temp1 |= LPTIM_TimeBaseInitStruct->LPTIM_EncoderMode; + } + else + { + temp1 |= LPTIM_TimeBaseInitStruct->LPTIM_ClockPolarity; + } + + temp1 |= LPTIM_TimeBaseInitStruct->LPTIM_ClockSource | LPTIM_TimeBaseInitStruct->LPTIM_ClockSampleTime \ + | LPTIM_TimeBaseInitStruct->LPTIM_TriggerSampleTime | LPTIM_TimeBaseInitStruct->LPTIM_ClockPrescaler \ + | LPTIM_TimeBaseInitStruct->LPTIM_TriggerSource | LPTIM_TimeBaseInitStruct->LPTIM_ExTriggerPolarity \ + | LPTIM_TimeBaseInitStruct->LPTIM_OutputPolarity | LPTIM_TimeBaseInitStruct->LPTIM_UpdateMode \ + | LPTIM_TimeBaseInitStruct->LPTIM_CountSource | LPTIM_TimeBaseInitStruct->LPTIM_InClockSource \ + | (LPTIM_TimeBaseInitStruct->LPTIM_TimeOut << 19) | (LPTIM_TimeBaseInitStruct->LPTIM_OnePulseMode << 20) \ + | (LPTIM_TimeBaseInitStruct->LPTIM_Encoder << 24) | (LPTIM_TimeBaseInitStruct->LPTIM_ForceOutHigh << 27); + + temp2 |= (LPTIM_TimeBaseInitStruct->LPTIM_SingleMode << 1) | (LPTIM_TimeBaseInitStruct->LPTIM_ContinuousMode << 2) \ + | (LPTIM_TimeBaseInitStruct->LPTIM_PWMOut << 3) | (LPTIM_TimeBaseInitStruct->LPTIM_CounterDirIndicat << 4); + + LPTIM->CFGR = temp1; + LPTIM->CR = temp2; + LPTIM->CMP = LPTIM_TimeBaseInitStruct->LPTIM_Pulse; + LPTIM->ARR = LPTIM_TimeBaseInitStruct->LPTIM_Period; +} + +/********************************************************************* + * @fn LPTIM_TimeBaseStructInit + * + * @brief Fills each LPTIM_TimeBaseInitStruct member with its default value. + * + * @param TIM_TimeBaseInitStruct - pointer to a LPTIM_TimeBaseInitTypeDef structure. + * + * @return none + */ +void LPTIM_TimeBaseStructInit(LPTIM_TimeBaseInitTypeDef *LPTIM_TimeBaseInitStruct) +{ + LPTIM_TimeBaseInitStruct->LPTIM_ClockSource = LPTIM_ClockSource_In; + LPTIM_TimeBaseInitStruct->LPTIM_ClockPolarity = LPTIM_ClockPolarity_Rising; + LPTIM_TimeBaseInitStruct->LPTIM_ClockSampleTime = LPTIM_ClockSampleTime_0T; + LPTIM_TimeBaseInitStruct->LPTIM_TriggerSampleTime = LPTIM_TriggerSampleTime_0T; + LPTIM_TimeBaseInitStruct->LPTIM_ClockPrescaler = LPTIM_TClockPrescaler_DIV1; + LPTIM_TimeBaseInitStruct->LPTIM_TriggerSource = LPTIM_TriggerSource_ETR; + LPTIM_TimeBaseInitStruct->LPTIM_ExTriggerPolarity = LPTIM_ExTriggerPolarity_Disable; + LPTIM_TimeBaseInitStruct->LPTIM_TimeOut = DISABLE; + LPTIM_TimeBaseInitStruct->LPTIM_OnePulseMode = DISABLE; + LPTIM_TimeBaseInitStruct->LPTIM_OutputPolarity = LPTIM_OutputPolarity_High; + LPTIM_TimeBaseInitStruct->LPTIM_UpdateMode = LPTIM_UpdateMode0; + LPTIM_TimeBaseInitStruct->LPTIM_CountSource = LPTIM_CountSource_Internal; + LPTIM_TimeBaseInitStruct->LPTIM_Encoder = DISABLE; + LPTIM_TimeBaseInitStruct->LPTIM_InClockSource = LPTIM_InClockSource_PCLK1; + LPTIM_TimeBaseInitStruct->LPTIM_ForceOutHigh = DISABLE; + LPTIM_TimeBaseInitStruct->LPTIM_SingleMode = DISABLE; + LPTIM_TimeBaseInitStruct->LPTIM_ContinuousMode = DISABLE; + LPTIM_TimeBaseInitStruct->LPTIM_PWMOut = DISABLE; + LPTIM_TimeBaseInitStruct->LPTIM_CounterDirIndicat = DISABLE; + LPTIM_TimeBaseInitStruct->LPTIM_Pulse = 0; + LPTIM_TimeBaseInitStruct->LPTIM_Period = 0x0001; +} + +/********************************************************************* + * @fn LPTIM_CounterDirIndicat_Cmd + * + * @brief Enable or Disable counter direction indicate function. + * + * @param NewState - ENABLE or DISABLE. + * + * @return none + */ +void LPTIM_CounterDirIndicat_Cmd(FunctionalState NewState) +{ + if(NewState) + { + LPTIM->CR |= (1<<3); + } + else{ + LPTIM->CR &= ~(1<<3); + } +} + +/********************************************************************* + * @fn LPTIM_OutCmd + * + * @brief Enable or Disable PWM out function. + * + * @param NewState - ENABLE or DISABLE. + * + * @return none + */ +void LPTIM_OutCmd(FunctionalState NewState) +{ + if(NewState) + { + LPTIM->CR |= (1<<3); + } + else{ + LPTIM->CR &= ~(1<<3); + } +} + +/********************************************************************* + * @fn LPTIM_Cmd + * + * @brief Enable or Disable LPTIM. + * + * @param NewState - ENABLE or DISABLE. + * + * @return none + */ +void LPTIM_Cmd(FunctionalState NewState) +{ + if(NewState) + { + LPTIM->CR |= (1<<0); + } + else{ + LPTIM->CR &= ~(1<<0); + } +} + +/********************************************************************* + * @fn LPTIM_GetCounter + * + * @brief Gets the LPTIM Counter value. + * + * @param none + * + * @return LPTIM->CNT - Counter Register value. + */ +uint16_t LPTIM_GetCounter(void) +{ + return LPTIM->CNT; +} + +/********************************************************************* + * @fn LPTIM_SetAutoreload + * + * @brief Sets the LPTIM Autoreload Register value. + * + * @param Autoreload - specifies the Autoreload register new value. + * + * @return none + */ +void LPTIM_SetAutoreload(uint16_t Autoreload) +{ + LPTIM->ARR = Autoreload; +} + +/********************************************************************* + * @fn LPTIM_SetCompare + * + * @brief Sets the LPTIM Capture Compare Register value. + * + * @param Compare - specifies the Capture Compare1 register new value. + * + * @return none + */ +void LPTIM_SetCompare(uint16_t Compare) +{ + LPTIM->CMP = Compare; +} + +/********************************************************************* + * @fn LPTIM_GetCapture + * + * @brief Gets the LPTIM Input Capture value. + * + * @param none + * + * @return LPTIM->CMP - Capture Compare Register value. + */ +uint16_t LPTIM_GetCapture(void) +{ + return LPTIM->CMP; +} + +/********************************************************************* + * @fn LPTIM_ITConfig + * + * @brief Enables or disables the specified LPTIM interrupts. + * + * @param LPTIM_IT - specifies the LPTIM interrupts sources to be enabled or disabled. + * LPTIM_IT_DOWN - LPTIM counter down Interrupt source. + * LPTIM_IT_UP - LPTIM counter up Interrupt source. + * LPTIM_IT_ARROK - LPTIM be loaded success Interrupt source. + * LPTIM_IT_CMPOK - LPTIM Capture Compare success Interrupt source. + * LPTIM_IT_EXTTRIG - TIM Trigger Interrupt source. + * LPTIM_IT_ARRM - TIM counter Count to ARR register Interrupt source. + * LPTIM_IT_CMPM - TIM counter Count to CMP register Interrupt source. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void LPTIM_ITConfig(uint32_t LPTIM_IT, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + LPTIM->IER |= LPTIM_IT; + } + else + { + LPTIM->IER &= (uint32_t)~LPTIM_IT; + } +} + +/********************************************************************* + * @fn LPTIM_GetFlagStatus + * + * @brief Checks whether the specified LPTIM flag is set or not. + * + * @param LPTIM_FLAG - specifies the flag to check. + * LPTIM_FLAG_DIR_SYNC - LPTIM counter direction indicate Flag. + * LPTIM_FLAG_DOWN - LPTIM counter down Flag. + * LPTIM_FLAG_UP - LPTIM counter up Flag. + * LPTIM_FLAG_ARROK - LPTIM be loaded success Flag. + * LPTIM_FLAG_CMPOK - LPTIM Capture Compare success Flag. + * LPTIM_FLAG_EXTTRIG - TIM Trigger Flag. + * LPTIM_FLAG_ARRM - TIM counter Count to ARR register Flag. + * LPTIM_FLAG_CMPM - TIM counter Count to CMP register Flag. + * + * @return none + */ +FlagStatus LPTIM_GetFlagStatus(uint32_t LPTIM_FLAG) +{ + FlagStatus bitstatus = RESET; + + if((LPTIM->ISR & LPTIM_FLAG) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn LPTIM_ClearFlag + * + * @brief Clears the LPTIM's pending flags. + * + * @param LPTIM_FLAG - specifies the flag to check. + * LPTIM_FLAG_DOWN - LPTIM counter down Flag. + * LPTIM_FLAG_UP - LPTIM counter up Flag. + * LPTIM_FLAG_ARROK - LPTIM be loaded success Flag. + * LPTIM_FLAG_CMPOK - LPTIM Capture Compare success Flag. + * LPTIM_FLAG_EXTTRIG - TIM Trigger Flag. + * LPTIM_FLAG_ARRM - TIM counter Count to ARR register Flag. + * LPTIM_FLAG_CMPM - TIM counter Count to CMP register Flag. + * + * @return none + */ +void LPTIM_ClearFlag(uint32_t LPTIM_FLAG) +{ + LPTIM->ICR |= (uint32_t)LPTIM_FLAG; +} + +/********************************************************************* + * @fn LPTIM_GetITStatus + * + * @brief Checks whether the LPTIM interrupt has occurred or not. + * + * @param LPTIM_IT - specifies the LPTIM interrupt source to check. + * LPTIM_FLAG_DIR_SYNC - LPTIM counter direction indicate Interrupt source. + * LPTIM_IT_DOWN - LPTIM counter down Interrupt source. + * LPTIM_IT_UP - LPTIM counter up Interrupt source. + * LPTIM_IT_ARROK - LPTIM be loaded success Interrupt source. + * LPTIM_IT_CMPOK - LPTIM Capture Compare success Interrupt source. + * LPTIM_IT_EXTTRIG - TIM Trigger Interrupt source. + * LPTIM_IT_ARRM - TIM counter Count to ARR register Interrupt source. + * LPTIM_IT_CMPM - TIM counter Count to CMP register Interrupt source. + * + * @return none + */ +ITStatus LPTIM_GetITStatus(uint32_t LPTIM_IT) +{ + ITStatus bitstatus = RESET; + + if((LPTIM->ISR & LPTIM_IT) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn LPTIM_ClearITPendingBit + * + * @brief Clears the LPTIM's interrupt pending bits. + * + * @param LPTIM_IT - specifies the LPTIM interrupt source to check. + * LPTIM_IT_DOWN - LPTIM counter down Interrupt source. + * LPTIM_IT_UP - LPTIM counter up Interrupt source. + * LPTIM_IT_ARROK - LPTIM be loaded success Interrupt source. + * LPTIM_IT_CMPOK - LPTIM Capture Compare success Interrupt source. + * LPTIM_IT_EXTTRIG - TIM Trigger Interrupt source. + * LPTIM_IT_ARRM - TIM counter Count to ARR register Interrupt source. + * LPTIM_IT_CMPM - TIM counter Count to CMP register Interrupt source. + * + * @return none + */ +void LPTIM_ClearITPendingBit(uint32_t LPTIM_IT) +{ + LPTIM->ICR |= (uint32_t)LPTIM_IT; +} + + + diff --git a/ZDBMS/BMS_MC/Peripheral/src/ch32l103_misc.c b/ZDBMS/BMS_MC/Peripheral/src/ch32l103_misc.c new file mode 100644 index 0000000..498f247 --- /dev/null +++ b/ZDBMS/BMS_MC/Peripheral/src/ch32l103_misc.c @@ -0,0 +1,81 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32l103_misc.c + * Author : WCH + * Version : V1.0.0 + * Date : 2023/12/26 + * Description : This file provides all the miscellaneous firmware functions . + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#include "ch32l103_misc.h" + +__IO uint32_t NVIC_Priority_Group = 0; + +/********************************************************************* + * @fn NVIC_PriorityGroupConfig + * + * @brief Configures the priority grouping - pre-emption priority and subpriority. + * + * @param NVIC_PriorityGroup - specifies the priority grouping bits length. + * NVIC_PriorityGroup_0 - 0 bits for pre-emption priority + * 3 bits for subpriority + * NVIC_PriorityGroup_1 - 1 bits for pre-emption priority + * 2 bits for subpriority + * + * @return none + */ +void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup) +{ + NVIC_Priority_Group = NVIC_PriorityGroup; +} + +/********************************************************************* + * @fn NVIC_Init + * + * @brief Initializes the NVIC peripheral according to the specified parameters in + * the NVIC_InitStruct. + * + * @param NVIC_InitStruct - pointer to a NVIC_InitTypeDef structure that contains the + * configuration information for the specified NVIC peripheral. + * interrupt nesting enable(CSR-0x804 bit1 = 1) + * NVIC_IRQChannelPreemptionPriority - range from 0 to 1. + * NVIC_IRQChannelSubPriority - range from 0 to 3. + * + * interrupt nesting disable(CSR-0x804 bit1 = 0) + * NVIC_IRQChannelPreemptionPriority - range is 0. + * NVIC_IRQChannelSubPriority - range from 0 to 7. + * + * @return none + */ +void NVIC_Init(NVIC_InitTypeDef *NVIC_InitStruct) +{ +#if (INTSYSCR_INEST == INTSYSCR_INEST_NoEN) + if(NVIC_Priority_Group == NVIC_PriorityGroup_0) + { + NVIC_SetPriority(NVIC_InitStruct->NVIC_IRQChannel, NVIC_InitStruct->NVIC_IRQChannelSubPriority << 4); + } +#else + if(NVIC_Priority_Group == NVIC_PriorityGroup_1) + { + if(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority == 1) + { + NVIC_SetPriority(NVIC_InitStruct->NVIC_IRQChannel, (1 << 7) | (NVIC_InitStruct->NVIC_IRQChannelSubPriority << 5)); + } + else if(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority == 0) + { + NVIC_SetPriority(NVIC_InitStruct->NVIC_IRQChannel, (0 << 7) | (NVIC_InitStruct->NVIC_IRQChannelSubPriority << 5)); + } + } +#endif + + if(NVIC_InitStruct->NVIC_IRQChannelCmd != DISABLE) + { + NVIC_EnableIRQ(NVIC_InitStruct->NVIC_IRQChannel); + } + else + { + NVIC_DisableIRQ(NVIC_InitStruct->NVIC_IRQChannel); + } +} diff --git a/ZDBMS/BMS_MC/Peripheral/src/ch32l103_opa.c b/ZDBMS/BMS_MC/Peripheral/src/ch32l103_opa.c new file mode 100644 index 0000000..ed39c5b --- /dev/null +++ b/ZDBMS/BMS_MC/Peripheral/src/ch32l103_opa.c @@ -0,0 +1,343 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32l103_opa.c + * Author : WCH + * Version : V1.0.0 + * Date : 2024/11/05 + * Description : This file provides all the OPA firmware functions. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#include "ch32l103_opa.h" + +/* FLASH Keys */ +#define OPCM_KEY1 ((uint32_t)0x45670123) +#define OPCM_KEY2 ((uint32_t)0xCDEF89AB) + +/* mask definition*/ +#define POLL_CNT_MASK ((uint16_t)0x7000) + +volatile uint32_t CTLR2_tmp = 0; + + +/******************************************************************************** + * @fn OPCM_Unlock + * + * @brief Unlocks the OPCM Controller. + * + * @return none + */ +void OPCM_Unlock(void) +{ + OPA->OPCMKEY = OPCM_KEY1; + OPA->OPCMKEY = OPCM_KEY2; +} + +/******************************************************************************** + * @fn OPCM_Lock + * + * @brief Locks the OPCM Controller. + * + * @return none + */ +void OPCM_Lock(void) +{ + OPA->CTLR1 |= (1<<7); +} + +/********************************************************************* + * @fn OPA_Init + * + * @brief Initializes the OPA peripheral according to the specified + * parameters in the OPA_InitStruct. + * + * @param OPA_InitStruct - pointer to a OPA_InitTypeDef structure + * + * @return none + */ +void OPA_Init(OPA_InitTypeDef *OPA_InitStruct) +{ + uint16_t tmp0 = 0, tmp1 = 0; + uint32_t tmp2 = 0; + + tmp0 = OPA->CFGR1; + tmp1 = OPA->CFGR2; + tmp2 = OPA->CTLR1; + + if(OPA_InitStruct->OPA_NUM == OPA1) + { + tmp1 &= 0xF800; + tmp2 &= 0x80000001; + + tmp1 |= (OPA_InitStruct->POLL_NUM << 9); + tmp2 |= (OPA_InitStruct->Mode << 1) | (OPA_InitStruct->PSEL << 4) \ + | (OPA_InitStruct->FB << 7) | (OPA_InitStruct->NSEL << 8) \ + | OPA_Trim; + } + + tmp0 |= (OPA_InitStruct->PSEL_POLL) | (OPA_InitStruct->BKIN_EN << 2) + | (OPA_InitStruct->RST_EN << 4) | (OPA_InitStruct->OUT_IE << 8) + | (OPA_InitStruct->CNT_IE << 10) | (OPA_InitStruct->NMI_IE << 11); + tmp1 |= OPA_InitStruct->OPA_POLL_Interval; + + OPA->CFGR1 = tmp0; + OPA->CFGR2 = tmp1; + OPA->CTLR1 = tmp2; +} + +/********************************************************************* + * @fn OPA_StructInit + * + * @brief Fills each OPA_StructInit member with its reset value. + * + * @param OPA_StructInit - pointer to a OPA_InitTypeDef structure + * + * @return none + */ +void OPA_StructInit(OPA_InitTypeDef *OPA_InitStruct) +{ + OPA_InitStruct->OPA_POLL_Interval = 0; + OPA_InitStruct->OPA_NUM = OPA1; + OPA_InitStruct->Mode = OUT_IO_OFF; + OPA_InitStruct->PSEL = CHP_OFF; + OPA_InitStruct->FB = FB_OFF; + OPA_InitStruct->NSEL = CHN_OFF; + OPA_InitStruct->PSEL_POLL = CHP_OPA1_OFF; + OPA_InitStruct->BKIN_EN = BKIN_OPA1_OFF; + OPA_InitStruct->RST_EN = RST_OPA1_OFF; + OPA_InitStruct->OUT_IE = OUT_IE_OPA1_OFF; + OPA_InitStruct->CNT_IE = CNT_IE_OFF; + OPA_InitStruct->NMI_IE = NMI_IE_OFF; + OPA_InitStruct->POLL_NUM = CHP_POLL_NUM_1; +} + +/********************************************************************* + * @fn OPA_Cmd + * + * @brief Enables or disables the specified OPA peripheral. + * + * @param OPA_NUM - Select OPA + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void OPA_Cmd(OPA_Num_TypeDef OPA_NUM, FunctionalState NewState) +{ + if(NewState == ENABLE) + { + OPA->CTLR1 |= (uint32_t)(1 << (OPA_NUM*16)); + } + else + { + OPA->CTLR1 &= ~(uint32_t)(1 << (OPA_NUM*16)); + } +} + +/********************************************************************* + * @fn OPA_LP_Cmd + * + * @brief Enables or disables the OPA enter low power mode. + * + * @param NewState - new state of the OPA enter low power mode + * (ENABLE or DISABLE). + * + * @return none + */ +void OPA_LP_Cmd(FunctionalState NewState) +{ + if(NewState) + { + OPA->CTLR1 |= (1 << 12); + } + else + { + OPA->CTLR1 &= ~(1 << 12); + } +} + +/********************************************************************* + * @fn OPA_CMP_Init + * + * @brief Initializes the CMP peripheral according to the specified + * parameters in the CMP_InitTypeDef. + * + * @param CMP_InitStruct - pointer to a CMP_InitTypeDef structure + * + * @return none + */ +void OPA_CMP_Init(CMP_InitTypeDef *CMP_InitStruct) +{ + uint32_t tmp1 = 0; + + tmp1 = CTLR2_tmp; + + if(CMP_InitStruct->CMP_NUM == CMP1) + { + tmp1 &= 0xFFFFFFC1; + tmp1 |= (CMP_InitStruct->Mode << 1) | (CMP_InitStruct->NSEL << 3) + | (CMP_InitStruct->PSEL << 4) | (CMP_InitStruct->HYEN <<5); + } + else if(CMP_InitStruct->CMP_NUM == CMP2) + { + tmp1 &= 0xFFFFC1FF; + tmp1 |= (CMP_InitStruct->Mode << 9) | (CMP_InitStruct->NSEL << 11) + | (CMP_InitStruct->PSEL << 12) | (CMP_InitStruct->HYEN <<13); + } + else if(CMP_InitStruct->CMP_NUM == CMP3) + { + tmp1 &= 0xFFC1FFFF; + tmp1 |= (CMP_InitStruct->Mode << 17) | (CMP_InitStruct->NSEL << 19) + | (CMP_InitStruct->PSEL << 20) | (CMP_InitStruct->HYEN <<21); + } + + CTLR2_tmp = tmp1; + OPA->CTLR2 = tmp1; +} + +/********************************************************************* + * @fn OPA_CMP_StructInit + * + * @brief Fills each OPA_CMP_StructInit member with its reset value. + * + * @param CMP_StructInit - pointer to a OPA_CMP_StructInit structure + * + * @return none + */ +void OPA_CMP_StructInit(CMP_InitTypeDef *CMP_InitStruct) +{ + CMP_InitStruct->CMP_NUM = CMP1; + CMP_InitStruct->Mode = OUT_IO0; + CMP_InitStruct->NSEL = CMP_CHN0; + CMP_InitStruct->PSEL = CMP_CHP_0; +} + +/********************************************************************* + * @fn OPA_CMP_Cmd + * + * @brief Enables or disables the specified CMP peripheral. + * + * @param CMP_NUM - Select CMP + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void OPA_CMP_Cmd(CMP_Num_TypeDef CMP_NUM, FunctionalState NewState) +{ + if(NewState == ENABLE) + { + CTLR2_tmp |= (uint32_t)(1 << (CMP_NUM*8)); + } + else + { + CTLR2_tmp &= ~(uint32_t)(1 << (CMP_NUM*8)); + } + + OPA->CTLR2 = CTLR2_tmp; +} + +/********************************************************************* + * @fn OPA_CMP_LP_Cmd + * + * @brief Enables or disables the CMP enter low power mode. + * + * @param CMP_NUM - Select CMP + * NewState - new state of the CMP enter low power mode + * (ENABLE or DISABLE). + * + * @return none + */ +void OPA_CMP_LP_Cmd(CMP_Num_TypeDef CMP_NUM, FunctionalState NewState) +{ + uint8_t tmp1 = 0; + + tmp1 = 6 + CMP_NUM * 8; + + if(NewState) + { + OPA->CTLR2 |= (1 << tmp1); + } + else + { + OPA->CTLR2 &= ~(1 << tmp1); + } +} + +/********************************************************************* + * @fn OPA_CMP_WakeUp_ModeConfig + * + * @brief Configures the CMP wake up Mode. + * + * @param CMP_WakeUP_Mode - Specifies the trigger signal active edge for wake up of the CMP. + * CMP_WakeUp_Rising_Falling - the trigger signal rise and fall edge for wake up. + * CMP_WakeUp_Rising - the trigger signal rise edge for wake up. + * CMP_WakeUp_Falling - the trigger signal fall edge for wake up. + * + * @return none + */ +void OPA_CMP_WakeUp_ModeConfig(uint32_t CMP_WakeUP_Mode) +{ + OPA->CTLR2 &= ~CMP_WakeUp_Falling; + OPA->CTLR2 |= CMP_WakeUP_Mode; +} + +/********************************************************************* + * @fn OPA_GetFlagStatus + * + * @brief Checks whether the OPA flag is set or not. + * + * @param OPA_FLAG - specifies the OPA flag to check. + * OPA_FLAG_OUT_OPA1 - OPA1 out flag + * OPA_FLAG_OUT_CNT - OPA out flag rising edge of sampling data + * + * @return FlagStatus - SET or RESET. + */ +FlagStatus OPA_GetFlagStatus(uint16_t OPA_FLAG) +{ + FlagStatus bitstatus = RESET; + + if((OPA->CFGR1 & OPA_FLAG) != (uint16_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn OPA_ClearFlag + * + * @brief Clears the OPA flag. + * + * @param OPA_FLAG - specifies the OPA flag to clear. + * OPA_FLAG_OUT_OPA1 - OPA1 out flag + * OPA_FLAG_OUT_CNT - OPA out flag rising edge of sampling data + * + * @return none + */ +void OPA_ClearFlag(uint16_t OPA_FLAG) +{ + OPA->CFGR1 &= (uint16_t)~OPA_FLAG; +} + +/********************************************************************* + * @fn OPA_POLL_CNT + * + * @brief Displays the current channel being polled by the OPA + * + * @param none + * + * @return OPA_POLL_NUM_TypeDef - Current channel for OPA polling + */ +OPA_POLL_NUM_TypeDef OPA_POLL_CNT(void) +{ + uint16_t tmp1 = 0; + tmp1 = OPA->CFGR2; + tmp1 &= POLL_CNT_MASK; + tmp1 = tmp1 >> 12; + return tmp1; +} diff --git a/ZDBMS/BMS_MC/Peripheral/src/ch32l103_pwr.c b/ZDBMS/BMS_MC/Peripheral/src/ch32l103_pwr.c new file mode 100644 index 0000000..550fd6d --- /dev/null +++ b/ZDBMS/BMS_MC/Peripheral/src/ch32l103_pwr.c @@ -0,0 +1,466 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32l103_pwr.c + * Author : WCH + * Version : V1.0.0 + * Date : 2024/01/22 + * Description : This file provides all the PWR firmware functions. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#include "ch32l103_pwr.h" +#include "ch32l103_rcc.h" + +/* PWR registers bit mask */ +/* CTLR register bit mask */ +#define CTLR_DS_MASK ((uint32_t)0xFFFFFFFC) +#define CTLR_PLS_MASK ((uint32_t)0xFFFFFF1F) + +/********************************************************************* + * @fn PWR_DeInit + * + * @brief Deinitializes the PWR peripheral registers to their default + * reset values. + * + * @return none + */ +void PWR_DeInit(void) +{ + RCC_PB1PeriphResetCmd(RCC_PB1Periph_PWR, ENABLE); + RCC_PB1PeriphResetCmd(RCC_PB1Periph_PWR, DISABLE); +} + +/********************************************************************* + * @fn PWR_BackupAccessCmd + * + * @brief Enables or disables access to the RTC and backup registers. + * + * @param NewState - new state of the access to the RTC and backup registers, + * This parameter can be: ENABLE or DISABLE. + * + * @return none + */ +void PWR_BackupAccessCmd(FunctionalState NewState) +{ + if(NewState) + { + PWR->CTLR |= (1 << 8); + } + else + { + PWR->CTLR &= ~(1 << 8); + } +} + +/********************************************************************* + * @fn PWR_PVDCmd + * + * @brief Enables or disables the Power Voltage Detector(PVD). + * + * @param NewState - new state of the PVD(ENABLE or DISABLE). + * + * @return none + */ +void PWR_PVDCmd(FunctionalState NewState) +{ + if(NewState) + { + PWR->CTLR |= (1 << 4); + } + else + { + PWR->CTLR &= ~(1 << 4); + } +} + +/********************************************************************* + * @fn PWR_PVDLevelConfig + * + * @brief Configures the voltage threshold detected by the Power Voltage + * Detector(PVD). + * + * @param PWR_PVDLevel - specifies the PVD detection level + * PWR_PVDLevel_0 - PVD detection level set to mode 0. + * PWR_PVDLevel_1 - PVD detection level set to mode 1. + * PWR_PVDLevel_2 - PVD detection level set to mode 2. + * PWR_PVDLevel_3 - PVD detection level set to mode 3. + * PWR_PVDLevel_4 - PVD detection level set to mode 4. + * PWR_PVDLevel_5 - PVD detection level set to mode 5. + * PWR_PVDLevel_6 - PVD detection level set to mode 6. + * PWR_PVDLevel_7 - PVD detection level set to mode 7. + * + * @return none + */ +void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel) +{ + uint32_t tmpreg = 0; + tmpreg = PWR->CTLR; + tmpreg &= CTLR_PLS_MASK; + tmpreg |= PWR_PVDLevel; + PWR->CTLR = tmpreg; +} + +/********************************************************************* + * @fn PWR_WakeUpPinCmd + * + * @brief Enables or disables the WakeUp Pin functionality. + * + * @param NewState - new state of the WakeUp Pin functionality + * (ENABLE or DISABLE). + * + * @return none + */ +void PWR_WakeUpPinCmd(FunctionalState NewState) +{ + if(NewState) + { + PWR->CSR |= (1 << 8); + } + else + { + PWR->CSR &= ~(1 << 8); + } +} + +/********************************************************************* + * @fn PWR_EnterSTOPMode + * + * @brief Enters STOP mode. + * + * @param PWR_Regulator - specifies the regulator state in STOP mode. + * PWR_Regulator_ON - STOP mode with regulator ON + * PWR_Regulator_LowPower - STOP mode with regulator in low power mode + * PWR_STOPEntry - specifies if STOP mode in entered with WFI or WFE instruction. + * PWR_STOPEntry_WFI - enter STOP mode with WFI instruction + * PWR_STOPEntry_WFE - enter STOP mode with WFE instruction + * + * @return none + */ +void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry) +{ + uint32_t tmpreg = 0; + tmpreg = PWR->CTLR; + tmpreg &= CTLR_DS_MASK; + tmpreg |= PWR_Regulator; + if(PWR_Regulator==PWR_Regulator_LowPower) + { + tmpreg &= ~(3 << 10); + tmpreg |= (1 <<11); + } + PWR->CTLR = tmpreg; + + NVIC->SCTLR |= (1 << 2); + + if(PWR_STOPEntry == PWR_STOPEntry_WFI) + { + __WFI(); + } + else + { + __WFE(); + } + + NVIC->SCTLR &= ~(1 << 2); +} + +/********************************************************************* + * @fn PWR_EnterSTANDBYMode + * + * @brief Enters STANDBY mode. + * + * @return none + */ +void PWR_EnterSTANDBYMode(void) +{ + uint32_t tmpreg = 0; + tmpreg = PWR->CTLR; + /* flash low power mode 1 */ + tmpreg &= ~(3 << 10); + tmpreg |= (1 << 11); + + tmpreg |= PWR_CTLR_CWUF; + tmpreg |= PWR_CTLR_PDDS; + + PWR->CTLR = tmpreg; + + NVIC->SCTLR |= (1 << 2); + + __WFI(); +} + +/********************************************************************* + * @fn PWR_GetFlagStatus + * + * @brief Checks whether the specified PWR flag is set or not. + * + * @param PWR_FLAG - specifies the flag to check. + * PWR_FLAG_WU - Wake Up flag + * PWR_FLAG_SB - StandBy flag + * PWR_FLAG_PVDO - PVD Output + * + * @return none + */ +FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG) +{ + FlagStatus bitstatus = RESET; + + if((PWR->CSR & PWR_FLAG) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/********************************************************************* + * @fn PWR_ClearFlag + * + * @brief Clears the PWR's pending flags. + * + * @param PWR_FLAG - specifies the flag to clear. + * PWR_FLAG_WU - Wake Up flag + * PWR_FLAG_SB - StandBy flag + * + * @return none + */ +void PWR_ClearFlag(uint32_t PWR_FLAG) +{ + PWR->CTLR |= PWR_FLAG << 2; +} + +/********************************************************************* + * @fn PWR_EnterSTANDBYMode_RAM + * + * @brief Enters STANDBY mode with RAM data retention function on. + * + * @return none + */ +void PWR_EnterSTANDBYMode_RAM(void) +{ + uint32_t tmpreg = 0; + tmpreg = PWR->CTLR; + + /* flash low power mode 1 */ + tmpreg &= ~(3 << 10); + tmpreg |= (1 << 11); + + tmpreg |= PWR_CTLR_CWUF; + tmpreg |= PWR_CTLR_PDDS; + + //2K+18K in standby power. + tmpreg |= (0x1 << 16) | (0x1 << 17); + + PWR->CTLR = tmpreg; + + NVIC->SCTLR |= (1 << 2); + + __WFI(); +} + +/********************************************************************* + * @fn PWR_EnterSTANDBYMode_RAM_LV + * + * @brief Enters STANDBY mode with RAM data retention function and LV mode on. + * + * @return none + */ +void PWR_EnterSTANDBYMode_RAM_LV(void) +{ + uint32_t tmpreg = 0; + tmpreg = PWR->CTLR; + + /* flash low power mode 1 */ + tmpreg &= ~(3 << 10); + tmpreg |= (1 << 11); + + tmpreg |= PWR_CTLR_CWUF; + tmpreg |= PWR_CTLR_PDDS; + + //2K+18K in standby power. + tmpreg |= (0x1 << 16) | (0x1 << 17); + //2K+18K in standby LV . + tmpreg |= (0x1 << 20); + + PWR->CTLR = tmpreg; + + NVIC->SCTLR |= (1 << 2); + + __WFI(); +} + +/********************************************************************* + * @fn PWR_EnterSTANDBYMode_RAM_VBAT_EN + * + * @brief Enters STANDBY mode with RAM data retention function on (VBAT Enable). + * + * @return none + */ +void PWR_EnterSTANDBYMode_RAM_VBAT_EN(void) +{ + uint32_t tmpreg = 0; + tmpreg = PWR->CTLR; + + /* flash low power mode 1 */ + tmpreg &= ~(3 << 10); + tmpreg |= (1 << 11); + + tmpreg |= PWR_CTLR_CWUF; + tmpreg |= PWR_CTLR_PDDS; + + //2K+18K in standby power (VBAT Enable). + tmpreg |= (0x1 << 18) | (0x1 << 19); + + PWR->CTLR = tmpreg; + + NVIC->SCTLR |= (1 << 2); + + __WFI(); +} + +/********************************************************************* + * @fn PWR_EnterSTANDBYMode_RAM_LV_VBAT_EN + * + * @brief Enters STANDBY mode with RAM data retention function and LV mode on(VBAT Enable). + * + * @return none + */ +void PWR_EnterSTANDBYMode_RAM_LV_VBAT_EN(void) +{ + uint32_t tmpreg = 0; + tmpreg = PWR->CTLR; + + /* flash low power mode 1 */ + tmpreg &= ~(3 << 10); + tmpreg |= (1 << 11); + + tmpreg |= PWR_CTLR_CWUF; + tmpreg |= PWR_CTLR_PDDS; + + //2K+18K in standby power (VBAT Enable). + tmpreg |= (0x1 << 18) | (0x1 << 19); + //2K+18K in standby LV . + tmpreg |= (0x1 << 20); + + PWR->CTLR = tmpreg; + + NVIC->SCTLR |= (1 << 2); + + __WFI(); +} + + +/********************************************************************* + * @fn PWR_EnterSTOPMode_RAM_LV + * + * @brief Enters STOP mode with RAM data retention function and LV mode on. + * + * @param PWR_Regulator - specifies the regulator state in STOP mode. + * PWR_Regulator_ON - STOP mode with regulator ON + * PWR_Regulator_LowPower - STOP mode with regulator in low power mode + * PWR_STOPEntry - specifies if STOP mode in entered with WFI or WFE instruction. + * PWR_STOPEntry_WFI - enter STOP mode with WFI instruction + * PWR_STOPEntry_WFE - enter STOP mode with WFE instruction + * + * @return none + */ +void PWR_EnterSTOPMode_RAM_LV(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry) +{ + uint32_t tmpreg = 0; + tmpreg = PWR->CTLR; + tmpreg &= CTLR_DS_MASK; + tmpreg |= PWR_Regulator; + tmpreg |= (0x1 << 20); + + if(PWR_Regulator==PWR_Regulator_LowPower) + { + tmpreg &= ~(3 << 10); + tmpreg |= (1 << 11); + } + + PWR->CTLR = tmpreg; + + NVIC->SCTLR |= (1 << 2); + + if(PWR_STOPEntry == PWR_STOPEntry_WFI) + { + __WFI(); + } + else + { + __WFE(); + } + + NVIC->SCTLR &= ~(1 << 2); +} + +/********************************************************************* + * @fn PWR_LDO_LP_Cmd + * + * @brief Enables or disables the LDO low power mode. + * + * @param NewState - new state of the LDO low power mode(ENABLE or DISABLE). + * + * @return none + */ +void PWR_LDO_LP_Cmd(FunctionalState NewState) +{ + if(NewState) + { + PWR->CTLR |= (1 << 13); + } + else + { + PWR->CTLR &= ~(1 << 13); + } +} + +/********************************************************************* + * @fn PWR_STOPMode_Auto_LDO_LP_Cmd + * + * @brief Enables or disables the LDO auto enter low power mode in + * stop mode. + * + * @param NewState - new state of the LDO auto enter low power mode + * in stop mode(ENABLE or DISABLE). + * + * @return none + */ +void PWR_STOPMode_Auto_LDO_LP_Cmd(FunctionalState NewState) +{ + if(NewState) + { + PWR->CTLR |= (1 << 12); + } + else + { + PWR->CTLR &= ~(1 << 12); + } +} + +/********************************************************************* + * @fn PWR_FLASH_LP_Cmd + * + * @brief Enables or disables the FLASH enter low power mode 0. + * + * @param NewState - new state of the FLASH enter low power mode 0. + * (ENABLE or DISABLE). + * + * @return none + */ +void PWR_FLASH_LP_Cmd(FunctionalState NewState) +{ + if(NewState) + { + PWR->CTLR |= (7 << 9); + } + else + { + PWR->CTLR &= ~(1 << 9); + } +} + + diff --git a/ZDBMS/BMS_MC/Peripheral/src/ch32l103_rcc.c b/ZDBMS/BMS_MC/Peripheral/src/ch32l103_rcc.c new file mode 100644 index 0000000..b701f1d --- /dev/null +++ b/ZDBMS/BMS_MC/Peripheral/src/ch32l103_rcc.c @@ -0,0 +1,1045 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32l103_rcc.c + * Author : WCH + * Version : V1.0.0 + * Date : 2023/07/08 + * Description : This file provides all the RCC firmware functions. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#include "ch32l103_rcc.h" + +/* RCC registers bit address in the alias region */ +#define RCC_OFFSET (RCC_BASE - PERIPH_BASE) + +/* BDCTLR Register */ +#define BDCTLR_OFFSET (RCC_OFFSET + 0x20) + +/* RCC registers bit mask */ + +/* CTLR register bit mask */ +#define CTLR_HSEBYP_Reset ((uint32_t)0xFFFBFFFF) +#define CTLR_HSEBYP_Set ((uint32_t)0x00040000) +#define CTLR_HSEON_Reset ((uint32_t)0xFFFEFFFF) +#define CTLR_HSEON_Set ((uint32_t)0x00010000) +#define CTLR_HSITRIM_Mask ((uint32_t)0xFFFFFF07) + +/* CFGR0 register bit mask */ +#define CFGR0_PLL_Mask ((uint32_t)0xFFC0FFFF) +#define CFGR0_PLLMull_Mask ((uint32_t)0x003C0000) +#define CFGR0_PLLSRC_Mask ((uint32_t)0x00010000) +#define CFGR0_PLLXTPRE_Mask ((uint32_t)0x00020000) +#define CFGR0_SWS_Mask ((uint32_t)0x0000000C) +#define CFGR0_SW_Mask ((uint32_t)0xFFFFFFFC) +#define CFGR0_HPRE_Reset_Mask ((uint32_t)0xFFFFFF0F) +#define CFGR0_HPRE_Set_Mask ((uint32_t)0x000000F0) +#define CFGR0_PPRE1_Reset_Mask ((uint32_t)0xFFFFF8FF) +#define CFGR0_PPRE1_Set_Mask ((uint32_t)0x00000700) +#define CFGR0_PPRE2_Reset_Mask ((uint32_t)0xFFFFC7FF) +#define CFGR0_PPRE2_Set_Mask ((uint32_t)0x00003800) +#define CFGR0_ADCPRE_Reset_Mask ((uint32_t)0x7FFF3FFF) +#define CFGR0_ADCPRE_Set_Mask ((uint32_t)0x0000C000) +#define CFGR0_ADCDUTY_Reset_Mask ((uint32_t)0x8FFFFFFF) + +/* RSTSCKR register bit mask */ +#define RSTSCKR_RMVF_Set ((uint32_t)0x01000000) + +/* RCC Flag Mask */ +#define FLAG_Mask ((uint8_t)0x1F) + +/* INTR register byte 2 (Bits[15:8]) base address */ +#define INTR_BYTE2_ADDRESS ((uint32_t)0x40021009) + +/* INTR register byte 3 (Bits[23:16]) base address */ +#define INTR_BYTE3_ADDRESS ((uint32_t)0x4002100A) + +/* CFGR0 register byte 4 (Bits[31:24]) base address */ +#define CFGR0_BYTE4_ADDRESS ((uint32_t)0x40021007) + +/* BDCTLR register base address */ +#define BDCTLR_ADDRESS (PERIPH_BASE + BDCTLR_OFFSET) + + +static __I uint8_t PBHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9}; +static __I uint8_t ADCPrescTable[4] = {2, 4, 6, 8}; + +/********************************************************************* + * @fn RCC_DeInit + * + * @brief Resets the RCC clock configuration to the default reset state. + * Note- + * HSE can not be stopped if it is used directly or through the PLL as system clock. + * @return none + */ +void RCC_DeInit(void) +{ + RCC->CTLR |= (uint32_t)0x00000001; + RCC->CFGR0 &= (uint32_t)0x08FF0000; + RCC->CTLR &= (uint32_t)0xFEF6FFFB; + RCC->CTLR &= (uint32_t)0xFFFBFFFF; + RCC->CFGR0 &= (uint32_t)0xFF00FFFF; + RCC->INTR = 0x009F0000; +} + +/********************************************************************* + * @fn RCC_HSEConfig + * + * @brief Configures the External High Speed oscillator (HSE). + * + * @param RCC_HSE - + * RCC_HSE_OFF - HSE oscillator OFF. + * RCC_HSE_ON - HSE oscillator ON. + * RCC_HSE_Bypass - HSE oscillator bypassed with external clock. + * Note - + * HSE can not be stopped if it is used directly or through the PLL as system clock. + * @return none + */ +void RCC_HSEConfig(uint32_t RCC_HSE) +{ + RCC->CTLR &= CTLR_HSEON_Reset; + RCC->CTLR &= CTLR_HSEBYP_Reset; + + switch(RCC_HSE) + { + case RCC_HSE_ON: + RCC->CTLR |= CTLR_HSEON_Set; + break; + + case RCC_HSE_Bypass: + RCC->CTLR |= CTLR_HSEBYP_Set | CTLR_HSEON_Set; + break; + + default: + break; + } +} + +/********************************************************************* + * @fn RCC_WaitForHSEStartUp + * + * @brief Waits for HSE start-up. + * + * @return READY - HSE oscillator is stable and ready to use. + * NoREADY - HSE oscillator not yet ready. + */ +ErrorStatus RCC_WaitForHSEStartUp(void) +{ + __IO uint32_t StartUpCounter = 0; + + ErrorStatus status = NoREADY; + FlagStatus HSEStatus = RESET; + + do + { + HSEStatus = RCC_GetFlagStatus(RCC_FLAG_HSERDY); + StartUpCounter++; + } while((StartUpCounter != HSE_STARTUP_TIMEOUT) && (HSEStatus == RESET)); + + if (RCC_GetFlagStatus(RCC_FLAG_HSERDY) != RESET) + { + status = READY; + } + else + { + status = NoREADY; + } + + return (status); +} + +/********************************************************************* + * @fn RCC_AdjustHSICalibrationValue + * + * @brief Adjusts the Internal High Speed oscillator (HSI) calibration value. + * + * @param HSICalibrationValue - specifies the calibration trimming value. + * This parameter must be a number between 0 and 0x1F. + * + * @return none + */ +void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue) +{ + uint32_t tmpreg = 0; + + tmpreg = RCC->CTLR; + tmpreg &= CTLR_HSITRIM_Mask; + tmpreg |= (uint32_t)HSICalibrationValue << 3; + RCC->CTLR = tmpreg; +} + +/********************************************************************* + * @fn RCC_HSICmd + * + * @brief Enables or disables the Internal High Speed oscillator (HSI). + * + * @param NewState - ENABLE or DISABLE. + * + * @return none + */ +void RCC_HSICmd(FunctionalState NewState) +{ + if(NewState) + { + RCC->CTLR |= (1<<0); + } + else + { + RCC->CTLR &= ~(1<<0); + } +} + +/********************************************************************* + * @fn RCC_PLLConfig + * + * @brief Configures the PLL clock source and multiplication factor. + * + * @param RCC_PLLSource - specifies the PLL entry clock source. + * RCC_PLLSource_HSI_Div2 - HSI oscillator clock divided by 2 + * selected as PLL clock entry. + * RCC_PLLSource_HSE_Div1 - HSI oscillator clock as PLL clock + * entry. + * RCC_PLLSource_HSE_Div2 - HSI oscillator clock divided by 2 + * as PLL clock entry. + * RCC_PLLMul - specifies the PLL multiplication factor. + * This parameter can be RCC_PLLMul_x where x:[2,16]. + * RCC_PLLMul_2 + * RCC_PLLMul_3 + * RCC_PLLMul_4 + * RCC_PLLMul_5 + * RCC_PLLMul_6 + * RCC_PLLMul_7 + * RCC_PLLMul_8 + * RCC_PLLMul_9 + * RCC_PLLMul_10 + * RCC_PLLMul_11 + * RCC_PLLMul_12 + * RCC_PLLMul_13 + * RCC_PLLMul_14 + * RCC_PLLMul_15 + * RCC_PLLMul_16 + * RCC_PLLMul_18 + * + * @return none + */ +void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t RCC_PLLMul) +{ + uint32_t tmpreg = 0; + + tmpreg = RCC->CFGR0; + + tmpreg &= CFGR0_PLL_Mask; + tmpreg |= RCC_PLLSource | RCC_PLLMul; + RCC->CFGR0 = tmpreg; +} + +/********************************************************************* + * @fn RCC_PLLCmd + * + * @brief Enables or disables the PLL. + * Note-The PLL can not be disabled if it is used as system clock. + * + * @param NewState - ENABLE or DISABLE. + * + * @return none + */ +void RCC_PLLCmd(FunctionalState NewState) +{ + if(NewState) + { + RCC->CTLR |= (1<<24); + } + else + { + RCC->CTLR &= ~(1<<24); + } +} + +/********************************************************************* + * @fn RCC_SYSCLKConfig + * + * @brief Configures the system clock (SYSCLK). + * + * @param RCC_SYSCLKSource - specifies the clock source used as system clock. + * RCC_SYSCLKSource_HSI - HSI selected as system clock. + * RCC_SYSCLKSource_HSE - HSE selected as system clock. + * RCC_SYSCLKSource_PLLCLK - PLL selected as system clock. + * + * @return none + */ +void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource) +{ + uint32_t tmpreg = 0; + + tmpreg = RCC->CFGR0; + tmpreg &= CFGR0_SW_Mask; + tmpreg |= RCC_SYSCLKSource; + RCC->CFGR0 = tmpreg; +} + +/********************************************************************* + * @fn RCC_GetSYSCLKSource + * + * @brief Returns the clock source used as system clock. + * + * @return 0x00 - HSI used as system clock. + * 0x04 - HSE used as system clock. + * 0x08 - PLL used as system clock. + */ +uint8_t RCC_GetSYSCLKSource(void) +{ + return ((uint8_t)(RCC->CFGR0 & CFGR0_SWS_Mask)); +} + +/********************************************************************* + * @fn RCC_HCLKConfig + * + * @brief Configures the HB clock (HCLK). + * + * @param RCC_SYSCLK - defines the HB clock divider. This clock is derived from + * the system clock (SYSCLK). + * RCC_SYSCLK_Div1 - HB clock = SYSCLK. + * RCC_SYSCLK_Div2 - HB clock = SYSCLK/2. + * RCC_SYSCLK_Div4 - HB clock = SYSCLK/4. + * RCC_SYSCLK_Div8 - HB clock = SYSCLK/8. + * RCC_SYSCLK_Div16 - HB clock = SYSCLK/16. + * RCC_SYSCLK_Div64 - HB clock = SYSCLK/64. + * RCC_SYSCLK_Div128 - HB clock = SYSCLK/128. + * RCC_SYSCLK_Div256 - HB clock = SYSCLK/256. + * RCC_SYSCLK_Div512 - HB clock = SYSCLK/512. + * + * @return none + */ +void RCC_HCLKConfig(uint32_t RCC_SYSCLK) +{ + uint32_t tmpreg = 0; + + tmpreg = RCC->CFGR0; + tmpreg &= CFGR0_HPRE_Reset_Mask; + tmpreg |= RCC_SYSCLK; + RCC->CFGR0 = tmpreg; +} + +/********************************************************************* + * @fn RCC_PCLK1Config + * + * @brief Configures the Low Speed PB clock (PCLK1). + * + * @param RCC_HCLK - defines the PB1 clock divider. This clock is derived from + * the HB clock (HCLK). + * RCC_HCLK_Div1 - PB1 clock = HCLK. + * RCC_HCLK_Div2 - PB1 clock = HCLK/2. + * RCC_HCLK_Div4 - PB1 clock = HCLK/4. + * RCC_HCLK_Div8 - PB1 clock = HCLK/8. + * RCC_HCLK_Div16 - PB1 clock = HCLK/16. + * + * @return none + */ +void RCC_PCLK1Config(uint32_t RCC_HCLK) +{ + uint32_t tmpreg = 0; + + tmpreg = RCC->CFGR0; + tmpreg &= CFGR0_PPRE1_Reset_Mask; + tmpreg |= RCC_HCLK; + RCC->CFGR0 = tmpreg; +} + +/********************************************************************* + * @fn RCC_PCLK2Config + * + * @brief Configures the High Speed PB clock (PCLK2). + * + * @param RCC_HCLK - defines the PB2 clock divider. This clock is derived from + * the HB clock (HCLK). + * RCC_HCLK_Div1 - PB2 clock = HCLK. + * RCC_HCLK_Div2 - PB2 clock = HCLK/2. + * RCC_HCLK_Div4 - PB2 clock = HCLK/4. + * RCC_HCLK_Div8 - PB2 clock = HCLK/8. + * RCC_HCLK_Div16 - PB2 clock = HCLK/16. + * @return none + */ +void RCC_PCLK2Config(uint32_t RCC_HCLK) +{ + uint32_t tmpreg = 0; + + tmpreg = RCC->CFGR0; + tmpreg &= CFGR0_PPRE2_Reset_Mask; + tmpreg |= RCC_HCLK << 3; + RCC->CFGR0 = tmpreg; +} + +/********************************************************************* + * @fn RCC_ITConfig + * + * @brief Enables or disables the specified RCC interrupts. + * + * @param RCC_IT - specifies the RCC interrupt sources to be enabled or disabled. + * RCC_IT_LSIRDY - LSI ready interrupt. + * RCC_IT_LSERDY - LSE ready interrupt. + * RCC_IT_HSIRDY - HSI ready interrupt. + * RCC_IT_HSERDY - HSE ready interrupt. + * RCC_IT_PLLRDY - PLL ready interrupt. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState) +{ + if (NewState != DISABLE) + { + *(__IO uint8_t *) INTR_BYTE2_ADDRESS |= RCC_IT; + } + else + { + *(__IO uint8_t *) INTR_BYTE2_ADDRESS &= (uint8_t)~RCC_IT; + } +} + +/********************************************************************* + * @fn RCC_USBCLKConfig + * + * @brief Configures the USB clock (USBCLK). + * + * @param RCC_USBCLKSource: specifies the USB clock source. This clock is + * derived from the PLL output. + * RCC_USBCLKSource_PLLCLK_Div1 - PLL clock selected as USB clock source(48Mhz). + * RCC_USBCLKSource_PLLCLK_Div2 - PLL clock selected as USB clock source(96MHz). + * RCC_USBCLKSource_PLLCLK_Div1_5 - PLL clock selected as USB clock source(72MHz). + * + * @return none + */ +void RCC_USBCLKConfig(uint32_t RCC_USBCLKSource) +{ + RCC->CFGR0 &= ~((uint32_t)3<<22); + RCC->CFGR0 |= RCC_USBCLKSource; +} + +/********************************************************************* + * @fn RCC_ADCCLKConfig + * + * @brief Configures the ADC clock (ADCCLK). + * + * @param ADC_CLK_S - defines the ADC clock. + * RCC_PCLK2_Div2 - ADC clock = PCLK2/2. + * RCC_PCLK2_Div4 - ADC clock = PCLK2/4. + * RCC_PCLK2_Div6 - ADC clock = PCLK2/6. + * RCC_PCLK2_Div8 - ADC clock = PCLK2/8. + * RCC_HCLK_ADC - ADC clock = HCLK. + * + * @return none + */ +void RCC_ADCCLKConfig(uint32_t ADC_CLK_S) +{ + uint32_t tmpreg = 0; + + tmpreg = RCC->CFGR0; + tmpreg &= CFGR0_ADCPRE_Reset_Mask; + tmpreg |= ADC_CLK_S; + RCC->CFGR0 = tmpreg; +} + +/********************************************************************* + * @fn RCC_LSEConfig + * + * @brief Configures the External Low Speed oscillator (LSE). + * + * @param RCC_LSE - specifies the new state of the LSE. + * RCC_LSE_OFF - LSE oscillator OFF. + * RCC_LSE_ON - LSE oscillator ON. + * RCC_LSE_Bypass - LSE oscillator bypassed with external clock. + * + * @return none + */ +void RCC_LSEConfig(uint8_t RCC_LSE) +{ + *(__IO uint8_t *) BDCTLR_ADDRESS = RCC_LSE_OFF; + *(__IO uint8_t *) BDCTLR_ADDRESS = RCC_LSE_OFF; + + switch(RCC_LSE) + { + case RCC_LSE_ON: + *(__IO uint8_t *) BDCTLR_ADDRESS = RCC_LSE_ON; + break; + + case RCC_LSE_Bypass: + *(__IO uint8_t *) BDCTLR_ADDRESS = RCC_LSE_Bypass | RCC_LSE_ON; + break; + + default: + break; + } +} + +/********************************************************************* + * @fn RCC_LSICmd + * + * @brief Enables or disables the Internal Low Speed oscillator (LSI). + * Note- + * LSI can not be disabled if the IWDG is running. + * + * @param NewState - ENABLE or DISABLE. + * + * @return none + */ +void RCC_LSICmd(FunctionalState NewState) +{ + if(NewState) + { + RCC->RSTSCKR |= (1<<0); + } + else{ + RCC->RSTSCKR &= ~(1<<0); + } +} + +/********************************************************************* + * @fn RCC_RTCCLKConfig + * + * @brief Once the RTC clock is selected it can't be changed unless the Backup domain is reset. + * + * @param RCC_RTCCLKSource - specifies the RTC clock source. + * RCC_RTCCLKSource_LSE - LSE selected as RTC clock. + * RCC_RTCCLKSource_LSI - LSI selected as RTC clock. + * RCC_RTCCLKSource_HSE_Div128 - HSE clock divided by 128 selected as RTC clock. + * Note- + * Once the RTC clock is selected it can't be changed unless the Backup domain is reset. + * + * @return none + */ +void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource) +{ + RCC->BDCTLR |= RCC_RTCCLKSource; +} + +/********************************************************************* + * @fn RCC_RTCCLKCmd + * + * @brief This function must be used only after the RTC clock was selected + * using the RCC_RTCCLKConfig function. + * + * @param NewState - ENABLE or DISABLE. + * + * @return none + */ +void RCC_RTCCLKCmd(FunctionalState NewState) +{ + if(NewState) + { + RCC->BDCTLR |= (1<<15); + } + else + { + RCC->BDCTLR &= ~(1<<15); + } +} + +/********************************************************************* + * @fn RCC_GetClocksFreq + * + * @brief The result of this function could be not correct when using + * fractional value for HSE crystal. + * + * @param RCC_Clocks - pointer to a RCC_ClocksTypeDef structure which will hold + * the clocks frequencies. + * + * @return none + */ +void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks) +{ + uint32_t tmp = 0, pllmull = 0, pllsource = 0, presc = 0; + + tmp = RCC->CFGR0 & CFGR0_SWS_Mask; + + switch (tmp) + { + case 0x00: + if(RCC->CTLR & (1<<2)) + { + RCC_Clocks->SYSCLK_Frequency = HSI_LP_VALUE; + } + else + { + RCC_Clocks->SYSCLK_Frequency = HSI_VALUE; + } + break; + + case 0x04: + RCC_Clocks->SYSCLK_Frequency = HSE_VALUE; + break; + + case 0x08: + pllmull = RCC->CFGR0 & CFGR0_PLLMull_Mask; + pllsource = RCC->CFGR0 & CFGR0_PLLSRC_Mask; + + pllmull = ( pllmull >> 18) + 2; + + if(pllmull == 17) pllmull = 18; + + + if (pllsource == 0x00) + { + if(EXTEN->EXTEN_CTR & EXTEN_PLL_HSI_PRE){ + RCC_Clocks->SYSCLK_Frequency = (HSI_VALUE) * pllmull; + } + else{ + RCC_Clocks->SYSCLK_Frequency = (HSI_VALUE >>1) * pllmull; + } + } + else + { + if ((RCC->CFGR0 & CFGR0_PLLXTPRE_Mask) != (uint32_t)RESET) + { + RCC_Clocks->SYSCLK_Frequency = (HSE_VALUE >> 1) * pllmull; + } + else + { + RCC_Clocks->SYSCLK_Frequency = HSE_VALUE * pllmull; + + } + } + + break; + + default: + RCC_Clocks->SYSCLK_Frequency = HSI_VALUE; + break; + } + + tmp = RCC->CFGR0 & CFGR0_HPRE_Set_Mask; + tmp = tmp >> 4; + presc = PBHBPrescTable[tmp]; + RCC_Clocks->HCLK_Frequency = RCC_Clocks->SYSCLK_Frequency >> presc; + tmp = RCC->CFGR0 & CFGR0_PPRE1_Set_Mask; + tmp = tmp >> 8; + presc = PBHBPrescTable[tmp]; + RCC_Clocks->PCLK1_Frequency = RCC_Clocks->HCLK_Frequency >> presc; + tmp = RCC->CFGR0 & CFGR0_PPRE2_Set_Mask; + tmp = tmp >> 11; + presc = PBHBPrescTable[tmp]; + RCC_Clocks->PCLK2_Frequency = RCC_Clocks->HCLK_Frequency >> presc; + + if(RCC->CFGR0 & (1<<31)) + { + RCC_Clocks->ADCCLK_Frequency = RCC_Clocks->HCLK_Frequency; + } + else + { + tmp = RCC->CFGR0 & CFGR0_ADCPRE_Set_Mask; + tmp = tmp >> 14; + presc = ADCPrescTable[tmp]; + RCC_Clocks->ADCCLK_Frequency = RCC_Clocks->PCLK2_Frequency / presc; + } +} + +/********************************************************************* + * @fn RCC_HBPeriphClockCmd + * + * @brief Enables or disables the HB peripheral clock. + * + * @param RCC_HBPeriph - specifies the HB peripheral to gates its clock. + * RCC_HBPeriph_DMA1. + * RCC_HBPeriph_SRAM. + * RCC_HBPeriph_CRC. + * RCC_HBPeriph_USBFS. + * RCC_HBPeriph_USBPD. + * Note- + * SRAM clock can be disabled only during sleep mode. + * NewState: ENABLE or DISABLE. + * + * @return none + */ +void RCC_HBPeriphClockCmd(uint32_t RCC_HBPeriph, FunctionalState NewState) +{ + if (NewState != DISABLE) + { + RCC->HBPCENR |= RCC_HBPeriph; + } + else + { + RCC->HBPCENR &= ~RCC_HBPeriph; + } +} + +/********************************************************************* + * @fn RCC_PB2PeriphClockCmd + * + * @brief Enables or disables the High Speed PB (PB2) peripheral clock. + * + * @param RCC_PB2Periph - specifies the PB2 peripheral to gates its clock. + * RCC_PB2Periph_AFIO. + * RCC_PB2Periph_GPIOA. + * RCC_PB2Periph_GPIOB. + * RCC_PB2Periph_GPIOC. + * RCC_PB2Periph_GPIOD. + * RCC_PB2Periph_ADC1. + * RCC_PB2Periph_TIM1. + * RCC_PB2Periph_SPI1. + * RCC_PB2Periph_TIM8 + * RCC_PB2Periph_USART1. + * NewState - ENABLE or DISABLE + * + * @return none + */ +void RCC_PB2PeriphClockCmd(uint32_t RCC_PB2Periph, FunctionalState NewState) +{ + if (NewState != DISABLE) + { + RCC->PB2PCENR |= RCC_PB2Periph; + } + else + { + RCC->PB2PCENR &= ~RCC_PB2Periph; + } +} + +/********************************************************************* + * @fn RCC_PB1PeriphClockCmd + * + * @brief Enables or disables the Low Speed PB (PB1) peripheral clock. + * + * @param RCC_PB1Periph - specifies the PB1 peripheral to gates its clock. + * RCC_PB1Periph_TIM2. + * RCC_PB1Periph_TIM3. + * RCC_PB1Periph_TIM4. + * RCC_PB1Periph_WWDG. + * RCC_PB1Periph_SPI2. + * RCC_PB1Periph_USART2. + * RCC_PB1Periph_USART3. + * RCC_PB1Periph_USART4 + * RCC_PB1Periph_I2C1. + * RCC_PB1Periph_I2C2. + * RCC_PB1Periph_CAN1. + * RCC_PB1Periph_BKP. + * RCC_PB1Periph_PWR. + * RCC_PB1Periph_LPTIM. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void RCC_PB1PeriphClockCmd(uint32_t RCC_PB1Periph, FunctionalState NewState) +{ + if (NewState != DISABLE) + { + RCC->PB1PCENR |= RCC_PB1Periph; + } + else + { + RCC->PB1PCENR &= ~RCC_PB1Periph; + } +} + +/********************************************************************* + * @fn RCC_PB2PeriphResetCmd + * + * @brief Forces or releases High Speed PB (PB2) peripheral reset. + * + * @param RCC_PB2Periph - specifies the PB2 peripheral to reset. + * RCC_PB2Periph_AFIO. + * RCC_PB2Periph_GPIOA. + * RCC_PB2Periph_GPIOB. + * RCC_PB2Periph_GPIOC. + * RCC_PB2Periph_GPIOD. + * RCC_PB2Periph_ADC1. + * RCC_PB2Periph_TIM1. + * RCC_PB2Periph_SPI1. + * RCC_PB2Periph_TIM8 + * RCC_PB2Periph_USART1. + * NewState - ENABLE or DISABLE + * + * @return none + */ +void RCC_PB2PeriphResetCmd(uint32_t RCC_PB2Periph, FunctionalState NewState) +{ + if (NewState != DISABLE) + { + RCC->PB2PRSTR |= RCC_PB2Periph; + } + else + { + RCC->PB2PRSTR &= ~RCC_PB2Periph; + } +} + +/********************************************************************* + * @fn RCC_PB1PeriphResetCmd + * + * @brief Forces or releases Low Speed PB (PB1) peripheral reset. + * + * @param RCC_PB1Periph - specifies the PB1 peripheral to reset. + * RCC_PB1Periph_TIM2. + * RCC_PB1Periph_TIM3. + * RCC_PB1Periph_TIM4. + * RCC_PB1Periph_WWDG. + * RCC_PB1Periph_SPI2. + * RCC_PB1Periph_USART2. + * RCC_PB1Periph_USART3. + * RCC_PB1Periph_USART4 + * RCC_PB1Periph_I2C1. + * RCC_PB1Periph_I2C2. + * RCC_PB1Periph_CAN1. + * RCC_PB1Periph_BKP. + * RCC_PB1Periph_PWR. + * RCC_PB1Periph_LPTIM. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void RCC_PB1PeriphResetCmd(uint32_t RCC_PB1Periph, FunctionalState NewState) +{ + if (NewState != DISABLE) + { + RCC->PB1PRSTR |= RCC_PB1Periph; + } + else + { + RCC->PB1PRSTR &= ~RCC_PB1Periph; + } +} + +/********************************************************************* + * @fn RCC_BackupResetCmd + * + * @brief Forces or releases the Backup domain reset. + * + * @param NewState - ENABLE or DISABLE. + * + * @return none + */ +void RCC_BackupResetCmd(FunctionalState NewState) +{ + if(NewState) + { + RCC->BDCTLR |= (1<<16); + } + else{ + RCC->BDCTLR &= ~(1<<16); + } +} + +/******************************************************************************* +* Function Name : RCC_ClockSecuritySystemCmd +* Description : Enables or disables the Clock Security System. +* Input : NewState: ENABLE or DISABLE. +* Return : None +*******************************************************************************/ +void RCC_ClockSecuritySystemCmd(FunctionalState NewState) +{ + if(NewState) + { + RCC->CTLR |= (1<<19); + } + else{ + RCC->CTLR &= ~(1<<19); + } +} + +/********************************************************************* + * @fn RCC_MCOConfig + * + * @brief Selects the clock source to output on MCO pin. + * + * @param RCC_MCO - specifies the clock source to output. + * RCC_MCO_NoClock - No clock selected. + * RCC_MCO_SYSCLK - System clock selected. + * RCC_MCO_HSI - HSI oscillator clock selected. + * RCC_MCO_HSE - HSE oscillator clock selected. + * RCC_MCO_PLLCLK_Div2 - PLL clock divided by 2 selected. + * + * @return none + */ +void RCC_MCOConfig(uint8_t RCC_MCO) +{ + *(__IO uint8_t *) CFGR0_BYTE4_ADDRESS = RCC_MCO; +} + +/********************************************************************* + * @fn RCC_GetFlagStatus + * + * @brief Checks whether the specified RCC flag is set or not. + * + * @param RCC_FLAG - specifies the flag to check. + * RCC_FLAG_HSIRDY - HSI oscillator clock ready. + * RCC_FLAG_HSERDY - HSE oscillator clock ready. + * RCC_FLAG_PLLRDY - PLL clock ready. + * RCC_FLAG_LSERDY - LSE oscillator clock ready. + * RCC_FLAG_LSIRDY - LSI oscillator clock ready. + * RCC_FLAG_PINRST - Pin reset. + * RCC_FLAG_PORRST - POR/PDR reset. + * RCC_FLAG_SFTRST - Software reset. + * RCC_FLAG_IWDGRST - Independent Watchdog reset. + * RCC_FLAG_WWDGRST - Window Watchdog reset. + * RCC_FLAG_LPWRRST - Low Power reset. + * + * @return FlagStatus - SET or RESET. + */ +FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG) +{ + uint32_t tmp = 0; + uint32_t statusreg = 0; + + FlagStatus bitstatus = RESET; + tmp = RCC_FLAG >> 5; + + if (tmp == 1) + { + statusreg = RCC->CTLR; + } + else if (tmp == 2) + { + statusreg = RCC->BDCTLR; + } + else + { + statusreg = RCC->RSTSCKR; + } + + tmp = RCC_FLAG & FLAG_Mask; + + if ((statusreg & ((uint32_t)1 << tmp)) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn RCC_ClearFlag + * + * @brief Clears the RCC reset flags. + * Note- + * The reset flags are: RCC_FLAG_PINRST, RCC_FLAG_PORRST, RCC_FLAG_SFTRST, + * RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST + * + * @return none + */ +void RCC_ClearFlag(void) +{ + RCC->RSTSCKR |= RSTSCKR_RMVF_Set; +} + +/********************************************************************* + * @fn RCC_GetITStatus + * + * @brief Checks whether the specified RCC interrupt has occurred or not. + * + * @param RCC_IT - specifies the RCC interrupt source to check. + * RCC_IT_LSIRDY - LSI ready interrupt. + * RCC_IT_LSERDY - LSE ready interrupt. + * RCC_IT_HSIRDY - HSI ready interrupt. + * RCC_IT_HSERDY - HSE ready interrupt. + * RCC_IT_PLLRDY - PLL ready interrupt. + * RCC_IT_CSS - Clock Security System interrupt. + * + * @return ITStatus - SET or RESET. + */ +ITStatus RCC_GetITStatus(uint8_t RCC_IT) +{ + ITStatus bitstatus = RESET; + + if ((RCC->INTR & RCC_IT) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn RCC_ClearITPendingBit + * + * @brief Clears the RCC's interrupt pending bits. + * + * @param RCC_IT - specifies the interrupt pending bit to clear. + * RCC_IT_LSIRDY - LSI ready interrupt. + * RCC_IT_LSERDY - LSE ready interrupt. + * RCC_IT_HSIRDY - HSI ready interrupt. + * RCC_IT_HSERDY - HSE ready interrupt. + * RCC_IT_PLLRDY - PLL ready interrupt. + * RCC_IT_CSS - Clock Security System interrupt. + * + * @return none + */ +void RCC_ClearITPendingBit(uint8_t RCC_IT) +{ + *(__IO uint8_t *) INTR_BYTE3_ADDRESS = RCC_IT; +} + +/********************************************************************* + * @fn RCC_ADCCLKDutyCycleConfig + * + * @brief Configures the ADC clock high level duty cycle. + * + * @param RCC_DutyCycle - high level duty cycle. + * RCC_ADC_H_Level_Mode0 - ADC clock high-level duty cycle is mode 0. + * RCC_ADC_H_Level_Mode1 - ADC clock high-level duty cycle is mode 1. + * RCC_ADC_H_Level_Mode2 - ADC clock high-level duty cycle is mode 2. + * RCC_ADC_H_Level_Mode3 - ADC clock high-level duty cycle is mode 3. + * RCC_ADC_H_Level_Mode4 - ADC clock high-level duty cycle is mode 4. + * RCC_ADC_H_Level_Mode5 - ADC clock high-level duty cycle is mode 5. + * RCC_ADC_H_Level_Mode6 - ADC clock high-level duty cycle is mode 6. + * RCC_ADC_H_Level_Mode7 - ADC clock high-level duty cycle is mode 7. + * + * @return none + */ +void RCC_ADCCLKDutyCycleConfig(uint32_t RCC_DutyCycle) +{ + RCC->CFGR0 &= CFGR0_ADCDUTY_Reset_Mask; + RCC->CFGR0 |= RCC_DutyCycle; +} + +/********************************************************************* + * @fn RCC_HSE_LP_Cmd + * + * @brief Enables or disables low power mode of the External High Speed + * oscillator (HSE). + * + * @param NewState - ENABLE or DISABLE. + * + * @return none + */ +void RCC_HSE_LP_Cmd(FunctionalState NewState) +{ + if(NewState) + { + RCC->CTLR |= (1<<20); + } + else + { + RCC->CTLR &= ~(1<<20); + } +} + +/********************************************************************* + * @fn RCC_HSI_LP_Cmd + * + * @brief Enables or disables low power mode of the Internal High Speed + * oscillator (HSI) . + * + * @param NewState - ENABLE or DISABLE. + * + * @return none + */ +void RCC_HSI_LP_Cmd(FunctionalState NewState) +{ + if(NewState) + { + RCC->CTLR |= (1<<2); + } + else + { + RCC->CTLR &= ~(1<<2); + } +} + + diff --git a/ZDBMS/BMS_MC/Peripheral/src/ch32l103_rtc.c b/ZDBMS/BMS_MC/Peripheral/src/ch32l103_rtc.c new file mode 100644 index 0000000..f4d6b8e --- /dev/null +++ b/ZDBMS/BMS_MC/Peripheral/src/ch32l103_rtc.c @@ -0,0 +1,281 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32l103_rtc.c + * Author : WCH + * Version : V1.0.0 + * Date : 2023/07/08 + * Description : This file provides all the RTC firmware functions. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#include "ch32l103_rtc.h" + +/* RTC_Private_Defines */ +#define RTC_LSB_MASK ((uint32_t)0x0000FFFF) /* RTC LSB Mask */ +#define PRLH_MSB_MASK ((uint32_t)0x000F0000) /* RTC Prescaler MSB Mask */ + +/********************************************************************* + * @fn RTC_ITConfig + * + * @brief Enables or disables the specified RTC interrupts. + * + * @param RTC_IT - specifies the RTC interrupts sources to be enabled or disabled. + * RTC_IT_OW - Overflow interrupt + * RTC_IT_ALR - Alarm interrupt + * RTC_IT_SEC - Second interrupt + * + * @return NewState - new state of the specified RTC interrupts(ENABLE or DISABLE). + */ +void RTC_ITConfig(uint16_t RTC_IT, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + RTC->CTLRH |= RTC_IT; + } + else + { + RTC->CTLRH &= (uint16_t)~RTC_IT; + } +} + +/********************************************************************* + * @fn RTC_EnterConfigMode + * + * @brief Enters the RTC configuration mode. + * + * @return none + */ +void RTC_EnterConfigMode(void) +{ + RTC->CTLRL |= RTC_CTLRL_CNF; +} + +/********************************************************************* + * @fn RTC_ExitConfigMode + * + * @brief Exits from the RTC configuration mode. + * + * @return none + */ +void RTC_ExitConfigMode(void) +{ + RTC->CTLRL &= (uint16_t) ~((uint16_t)RTC_CTLRL_CNF); +} + +/********************************************************************* + * @fn RTC_GetCounter + * + * @brief Gets the RTC counter value + * + * @return RTC counter value + */ +uint32_t RTC_GetCounter(void) +{ + uint16_t high1 = 0, high2 = 0, low = 0; + + high1 = RTC->CNTH; + low = RTC->CNTL; + high2 = RTC->CNTH; + + if(high1 != high2) + { + return (((uint32_t)high2 << 16) | RTC->CNTL); + } + else + { + return (((uint32_t)high1 << 16) | low); + } +} + +/********************************************************************* + * @fn RTC_SetCounter + * + * @brief Sets the RTC counter value. + * + * @param CounterValue - RTC counter new value. + * + * @return RTC counter value + */ +void RTC_SetCounter(uint32_t CounterValue) +{ + RTC_EnterConfigMode(); + RTC->CNTH = CounterValue >> 16; + RTC->CNTL = (CounterValue & RTC_LSB_MASK); + RTC_ExitConfigMode(); +} + +/********************************************************************* + * @fn RTC_SetPrescaler + * + * @brief Sets the RTC prescaler value + * + * @param PrescalerValue - RTC prescaler new value + * + * @return none + */ +void RTC_SetPrescaler(uint32_t PrescalerValue) +{ + RTC_EnterConfigMode(); + RTC->PSCRH = (PrescalerValue & PRLH_MSB_MASK) >> 16; + RTC->PSCRL = (PrescalerValue & RTC_LSB_MASK); + RTC_ExitConfigMode(); +} + +/********************************************************************* + * @fn RTC_SetAlarm + * + * @brief Sets the RTC alarm value + * + * @param AlarmValue - RTC alarm new value + * + * @return none + */ +void RTC_SetAlarm(uint32_t AlarmValue) +{ + RTC_EnterConfigMode(); + RTC->ALRMH = AlarmValue >> 16; + RTC->ALRML = (AlarmValue & RTC_LSB_MASK); + RTC_ExitConfigMode(); +} + +/********************************************************************* + * @fn RTC_GetDivider + * + * @brief Gets the RTC divider value + * + * @return RTC Divider value + */ +uint32_t RTC_GetDivider(void) +{ + uint32_t tmp = 0x00; + tmp = ((uint32_t)RTC->DIVH & (uint32_t)0x000F) << 16; + tmp |= RTC->DIVL; + return tmp; +} + +/********************************************************************* + * @fn RTC_WaitForLastTask + * + * @brief Waits until last write operation on RTC registers has finished + * Note- + * This function must be called before any write to RTC registers. + * @return none + */ +void RTC_WaitForLastTask(void) +{ + while((RTC->CTLRL & RTC_FLAG_RTOFF) == (uint16_t)RESET) + { + } +} + +/********************************************************************* + * @fn RTC_WaitForSynchro + * + * @brief Waits until the RTC registers are synchronized with RTC PB clock + * Note- + * This function must be called before any read operation after an PB reset + * or an PB clock stop. + * + * @return none + */ +void RTC_WaitForSynchro(void) +{ + RTC->CTLRL &= (uint16_t)~RTC_FLAG_RSF; + while((RTC->CTLRL & RTC_FLAG_RSF) == (uint16_t)RESET) + { + } +} + +/********************************************************************* + * @fn RTC_GetFlagStatus + * + * @brief Checks whether the specified RTC flag is set or not + * + * @param RTC_FLAG- specifies the flag to check + * RTC_FLAG_RTOFF - RTC Operation OFF flag + * RTC_FLAG_RSF - Registers Synchronized flag + * RTC_FLAG_OW - Overflow flag + * RTC_FLAG_ALR - Alarm flag + * RTC_FLAG_SEC - Second flag + * + * @return The new state of RTC_FLAG (SET or RESET) + */ +FlagStatus RTC_GetFlagStatus(uint16_t RTC_FLAG) +{ + FlagStatus bitstatus = RESET; + if((RTC->CTLRL & RTC_FLAG) != (uint16_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/********************************************************************* + * @fn RTC_ClearFlag + * + * @brief Clears the RTC's pending flags + * + * @param RTC_FLAG - specifies the flag to clear + * RTC_FLAG_RSF - Registers Synchronized flag + * RTC_FLAG_OW - Overflow flag + * RTC_FLAG_ALR - Alarm flag + * RTC_FLAG_SEC - Second flag + * + * @return none + */ +void RTC_ClearFlag(uint16_t RTC_FLAG) +{ + RTC->CTLRL &= (uint16_t)~RTC_FLAG; +} + +/********************************************************************* + * @fn RTC_GetITStatus + * + * @brief Checks whether the specified RTC interrupt has occurred or not + * + * @param RTC_IT - specifies the RTC interrupts sources to check + * RTC_FLAG_OW - Overflow interrupt + * RTC_FLAG_ALR - Alarm interrupt + * RTC_FLAG_SEC - Second interrupt + * + * @return The new state of the RTC_IT (SET or RESET) + */ +ITStatus RTC_GetITStatus(uint16_t RTC_IT) +{ + ITStatus bitstatus = RESET; + + bitstatus = (ITStatus)(RTC->CTLRL & RTC_IT); + if(((RTC->CTLRH & RTC_IT) != (uint16_t)RESET) && (bitstatus != (uint16_t)RESET)) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/********************************************************************* + * @fn RTC_ClearITPendingBit + * + * @brief Clears the RTC's interrupt pending bits + * + * @param RTC_IT - specifies the interrupt pending bit to clear + * RTC_FLAG_OW - Overflow interrupt + * RTC_FLAG_ALR - Alarm interrupt + * RTC_FLAG_SEC - Second interrupt + * + * @return none + */ +void RTC_ClearITPendingBit(uint16_t RTC_IT) +{ + RTC->CTLRL &= (uint16_t)~RTC_IT; +} + + diff --git a/ZDBMS/BMS_MC/Peripheral/src/ch32l103_spi.c b/ZDBMS/BMS_MC/Peripheral/src/ch32l103_spi.c new file mode 100644 index 0000000..9197c02 --- /dev/null +++ b/ZDBMS/BMS_MC/Peripheral/src/ch32l103_spi.c @@ -0,0 +1,536 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32l103_spi.c + * Author : WCH + * Version : V1.0.0 + * Date : 2024/06/05 + * Description : This file provides all the SPI firmware functions. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#include "ch32l103_spi.h" +#include "ch32l103_rcc.h" + +/* SPI SPE mask */ +#define CTLR1_SPE_Set ((uint16_t)0x0040) +#define CTLR1_SPE_Reset ((uint16_t)0xFFBF) + +/* SPI CRCNext mask */ +#define CTLR1_CRCNext_Set ((uint16_t)0x1000) + +/* SPI CRCEN mask */ +#define CTLR1_CRCEN_Set ((uint16_t)0x2000) +#define CTLR1_CRCEN_Reset ((uint16_t)0xDFFF) + +/* SPI SSOE mask */ +#define CTLR2_SSOE_Set ((uint16_t)0x0004) +#define CTLR2_SSOE_Reset ((uint16_t)0xFFFB) + +/* SPI registers Masks */ +#define CTLR1_CLEAR_Mask ((uint16_t)0x3040) +#define I2SCFGR_CLEAR_Mask ((uint16_t)0xF040) + +/********************************************************************* + * @fn SPI_I2S_DeInit + * + * @brief Deinitializes the SPIx peripheral registers to their default + * reset values. + * + * @param SPIx - where x can be 1 or 2 to select the SPI peripheral. + * + * @return none + */ +void SPI_I2S_DeInit(SPI_TypeDef *SPIx) +{ + if(SPIx == SPI1) + { + RCC_PB2PeriphResetCmd(RCC_PB2Periph_SPI1, ENABLE); + RCC_PB2PeriphResetCmd(RCC_PB2Periph_SPI1, DISABLE); + } + else if(SPIx == SPI2) + { + RCC_PB1PeriphResetCmd(RCC_PB1Periph_SPI2, ENABLE); + RCC_PB1PeriphResetCmd(RCC_PB1Periph_SPI2, DISABLE); + } +} + +/********************************************************************* + * @fn SPI_Init + * + * @brief Initializes the SPIx peripheral according to the specified + * parameters in the SPI_InitStruct. + * When using SPI slave mode to send data, the CPOL bit should be set to 1. + * + * @param SPIx - where x can be 1 or 2 to select the SPI peripheral. + * SPI_InitStruct - pointer to a SPI_InitTypeDef structure that + * contains the configuration information for the specified SPI peripheral. + * + * @return none + */ +void SPI_Init(SPI_TypeDef *SPIx, SPI_InitTypeDef *SPI_InitStruct) +{ + uint16_t tmpreg = 0; + + tmpreg = SPIx->CTLR1; + tmpreg &= CTLR1_CLEAR_Mask; + tmpreg |= (uint16_t)((uint32_t)SPI_InitStruct->SPI_Direction | SPI_InitStruct->SPI_Mode | + SPI_InitStruct->SPI_DataSize | SPI_InitStruct->SPI_CPOL | + SPI_InitStruct->SPI_CPHA | SPI_InitStruct->SPI_NSS | + SPI_InitStruct->SPI_BaudRatePrescaler | SPI_InitStruct->SPI_FirstBit); + + SPIx->CTLR1 = tmpreg; + SPIx->CRCR = SPI_InitStruct->SPI_CRCPolynomial; +} + +/********************************************************************* + * @fn SPI_StructInit + * + * @brief Fills each SPI_InitStruct member with its default value. + * + * @param SPI_InitStruct - pointer to a SPI_InitTypeDef structure which + * will be initialized. + * + * @return none + */ +void SPI_StructInit(SPI_InitTypeDef *SPI_InitStruct) +{ + SPI_InitStruct->SPI_Direction = SPI_Direction_2Lines_FullDuplex; + SPI_InitStruct->SPI_Mode = SPI_Mode_Slave; + SPI_InitStruct->SPI_DataSize = SPI_DataSize_8b; + SPI_InitStruct->SPI_CPOL = SPI_CPOL_Low; + SPI_InitStruct->SPI_CPHA = SPI_CPHA_1Edge; + SPI_InitStruct->SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_2; + SPI_InitStruct->SPI_FirstBit = SPI_FirstBit_MSB; + SPI_InitStruct->SPI_CRCPolynomial = 7; +} + +/********************************************************************* + * @fn SPI_Cmd + * + * @brief Enables or disables the specified SPI peripheral. + * + * @param SPIx - where x can be 1 or 2 to select the SPI peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void SPI_Cmd(SPI_TypeDef *SPIx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + SPIx->CTLR1 |= CTLR1_SPE_Set; + } + else + { + SPIx->CTLR1 &= CTLR1_SPE_Reset; + } +} + +/********************************************************************* + * @fn SPI_I2S_ITConfig + * + * @brief Enables or disables the specified SPI interrupts. + * + * @param SPIx - where x can be + * - 1 or 2 in SPI mode. + * SPI_I2S_IT - specifies the SPI/I2S interrupt source to be + * enabled or disabled. + * SPI_I2S_IT_TXE - Tx buffer empty interrupt mask. + * SPI_I2S_IT_RXNE - Rx buffer not empty interrupt mask. + * SPI_I2S_IT_ERR - Error interrupt mask. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void SPI_I2S_ITConfig(SPI_TypeDef *SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState) +{ + uint16_t itpos = 0, itmask = 0; + + itpos = SPI_I2S_IT >> 4; + itmask = (uint16_t)1 << (uint16_t)itpos; + + if(NewState != DISABLE) + { + SPIx->CTLR2 |= itmask; + } + else + { + SPIx->CTLR2 &= (uint16_t)~itmask; + } +} + +/********************************************************************* + * @fn SPI_I2S_DMACmd + * + * @brief Enables or disables the SPIx DMA interface. + * + * @param SPIx - where x can be + * - 1 or 2 in SPI mode. + * SPI_I2S_DMAReq - specifies the SPI DMA transfer request to + * be enabled or disabled. + * SPI_I2S_DMAReq_Tx - Tx buffer DMA transfer request. + * SPI_I2S_DMAReq_Rx - Rx buffer DMA transfer request. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void SPI_I2S_DMACmd(SPI_TypeDef *SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + SPIx->CTLR2 |= SPI_I2S_DMAReq; + } + else + { + SPIx->CTLR2 &= (uint16_t)~SPI_I2S_DMAReq; + } +} + +/********************************************************************* + * @fn SPI_I2S_SendData + * + * @brief Transmits a Data through the SPIx peripheral. + * + * @param SPIx - where x can be + * - 1 or 2 in SPI mode. + * Data - Data to be transmitted. + * + * @return none + */ +void SPI_I2S_SendData(SPI_TypeDef *SPIx, uint16_t Data) +{ + SPIx->DATAR = Data; +} + +/********************************************************************* + * @fn SPI_I2S_ReceiveData + * + * @brief Returns the most recent received data by the SPIx peripheral. + * + * @param SPIx - where x can be + * - 1 or 2 in SPI mode. + * Data - Data to be transmitted. + * + * @return SPIx->DATAR - The value of the received data. + */ +uint16_t SPI_I2S_ReceiveData(SPI_TypeDef *SPIx) +{ + return SPIx->DATAR; +} + +/********************************************************************* + * @fn SPI_NSSInternalSoftwareConfig + * + * @brief Configures internally by software the NSS pin for the selected SPI. + * + * @param SPIx - where x can be 1 or 2 to select the SPI peripheral. + * SPI_NSSInternalSoft - + * SPI_NSSInternalSoft_Set - Set NSS pin internally. + * SPI_NSSInternalSoft_Reset - Reset NSS pin internally. + * + * @return none + */ +void SPI_NSSInternalSoftwareConfig(SPI_TypeDef *SPIx, uint16_t SPI_NSSInternalSoft) +{ + if(SPI_NSSInternalSoft != SPI_NSSInternalSoft_Reset) + { + SPIx->CTLR1 |= SPI_NSSInternalSoft_Set; + } + else + { + SPIx->CTLR1 &= SPI_NSSInternalSoft_Reset; + } +} + +/********************************************************************* + * @fn SPI_SSOutputCmd + * + * @brief Enables or disables the SS output for the selected SPI. + * + * @param SPIx - where x can be 1 or 2 to select the SPI peripheral. + * NewState - new state of the SPIx SS output. + * + * @return none + */ +void SPI_SSOutputCmd(SPI_TypeDef *SPIx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + SPIx->CTLR2 |= CTLR2_SSOE_Set; + } + else + { + SPIx->CTLR2 &= CTLR2_SSOE_Reset; + } +} + +/********************************************************************* + * @fn SPI_DataSizeConfig + * + * @brief Configures the data size for the selected SPI. + * + * @param SPIx - where x can be 1 or 2 to select the SPI peripheral. + * SPI_DataSize - specifies the SPI data size. + * SPI_DataSize_16b - Set data frame format to 16bit. + * SPI_DataSize_8b - Set data frame format to 8bit. + * + * @return none + */ +void SPI_DataSizeConfig(SPI_TypeDef *SPIx, uint16_t SPI_DataSize) +{ + SPIx->CTLR1 &= (uint16_t)~SPI_DataSize_16b; + SPIx->CTLR1 |= SPI_DataSize; +} + +/********************************************************************* + * @fn SPI_TransmitCRC + * + * @brief Transmit the SPIx CRC value. + * + * @param SPIx - where x can be 1 or 2 to select the SPI peripheral. + * + * @return none + */ +void SPI_TransmitCRC(SPI_TypeDef *SPIx) +{ + SPIx->CTLR1 |= CTLR1_CRCNext_Set; +} + +/********************************************************************* + * @fn SPI_CalculateCRC + * + * @brief Enables or disables the CRC value calculation of the transferred bytes. + * + * @param SPIx - where x can be 1 or 2 to select the SPI peripheral. + * NewState - new state of the SPIx CRC value calculation. + * + * @return none + */ +void SPI_CalculateCRC(SPI_TypeDef *SPIx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + SPIx->CTLR1 |= CTLR1_CRCEN_Set; + } + else + { + SPIx->CTLR1 &= CTLR1_CRCEN_Reset; + } +} + +/********************************************************************* + * @fn SPI_GetCRC + * + * @brief Returns the transmit or the receive CRC register value for the specified SPI. + * + * @param SPIx - where x can be 1 or 2 to select the SPI peripheral. + * SPI_CRC - specifies the CRC register to be read. + * SPI_CRC_Tx - Selects Tx CRC register. + * SPI_CRC_Rx - Selects Rx CRC register. + * + * @return crcreg - The selected CRC register value. + */ +uint16_t SPI_GetCRC(SPI_TypeDef *SPIx, uint8_t SPI_CRC) +{ + uint16_t crcreg = 0; + + if(SPI_CRC != SPI_CRC_Rx) + { + crcreg = SPIx->TCRCR; + } + else + { + crcreg = SPIx->RCRCR; + } + + return crcreg; +} + +/********************************************************************* + * @fn SPI_GetCRCPolynomial + * + * @brief Returns the CRC Polynomial register value for the specified SPI. + * + * @param SPIx - where x can be 1 or 2 to select the SPI peripheral. + * + * @return SPIx->CRCR - The CRC Polynomial register value. + */ +uint16_t SPI_GetCRCPolynomial(SPI_TypeDef *SPIx) +{ + return SPIx->CRCR; +} + +/********************************************************************* + * @fn SPI_BiDirectionalLineConfig + * + * @brief Selects the data transfer direction in bi-directional mode + * for the specified SPI. + * + * @param SPIx - where x can be 1 or 2 to select the SPI peripheral. + * SPI_Direction - specifies the data transfer direction in + * bi-directional mode. + * SPI_Direction_Tx - Selects Tx transmission direction. + * SPI_Direction_Rx - Selects Rx receive direction. + * + * @return none + */ +void SPI_BiDirectionalLineConfig(SPI_TypeDef *SPIx, uint16_t SPI_Direction) +{ + if(SPI_Direction == SPI_Direction_Tx) + { + SPIx->CTLR1 |= SPI_Direction_Tx; + } + else + { + SPIx->CTLR1 &= SPI_Direction_Rx; + } +} + +/********************************************************************* + * @fn SPI_I2S_GetFlagStatus + * + * @brief Checks whether the specified SPI flag is set or not. + * + * @param SPIx - where x can be + * - 1 or 2 in SPI mode. + * SPI_I2S_FLAG - specifies the SPI flag to check. + * SPI_I2S_FLAG_TXE - Transmit buffer empty flag. + * SPI_I2S_FLAG_RXNE - Receive buffer not empty flag. + * SPI_I2S_FLAG_BSY - Busy flag. + * SPI_I2S_FLAG_OVR - Overrun flag. + * SPI_FLAG_MODF - Mode Fault flag. + * SPI_FLAG_CRCERR - CRC Error flag. + * + * @return FlagStatus - SET or RESET. + */ +FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef *SPIx, uint16_t SPI_I2S_FLAG) +{ + FlagStatus bitstatus = RESET; + + if((SPIx->STATR & SPI_I2S_FLAG) != (uint16_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn SPI_I2S_ClearFlag + * + * @brief Clears the SPIx CRC Error (CRCERR) flag. + * + * @param SPIx - where x can be + * - 1 or 2 in SPI mode. + * SPI_I2S_FLAG - specifies the SPI flag to clear. + * SPI_FLAG_CRCERR - CRC Error flag. + * Note- + * - OVR (OverRun error) flag is cleared by software sequence - a read + * operation to SPI_DATAR register (SPI_I2S_ReceiveData()) followed by a read + * operation to SPI_STATR register (SPI_I2S_GetFlagStatus()). + * - MODF (Mode Fault) flag is cleared by software sequence - a read/write + * operation to SPI_STATR register (SPI_I2S_GetFlagStatus()) followed by a + * write operation to SPI_CTLR1 register (SPI_Cmd() to enable the SPI). + * @return FlagStatus - SET or RESET. + */ +void SPI_I2S_ClearFlag(SPI_TypeDef *SPIx, uint16_t SPI_I2S_FLAG) +{ + SPIx->STATR = (uint16_t)~SPI_I2S_FLAG; +} + +/********************************************************************* + * @fn SPI_I2S_GetITStatus + * + * @brief Checks whether the specified SPI interrupt has occurred or not. + * + * @param SPIx - where x can be + * - 1 or 2 in SPI mode. + * SPI_I2S_IT - specifies the SPI interrupt source to check.. + * SPI_I2S_IT_TXE - Transmit buffer empty interrupt. + * SPI_I2S_IT_RXNE - Receive buffer not empty interrupt. + * SPI_I2S_IT_OVR - Overrun interrupt. + * SPI_IT_MODF - Mode Fault interrupt. + * SPI_IT_CRCERR - CRC Error interrupt. + * + * @return FlagStatus - SET or RESET. + */ +ITStatus SPI_I2S_GetITStatus(SPI_TypeDef *SPIx, uint8_t SPI_I2S_IT) +{ + ITStatus bitstatus = RESET; + uint16_t itpos = 0, itmask = 0, enablestatus = 0; + + itpos = 0x01 << (SPI_I2S_IT & 0x0F); + itmask = SPI_I2S_IT >> 4; + itmask = 0x01 << itmask; + enablestatus = (SPIx->CTLR2 & itmask); + + if(((SPIx->STATR & itpos) != (uint16_t)RESET) && enablestatus) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn SPI_I2S_ClearITPendingBit + * + * @brief Clears the SPIx CRC Error (CRCERR) interrupt pending bit. + * + * @param SPIx - where x can be + * - 1 or 2 in SPI mode. + * SPI_I2S_IT - specifies the SPI interrupt pending bit to clear. + * SPI_IT_CRCERR - CRC Error interrupt. + * Note- + * - OVR (OverRun Error) interrupt pending bit is cleared by software + * sequence - a read operation to SPI_DATAR register (SPI_I2S_ReceiveData()) + * followed by a read operation to SPI_STATR register (SPI_I2S_GetITStatus()). + * - MODF (Mode Fault) interrupt pending bit is cleared by software sequence: + * a read/write operation to SPI_STATR register (SPI_I2S_GetITStatus()) + * followed by a write operation to SPI_CTLR1 register (SPI_Cmd() to enable + * the SPI). + * + * @return none + */ +void SPI_I2S_ClearITPendingBit(SPI_TypeDef *SPIx, uint8_t SPI_I2S_IT) +{ + uint16_t itpos = 0; + + itpos = 0x01 << (SPI_I2S_IT & 0x0F); + SPIx->STATR = (uint16_t)~itpos; +} + +/********************************************************************* + * @fn SPI_HighSpeedRead_Cmd + * + * @brief Enables or disables the SPI high speed read mode. + * Note - + * Read enable in SPI high-speed mode (CLK is more than + * or equal to 36MHz). This mode is valid only when clock + * is divided by 2 (BR in CTLR1 = 000). + * + * @param SPIx - where x can be 1 or 2 to select the SPI peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void SPI_HighSpeedRead_Cmd(SPI_TypeDef *SPIx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + SPIx->HSCR |= (1 << 0); + } + else + { + SPIx->HSCR &= ~(1 << 0); + } +} diff --git a/ZDBMS/BMS_MC/Peripheral/src/ch32l103_tim.c b/ZDBMS/BMS_MC/Peripheral/src/ch32l103_tim.c new file mode 100644 index 0000000..b16233f --- /dev/null +++ b/ZDBMS/BMS_MC/Peripheral/src/ch32l103_tim.c @@ -0,0 +1,2412 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32l103_tim.c + * Author : WCH + * Version : V1.0.0 + * Date : 2023/07/08 + * Description : This file provides all the TIM firmware functions. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#include "ch32l103_tim.h" +#include "ch32l103_rcc.h" + +/* TIM registers bit mask */ +#define SMCFGR_ETR_Mask ((uint16_t)0x00FF) +#define CHCTLR_Offset ((uint16_t)0x0018) +#define CCER_CCE_Set ((uint16_t)0x0001) +#define CCER_CCNE_Set ((uint16_t)0x0004) + +static void TI1_Config(TIM_TypeDef *TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, + uint16_t TIM_ICFilter); +static void TI2_Config(TIM_TypeDef *TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, + uint16_t TIM_ICFilter); +static void TI3_Config(TIM_TypeDef *TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, + uint16_t TIM_ICFilter); +static void TI4_Config(TIM_TypeDef *TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, + uint16_t TIM_ICFilter); + +/********************************************************************* + * @fn TIM_DeInit + * + * @brief Deinitializes the TIMx peripheral registers to their default + * reset values. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * + * @return none + */ +void TIM_DeInit(TIM_TypeDef *TIMx) +{ + if(TIMx == TIM1) + { + RCC_PB2PeriphResetCmd(RCC_PB2Periph_TIM1, ENABLE); + RCC_PB2PeriphResetCmd(RCC_PB2Periph_TIM1, DISABLE); + } + else if(TIMx == TIM2) + { + RCC_PB1PeriphResetCmd(RCC_PB1Periph_TIM2, ENABLE); + RCC_PB1PeriphResetCmd(RCC_PB1Periph_TIM2, DISABLE); + } + else if(TIMx == TIM3) + { + RCC_PB1PeriphResetCmd(RCC_PB1Periph_TIM3, ENABLE); + RCC_PB1PeriphResetCmd(RCC_PB1Periph_TIM3, DISABLE); + } + else if(TIMx == TIM4) + { + RCC_PB1PeriphResetCmd(RCC_PB1Periph_TIM4, ENABLE); + RCC_PB1PeriphResetCmd(RCC_PB1Periph_TIM4, DISABLE); + } +} + +/********************************************************************* + * @fn TIM_TimeBaseInit + * + * @brief Initializes the TIMx Time Base Unit peripheral according to + * the specified parameters in the TIM_TimeBaseInitStruct. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_TimeBaseInitStruct - pointer to a TIM_TimeBaseInitTypeDef + * structure. + * + * @return none + */ +void TIM_TimeBaseInit(TIM_TypeDef *TIMx, TIM_TimeBaseInitTypeDef *TIM_TimeBaseInitStruct) +{ + uint16_t tmpcr1 = 0; + + tmpcr1 = TIMx->CTLR1; + + if((TIMx == TIM1) || (TIMx == TIM2) || (TIMx == TIM3) || (TIMx == TIM4)) + { + tmpcr1 &= (uint16_t)(~((uint16_t)(TIM_DIR | TIM_CMS))); + tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->TIM_CounterMode; + } + + tmpcr1 &= (uint16_t)(~((uint16_t)TIM_CTLR1_CKD)); + tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->TIM_ClockDivision; + + TIMx->CTLR1 = tmpcr1; + + if(TIMx == TIM4) TIMx->ATRLR_TIM4 = TIM_TimeBaseInitStruct->TIM_Period; + else TIMx->ATRLR = (uint16_t)TIM_TimeBaseInitStruct->TIM_Period; + + TIMx->PSC = TIM_TimeBaseInitStruct->TIM_Prescaler; + + if((TIMx == TIM1)) + { + TIMx->RPTCR = TIM_TimeBaseInitStruct->TIM_RepetitionCounter; + } + + TIMx->SWEVGR = TIM_PSCReloadMode_Immediate; +} + +/********************************************************************* + * @fn TIM_OC1Init + * + * @brief Initializes the TIMx Channel1 according to the specified + * parameters in the TIM_OCInitStruct. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_OCInitStruct - pointer to a TIM_OCInitTypeDef structure. + * + * @return none + */ +void TIM_OC1Init(TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct) +{ + uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; + + TIMx->CCER &= (uint16_t)(~(uint16_t)TIM_CC1E); + tmpccer = TIMx->CCER; + tmpcr2 = TIMx->CTLR2; + tmpccmrx = TIMx->CHCTLR1; + tmpccmrx &= (uint16_t)(~((uint16_t)TIM_OC1M)); + tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CC1S)); + tmpccmrx |= TIM_OCInitStruct->TIM_OCMode; + tmpccer &= (uint16_t)(~((uint16_t)TIM_CC1P)); + tmpccer |= TIM_OCInitStruct->TIM_OCPolarity; + tmpccer |= TIM_OCInitStruct->TIM_OutputState; + + if((TIMx == TIM1)) + { + tmpccer &= (uint16_t)(~((uint16_t)TIM_CC1NP)); + tmpccer |= TIM_OCInitStruct->TIM_OCNPolarity; + + tmpccer &= (uint16_t)(~((uint16_t)TIM_CC1NE)); + tmpccer |= TIM_OCInitStruct->TIM_OutputNState; + + tmpcr2 &= (uint16_t)(~((uint16_t)TIM_OIS1)); + tmpcr2 &= (uint16_t)(~((uint16_t)TIM_OIS1N)); + + tmpcr2 |= TIM_OCInitStruct->TIM_OCIdleState; + tmpcr2 |= TIM_OCInitStruct->TIM_OCNIdleState; + } + + TIMx->CTLR2 = tmpcr2; + TIMx->CHCTLR1 = tmpccmrx; + if(TIMx == TIM4) TIMx->CH1CVR_TIM4 = TIM_OCInitStruct->TIM_Pulse; + else TIMx->CH1CVR = (uint16_t)TIM_OCInitStruct->TIM_Pulse; + TIMx->CCER = tmpccer; +} + +/********************************************************************* + * @fn TIM_OC2Init + * + * @brief Initializes the TIMx Channel2 according to the specified + * parameters in the TIM_OCInitStruct. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_OCInitStruct - pointer to a TIM_OCInitTypeDef structure. + * + * @return none + */ +void TIM_OC2Init(TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct) +{ + uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; + + TIMx->CCER &= (uint16_t)(~((uint16_t)TIM_CC2E)); + tmpccer = TIMx->CCER; + tmpcr2 = TIMx->CTLR2; + tmpccmrx = TIMx->CHCTLR1; + tmpccmrx &= (uint16_t)(~((uint16_t)TIM_OC2M)); + tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CC2S)); + tmpccmrx |= (uint16_t)(TIM_OCInitStruct->TIM_OCMode << 8); + tmpccer &= (uint16_t)(~((uint16_t)TIM_CC2P)); + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 4); + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 4); + + if((TIMx == TIM1)) + { + tmpccer &= (uint16_t)(~((uint16_t)TIM_CC2NP)); + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCNPolarity << 4); + tmpccer &= (uint16_t)(~((uint16_t)TIM_CC2NE)); + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputNState << 4); + + tmpcr2 &= (uint16_t)(~((uint16_t)TIM_OIS2)); + tmpcr2 &= (uint16_t)(~((uint16_t)TIM_OIS2N)); + tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 2); + tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCNIdleState << 2); + } + + TIMx->CTLR2 = tmpcr2; + TIMx->CHCTLR1 = tmpccmrx; + if(TIMx == TIM4) TIMx->CH2CVR_TIM4 = TIM_OCInitStruct->TIM_Pulse; + else TIMx->CH2CVR = (uint16_t)TIM_OCInitStruct->TIM_Pulse; + TIMx->CCER = tmpccer; +} + +/********************************************************************* + * @fn TIM_OC3Init + * + * @brief Initializes the TIMx Channel3 according to the specified + * parameters in the TIM_OCInitStruct. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_OCInitStruct - pointer to a TIM_OCInitTypeDef structure. + * + * @return none + */ +void TIM_OC3Init(TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct) +{ + uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; + + TIMx->CCER &= (uint16_t)(~((uint16_t)TIM_CC3E)); + tmpccer = TIMx->CCER; + tmpcr2 = TIMx->CTLR2; + tmpccmrx = TIMx->CHCTLR2; + tmpccmrx &= (uint16_t)(~((uint16_t)TIM_OC3M)); + tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CC3S)); + tmpccmrx |= TIM_OCInitStruct->TIM_OCMode; + tmpccer &= (uint16_t)(~((uint16_t)TIM_CC3P)); + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 8); + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 8); + + if((TIMx == TIM1)) + { + tmpccer &= (uint16_t)(~((uint16_t)TIM_CC3NP)); + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCNPolarity << 8); + tmpccer &= (uint16_t)(~((uint16_t)TIM_CC3NE)); + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputNState << 8); + tmpcr2 &= (uint16_t)(~((uint16_t)TIM_OIS3)); + tmpcr2 &= (uint16_t)(~((uint16_t)TIM_OIS3N)); + tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 4); + tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCNIdleState << 4); + } + + TIMx->CTLR2 = tmpcr2; + TIMx->CHCTLR2 = tmpccmrx; + if(TIMx == TIM4) TIMx->CH3CVR_TIM4 = TIM_OCInitStruct->TIM_Pulse; + else TIMx->CH3CVR = (uint16_t)TIM_OCInitStruct->TIM_Pulse; + TIMx->CCER = tmpccer; +} + +/********************************************************************* + * @fn TIM_OC4Init + * + * @brief Initializes the TIMx Channel4 according to the specified + * parameters in the TIM_OCInitStruct. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_OCInitStruct - pointer to a TIM_OCInitTypeDef structure. + * + * @return none + */ +void TIM_OC4Init(TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct) +{ + uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; + + TIMx->CCER &= (uint16_t)(~((uint16_t)TIM_CC4E)); + tmpccer = TIMx->CCER; + tmpcr2 = TIMx->CTLR2; + tmpccmrx = TIMx->CHCTLR2; + tmpccmrx &= (uint16_t)(~((uint16_t)TIM_OC4M)); + tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CC4S)); + tmpccmrx |= (uint16_t)(TIM_OCInitStruct->TIM_OCMode << 8); + tmpccer &= (uint16_t)(~((uint16_t)TIM_CC4P)); + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 12); + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 12); + + if((TIMx == TIM1)) + { + tmpcr2 &= (uint16_t)(~((uint16_t)TIM_OIS4)); + tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 6); + } + + TIMx->CTLR2 = tmpcr2; + TIMx->CHCTLR2 = tmpccmrx; + if(TIMx == TIM4) TIMx->CH4CVR_TIM4 = TIM_OCInitStruct->TIM_Pulse; + else TIMx->CH4CVR = (uint16_t)TIM_OCInitStruct->TIM_Pulse; + TIMx->CCER = tmpccer; +} + +/********************************************************************* + * @fn TIM_ICInit + * + * @brief IInitializes the TIM peripheral according to the specified + * parameters in the TIM_ICInitStruct. + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_ICInitStruct - pointer to a TIM_ICInitTypeDef structure. + * + * @return none + */ +void TIM_ICInit(TIM_TypeDef *TIMx, TIM_ICInitTypeDef *TIM_ICInitStruct) +{ + if(TIM_ICInitStruct->TIM_Channel == TIM_Channel_1) + { + TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, + TIM_ICInitStruct->TIM_ICSelection, + TIM_ICInitStruct->TIM_ICFilter); + TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + } + else if(TIM_ICInitStruct->TIM_Channel == TIM_Channel_2) + { + TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, + TIM_ICInitStruct->TIM_ICSelection, + TIM_ICInitStruct->TIM_ICFilter); + TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + } + else if(TIM_ICInitStruct->TIM_Channel == TIM_Channel_3) + { + TI3_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, + TIM_ICInitStruct->TIM_ICSelection, + TIM_ICInitStruct->TIM_ICFilter); + TIM_SetIC3Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + } + else + { + TI4_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, + TIM_ICInitStruct->TIM_ICSelection, + TIM_ICInitStruct->TIM_ICFilter); + TIM_SetIC4Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + } +} + +/********************************************************************* + * @fn TIM_PWMIConfig + * + * @brief Configures the TIM peripheral according to the specified + * parameters in the TIM_ICInitStruct to measure an external + * PWM signal. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_ICInitStruct - pointer to a TIM_ICInitTypeDef structure. + * + * @return none + */ +void TIM_PWMIConfig(TIM_TypeDef *TIMx, TIM_ICInitTypeDef *TIM_ICInitStruct) +{ + uint16_t icoppositepolarity = TIM_ICPolarity_Rising; + uint16_t icoppositeselection = TIM_ICSelection_DirectTI; + + if(TIM_ICInitStruct->TIM_ICPolarity == TIM_ICPolarity_Rising) + { + icoppositepolarity = TIM_ICPolarity_Falling; + } + else + { + icoppositepolarity = TIM_ICPolarity_Rising; + } + + if(TIM_ICInitStruct->TIM_ICSelection == TIM_ICSelection_DirectTI) + { + icoppositeselection = TIM_ICSelection_IndirectTI; + } + else + { + icoppositeselection = TIM_ICSelection_DirectTI; + } + + if(TIM_ICInitStruct->TIM_Channel == TIM_Channel_1) + { + TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection, + TIM_ICInitStruct->TIM_ICFilter); + TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + TI2_Config(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter); + TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + } + else + { + TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection, + TIM_ICInitStruct->TIM_ICFilter); + TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + TI1_Config(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter); + TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + } +} + +/********************************************************************* + * @fn TIM_BDTRConfig + * + * @brief Configures the: Break feature, dead time, Lock level, the OSSI, + * the OSSR State and the AOE(automatic output enable). + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_BDTRInitStruct - pointer to a TIM_BDTRInitTypeDef structure. + * + * @return none + */ +void TIM_BDTRConfig(TIM_TypeDef *TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct) +{ + TIMx->BDTR = (uint32_t)TIM_BDTRInitStruct->TIM_OSSRState | TIM_BDTRInitStruct->TIM_OSSIState | + TIM_BDTRInitStruct->TIM_LOCKLevel | TIM_BDTRInitStruct->TIM_DeadTime | + TIM_BDTRInitStruct->TIM_Break | TIM_BDTRInitStruct->TIM_BreakPolarity | + TIM_BDTRInitStruct->TIM_AutomaticOutput; +} + +/********************************************************************* + * @fn TIM_TimeBaseStructInit + * + * @brief Fills each TIM_TimeBaseInitStruct member with its default value. + * + * @param TIM_TimeBaseInitStruct - pointer to a TIM_TimeBaseInitTypeDef structure. + * + * @return none + */ +void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef *TIM_TimeBaseInitStruct) +{ + TIM_TimeBaseInitStruct->TIM_Period = 0xFFFF; + TIM_TimeBaseInitStruct->TIM_Prescaler = 0x0000; + TIM_TimeBaseInitStruct->TIM_ClockDivision = TIM_CKD_DIV1; + TIM_TimeBaseInitStruct->TIM_CounterMode = TIM_CounterMode_Up; + TIM_TimeBaseInitStruct->TIM_RepetitionCounter = 0x0000; +} + +/********************************************************************* + * @fn TIM_OCStructInit + * + * @brief Fills each TIM_OCInitStruct member with its default value. + * + * @param TIM_OCInitStruct - pointer to a TIM_OCInitTypeDef structure. + * + * @return none + */ +void TIM_OCStructInit(TIM_OCInitTypeDef *TIM_OCInitStruct) +{ + TIM_OCInitStruct->TIM_OCMode = TIM_OCMode_Timing; + TIM_OCInitStruct->TIM_OutputState = TIM_OutputState_Disable; + TIM_OCInitStruct->TIM_OutputNState = TIM_OutputNState_Disable; + TIM_OCInitStruct->TIM_Pulse = 0x0000; + TIM_OCInitStruct->TIM_OCPolarity = TIM_OCPolarity_High; + TIM_OCInitStruct->TIM_OCNPolarity = TIM_OCPolarity_High; + TIM_OCInitStruct->TIM_OCIdleState = TIM_OCIdleState_Reset; + TIM_OCInitStruct->TIM_OCNIdleState = TIM_OCNIdleState_Reset; +} + +/********************************************************************* + * @fn TIM_ICStructInit + * + * @brief Fills each TIM_ICInitStruct member with its default value. + * + * @param TIM_ICInitStruct - pointer to a TIM_ICInitTypeDef structure. + * + * @return none + */ +void TIM_ICStructInit(TIM_ICInitTypeDef *TIM_ICInitStruct) +{ + TIM_ICInitStruct->TIM_Channel = TIM_Channel_1; + TIM_ICInitStruct->TIM_ICPolarity = TIM_ICPolarity_Rising; + TIM_ICInitStruct->TIM_ICSelection = TIM_ICSelection_DirectTI; + TIM_ICInitStruct->TIM_ICPrescaler = TIM_ICPSC_DIV1; + TIM_ICInitStruct->TIM_ICFilter = 0x00; +} + +/********************************************************************* + * @fn TIM_BDTRStructInit + * + * @brief Fills each TIM_BDTRInitStruct member with its default value. + * + * @param TIM_BDTRInitStruct - pointer to a TIM_BDTRInitTypeDef structure. + * + * @return none + */ +void TIM_BDTRStructInit(TIM_BDTRInitTypeDef *TIM_BDTRInitStruct) +{ + TIM_BDTRInitStruct->TIM_OSSRState = TIM_OSSRState_Disable; + TIM_BDTRInitStruct->TIM_OSSIState = TIM_OSSIState_Disable; + TIM_BDTRInitStruct->TIM_LOCKLevel = TIM_LOCKLevel_OFF; + TIM_BDTRInitStruct->TIM_DeadTime = 0x00; + TIM_BDTRInitStruct->TIM_Break = TIM_Break_Disable; + TIM_BDTRInitStruct->TIM_BreakPolarity = TIM_BreakPolarity_Low; + TIM_BDTRInitStruct->TIM_AutomaticOutput = TIM_AutomaticOutput_Disable; +} + +/********************************************************************* + * @fn TIM_Cmd + * + * @brief Enables or disables the specified TIM peripheral. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void TIM_Cmd(TIM_TypeDef *TIMx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + TIMx->CTLR1 |= TIM_CEN; + } + else + { + TIMx->CTLR1 &= (uint16_t)(~((uint16_t)TIM_CEN)); + } +} + +/********************************************************************* + * @fn TIM_CtrlPWMOutputs + * + * @brief Enables or disables the TIM peripheral Main Outputs. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void TIM_CtrlPWMOutputs(TIM_TypeDef *TIMx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + TIMx->BDTR |= TIM_MOE; + } + else + { + TIMx->BDTR &= (uint16_t)(~((uint16_t)TIM_MOE)); + } +} + +/********************************************************************* + * @fn TIM_ITConfig + * + * @brief Enables or disables the specified TIM interrupts. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_IT - specifies the TIM interrupts sources to be enabled or disabled. + * TIM_IT_Update - TIM update Interrupt source. + * TIM_IT_CC1 - TIM Capture Compare 1 Interrupt source. + * TIM_IT_CC2 - TIM Capture Compare 2 Interrupt source + * TIM_IT_CC3 - TIM Capture Compare 3 Interrupt source. + * TIM_IT_CC4 - TIM Capture Compare 4 Interrupt source. + * TIM_IT_COM - TIM Commutation Interrupt source. + * TIM_IT_Trigger - TIM Trigger Interrupt source. + * TIM_IT_Break - TIM Break Interrupt source. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void TIM_ITConfig(TIM_TypeDef *TIMx, uint16_t TIM_IT, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + TIMx->DMAINTENR |= TIM_IT; + } + else + { + TIMx->DMAINTENR &= (uint16_t)~TIM_IT; + } +} + +/******************************************************************************* + * @fn TIM_GenerateEvent + * + * @brief Configures the TIMx event to be generate by software. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_EventSource - specifies the event source. + * TIM_EventSource_Update - Timer update Event source. + * TIM_EventSource_CC1 - Timer Capture Compare 1 Event source. + * TIM_EventSource_CC2 - Timer Capture Compare 2 Event source. + * TIM_EventSource_CC3 - Timer Capture Compare 3 Event source. + * TIM_EventSource_CC4 - Timer Capture Compare 4 Event source. + * TIM_EventSource_COM - Timer COM event source. + * TIM_EventSource_Trigger - Timer Trigger Event source. + * TIM_EventSource_Break - Timer Break event source. + * + * @return None + */ +void TIM_GenerateEvent(TIM_TypeDef *TIMx, uint16_t TIM_EventSource) +{ + TIMx->SWEVGR = TIM_EventSource; +} + +/********************************************************************* + * @fn TIM_DMAConfig + * + * @brief Configures the TIMx's DMA interface. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_DMABase - DMA Base address. + * TIM_DMABase_CR. + * TIM_DMABase_CR2. + * TIM_DMABase_SMCR. + * TIM_DMABase_DIER. + * TIM1_DMABase_SR. + * TIM_DMABase_EGR. + * TIM_DMABase_CCMR1. + * TIM_DMABase_CCMR2. + * TIM_DMABase_CCER. + * TIM_DMABase_CNT. + * TIM_DMABase_PSC. + * TIM_DMABase_CCR1. + * TIM_DMABase_CCR2. + * TIM_DMABase_CCR3. + * TIM_DMABase_CCR4. + * TIM_DMABase_BDTR. + * TIM_DMABase_DCR. + * TIM_DMABurstLength - DMA Burst length. + * TIM_DMABurstLength_1Transfer. + * TIM_DMABurstLength_18Transfers. + * + * @return none + */ +void TIM_DMAConfig(TIM_TypeDef *TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength) +{ + TIMx->DMACFGR = TIM_DMABase | TIM_DMABurstLength; +} + +/********************************************************************* + * @fn TIM_DMACmd + * + * @brief Enables or disables the TIMx's DMA Requests. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_DMASource - specifies the DMA Request sources. + * TIM_DMA_Update - TIM update Interrupt source. + * TIM_DMA_CC1 - TIM Capture Compare 1 DMA source. + * TIM_DMA_CC2 - TIM Capture Compare 2 DMA source. + * TIM_DMA_CC3 - TIM Capture Compare 3 DMA source. + * TIM_DMA_CC4 - TIM Capture Compare 4 DMA source. + * TIM_DMA_COM - TIM Commutation DMA source. + * TIM_DMA_Trigger - TIM Trigger DMA source. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void TIM_DMACmd(TIM_TypeDef *TIMx, uint16_t TIM_DMASource, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + TIMx->DMAINTENR |= TIM_DMASource; + } + else + { + TIMx->DMAINTENR &= (uint16_t)~TIM_DMASource; + } +} + +/********************************************************************* + * @fn TIM_InternalClockConfig + * + * @brief Configures the TIMx internal Clock. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * + * @return none + */ +void TIM_InternalClockConfig(TIM_TypeDef *TIMx) +{ + TIMx->SMCFGR &= (uint16_t)(~((uint16_t)TIM_SMS)); +} + +/********************************************************************* + * @fn TIM_ITRxExternalClockConfig + * + * @brief Configures the TIMx Internal Trigger as External Clock. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_InputTriggerSource: Trigger source. + * TIM_TS_ITR0 - Internal Trigger 0. + * TIM_TS_ITR1 - Internal Trigger 1. + * TIM_TS_ITR2 - Internal Trigger 2. + * TIM_TS_ITR3 - Internal Trigger 3. + * + * @return none + */ +void TIM_ITRxExternalClockConfig(TIM_TypeDef *TIMx, uint16_t TIM_InputTriggerSource) +{ + TIM_SelectInputTrigger(TIMx, TIM_InputTriggerSource); + TIMx->SMCFGR |= TIM_SlaveMode_External1; +} + +/********************************************************************* + * @fn TIM_TIxExternalClockConfig + * + * @brief Configures the TIMx Trigger as External Clock. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_TIxExternalCLKSource - Trigger source. + * TIM_TIxExternalCLK1Source_TI1ED - TI1 Edge Detector. + * TIM_TIxExternalCLK1Source_TI1 - Filtered Timer Input 1. + * TIM_TIxExternalCLK1Source_TI2 - Filtered Timer Input 2. + * TIM_ICPolarity - specifies the TIx Polarity. + * TIM_ICPolarity_Rising. + * TIM_ICPolarity_Falling. + * TIM_DMA_COM - TIM Commutation DMA source. + * TIM_DMA_Trigger - TIM Trigger DMA source. + * ICFilter - specifies the filter value. + * This parameter must be a value between 0x0 and 0xF. + * + * @return none + */ +void TIM_TIxExternalClockConfig(TIM_TypeDef *TIMx, uint16_t TIM_TIxExternalCLKSource, + uint16_t TIM_ICPolarity, uint16_t ICFilter) +{ + if(TIM_TIxExternalCLKSource == TIM_TIxExternalCLK1Source_TI2) + { + TI2_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter); + } + else + { + TI1_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter); + } + + TIM_SelectInputTrigger(TIMx, TIM_TIxExternalCLKSource); + TIMx->SMCFGR |= TIM_SlaveMode_External1; +} + +/********************************************************************* + * @fn TIM_ETRClockMode1Config + * + * @brief Configures the External clock Mode1. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_ExtTRGPrescaler - The external Trigger Prescaler. + * TIM_ExtTRGPSC_OFF - ETRP Prescaler OFF. + * TIM_ExtTRGPSC_DIV2 - ETRP frequency divided by 2. + * TIM_ExtTRGPSC_DIV4 - ETRP frequency divided by 4. + * TIM_ExtTRGPSC_DIV8 - ETRP frequency divided by 8. + * TIM_ExtTRGPolarity - The external Trigger Polarity. + * TIM_ExtTRGPolarity_Inverted - active low or falling edge active. + * TIM_ExtTRGPolarity_NonInverted - active high or rising edge active. + * ExtTRGFilter - External Trigger Filter. + * This parameter must be a value between 0x0 and 0xF. + * + * @return none + */ +void TIM_ETRClockMode1Config(TIM_TypeDef *TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, + uint16_t ExtTRGFilter) +{ + uint16_t tmpsmcr = 0; + + TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter); + tmpsmcr = TIMx->SMCFGR; + tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMS)); + tmpsmcr |= TIM_SlaveMode_External1; + tmpsmcr &= (uint16_t)(~((uint16_t)TIM_TS)); + tmpsmcr |= TIM_TS_ETRF; + TIMx->SMCFGR = tmpsmcr; +} + +/********************************************************************* + * @fn TIM_ETRClockMode2Config + * + * @brief Configures the External clock Mode2. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_ExtTRGPrescaler - The external Trigger Prescaler. + * TIM_ExtTRGPSC_OFF - ETRP Prescaler OFF. + * TIM_ExtTRGPSC_DIV2 - ETRP frequency divided by 2. + * TIM_ExtTRGPSC_DIV4 - ETRP frequency divided by 4. + * TIM_ExtTRGPSC_DIV8 - ETRP frequency divided by 8. + * TIM_ExtTRGPolarity - The external Trigger Polarity. + * TIM_ExtTRGPolarity_Inverted - active low or falling edge active. + * TIM_ExtTRGPolarity_NonInverted - active high or rising edge active. + * ExtTRGFilter - External Trigger Filter. + * This parameter must be a value between 0x0 and 0xF. + * + * @return none + */ +void TIM_ETRClockMode2Config(TIM_TypeDef *TIMx, uint16_t TIM_ExtTRGPrescaler, + uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter) +{ + TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter); + TIMx->SMCFGR |= TIM_ECE; +} + +/********************************************************************* + * @fn TIM_ETRConfig + * + * @brief Configures the TIMx External Trigger (ETR). + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_ExtTRGPrescaler - The external Trigger Prescaler. + * TIM_ExtTRGPSC_OFF - ETRP Prescaler OFF. + * TIM_ExtTRGPSC_DIV2 - ETRP frequency divided by 2. + * TIM_ExtTRGPSC_DIV4 - ETRP frequency divided by 4. + * TIM_ExtTRGPSC_DIV8 - ETRP frequency divided by 8. + * TIM_ExtTRGPolarity - The external Trigger Polarity. + * TIM_ExtTRGPolarity_Inverted - active low or falling edge active. + * TIM_ExtTRGPolarity_NonInverted - active high or rising edge active. + * ExtTRGFilter - External Trigger Filter. + * This parameter must be a value between 0x0 and 0xF. + * + * @return none + */ +void TIM_ETRConfig(TIM_TypeDef *TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, + uint16_t ExtTRGFilter) +{ + uint16_t tmpsmcr = 0; + + tmpsmcr = TIMx->SMCFGR; + tmpsmcr &= SMCFGR_ETR_Mask; + tmpsmcr |= (uint16_t)(TIM_ExtTRGPrescaler | (uint16_t)(TIM_ExtTRGPolarity | (uint16_t)(ExtTRGFilter << (uint16_t)8))); + TIMx->SMCFGR = tmpsmcr; +} + +/********************************************************************* + * @fn TIM_PrescalerConfig + * + * @brief Configures the TIMx Prescaler. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * Prescaler - specifies the Prescaler Register value. + * TIM_PSCReloadMode - specifies the TIM Prescaler Reload mode. + * TIM_PSCReloadMode - specifies the TIM Prescaler Reload mode. + * TIM_PSCReloadMode_Update - The Prescaler is loaded at the update event. + * TIM_PSCReloadMode_Immediate - The Prescaler is loaded immediately. + * + * @return none + */ +void TIM_PrescalerConfig(TIM_TypeDef *TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode) +{ + TIMx->PSC = Prescaler; + TIMx->SWEVGR = TIM_PSCReloadMode; +} + +/********************************************************************* + * @fn TIM_CounterModeConfig + * + * @brief Specifies the TIMx Counter Mode to be used. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_CounterMode - specifies the Counter Mode to be used. + * TIM_CounterMode_Up - TIM Up Counting Mode. + * TIM_CounterMode_Down - TIM Down Counting Mode. + * TIM_CounterMode_CenterAligned1 - TIM Center Aligned Mode1. + * TIM_CounterMode_CenterAligned2 - TIM Center Aligned Mode2. + * TIM_CounterMode_CenterAligned3 - TIM Center Aligned Mode3. + * + * @return none + */ +void TIM_CounterModeConfig(TIM_TypeDef *TIMx, uint16_t TIM_CounterMode) +{ + uint16_t tmpcr1 = 0; + + tmpcr1 = TIMx->CTLR1; + tmpcr1 &= (uint16_t)(~((uint16_t)(TIM_DIR | TIM_CMS))); + tmpcr1 |= TIM_CounterMode; + TIMx->CTLR1 = tmpcr1; +} + +/********************************************************************* + * @fn TIM_SelectInputTrigger + * + * @brief Selects the Input Trigger source. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_InputTriggerSource - The Input Trigger source. + * TIM_TS_ITR0 - Internal Trigger 0. + * TIM_TS_ITR1 - Internal Trigger 1. + * TIM_TS_ITR2 - Internal Trigger 2. + * TIM_TS_ITR3 - Internal Trigger 3. + * TIM_TS_TI1F_ED - TI1 Edge Detector. + * TIM_TS_TI1FP1 - Filtered Timer Input 1. + * TIM_TS_TI2FP2 - Filtered Timer Input 2. + * TIM_TS_ETRF - External Trigger input. + * + * @return none + */ +void TIM_SelectInputTrigger(TIM_TypeDef *TIMx, uint16_t TIM_InputTriggerSource) +{ + uint16_t tmpsmcr = 0; + + tmpsmcr = TIMx->SMCFGR; + tmpsmcr &= (uint16_t)(~((uint16_t)TIM_TS)); + tmpsmcr |= TIM_InputTriggerSource; + TIMx->SMCFGR = tmpsmcr; +} + +/********************************************************************* + * @fn TIM_EncoderInterfaceConfig + * + * @brief Configures the TIMx Encoder Interface. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_EncoderMode - specifies the TIMx Encoder Mode. + * TIM_EncoderMode_TI1 - Counter counts on TI1FP1 edge depending + * on TI2FP2 level. + * TIM_EncoderMode_TI2 - Counter counts on TI2FP2 edge depending + * on TI1FP1 level. + * TIM_EncoderMode_TI12 - Counter counts on both TI1FP1 and + * TI2FP2 edges depending. + * TIM_IC1Polarity - specifies the IC1 Polarity. + * TIM_ICPolarity_Falling - IC Falling edge. + * TTIM_ICPolarity_Rising - IC Rising edge. + * TIM_IC2Polarity - specifies the IC2 Polarity. + * TIM_ICPolarity_Falling - IC Falling edge. + * TIM_ICPolarity_Rising - IC Rising edge. + * + * @return none + */ +void TIM_EncoderInterfaceConfig(TIM_TypeDef *TIMx, uint16_t TIM_EncoderMode, + uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity) +{ + uint16_t tmpsmcr = 0; + uint16_t tmpccmr1 = 0; + uint16_t tmpccer = 0; + + tmpsmcr = TIMx->SMCFGR; + tmpccmr1 = TIMx->CHCTLR1; + tmpccer = TIMx->CCER; + tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMS)); + tmpsmcr |= TIM_EncoderMode; + tmpccmr1 &= (uint16_t)(((uint16_t) ~((uint16_t)TIM_CC1S)) & (uint16_t)(~((uint16_t)TIM_CC2S))); + tmpccmr1 |= TIM_CC1S_0 | TIM_CC2S_0; + tmpccer &= (uint16_t)(((uint16_t) ~((uint16_t)TIM_CC1P)) & ((uint16_t) ~((uint16_t)TIM_CC2P))); + tmpccer |= (uint16_t)(TIM_IC1Polarity | (uint16_t)(TIM_IC2Polarity << (uint16_t)4)); + TIMx->SMCFGR = tmpsmcr; + TIMx->CHCTLR1 = tmpccmr1; + TIMx->CCER = tmpccer; +} + +/********************************************************************* + * @fn TIM_ForcedOC1Config + * + * @brief Forces the TIMx output 1 waveform to active or inactive level. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_ForcedAction - specifies the forced Action to be set to the + * output waveform. + * TIM_ForcedAction_Active - Force active level on OC1REF. + * TIM_ForcedAction_InActive - Force inactive level on OC1REF. + * + * @return none + */ +void TIM_ForcedOC1Config(TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction) +{ + uint16_t tmpccmr1 = 0; + + tmpccmr1 = TIMx->CHCTLR1; + tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_OC1M); + tmpccmr1 |= TIM_ForcedAction; + TIMx->CHCTLR1 = tmpccmr1; +} + +/********************************************************************* + * @fn TIM_ForcedOC2Config + * + * @brief Forces the TIMx output 2 waveform to active or inactive level. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_ForcedAction - specifies the forced Action to be set to the + * output waveform. + * TIM_ForcedAction_Active - Force active level on OC2REF. + * TIM_ForcedAction_InActive - Force inactive level on OC2REF. + * + * @return none + */ +void TIM_ForcedOC2Config(TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction) +{ + uint16_t tmpccmr1 = 0; + + tmpccmr1 = TIMx->CHCTLR1; + tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_OC2M); + tmpccmr1 |= (uint16_t)(TIM_ForcedAction << 8); + TIMx->CHCTLR1 = tmpccmr1; +} + +/********************************************************************* + * @fn TIM_ForcedOC3Config + * + * @brief Forces the TIMx output 3 waveform to active or inactive level. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_ForcedAction - specifies the forced Action to be set to the + * output waveform. + * TIM_ForcedAction_Active - Force active level on OC3REF. + * TIM_ForcedAction_InActive - Force inactive level on OC3REF. + * + * @return none + */ +void TIM_ForcedOC3Config(TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction) +{ + uint16_t tmpccmr2 = 0; + + tmpccmr2 = TIMx->CHCTLR2; + tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_OC3M); + tmpccmr2 |= TIM_ForcedAction; + TIMx->CHCTLR2 = tmpccmr2; +} + +/********************************************************************* + * @fn TIM_ForcedOC4Config + * + * @brief Forces the TIMx output 4 waveform to active or inactive level. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_ForcedAction - specifies the forced Action to be set to the + * output waveform. + * TIM_ForcedAction_Active - Force active level on OC4REF. + * TIM_ForcedAction_InActive - Force inactive level on OC4REF. + * + * @return none + */ +void TIM_ForcedOC4Config(TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction) +{ + uint16_t tmpccmr2 = 0; + + tmpccmr2 = TIMx->CHCTLR2; + tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_OC4M); + tmpccmr2 |= (uint16_t)(TIM_ForcedAction << 8); + TIMx->CHCTLR2 = tmpccmr2; +} + +/********************************************************************* + * @fn TIM_ARRPreloadConfig + * + * @brief Enables or disables TIMx peripheral Preload register on ARR. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void TIM_ARRPreloadConfig(TIM_TypeDef *TIMx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + TIMx->CTLR1 |= TIM_ARPE; + } + else + { + TIMx->CTLR1 &= (uint16_t) ~((uint16_t)TIM_ARPE); + } +} + +/********************************************************************* + * @fn TIM_SelectCOM + * + * @brief Selects the TIM peripheral Commutation event. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void TIM_SelectCOM(TIM_TypeDef *TIMx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + TIMx->CTLR2 |= TIM_CCUS; + } + else + { + TIMx->CTLR2 &= (uint16_t) ~((uint16_t)TIM_CCUS); + } +} + +/********************************************************************* + * @fn TIM_SelectCCDMA + * + * @brief Selects the TIMx peripheral Capture Compare DMA source. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void TIM_SelectCCDMA(TIM_TypeDef *TIMx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + TIMx->CTLR2 |= TIM_CCDS; + } + else + { + TIMx->CTLR2 &= (uint16_t) ~((uint16_t)TIM_CCDS); + } +} + +/********************************************************************* + * @fn TIM_CCPreloadControl + * + * @brief DSets or Resets the TIM peripheral Capture Compare Preload Control bit. + * reset values. + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void TIM_CCPreloadControl(TIM_TypeDef *TIMx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + TIMx->CTLR2 |= TIM_CCPC; + } + else + { + TIMx->CTLR2 &= (uint16_t) ~((uint16_t)TIM_CCPC); + } +} + +/********************************************************************* + * @fn TIM_OC1PreloadConfig + * + * @brief Enables or disables the TIMx peripheral Preload register on CCR1. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_OCPreload - new state of the TIMx peripheral Preload register. + * TIM_OCPreload_Enable. + * TIM_OCPreload_Disable. + * + * @return none + */ +void TIM_OC1PreloadConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPreload) +{ + uint16_t tmpccmr1 = 0; + + tmpccmr1 = TIMx->CHCTLR1; + tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_OC1PE); + tmpccmr1 |= TIM_OCPreload; + TIMx->CHCTLR1 = tmpccmr1; +} + +/********************************************************************* + * @fn TIM_OC2PreloadConfig + * + * @brief Enables or disables the TIMx peripheral Preload register on CCR2. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_OCPreload - new state of the TIMx peripheral Preload register. + * TIM_OCPreload_Enable. + * TIM_OCPreload_Disable. + * + * @return none + */ +void TIM_OC2PreloadConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPreload) +{ + uint16_t tmpccmr1 = 0; + + tmpccmr1 = TIMx->CHCTLR1; + tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_OC2PE); + tmpccmr1 |= (uint16_t)(TIM_OCPreload << 8); + TIMx->CHCTLR1 = tmpccmr1; +} + +/********************************************************************* + * @fn TIM_OC3PreloadConfig + * + * @brief Enables or disables the TIMx peripheral Preload register on CCR3. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_OCPreload - new state of the TIMx peripheral Preload register. + * TIM_OCPreload_Enable. + * TIM_OCPreload_Disable. + * + * @return none + */ +void TIM_OC3PreloadConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPreload) +{ + uint16_t tmpccmr2 = 0; + + tmpccmr2 = TIMx->CHCTLR2; + tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_OC3PE); + tmpccmr2 |= TIM_OCPreload; + TIMx->CHCTLR2 = tmpccmr2; +} + +/********************************************************************* + * @fn TIM_OC4PreloadConfig + * + * @brief Enables or disables the TIMx peripheral Preload register on CCR4. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_OCPreload - new state of the TIMx peripheral Preload register. + * TIM_OCPreload_Enable. + * TIM_OCPreload_Disable. + * + * @return none + */ +void TIM_OC4PreloadConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPreload) +{ + uint16_t tmpccmr2 = 0; + + tmpccmr2 = TIMx->CHCTLR2; + tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_OC4PE); + tmpccmr2 |= (uint16_t)(TIM_OCPreload << 8); + TIMx->CHCTLR2 = tmpccmr2; +} + +/********************************************************************* + * @fn TIM_OC1FastConfig + * + * @brief Configures the TIMx Output Compare 1 Fast feature. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_OCFast - new state of the Output Compare Fast Enable Bit. + * TIM_OCFast_Enable - TIM output compare fast enable. + * TIM_OCFast_Disable - TIM output compare fast disable. + * + * @return none + */ +void TIM_OC1FastConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCFast) +{ + uint16_t tmpccmr1 = 0; + + tmpccmr1 = TIMx->CHCTLR1; + tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_OC1FE); + tmpccmr1 |= TIM_OCFast; + TIMx->CHCTLR1 = tmpccmr1; +} + +/********************************************************************* + * @fn TIM_OC2FastConfig + * + * @brief Configures the TIMx Output Compare 2 Fast feature. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_OCFast - new state of the Output Compare Fast Enable Bit. + * TIM_OCFast_Enable - TIM output compare fast enable. + * TIM_OCFast_Disable - TIM output compare fast disable. + * + * @return none + */ +void TIM_OC2FastConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCFast) +{ + uint16_t tmpccmr1 = 0; + + tmpccmr1 = TIMx->CHCTLR1; + tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_OC2FE); + tmpccmr1 |= (uint16_t)(TIM_OCFast << 8); + TIMx->CHCTLR1 = tmpccmr1; +} + +/********************************************************************* + * @fn TIM_OC3FastConfig + * + * @brief Configures the TIMx Output Compare 3 Fast feature. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_OCFast - new state of the Output Compare Fast Enable Bit. + * TIM_OCFast_Enable - TIM output compare fast enable. + * TIM_OCFast_Disable - TIM output compare fast disable. + * + * @return none + */ +void TIM_OC3FastConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCFast) +{ + uint16_t tmpccmr2 = 0; + + tmpccmr2 = TIMx->CHCTLR2; + tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_OC3FE); + tmpccmr2 |= TIM_OCFast; + TIMx->CHCTLR2 = tmpccmr2; +} + +/********************************************************************* + * @fn TIM_OC4FastConfig + * + * @brief Configures the TIMx Output Compare 4 Fast feature. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_OCFast - new state of the Output Compare Fast Enable Bit. + * TIM_OCFast_Enable - TIM output compare fast enable. + * TIM_OCFast_Disable - TIM output compare fast disable. + * + * @return none + */ +void TIM_OC4FastConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCFast) +{ + uint16_t tmpccmr2 = 0; + + tmpccmr2 = TIMx->CHCTLR2; + tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_OC4FE); + tmpccmr2 |= (uint16_t)(TIM_OCFast << 8); + TIMx->CHCTLR2 = tmpccmr2; +} + +/********************************************************************* + * @fn TIM_ClearOC1Ref + * + * @brief Clears or safeguards the OCREF1 signal on an external event. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_OCClear - new state of the Output Compare Clear Enable Bit. + * TIM_OCClear_Enable - TIM Output clear enable. + * TIM_OCClear_Disable - TIM Output clear disable. + * + * @return none + */ +void TIM_ClearOC1Ref(TIM_TypeDef *TIMx, uint16_t TIM_OCClear) +{ + uint16_t tmpccmr1 = 0; + + tmpccmr1 = TIMx->CHCTLR1; + tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_OC1CE); + tmpccmr1 |= TIM_OCClear; + TIMx->CHCTLR1 = tmpccmr1; +} + +/********************************************************************* + * @fn TIM_ClearOC2Ref + * + * @brief Clears or safeguards the OCREF2 signal on an external event. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_OCClear - new state of the Output Compare Clear Enable Bit. + * TIM_OCClear_Enable - TIM Output clear enable. + * TIM_OCClear_Disable - TIM Output clear disable. + * + * @return none + */ +void TIM_ClearOC2Ref(TIM_TypeDef *TIMx, uint16_t TIM_OCClear) +{ + uint16_t tmpccmr1 = 0; + + tmpccmr1 = TIMx->CHCTLR1; + tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_OC2CE); + tmpccmr1 |= (uint16_t)(TIM_OCClear << 8); + TIMx->CHCTLR1 = tmpccmr1; +} + +/********************************************************************* + * @fn TIM_ClearOC3Ref + * + * @brief Clears or safeguards the OCREF3 signal on an external event. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_OCClear - new state of the Output Compare Clear Enable Bit. + * TIM_OCClear_Enable - TIM Output clear enable. + * TIM_OCClear_Disable - TIM Output clear disable. + * + * @return none + */ +void TIM_ClearOC3Ref(TIM_TypeDef *TIMx, uint16_t TIM_OCClear) +{ + uint16_t tmpccmr2 = 0; + + tmpccmr2 = TIMx->CHCTLR2; + tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_OC3CE); + tmpccmr2 |= TIM_OCClear; + TIMx->CHCTLR2 = tmpccmr2; +} + +/********************************************************************* + * @fn TIM_ClearOC4Ref + * + * @brief Clears or safeguards the OCREF4 signal on an external event. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_OCClear - new state of the Output Compare Clear Enable Bit. + * TIM_OCClear_Enable - TIM Output clear enable. + * TIM_OCClear_Disable - TIM Output clear disable. + * + * @return none + */ +void TIM_ClearOC4Ref(TIM_TypeDef *TIMx, uint16_t TIM_OCClear) +{ + uint16_t tmpccmr2 = 0; + + tmpccmr2 = TIMx->CHCTLR2; + tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_OC4CE); + tmpccmr2 |= (uint16_t)(TIM_OCClear << 8); + TIMx->CHCTLR2 = tmpccmr2; +} + +/********************************************************************* + * @fn TIM_OC1PolarityConfig + * + * @brief Configures the TIMx channel 1 polarity. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_OCPolarity - specifies the OC1 Polarity. + * TIM_OCPolarity_High - Output Compare active high. + * TIM_OCPolarity_Low - Output Compare active low. + * + * @return none + */ +void TIM_OC1PolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity) +{ + uint16_t tmpccer = 0; + + tmpccer = TIMx->CCER; + tmpccer &= (uint16_t) ~((uint16_t)TIM_CC1P); + tmpccer |= TIM_OCPolarity; + TIMx->CCER = tmpccer; +} + +/********************************************************************* + * @fn TIM_OC1NPolarityConfig + * + * @brief Configures the TIMx channel 1 polarity. + * + * @param TIMx - where x can be 1 to select the TIM peripheral. + * TIM_OCNPolarity - specifies the OC1N Polarity. + * TIM_OCNPolarity_High - Output Compare active high. + * TIM_OCNPolarity_Low - Output Compare active low. + * + * @return none + */ +void TIM_OC1NPolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCNPolarity) +{ + uint16_t tmpccer = 0; + + tmpccer = TIMx->CCER; + tmpccer &= (uint16_t) ~((uint16_t)TIM_CC1NP); + tmpccer |= TIM_OCNPolarity; + TIMx->CCER = tmpccer; +} + +/********************************************************************* + * @fn TIM_OC2PolarityConfig + * + * @brief Configures the TIMx channel 2 polarity. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_OCPolarity - specifies the OC2 Polarity. + * TIM_OCPolarity_High - Output Compare active high. + * TIM_OCPolarity_Low - Output Compare active low. + * + * @return none + */ +void TIM_OC2PolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity) +{ + uint16_t tmpccer = 0; + + tmpccer = TIMx->CCER; + tmpccer &= (uint16_t) ~((uint16_t)TIM_CC2P); + tmpccer |= (uint16_t)(TIM_OCPolarity << 4); + TIMx->CCER = tmpccer; +} + +/********************************************************************* + * @fn TIM_OC2NPolarityConfig + * + * @brief Configures the TIMx channel 2 polarity. + * + * @param TIMx - where x can be 1 to select the TIM peripheral. + * TIM_OCNPolarity - specifies the OC1N Polarity. + * TIM_OCNPolarity_High - Output Compare active high. + * TIM_OCNPolarity_Low - Output Compare active low. + * + * @return none + */ +void TIM_OC2NPolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCNPolarity) +{ + uint16_t tmpccer = 0; + + tmpccer = TIMx->CCER; + tmpccer &= (uint16_t) ~((uint16_t)TIM_CC2NP); + tmpccer |= (uint16_t)(TIM_OCNPolarity << 4); + TIMx->CCER = tmpccer; +} + +/********************************************************************* + * @fn TIM_OC3PolarityConfig + * + * @brief Configures the TIMx Channel 3 polarity. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * TIM_OCPolarit - specifies the OC3 Polarity. + * TIM_OCPolarity_High - Output Compare active high. + * TIM_OCPolarity_Low - Output Compare active low. + * + * @return none + */ +void TIM_OC3PolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity) +{ + uint16_t tmpccer = 0; + + tmpccer = TIMx->CCER; + tmpccer &= (uint16_t) ~((uint16_t)TIM_CC3P); + tmpccer |= (uint16_t)(TIM_OCPolarity << 8); + TIMx->CCER = tmpccer; +} + +/********************************************************************* + * @fn TIM_OC3NPolarityConfig + * + * @brief Configures the TIMx Channel 3N polarity. + * + * @param TIMx - where x can be 1 to select the TIM peripheral. + * TIM_OCNPolarity - specifies the OC2N Polarity. + * TIM_OCNPolarity_High - Output Compare active high. + * TIM_OCNPolarity_Low - Output Compare active low. + * + * @return none + */ +void TIM_OC3NPolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCNPolarity) +{ + uint16_t tmpccer = 0; + + tmpccer = TIMx->CCER; + tmpccer &= (uint16_t) ~((uint16_t)TIM_CC3NP); + tmpccer |= (uint16_t)(TIM_OCNPolarity << 8); + TIMx->CCER = tmpccer; +} + +/********************************************************************* + * @fn TIM_OC4PolarityConfig + * + * @brief Configures the TIMx Channel 4 polarity. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * TIM_OCPolarit - specifies the OC3 Polarity. + * TIM_OCPolarity_High - Output Compare active high. + * TIM_OCPolarity_Low - Output Compare active low. + * + * @return none + */ +void TIM_OC4PolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity) +{ + uint16_t tmpccer = 0; + + tmpccer = TIMx->CCER; + tmpccer &= (uint16_t) ~((uint16_t)TIM_CC4P); + tmpccer |= (uint16_t)(TIM_OCPolarity << 12); + TIMx->CCER = tmpccer; +} + +/********************************************************************* + * @fn TIM_CCxCmd + * + * @brief Enables or disables the TIM Capture Compare Channel x. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * TIM_Channel - specifies the TIM Channel. + * TIM_Channel_1 - TIM Channel 1. + * TIM_Channel_2 - TIM Channel 2. + * TIM_Channel_3 - TIM Channel 3. + * TIM_Channel_4 - TIM Channel 4. + * TIM_CCx - specifies the TIM Channel CCxE bit new state. + * TIM_CCx_Enable. + * TIM_CCx_Disable. + * + * @return none + */ +void TIM_CCxCmd(TIM_TypeDef *TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx) +{ + uint16_t tmp = 0; + + tmp = CCER_CCE_Set << TIM_Channel; + TIMx->CCER &= (uint16_t)~tmp; + TIMx->CCER |= (uint16_t)(TIM_CCx << TIM_Channel); +} + +/********************************************************************* + * @fn TIM_CCxNCmd + * + * @brief Enables or disables the TIM Capture Compare Channel xN. + * + * @param TIMx - where x can be 1 select the TIM peripheral. + * TIM_Channel - specifies the TIM Channel. + * TIM_Channel_1 - TIM Channel 1. + * TIM_Channel_2 - TIM Channel 2. + * TIM_Channel_3 - TIM Channel 3. + * TIM_CCxN - specifies the TIM Channel CCxNE bit new state. + * TIM_CCxN_Enable. + * TIM_CCxN_Disable. + * + * @return none + */ +void TIM_CCxNCmd(TIM_TypeDef *TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN) +{ + uint16_t tmp = 0; + + tmp = CCER_CCNE_Set << TIM_Channel; + TIMx->CCER &= (uint16_t)~tmp; + TIMx->CCER |= (uint16_t)(TIM_CCxN << TIM_Channel); +} + +/********************************************************************* + * @fn TIM_SelectOCxM + * + * @brief Selects the TIM Output Compare Mode. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * TIM_Channel - specifies the TIM Channel. + * TIM_Channel_1 - TIM Channel 1. + * TIM_Channel_2 - TIM Channel 2. + * TIM_Channel_3 - TIM Channel 3. + * TIM_Channel_4 - TIM Channel 4. + * TIM_OCMode - specifies the TIM Output Compare Mode. + * TIM_OCMode_Timing. + * TIM_OCMode_Active. + * TIM_OCMode_Toggle. + * TIM_OCMode_PWM1. + * TIM_OCMode_PWM2. + * TIM_ForcedAction_Active. + * TIM_ForcedAction_InActive. + * + * @return none + */ +void TIM_SelectOCxM(TIM_TypeDef *TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode) +{ + uint32_t tmp = 0; + uint16_t tmp1 = 0; + + tmp = (uint32_t)TIMx; + tmp += CHCTLR_Offset; + tmp1 = CCER_CCE_Set << (uint16_t)TIM_Channel; + TIMx->CCER &= (uint16_t)~tmp1; + + if((TIM_Channel == TIM_Channel_1) || (TIM_Channel == TIM_Channel_3)) + { + tmp += (TIM_Channel >> 1); + *(__IO uint32_t *)tmp &= (uint32_t) ~((uint32_t)TIM_OC1M); + *(__IO uint32_t *)tmp |= TIM_OCMode; + } + else + { + tmp += (uint16_t)(TIM_Channel - (uint16_t)4) >> (uint16_t)1; + *(__IO uint32_t *)tmp &= (uint32_t) ~((uint32_t)TIM_OC2M); + *(__IO uint32_t *)tmp |= (uint16_t)(TIM_OCMode << 8); + } +} + +/********************************************************************* + * @fn TIM_UpdateDisableConfig + * + * @brief Enables or Disables the TIMx Update event. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void TIM_UpdateDisableConfig(TIM_TypeDef *TIMx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + TIMx->CTLR1 |= TIM_UDIS; + } + else + { + TIMx->CTLR1 &= (uint16_t) ~((uint16_t)TIM_UDIS); + } +} + +/********************************************************************* + * @fn TIM_UpdateRequestConfig + * + * @brief Configures the TIMx Update Request Interrupt source. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * TIM_UpdateSource - specifies the Update source. + * TIM_UpdateSource_Regular. + * TIM_UpdateSource_Global. + * + * @return none + */ +void TIM_UpdateRequestConfig(TIM_TypeDef *TIMx, uint16_t TIM_UpdateSource) +{ + if(TIM_UpdateSource != TIM_UpdateSource_Global) + { + TIMx->CTLR1 |= TIM_URS; + } + else + { + TIMx->CTLR1 &= (uint16_t) ~((uint16_t)TIM_URS); + } +} + +/********************************************************************* + * @fn TIM_SelectHallSensor + * + * @brief Enables or disables the TIMx's Hall sensor interface. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void TIM_SelectHallSensor(TIM_TypeDef *TIMx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + TIMx->CTLR2 |= TIM_TI1S; + } + else + { + TIMx->CTLR2 &= (uint16_t) ~((uint16_t)TIM_TI1S); + } +} + +/********************************************************************* + * @fn TIM_SelectOnePulseMode + * + * @brief Selects the TIMx's One Pulse Mode. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * TIM_OPMode - specifies the OPM Mode to be used. + * TIM_OPMode_Single. + * TIM_OPMode_Repetitive. + * + * @return none + */ +void TIM_SelectOnePulseMode(TIM_TypeDef *TIMx, uint16_t TIM_OPMode) +{ + TIMx->CTLR1 &= (uint16_t) ~((uint16_t)TIM_OPM); + TIMx->CTLR1 |= TIM_OPMode; +} + +/********************************************************************* + * @fn TIM_SelectOutputTrigger + * + * @brief Selects the TIMx Trigger Output Mode. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * TIM_TRGOSource - specifies the Trigger Output source. + * TIM_TRGOSource_Reset - The UG bit in the TIM_EGR register is + * used as the trigger output (TRGO). + * TIM_TRGOSource_Enable - The Counter Enable CEN is used as the + * trigger output (TRGO). + * TIM_TRGOSource_Update - The update event is selected as the + * trigger output (TRGO). + * TIM_TRGOSource_OC1 - The trigger output sends a positive pulse + * when the CC1IF flag is to be set, as soon as a capture or compare match occurs (TRGO). + * TIM_TRGOSource_OC1Ref - OC1REF signal is used as the trigger output (TRGO). + * TIM_TRGOSource_OC2Ref - OC2REF signal is used as the trigger output (TRGO). + * TIM_TRGOSource_OC3Ref - OC3REF signal is used as the trigger output (TRGO). + * TIM_TRGOSource_OC4Ref - OC4REF signal is used as the trigger output (TRGO). + * + * @return none + */ +void TIM_SelectOutputTrigger(TIM_TypeDef *TIMx, uint16_t TIM_TRGOSource) +{ + TIMx->CTLR2 &= (uint16_t) ~((uint16_t)TIM_MMS); + TIMx->CTLR2 |= TIM_TRGOSource; +} + +/********************************************************************* + * @fn TIM_SelectSlaveMode + * + * @brief Selects the TIMx Slave Mode. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * TIM_SlaveMode - specifies the Timer Slave Mode. + * TIM_SlaveMode_Reset - Rising edge of the selected trigger + * signal (TRGI) re-initializes. + * TIM_SlaveMode_Gated - The counter clock is enabled when the + * trigger signal (TRGI) is high. + * TIM_SlaveMode_Trigger - The counter starts at a rising edge + * of the trigger TRGI. + * TIM_SlaveMode_External1 - Rising edges of the selected trigger + * (TRGI) clock the counter. + * + * @return none + */ +void TIM_SelectSlaveMode(TIM_TypeDef *TIMx, uint16_t TIM_SlaveMode) +{ + TIMx->SMCFGR &= (uint16_t) ~((uint16_t)TIM_SMS); + TIMx->SMCFGR |= TIM_SlaveMode; +} + +/********************************************************************* + * @fn TIM_SelectMasterSlaveMode + * + * @brief Sets or Resets the TIMx Master/Slave Mode. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * TIM_MasterSlaveMode - specifies the Timer Master Slave Mode. + * TIM_MasterSlaveMode_Enable - synchronization between the current + * timer and its slaves (through TRGO). + * TIM_MasterSlaveMode_Disable - No action. + * + * @return none + */ +void TIM_SelectMasterSlaveMode(TIM_TypeDef *TIMx, uint16_t TIM_MasterSlaveMode) +{ + TIMx->SMCFGR &= (uint16_t) ~((uint16_t)TIM_MSM); + TIMx->SMCFGR |= TIM_MasterSlaveMode; +} + +/********************************************************************* + * @fn TIM_SetCounter + * + * @brief Sets the TIMx Counter Register value. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * Counter - specifies the Counter register new value. + * + * @return none + */ +void TIM_SetCounter(TIM_TypeDef *TIMx, uint32_t Counter) +{ + if(TIMx == TIM4) TIMx->CNT_TIM4 = Counter; + else TIMx->CNT = (uint16_t)Counter; +} + +/********************************************************************* + * @fn TIM_SetAutoreload + * + * @brief Sets the TIMx Autoreload Register value. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * Autoreload - specifies the Autoreload register new value. + * + * @return none + */ +void TIM_SetAutoreload(TIM_TypeDef *TIMx, uint32_t Autoreload) +{ + if(TIMx == TIM4) TIMx->ATRLR_TIM4 = Autoreload; + else TIMx->ATRLR = (uint16_t)Autoreload; +} + +/********************************************************************* + * @fn TIM_SetCompare1 + * + * @brief Sets the TIMx Capture Compare1 Register value. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * Compare1 - specifies the Capture Compare1 register new value. + * + * @return none + */ +void TIM_SetCompare1(TIM_TypeDef *TIMx, uint32_t Compare1) +{ + if(TIMx == TIM4) TIMx->CH1CVR_TIM4 = Compare1; + else TIMx->CH1CVR = (uint16_t)Compare1; +} + +/********************************************************************* + * @fn TIM_SetCompare2 + * + * @brief Sets the TIMx Capture Compare2 Register value. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * Compare1 - specifies the Capture Compare1 register new value. + * + * @return none + */ +void TIM_SetCompare2(TIM_TypeDef *TIMx, uint32_t Compare2) +{ + if(TIMx == TIM4) TIMx->CH2CVR_TIM4 = Compare2; + else TIMx->CH2CVR = (uint16_t)Compare2; +} + +/********************************************************************* + * @fn TIM_SetCompare3 + * + * @brief Sets the TIMx Capture Compare3 Register value. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * Compare1 - specifies the Capture Compare1 register new value. + * + * @return none + */ +void TIM_SetCompare3(TIM_TypeDef *TIMx, uint32_t Compare3) +{ + if(TIMx == TIM4) TIMx->CH3CVR_TIM4 = Compare3; + else TIMx->CH3CVR = (uint16_t)Compare3; +} + +/********************************************************************* + * @fn TIM_SetCompare4 + * + * @brief Sets the TIMx Capture Compare4 Register value. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * Compare1 - specifies the Capture Compare1 register new value. + * + * @return none + */ +void TIM_SetCompare4(TIM_TypeDef *TIMx, uint32_t Compare4) +{ + if(TIMx == TIM4) TIMx->CH4CVR_TIM4 = Compare4; + else TIMx->CH4CVR = (uint16_t)Compare4; +} + +/********************************************************************* + * @fn TIM_SetIC1Prescaler + * + * @brief Sets the TIMx Input Capture 1 prescaler. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * TIM_ICPSC - specifies the Input Capture1 prescaler new value. + * TIM_ICPSC_DIV1 - no prescaler. + * TIM_ICPSC_DIV2 - capture is done once every 2 events. + * TIM_ICPSC_DIV4 - capture is done once every 4 events. + * TIM_ICPSC_DIV8 - capture is done once every 8 events. + * + * @return none + */ +void TIM_SetIC1Prescaler(TIM_TypeDef *TIMx, uint16_t TIM_ICPSC) +{ + TIMx->CHCTLR1 &= (uint16_t) ~((uint16_t)TIM_IC1PSC); + TIMx->CHCTLR1 |= TIM_ICPSC; +} + +/********************************************************************* + * @fn TIM_SetIC2Prescaler + * + * @brief Sets the TIMx Input Capture 2 prescaler. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * TIM_ICPSC - specifies the Input Capture1 prescaler new value. + * TIM_ICPSC_DIV1 - no prescaler. + * TIM_ICPSC_DIV2 - capture is done once every 2 events. + * TIM_ICPSC_DIV4 - capture is done once every 4 events. + * TIM_ICPSC_DIV8 - capture is done once every 8 events. + * + * @return none + */ +void TIM_SetIC2Prescaler(TIM_TypeDef *TIMx, uint16_t TIM_ICPSC) +{ + TIMx->CHCTLR1 &= (uint16_t) ~((uint16_t)TIM_IC2PSC); + TIMx->CHCTLR1 |= (uint16_t)(TIM_ICPSC << 8); +} + +/********************************************************************* + * @fn TIM_SetIC3Prescaler + * + * @brief Sets the TIMx Input Capture 3 prescaler. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * TIM_ICPSC - specifies the Input Capture1 prescaler new value. + * TIM_ICPSC_DIV1 - no prescaler. + * TIM_ICPSC_DIV2 - capture is done once every 2 events. + * TIM_ICPSC_DIV4 - capture is done once every 4 events. + * TIM_ICPSC_DIV8 - capture is done once every 8 events. + * + * @return none + */ +void TIM_SetIC3Prescaler(TIM_TypeDef *TIMx, uint16_t TIM_ICPSC) +{ + TIMx->CHCTLR2 &= (uint16_t) ~((uint16_t)TIM_IC3PSC); + TIMx->CHCTLR2 |= TIM_ICPSC; +} + +/********************************************************************* + * @fn TIM_SetIC4Prescaler + * + * @brief Sets the TIMx Input Capture 4 prescaler. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * TIM_ICPSC - specifies the Input Capture1 prescaler new value. + * TIM_ICPSC_DIV1 - no prescaler. + * TIM_ICPSC_DIV2 - capture is done once every 2 events. + * TIM_ICPSC_DIV4 - capture is done once every 4 events. + * TIM_ICPSC_DIV8 - capture is done once every 8 events. + * + * @return none + */ +void TIM_SetIC4Prescaler(TIM_TypeDef *TIMx, uint16_t TIM_ICPSC) +{ + TIMx->CHCTLR2 &= (uint16_t) ~((uint16_t)TIM_IC4PSC); + TIMx->CHCTLR2 |= (uint16_t)(TIM_ICPSC << 8); +} + +/********************************************************************* + * @fn TIM_SetClockDivision + * + * @brief Sets the TIMx Clock Division value. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * TIM_CKD - specifies the clock division value. + * TIM_CKD_DIV1 - TDTS = Tck_tim. + * TIM_CKD_DIV2 - TDTS = 2*Tck_tim. + * TIM_CKD_DIV4 - TDTS = 4*Tck_tim. + * + * @return none + */ +void TIM_SetClockDivision(TIM_TypeDef *TIMx, uint16_t TIM_CKD) +{ + TIMx->CTLR1 &= (uint16_t) ~((uint16_t)TIM_CTLR1_CKD); + TIMx->CTLR1 |= TIM_CKD; +} + +/********************************************************************* + * @fn TIM_GetCapture1 + * + * @brief Gets the TIMx Input Capture 1 value. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * + * @return TIMx->CH1CVR - Capture Compare 1 Register value. + */ +uint32_t TIM_GetCapture1(TIM_TypeDef *TIMx) +{ + if(TIMx == TIM4) return TIMx->CH1CVR_TIM4; + else return TIMx->CH1CVR; +} + +/********************************************************************* + * @fn TIM_GetCapture2 + * + * @brief Gets the TIMx Input Capture 2 value. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * + * @return TIMx->CH2CVR - Capture Compare 2 Register value. + */ +uint32_t TIM_GetCapture2(TIM_TypeDef *TIMx) +{ + if(TIMx == TIM4) return TIMx->CH2CVR_TIM4; + else return TIMx->CH2CVR; +} + +/********************************************************************* + * @fn TIM_GetCapture3 + * + * @brief Gets the TIMx Input Capture 3 value. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * + * @return TIMx->CH3CVR - Capture Compare 3 Register value. + */ +uint32_t TIM_GetCapture3(TIM_TypeDef *TIMx) +{ + if(TIMx == TIM4) return TIMx->CH3CVR_TIM4; + else return TIMx->CH3CVR; +} + +/********************************************************************* + * @fn TIM_GetCapture4 + * + * @brief Gets the TIMx Input Capture 4 value. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * + * @return TIMx->CH4CVR - Capture Compare 4 Register value. + */ +uint32_t TIM_GetCapture4(TIM_TypeDef *TIMx) +{ + if(TIMx == TIM4) return TIMx->CH4CVR_TIM4; + else return TIMx->CH4CVR; +} + +/********************************************************************* + * @fn TIM_GetCounter + * + * @brief Gets the TIMx Counter value. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * + * @return TIMx->CNT - Counter Register value. + */ +uint32_t TIM_GetCounter(TIM_TypeDef *TIMx) +{ + if(TIMx == TIM4) return TIMx->CNT_TIM4; + else return TIMx->CNT; +} + +/********************************************************************* + * @fn TIM_GetPrescaler + * + * @brief Gets the TIMx Prescaler value. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * + * @return TIMx->PSC - Prescaler Register value. + */ +uint16_t TIM_GetPrescaler(TIM_TypeDef *TIMx) +{ + return TIMx->PSC; +} + +/********************************************************************* + * @fn TIM_GetFlagStatus + * + * @brief Checks whether the specified TIM flag is set or not. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * TIM_FLAG - specifies the flag to check. + * TIM_FLAG_Update - TIM update Flag. + * TIM_FLAG_CC1 - TIM Capture Compare 1 Flag. + * TIM_FLAG_CC2 - TIM Capture Compare 2 Flag. + * TIM_FLAG_CC3 - TIM Capture Compare 3 Flag. + * TIM_FLAG_CC4 - TIM Capture Compare 4 Flag. + * TIM_FLAG_COM - TIM Commutation Flag. + * TIM_FLAG_Trigger - TIM Trigger Flag. + * TIM_FLAG_Break - TIM Break Flag. + * TIM_FLAG_CC1OF - TIM Capture Compare 1 overcapture Flag. + * TIM_FLAG_CC2OF - TIM Capture Compare 2 overcapture Flag. + * TIM_FLAG_CC3OF - TIM Capture Compare 3 overcapture Flag. + * TIM_FLAG_CC4OF - TIM Capture Compare 4 overcapture Flag. + * + * @return none + */ +FlagStatus TIM_GetFlagStatus(TIM_TypeDef *TIMx, uint16_t TIM_FLAG) +{ + ITStatus bitstatus = RESET; + + if((TIMx->INTFR & TIM_FLAG) != (uint16_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn TIM_ClearFlag + * + * @brief Clears the TIMx's pending flags. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * TIM_FLAG - specifies the flag to check. + * TIM_FLAG_Update - TIM update Flag. + * TIM_FLAG_CC1 - TIM Capture Compare 1 Flag. + * TIM_FLAG_CC2 - TIM Capture Compare 2 Flag. + * TIM_FLAG_CC3 - TIM Capture Compare 3 Flag. + * TIM_FLAG_CC4 - TIM Capture Compare 4 Flag. + * TIM_FLAG_COM - TIM Commutation Flag. + * TIM_FLAG_Trigger - TIM Trigger Flag. + * TIM_FLAG_Break - TIM Break Flag. + * TIM_FLAG_CC1OF - TIM Capture Compare 1 overcapture Flag. + * TIM_FLAG_CC2OF - TIM Capture Compare 2 overcapture Flag. + * TIM_FLAG_CC3OF - TIM Capture Compare 3 overcapture Flag. + * TIM_FLAG_CC4OF - TIM Capture Compare 4 overcapture Flag. + * + * @return none + */ +void TIM_ClearFlag(TIM_TypeDef *TIMx, uint16_t TIM_FLAG) +{ + TIMx->INTFR = (uint16_t)~TIM_FLAG; +} + +/********************************************************************* + * @fn TIM_GetITStatus + * + * @brief Checks whether the TIM interrupt has occurred or not. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * TIM_IT - specifies the TIM interrupt source to check. + * TIM_IT_Update - TIM update Interrupt source. + * TIM_IT_CC1 - TIM Capture Compare 1 Interrupt source. + * TIM_IT_CC2 - TIM Capture Compare 2 Interrupt source. + * TIM_IT_CC3 - TIM Capture Compare 3 Interrupt source. + * TIM_IT_CC4 - TIM Capture Compare 4 Interrupt source. + * TIM_IT_COM - TIM Commutation Interrupt source. + * TIM_IT_Trigger - TIM Trigger Interrupt source. + * TIM_IT_Break - TIM Break Interrupt source. + * + * @return none + */ +ITStatus TIM_GetITStatus(TIM_TypeDef *TIMx, uint16_t TIM_IT) +{ + ITStatus bitstatus = RESET; + uint16_t itstatus = 0x0, itenable = 0x0; + + itstatus = TIMx->INTFR & TIM_IT; + + itenable = TIMx->DMAINTENR & TIM_IT; + if((itstatus != (uint16_t)RESET) && (itenable != (uint16_t)RESET)) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn TIM_ClearITPendingBit + * + * @brief Clears the TIMx's interrupt pending bits. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * TIM_IT - specifies the TIM interrupt source to check. + * TIM_IT_Update - TIM update Interrupt source. + * TIM_IT_CC1 - TIM Capture Compare 1 Interrupt source. + * TIM_IT_CC2 - TIM Capture Compare 2 Interrupt source. + * TIM_IT_CC3 - TIM Capture Compare 3 Interrupt source. + * TIM_IT_CC4 - TIM Capture Compare 4 Interrupt source. + * TIM_IT_COM - TIM Commutation Interrupt source. + * TIM_IT_Trigger - TIM Trigger Interrupt source. + * TIM_IT_Break - TIM Break Interrupt source. + * + * @return none + */ +void TIM_ClearITPendingBit(TIM_TypeDef *TIMx, uint16_t TIM_IT) +{ + TIMx->INTFR = (uint16_t)~TIM_IT; +} + +/********************************************************************* + * @fn TI1_Config + * + * @brief Configure the TI1 as Input. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * IM_ICPolarity - The Input Polarity. + * TIM_ICPolarity_Rising. + * TIM_ICPolarity_Falling. + * TIM_ICSelection - specifies the input to be used. + * TIM_ICSelection_DirectTI - TIM Input 1 is selected to be + * connected to IC1. + * TIM_ICSelection_IndirectTI - TIM Input 1 is selected to be + * connected to IC2. + * TIM_ICSelection_TRC - TIM Input 1 is selected to be connected + * to TRC. + * TIM_ICFilter - Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * + * @return none + */ +static void TI1_Config(TIM_TypeDef *TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, + uint16_t TIM_ICFilter) +{ + uint16_t tmpccmr1 = 0, tmpccer = 0; + + TIMx->CCER &= (uint16_t) ~((uint16_t)TIM_CC1E); + tmpccmr1 = TIMx->CHCTLR1; + tmpccer = TIMx->CCER; + tmpccmr1 &= (uint16_t)(((uint16_t) ~((uint16_t)TIM_CC1S)) & ((uint16_t) ~((uint16_t)TIM_IC1F))); + tmpccmr1 |= (uint16_t)(TIM_ICSelection | (uint16_t)(TIM_ICFilter << (uint16_t)4)); + + if((TIMx == TIM1) || (TIMx == TIM2) || (TIMx == TIM3) || (TIMx == TIM4)) + { + tmpccer &= (uint16_t) ~((uint16_t)(TIM_CC1P)); + tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CC1E); + } + else + { + tmpccer &= (uint16_t) ~((uint16_t)(TIM_CC1P | TIM_CC1NP)); + tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CC1E); + } + + TIMx->CHCTLR1 = tmpccmr1; + TIMx->CCER = tmpccer; +} + +/********************************************************************* + * @fn TI2_Config + * + * @brief Configure the TI2 as Input. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * IM_ICPolarity - The Input Polarity. + * TIM_ICPolarity_Rising. + * TIM_ICPolarity_Falling. + * TIM_ICSelection - specifies the input to be used. + * TIM_ICSelection_DirectTI - TIM Input 1 is selected to be + * connected to IC1. + * TIM_ICSelection_IndirectTI - TIM Input 1 is selected to be + * connected to IC2. + * TIM_ICSelection_TRC - TIM Input 1 is selected to be connected + * to TRC. + * TIM_ICFilter - Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * + * @return none + */ +static void TI2_Config(TIM_TypeDef *TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, + uint16_t TIM_ICFilter) +{ + uint16_t tmpccmr1 = 0, tmpccer = 0, tmp = 0; + + TIMx->CCER &= (uint16_t) ~((uint16_t)TIM_CC2E); + tmpccmr1 = TIMx->CHCTLR1; + tmpccer = TIMx->CCER; + tmp = (uint16_t)(TIM_ICPolarity << 4); + tmpccmr1 &= (uint16_t)(((uint16_t) ~((uint16_t)TIM_CC2S)) & ((uint16_t) ~((uint16_t)TIM_IC2F))); + tmpccmr1 |= (uint16_t)(TIM_ICFilter << 12); + tmpccmr1 |= (uint16_t)(TIM_ICSelection << 8); + + if((TIMx == TIM1) || (TIMx == TIM2) || (TIMx == TIM3) || (TIMx == TIM4)) + { + tmpccer &= (uint16_t) ~((uint16_t)(TIM_CC2P)); + tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CC2E); + } + else + { + tmpccer &= (uint16_t) ~((uint16_t)(TIM_CC2P | TIM_CC2NP)); + tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CC2E); + } + + TIMx->CHCTLR1 = tmpccmr1; + TIMx->CCER = tmpccer; +} + +/********************************************************************* + * @fn TI3_Config + * + * @brief Configure the TI3 as Input. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * IM_ICPolarity - The Input Polarity. + * TIM_ICPolarity_Rising. + * TIM_ICPolarity_Falling. + * TIM_ICSelection - specifies the input to be used. + * TIM_ICSelection_DirectTI - TIM Input 1 is selected to be + * connected to IC1. + * TIM_ICSelection_IndirectTI - TIM Input 1 is selected to be + * connected to IC2. + * TIM_ICSelection_TRC - TIM Input 1 is selected to be connected + * to TRC. + * TIM_ICFilter - Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * + * @return none + */ +static void TI3_Config(TIM_TypeDef *TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, + uint16_t TIM_ICFilter) +{ + uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0; + + TIMx->CCER &= (uint16_t) ~((uint16_t)TIM_CC3E); + tmpccmr2 = TIMx->CHCTLR2; + tmpccer = TIMx->CCER; + tmp = (uint16_t)(TIM_ICPolarity << 8); + tmpccmr2 &= (uint16_t)(((uint16_t) ~((uint16_t)TIM_CC3S)) & ((uint16_t) ~((uint16_t)TIM_IC3F))); + tmpccmr2 |= (uint16_t)(TIM_ICSelection | (uint16_t)(TIM_ICFilter << (uint16_t)4)); + + if((TIMx == TIM1) || (TIMx == TIM2) || (TIMx == TIM3) || (TIMx == TIM4)) + { + tmpccer &= (uint16_t) ~((uint16_t)(TIM_CC3P)); + tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CC3E); + } + else + { + tmpccer &= (uint16_t) ~((uint16_t)(TIM_CC3P | TIM_CC3NP)); + tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CC3E); + } + + TIMx->CHCTLR2 = tmpccmr2; + TIMx->CCER = tmpccer; +} + +/********************************************************************* + * @fn TI4_Config + * + * @brief Configure the TI4 as Input. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * TIM_ICPolarity - The Input Polarity. + * TIM_ICPolarity_Rising. + * TIM_ICPolarity_Falling. + * TIM_ICSelection - specifies the input to be used. + * TIM_ICSelection_DirectTI - TIM Input 1 is selected to be + * connected to IC1. + * TIM_ICSelection_IndirectTI - TIM Input 1 is selected to be + * connected to IC2. + * TIM_ICSelection_TRC - TIM Input 1 is selected to be connected + * to TRC. + * TIM_ICFilter - Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * + * @return none + */ +static void TI4_Config(TIM_TypeDef *TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, + uint16_t TIM_ICFilter) +{ + uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0; + + TIMx->CCER &= (uint16_t) ~((uint16_t)TIM_CC4E); + tmpccmr2 = TIMx->CHCTLR2; + tmpccer = TIMx->CCER; + tmp = (uint16_t)(TIM_ICPolarity << 12); + tmpccmr2 &= (uint16_t)((uint16_t)(~(uint16_t)TIM_CC4S) & ((uint16_t) ~((uint16_t)TIM_IC4F))); + tmpccmr2 |= (uint16_t)(TIM_ICSelection << 8); + tmpccmr2 |= (uint16_t)(TIM_ICFilter << 12); + + if((TIMx == TIM1) || (TIMx == TIM2) || (TIMx == TIM3) || (TIMx == TIM4)) + { + tmpccer &= (uint16_t) ~((uint16_t)(TIM_CC4P)); + tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CC4E); + } + else + { + tmpccer &= (uint16_t) ~((uint16_t)(TIM_CC3P)); + tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CC4E); + } + + TIMx->CHCTLR2 = tmpccmr2; + TIMx->CCER = tmpccer; +} + +/********************************************************************* + * @fn TIM_CaptureLevelIndicate_Cmd + * + * @brief Enables or disables the TIMx Capture Level Indicate function. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void TIM_CaptureLevelIndicate_Cmd(TIM_TypeDef *TIMx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + TIMx->CTLR1 |= (1 << 15); + } + else + { + TIMx->CTLR1 &= ~(1 << 15); + } +} + +/********************************************************************* + * @fn TIM_CaptureModeConfig + * + * @brief Configures the TIMx capture mode. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * TIM_CaptureMode - the TIMx capture mode. + * TIM_Capture_Mode0 - When the counter overflows, capture count + * as actual count value. + * TIM_Capture_Mode1 - When the counter overflows, capture count + * as 0xFFFF. + * + * @return none + */ +void TIM_CaptureModeConfig(TIM_TypeDef *TIMx, uint16_t TIM_CaptureMode) +{ + TIMx->CTLR1 &= ~(TIM_Capture_Mode1); + + if(TIM_CaptureMode == TIM_Capture_Mode1) + { + TIMx->CTLR1 |= TIM_Capture_Mode1; + } +} diff --git a/ZDBMS/BMS_MC/Peripheral/src/ch32l103_usart.c b/ZDBMS/BMS_MC/Peripheral/src/ch32l103_usart.c new file mode 100644 index 0000000..07d0dca --- /dev/null +++ b/ZDBMS/BMS_MC/Peripheral/src/ch32l103_usart.c @@ -0,0 +1,816 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32l103_usart.c + * Author : WCH + * Version : V1.0.0 + * Date : 2023/07/08 + * Description : This file provides all the USART firmware functions. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#include "ch32l103_usart.h" +#include "ch32l103_rcc.h" + +/* USART_Private_Defines */ +#define CTLR1_UE_Set ((uint16_t)0x2000) /* USART Enable Mask */ +#define CTLR1_UE_Reset ((uint16_t)0xDFFF) /* USART Disable Mask */ + +#define CTLR1_WAKE_Mask ((uint16_t)0xF7FF) /* USART WakeUp Method Mask */ + +#define CTLR1_RWU_Set ((uint16_t)0x0002) /* USART mute mode Enable Mask */ +#define CTLR1_RWU_Reset ((uint16_t)0xFFFD) /* USART mute mode Enable Mask */ +#define CTLR1_SBK_Set ((uint16_t)0x0001) /* USART Break Character send Mask */ +#define CTLR1_CLEAR_Mask ((uint16_t)0xE9F3) /* USART CTLR1 Mask */ +#define CTLR2_Address_Mask ((uint16_t)0xFFF0) /* USART address Mask */ + +#define CTLR2_LINEN_Set ((uint16_t)0x4000) /* USART LIN Enable Mask */ +#define CTLR2_LINEN_Reset ((uint16_t)0xBFFF) /* USART LIN Disable Mask */ + +#define CTLR2_LBDL_Mask ((uint16_t)0xFFDF) /* USART LIN Break detection Mask */ +#define CTLR2_STOP_CLEAR_Mask ((uint16_t)0xCFFF) /* USART CTLR2 STOP Bits Mask */ +#define CTLR2_CLOCK_CLEAR_Mask ((uint16_t)0xF0FF) /* USART CTLR2 Clock Mask */ + +#define CTLR3_SCEN_Set ((uint16_t)0x0020) /* USART SC Enable Mask */ +#define CTLR3_SCEN_Reset ((uint16_t)0xFFDF) /* USART SC Disable Mask */ + +#define CTLR3_NACK_Set ((uint16_t)0x0010) /* USART SC NACK Enable Mask */ +#define CTLR3_NACK_Reset ((uint16_t)0xFFEF) /* USART SC NACK Disable Mask */ + +#define CTLR3_HDSEL_Set ((uint16_t)0x0008) /* USART Half-Duplex Enable Mask */ +#define CTLR3_HDSEL_Reset ((uint16_t)0xFFF7) /* USART Half-Duplex Disable Mask */ + +#define CTLR3_IRLP_Mask ((uint16_t)0xFFFB) /* USART IrDA LowPower mode Mask */ +#define CTLR3_CLEAR_Mask ((uint16_t)0xFCFF) /* USART CTLR3 Mask */ + +#define CTLR3_IREN_Set ((uint16_t)0x0002) /* USART IrDA Enable Mask */ +#define CTLR3_IREN_Reset ((uint16_t)0xFFFD) /* USART IrDA Disable Mask */ +#define GPR_LSB_Mask ((uint16_t)0x00FF) /* Guard Time Register LSB Mask */ +#define GPR_MSB_Mask ((uint16_t)0xFF00) /* Guard Time Register MSB Mask */ +#define IT_Mask ((uint16_t)0x001F) /* USART Interrupt Mask */ + +/* USART OverSampling-8 Mask */ +#define CTLR1_OVER8_Set ((uint16_t)0x8000) /* USART OVER8 mode Enable Mask */ +#define CTLR1_OVER8_Reset ((uint16_t)0x7FFF) /* USART OVER8 mode Disable Mask */ + +/* USART One Bit Sampling Mask */ +#define CTLR3_ONEBITE_Set ((uint16_t)0x0800) /* USART ONEBITE mode Enable Mask */ +#define CTLR3_ONEBITE_Reset ((uint16_t)0xF7FF) /* USART ONEBITE mode Disable Mask */ + +/********************************************************************* + * @fn USART_DeInit + * + * @brief Deinitializes the USARTx peripheral registers to their default + * reset values. + * + * @param USARTx - where x can be 1, 2, 3 or 4 to select the UART peripheral. + * + * @return none + */ +void USART_DeInit(USART_TypeDef *USARTx) +{ + if(USARTx == USART1) + { + RCC_PB2PeriphResetCmd(RCC_PB2Periph_USART1, ENABLE); + RCC_PB2PeriphResetCmd(RCC_PB2Periph_USART1, DISABLE); + } + else if(USARTx == USART2) + { + RCC_PB1PeriphResetCmd(RCC_PB1Periph_USART2, ENABLE); + RCC_PB1PeriphResetCmd(RCC_PB1Periph_USART2, DISABLE); + } + else if(USARTx == USART3) + { + RCC_PB1PeriphResetCmd(RCC_PB1Periph_USART3, ENABLE); + RCC_PB1PeriphResetCmd(RCC_PB1Periph_USART3, DISABLE); + } + else if(USARTx == USART4) + { + RCC_PB1PeriphResetCmd(RCC_PB1Periph_USART4, ENABLE); + RCC_PB1PeriphResetCmd(RCC_PB1Periph_USART4, DISABLE); + } +} + +/********************************************************************* + * @fn USART_Init + * + * @brief Initializes the USARTx peripheral according to the specified + * parameters in the USART_InitStruct. + * + * @param USARTx - where x can be 1, 2, 3 or 4 to select the UART peripheral. + * USART_InitStruct - pointer to a USART_InitTypeDef structure + * that contains the configuration information for the specified + * USART peripheral. + * + * @return none + */ +void USART_Init(USART_TypeDef *USARTx, USART_InitTypeDef *USART_InitStruct) +{ + uint32_t tmpreg = 0x00, PBclock = 0x00; + uint32_t integerdivider = 0x00; + uint32_t fractionaldivider = 0x00; + uint32_t usartxbase = 0; + RCC_ClocksTypeDef RCC_ClocksStatus; + + if(USART_InitStruct->USART_HardwareFlowControl != USART_HardwareFlowControl_None) + { + } + + usartxbase = (uint32_t)USARTx; + tmpreg = USARTx->CTLR2; + tmpreg &= CTLR2_STOP_CLEAR_Mask; + tmpreg |= (uint32_t)USART_InitStruct->USART_StopBits; + + USARTx->CTLR2 = (uint16_t)tmpreg; + tmpreg = USARTx->CTLR1; + tmpreg &= CTLR1_CLEAR_Mask; + tmpreg |= (uint32_t)USART_InitStruct->USART_WordLength | USART_InitStruct->USART_Parity | + USART_InitStruct->USART_Mode; + USARTx->CTLR1 = (uint16_t)tmpreg; + + tmpreg = USARTx->CTLR3; + tmpreg &= CTLR3_CLEAR_Mask; + tmpreg |= USART_InitStruct->USART_HardwareFlowControl; + USARTx->CTLR3 = (uint16_t)tmpreg; + + RCC_GetClocksFreq(&RCC_ClocksStatus); + + if(usartxbase == USART1_BASE) + { + PBclock = RCC_ClocksStatus.PCLK2_Frequency; + } + else + { + PBclock = RCC_ClocksStatus.PCLK1_Frequency; + } + + if((USARTx->CTLR1 & CTLR1_OVER8_Set) != 0) + { + integerdivider = ((25 * PBclock) / (2 * (USART_InitStruct->USART_BaudRate))); + } + else + { + integerdivider = ((25 * PBclock) / (4 * (USART_InitStruct->USART_BaudRate))); + } + tmpreg = (integerdivider / 100) << 4; + + fractionaldivider = integerdivider - (100 * (tmpreg >> 4)); + + if((USARTx->CTLR1 & CTLR1_OVER8_Set) != 0) + { + tmpreg |= ((((fractionaldivider * 8) + 50) / 100)) & ((uint8_t)0x07); + } + else + { + tmpreg |= ((((fractionaldivider * 16) + 50) / 100)) & ((uint8_t)0x0F); + } + + USARTx->BRR = (uint16_t)tmpreg; +} + +/********************************************************************* + * @fn USART_StructInit + * + * @brief Fills each USART_InitStruct member with its default value. + * + * @param USART_InitStruct: pointer to a USART_InitTypeDef structure + * which will be initialized. + * + * @return none + */ +void USART_StructInit(USART_InitTypeDef *USART_InitStruct) +{ + USART_InitStruct->USART_BaudRate = 9600; + USART_InitStruct->USART_WordLength = USART_WordLength_8b; + USART_InitStruct->USART_StopBits = USART_StopBits_1; + USART_InitStruct->USART_Parity = USART_Parity_No; + USART_InitStruct->USART_Mode = USART_Mode_Rx | USART_Mode_Tx; + USART_InitStruct->USART_HardwareFlowControl = USART_HardwareFlowControl_None; +} + +/********************************************************************* + * @fn USART_ClockInit + * + * @brief Initializes the USARTx peripheral Clock according to the + * specified parameters in the USART_ClockInitStruct . + * + * @param USARTx - where x can be 1, 2, 3 or 4 to select the USART peripheral. + * USART_ClockInitStruct - pointer to a USART_ClockInitTypeDef + * structure that contains the configuration information for the specified + * USART peripheral. + * + * @return none + */ +void USART_ClockInit(USART_TypeDef *USARTx, USART_ClockInitTypeDef *USART_ClockInitStruct) +{ + uint32_t tmpreg = 0x00; + + tmpreg = USARTx->CTLR2; + tmpreg &= CTLR2_CLOCK_CLEAR_Mask; + tmpreg |= (uint32_t)USART_ClockInitStruct->USART_Clock | USART_ClockInitStruct->USART_CPOL | + USART_ClockInitStruct->USART_CPHA | USART_ClockInitStruct->USART_LastBit; + USARTx->CTLR2 = (uint16_t)tmpreg; +} + +/********************************************************************* + * @fn USART_ClockStructInit + * + * @brief Fills each USART_ClockStructInit member with its default value. + * + * @param USART_ClockInitStruct - pointer to a USART_ClockInitTypeDef + * structure which will be initialized. + * + * @return none + */ +void USART_ClockStructInit(USART_ClockInitTypeDef *USART_ClockInitStruct) +{ + USART_ClockInitStruct->USART_Clock = USART_Clock_Disable; + USART_ClockInitStruct->USART_CPOL = USART_CPOL_Low; + USART_ClockInitStruct->USART_CPHA = USART_CPHA_1Edge; + USART_ClockInitStruct->USART_LastBit = USART_LastBit_Disable; +} + +/********************************************************************* + * @fn USART_Cmd + * + * @brief Enables or disables the specified USART peripheral. + * + * @param USARTx - where x can be 1, 2, 3 or 4 to select the USART peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void USART_Cmd(USART_TypeDef *USARTx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + USARTx->CTLR1 |= CTLR1_UE_Set; + } + else + { + USARTx->CTLR1 &= CTLR1_UE_Reset; + } +} + +/********************************************************************* + * @fn USART_ITConfig + * + * @brief Enables or disables the specified USART interrupts. + * reset values. + * + * @param USARTx - where x can be 1, 2, 3 or 4 to select the USART peripheral. + * USART_IT - specifies the USART interrupt sources to be enabled or disabled. + * USART_IT_LBD - LIN Break detection interrupt. + * USART_IT_TXE - Transmit Data Register empty interrupt. + * USART_IT_TC - Transmission complete interrupt. + * USART_IT_RXNE - Receive Data register not empty interrupt. + * USART_IT_IDLE - Idle line detection interrupt. + * USART_IT_PE - Parity Error interrupt. + * USART_IT_ERR - Error interrupt. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void USART_ITConfig(USART_TypeDef *USARTx, uint16_t USART_IT, FunctionalState NewState) +{ + uint32_t usartreg = 0x00, itpos = 0x00, itmask = 0x00; + uint32_t usartxbase = 0x00; + + usartxbase = (uint32_t)USARTx; + usartreg = (((uint8_t)USART_IT) >> 0x05); + itpos = USART_IT & IT_Mask; + itmask = (((uint32_t)0x01) << itpos); + + if(usartreg == 0x01) + { + usartxbase += 0x0C; + } + else if(usartreg == 0x02) + { + usartxbase += 0x10; + } + else + { + usartxbase += 0x14; + } + + if(NewState != DISABLE) + { + *(__IO uint32_t *)usartxbase |= itmask; + } + else + { + *(__IO uint32_t *)usartxbase &= ~itmask; + } +} + +/********************************************************************* + * @fn USART_DMACmd + * + * @brief Enables or disables the USART DMA interface. + * + * @param USARTx - where x can be 1, 2, 3 or 4 to select the USART peripheral. + * USART_DMAReq - specifies the DMA request. + * USART_DMAReq_Tx - USART DMA transmit request. + * USART_DMAReq_Rx - USART DMA receive request. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void USART_DMACmd(USART_TypeDef *USARTx, uint16_t USART_DMAReq, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + USARTx->CTLR3 |= USART_DMAReq; + } + else + { + USARTx->CTLR3 &= (uint16_t)~USART_DMAReq; + } +} + +/********************************************************************* + * @fn USART_SetAddress + * + * @brief Sets the address of the USART node. + * + * @param USARTx - where x can be 1, 2, 3 or 4 to select the USART peripheral. + * USART_Address - Indicates the address of the USART node. + * + * @return none + */ +void USART_SetAddress(USART_TypeDef *USARTx, uint8_t USART_Address) +{ + USARTx->CTLR2 &= CTLR2_Address_Mask; + USARTx->CTLR2 |= USART_Address; +} + +/********************************************************************* + * @fn USART_WakeUpConfig + * + * @brief Selects the USART WakeUp method. + * + * @param USARTx - where x can be 1, 2, 3 or 4 to select the USART peripheral. + * USART_WakeUp - specifies the USART wakeup method. + * USART_WakeUp_IdleLine - WakeUp by an idle line detection. + * USART_WakeUp_AddressMark - WakeUp by an address mark. + * + * @return none + */ +void USART_WakeUpConfig(USART_TypeDef *USARTx, uint16_t USART_WakeUp) +{ + USARTx->CTLR1 &= CTLR1_WAKE_Mask; + USARTx->CTLR1 |= USART_WakeUp; +} + +/********************************************************************* + * @fn USART_ReceiverWakeUpCmd + * + * @brief Determines if the USART is in mute mode or not. + * + * @param USARTx - where x can be 1, 2, 3 or 4 to select the USART peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void USART_ReceiverWakeUpCmd(USART_TypeDef *USARTx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + USARTx->CTLR1 |= CTLR1_RWU_Set; + } + else + { + USARTx->CTLR1 &= CTLR1_RWU_Reset; + } +} + +/********************************************************************* + * @fn USART_LINBreakDetectLengthConfig + * + * @brief Sets the USART LIN Break detection length. + * + * @param USARTx - where x can be 1, 2, 3 or 4 to select the USART peripheral. + * USART_LINBreakDetectLength - specifies the LIN break detection length. + * USART_LINBreakDetectLength_10b - 10-bit break detection. + * USART_LINBreakDetectLength_11b - 11-bit break detection. + * + * @return none + */ +void USART_LINBreakDetectLengthConfig(USART_TypeDef *USARTx, uint16_t USART_LINBreakDetectLength) +{ + USARTx->CTLR2 &= CTLR2_LBDL_Mask; + USARTx->CTLR2 |= USART_LINBreakDetectLength; +} + +/********************************************************************* + * @fn USART_LINCmd + * + * @brief Enables or disables the USART LIN mode. + * + * @param USARTx - where x can be 1, 2, 3 or 4 to select the USART peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void USART_LINCmd(USART_TypeDef *USARTx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + USARTx->CTLR2 |= CTLR2_LINEN_Set; + } + else + { + USARTx->CTLR2 &= CTLR2_LINEN_Reset; + } +} + +/********************************************************************* + * @fn USART_SendData + * + * @brief Transmits single data through the USARTx peripheral. + * + * @param USARTx - where x can be 1, 2, 3 or 4 to select the USART peripheral. + * Data - the data to transmit. + * + * @return none + */ +void USART_SendData(USART_TypeDef *USARTx, uint16_t Data) +{ + USARTx->DATAR = (Data & (uint16_t)0x01FF); +} + +/********************************************************************* + * @fn USART_ReceiveData + * + * @brief Returns the most recent received data by the USARTx peripheral. + * + * @param USARTx - where x can be 1, 2, 3 or 4 to select the USART peripheral. + * + * @return The received data. + */ +uint16_t USART_ReceiveData(USART_TypeDef *USARTx) +{ + return (uint16_t)(USARTx->DATAR & (uint16_t)0x01FF); +} + +/********************************************************************* + * @fn USART_SendBreak + * + * @brief Transmits break characters. + * + * @param USARTx - where x can be 1, 2, 3 or 4 to select the USART peripheral. + * + * @return none + */ +void USART_SendBreak(USART_TypeDef *USARTx) +{ + USARTx->CTLR1 |= CTLR1_SBK_Set; +} + +/********************************************************************* + * @fn USART_SetGuardTime + * + * @brief Sets the specified USART guard time. + * + * @param USARTx - where x can be 1, 2, 3 or 4 to select the USART peripheral. + * USART_GuardTime - specifies the guard time. + * + * @return none + */ +void USART_SetGuardTime(USART_TypeDef *USARTx, uint8_t USART_GuardTime) +{ + USARTx->GPR &= GPR_LSB_Mask; + USARTx->GPR |= (uint16_t)((uint16_t)USART_GuardTime << 0x08); +} + +/********************************************************************* + * @fn USART_SetPrescaler + * + * @brief Sets the system clock prescaler. + * + * @param USARTx - where x can be 1, 2, 3 or 4 to select the USART peripheral. + * USART_Prescaler - specifies the prescaler clock. + * + * @return none + */ +void USART_SetPrescaler(USART_TypeDef *USARTx, uint8_t USART_Prescaler) +{ + USARTx->GPR &= GPR_MSB_Mask; + USARTx->GPR |= USART_Prescaler; +} + +/********************************************************************* + * @fn USART_SmartCardCmd + * + * @brief Enables or disables the USART Smart Card mode. + * + * @param USARTx - where x can be 1, 2, 3 or 4 to select the USART peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void USART_SmartCardCmd(USART_TypeDef *USARTx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + USARTx->CTLR3 |= CTLR3_SCEN_Set; + } + else + { + USARTx->CTLR3 &= CTLR3_SCEN_Reset; + } +} + +/********************************************************************* + * @fn USART_SmartCardNACKCmd + * + * @brief Enables or disables NACK transmission. + * + * @param USARTx - where x can be 1, 2, 3 or 4 to select the USART peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void USART_SmartCardNACKCmd(USART_TypeDef *USARTx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + USARTx->CTLR3 |= CTLR3_NACK_Set; + } + else + { + USARTx->CTLR3 &= CTLR3_NACK_Reset; + } +} + +/********************************************************************* + * @fn USART_HalfDuplexCmd + * + * @brief Enables or disables the USART Half Duplex communication. + * + * @param USARTx - where x can be 1, 2, 3 or 4 to select the USART peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void USART_HalfDuplexCmd(USART_TypeDef *USARTx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + USARTx->CTLR3 |= CTLR3_HDSEL_Set; + } + else + { + USARTx->CTLR3 &= CTLR3_HDSEL_Reset; + } +} + +/********************************************************************* + * @fn USART_OverSampling8Cmd + * + * @brief Enables or disables the USART's 8x oversampling mode. + * + * @param USARTx - where x can be 1, 2, 3 or 4 to select the USART peripheral. + * NewState - ENABLE or DISABLE. + * Note- + * This function has to be called before calling USART_Init() + * function in order to have correct baudrate Divider value. + * @return none + */ +void USART_OverSampling8Cmd(USART_TypeDef *USARTx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + USARTx->CTLR1 |= CTLR1_OVER8_Set; + } + else + { + USARTx->CTLR1 &= CTLR1_OVER8_Reset; + } +} + +/********************************************************************* + * @fn USART_OneBitMethodCmd + * + * @brief Enables or disables the USART's one bit sampling method. + * + * @param USARTx - where x can be 1, 2, 3 or 4 to select the USART peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void USART_OneBitMethodCmd(USART_TypeDef *USARTx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + USARTx->CTLR3 |= CTLR3_ONEBITE_Set; + } + else + { + USARTx->CTLR3 &= CTLR3_ONEBITE_Reset; + } +} + +/********************************************************************* + * @fn USART_IrDAConfig + * + * @brief Configures the USART's IrDA interface. + * + * @param USARTx - where x can be 1, 2, 3 or 4 to select the USART peripheral. + * USART_IrDAMode - specifies the IrDA mode. + * USART_IrDAMode_LowPower. + * USART_IrDAMode_Normal. + * + * @return none + */ +void USART_IrDAConfig(USART_TypeDef *USARTx, uint16_t USART_IrDAMode) +{ + USARTx->CTLR3 &= CTLR3_IRLP_Mask; + USARTx->CTLR3 |= USART_IrDAMode; +} + +/********************************************************************* + * @fn USART_IrDACmd + * + * @brief Enables or disables the USART's IrDA interface. + * + * @param USARTx - where x can be 1, 2, 3 or 4 to select the USART peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void USART_IrDACmd(USART_TypeDef *USARTx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + USARTx->CTLR3 |= CTLR3_IREN_Set; + } + else + { + USARTx->CTLR3 &= CTLR3_IREN_Reset; + } +} + +/********************************************************************* + * @fn USART_GetFlagStatus + * + * @brief Checks whether the specified USART flag is set or not. + * + * @param USARTx - where x can be 1, 2, 3 or 4 to select the USART peripheral. + * USART_FLAG - specifies the flag to check. + * USART_FLAG_RX_BUSY - Receive data busy flag. + * USART_FLAG_CTS - CTS state detection flag. + * USART_FLAG_LBD - LIN Break detection flag. + * USART_FLAG_TXE - Transmit data register empty flag. + * USART_FLAG_TC - Transmission Complete flag. + * USART_FLAG_RXNE - Receive data register not empty flag. + * USART_FLAG_IDLE - Idle Line detection flag. + * USART_FLAG_ORE - OverRun Error flag. + * USART_FLAG_NE - Noise Error flag. + * USART_FLAG_FE - Framing Error flag. + * USART_FLAG_PE - Parity Error flag. + * + * @return bitstatus: SET or RESET + */ +FlagStatus USART_GetFlagStatus(USART_TypeDef *USARTx, uint16_t USART_FLAG) +{ + FlagStatus bitstatus = RESET; + + + if((USARTx->STATR & USART_FLAG) != (uint16_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn USART_ClearFlag + * + * @brief Clears the USARTx's pending flags. + * + * @param USARTx - where x can be 1, 2, 3 or 4 to select the USART peripheral. + * USART_FLAG - specifies the flag to clear. + * USART_FLAG_CTS - CTS state detection flag. + * USART_FLAG_LBD - LIN Break detection flag. + * USART_FLAG_TC - Transmission Complete flag. + * USART_FLAG_RXNE - Receive data register not empty flag. + * Note- + * - PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun + * error) and IDLE (Idle line detected) flags are cleared by software + * sequence: a read operation to USART_STATR register (USART_GetFlagStatus()) + * followed by a read operation to USART_DATAR register (USART_ReceiveData()). + * - RXNE flag can be also cleared by a read to the USART_DATAR register + * (USART_ReceiveData()). + * - TC flag can be also cleared by software sequence: a read operation to + * USART_STATR register (USART_GetFlagStatus()) followed by a write operation + * to USART_DATAR register (USART_SendData()). + * - TXE flag is cleared only by a write to the USART_DATAR register + * (USART_SendData()). + * @return none + */ +void USART_ClearFlag(USART_TypeDef *USARTx, uint16_t USART_FLAG) +{ + USARTx->STATR = (uint16_t)~USART_FLAG; +} + +/********************************************************************* + * @fn USART_GetITStatus + * + * @brief Checks whether the specified USART interrupt has occurred or not. + * + * @param USARTx - where x can be 1, 2, 3 or 4 to select the USART peripheral. + * USART_IT - specifies the USART interrupt source to check. + * USART_IT_CTS - CTS state detection interrupt. + * USART_IT_LBD - LIN Break detection interrupt. + * USART_IT_TXE - Tansmit Data Register empty interrupt. + * USART_IT_TC - Transmission complete interrupt. + * USART_IT_RXNE - Receive Data register not empty interrupt. + * USART_IT_IDLE - Idle line detection interrupt. + * USART_IT_ORE_RX - OverRun Error interrupt if the RXNEIE bit is set. + * USART_IT_ORE_ER - OverRun Error interrupt if the EIE bit is set. + * USART_IT_NE - Noise Error interrupt. + * USART_IT_FE - Framing Error interrupt. + * USART_IT_PE - Parity Error interrupt. + * + * @return bitstatus - SET or RESET. + */ +ITStatus USART_GetITStatus(USART_TypeDef *USARTx, uint16_t USART_IT) +{ + uint32_t bitpos = 0x00, itmask = 0x00, usartreg = 0x00; + ITStatus bitstatus = RESET; + + usartreg = (((uint8_t)USART_IT) >> 0x05); + itmask = USART_IT & IT_Mask; + itmask = (uint32_t)0x01 << itmask; + + if(usartreg == 0x01) + { + itmask &= USARTx->CTLR1; + } + else if(usartreg == 0x02) + { + itmask &= USARTx->CTLR2; + } + else + { + itmask &= USARTx->CTLR3; + } + + bitpos = USART_IT >> 0x08; + bitpos = (uint32_t)0x01 << bitpos; + bitpos &= USARTx->STATR; + + if((itmask != (uint16_t)RESET) && (bitpos != (uint16_t)RESET)) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn USART_ClearITPendingBit + * + * @brief Clears the USARTx's interrupt pending bits. + * + * @param USARTx - where x can be 1, 2, 3 or 4 to select the USART peripheral. + * USART_IT - specifies the interrupt pending bit to clear. + * USART_IT_CTS - CTS state detection interrupt. + * USART_IT_LBD - LIN Break detection interrupt. + * USART_IT_TC - Transmission complete interrupt. + * USART_IT_RXNE - Receive Data register not empty interrupt. + * Note- + * - PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun + * error) and IDLE (Idle line detected) pending bits are cleared by + * software sequence: a read operation to USART_STATR register + * (USART_GetITStatus()) followed by a read operation to USART_DATAR register + * (USART_ReceiveData()). + * - RXNE pending bit can be also cleared by a read to the USART_DATAR register + * (USART_ReceiveData()). + * - TC pending bit can be also cleared by software sequence: a read + * operation to USART_STATR register (USART_GetITStatus()) followed by a write + * operation to USART_DATAR register (USART_SendData()). + * - TXE pending bit is cleared only by a write to the USART_DATAR register + * (USART_SendData()). + * + * @return none + */ +void USART_ClearITPendingBit(USART_TypeDef *USARTx, uint16_t USART_IT) +{ + uint16_t bitpos = 0x00, itmask = 0x00; + + bitpos = USART_IT >> 0x08; + itmask = ((uint16_t)0x01 << (uint16_t)bitpos); + USARTx->STATR = (uint16_t)~itmask; +} diff --git a/ZDBMS/BMS_MC/Peripheral/src/ch32l103_wwdg.c b/ZDBMS/BMS_MC/Peripheral/src/ch32l103_wwdg.c new file mode 100644 index 0000000..566a71c --- /dev/null +++ b/ZDBMS/BMS_MC/Peripheral/src/ch32l103_wwdg.c @@ -0,0 +1,142 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32l103_wwdg.c + * Author : WCH + * Version : V1.0.0 + * Date : 2023/07/08 + * Description : This file provides all the WWDG firmware functions. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#include "ch32l103_wwdg.h" +#include "ch32l103_rcc.h" + +/* CTLR register bit mask */ +#define CTLR_WDGA_Set ((uint32_t)0x00000080) + +/* CFGR register bit mask */ +#define CFGR_WDGTB_Mask ((uint32_t)0xFFFFFE7F) +#define CFGR_W_Mask ((uint32_t)0xFFFFFF80) +#define BIT_Mask ((uint8_t)0x7F) + +/********************************************************************* + * @fn WWDG_DeInit + * + * @brief Deinitializes the WWDG peripheral registers to their default reset values + * + * @return none + */ +void WWDG_DeInit(void) +{ + RCC_PB1PeriphResetCmd(RCC_PB1Periph_WWDG, ENABLE); + RCC_PB1PeriphResetCmd(RCC_PB1Periph_WWDG, DISABLE); +} + +/********************************************************************* + * @fn WWDG_SetPrescaler + * + * @brief Sets the WWDG Prescaler + * + * @param WWDG_Prescaler - specifies the WWDG Prescaler + * WWDG_Prescaler_1 - WWDG counter clock = (PCLK1/4096)/1 + * WWDG_Prescaler_2 - WWDG counter clock = (PCLK1/4096)/2 + * WWDG_Prescaler_4 - WWDG counter clock = (PCLK1/4096)/4 + * WWDG_Prescaler_8 - WWDG counter clock = (PCLK1/4096)/8 + * + * @return none + */ +void WWDG_SetPrescaler(uint32_t WWDG_Prescaler) +{ + uint32_t tmpreg = 0; + tmpreg = WWDG->CFGR & CFGR_WDGTB_Mask; + tmpreg |= WWDG_Prescaler; + WWDG->CFGR = tmpreg; +} + +/********************************************************************* + * @fn WWDG_SetWindowValue + * + * @brief Sets the WWDG window value + * + * @param WindowValue - specifies the window value to be compared to the + * downcounter,which must be lower than 0x80 + * + * @return none + */ +void WWDG_SetWindowValue(uint8_t WindowValue) +{ + __IO uint32_t tmpreg = 0; + + tmpreg = WWDG->CFGR & CFGR_W_Mask; + + tmpreg |= WindowValue & (uint32_t)BIT_Mask; + + WWDG->CFGR = tmpreg; +} + +/********************************************************************* + * @fn WWDG_EnableIT + * + * @brief Enables the WWDG Early Wakeup interrupt(EWI) + * + * @return none + */ +void WWDG_EnableIT(void) +{ + WWDG->CFGR |= (1 << 9); +} + +/********************************************************************* + * @fn WWDG_SetCounter + * + * @brief Sets the WWDG counter value + * + * @param Counter - specifies the watchdog counter value,which must be a + * number between 0x40 and 0x7F + * + * @return none + */ +void WWDG_SetCounter(uint8_t Counter) +{ + WWDG->CTLR = Counter & BIT_Mask; +} + +/********************************************************************* + * @fn WWDG_Enable + * + * @brief Enables WWDG and load the counter value + * + * @param Counter - specifies the watchdog counter value,which must be a + * number between 0x40 and 0x7F + * + * @return none + */ +void WWDG_Enable(uint8_t Counter) +{ + WWDG->CTLR = CTLR_WDGA_Set | Counter; +} + +/********************************************************************* + * @fn WWDG_GetFlagStatus + * + * @brief Checks whether the Early Wakeup interrupt flag is set or not + * + * @return The new state of the Early Wakeup interrupt flag (SET or RESET) + */ +FlagStatus WWDG_GetFlagStatus(void) +{ + return (FlagStatus)(WWDG->STATR); +} + +/********************************************************************* + * @fn WWDG_ClearFlag + * + * @brief Clears Early Wakeup interrupt flag + * + * @return none + */ +void WWDG_ClearFlag(void) +{ + WWDG->STATR = (uint32_t)RESET; +} diff --git a/ZDBMS/BMS_MC/Startup/startup_ch32l103.S b/ZDBMS/BMS_MC/Startup/startup_ch32l103.S new file mode 100644 index 0000000..fbe5f97 --- /dev/null +++ b/ZDBMS/BMS_MC/Startup/startup_ch32l103.S @@ -0,0 +1,269 @@ +;/********************************** (C) COPYRIGHT ******************************* +;* File Name : startup_ch32l103.s +;* Author : WCH +;* Version : V1.0.0 +;* Date : 2024/05/06 +;* Description : CH32L103 vector table for eclipse toolchain. +;********************************************************************************* +;* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +;* Attention: This software (modified or not) and binary are used for +;* microcontroller manufactured by Nanjing Qinheng Microelectronics. +;*******************************************************************************/ + + .section .init,"ax",@progbits + .global _start + .align 1 +_start: + j handle_reset + + .section .vector,"ax",@progbits + .align 1 +_vector_base: + .option norvc; + .word _start + .word 0 + .word NMI_Handler /* NMI */ + .word HardFault_Handler /* Hard Fault */ + .word 0 + .word Ecall_M_Mode_Handler /* Ecall M Mode */ + .word 0 + .word 0 + .word Ecall_U_Mode_Handler /* Ecall U Mode */ + .word Break_Point_Handler /* Break Point */ + .word 0 + .word 0 + .word SysTick_Handler /* SysTick */ + .word 0 + .word SW_Handler /* SW */ + .word 0 + /* External Interrupts */ + .word WWDG_IRQHandler /* Window Watchdog */ + .word PVD_IRQHandler /* PVD through EXTI Line detect */ + .word TAMPER_IRQHandler /* TAMPER */ + .word RTC_IRQHandler /* RTC */ + .word FLASH_IRQHandler /* Flash */ + .word RCC_IRQHandler /* RCC */ + .word EXTI0_IRQHandler /* EXTI Line 0 */ + .word EXTI1_IRQHandler /* EXTI Line 1 */ + .word EXTI2_IRQHandler /* EXTI Line 2 */ + .word EXTI3_IRQHandler /* EXTI Line 3 */ + .word EXTI4_IRQHandler /* EXTI Line 4 */ + .word DMA1_Channel1_IRQHandler /* DMA1 Channel 1 */ + .word DMA1_Channel2_IRQHandler /* DMA1 Channel 2 */ + .word DMA1_Channel3_IRQHandler /* DMA1 Channel 3 */ + .word DMA1_Channel4_IRQHandler /* DMA1 Channel 4 */ + .word DMA1_Channel5_IRQHandler /* DMA1 Channel 5 */ + .word DMA1_Channel6_IRQHandler /* DMA1 Channel 6 */ + .word DMA1_Channel7_IRQHandler /* DMA1 Channel 7 */ + .word ADC_IRQHandler /* ADC */ + .word USB_HP_CAN1_TX_IRQHandler /* USB HP and CAN1 TX */ + .word USB_LP_CAN1_RX0_IRQHandler /* USB LP and CAN1RX0 */ + .word CAN1_RX1_IRQHandler /* CAN1 RX1 */ + .word CAN1_SCE_IRQHandler /* CAN1 SCE */ + .word EXTI9_5_IRQHandler /* EXTI Line 9..5 */ + .word TIM1_BRK_IRQHandler /* TIM1 Break */ + .word TIM1_UP_IRQHandler /* TIM1 Update */ + .word TIM1_TRG_COM_IRQHandler /* TIM1 Trigger and Commutation */ + .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */ + .word TIM2_IRQHandler /* TIM2 */ + .word TIM3_IRQHandler /* TIM3 */ + .word TIM4_IRQHandler /* TIM4 */ + .word I2C1_EV_IRQHandler /* I2C1 Event */ + .word I2C1_ER_IRQHandler /* I2C1 Error */ + .word I2C2_EV_IRQHandler /* I2C2 Event */ + .word I2C2_ER_IRQHandler /* I2C2 Error */ + .word SPI1_IRQHandler /* SPI1 */ + .word SPI2_IRQHandler /* SPI2 */ + .word USART1_IRQHandler /* USART1 */ + .word USART2_IRQHandler /* USART2 */ + .word USART3_IRQHandler /* USART3 */ + .word EXTI15_10_IRQHandler /* EXTI Line 15..10 */ + .word RTCAlarm_IRQHandler /* RTC Alarm through EXTI Line */ + .word LPTIMWakeUp_IRQHandler /* LPTIM Wake up */ + .word USBFS_IRQHandler /* USBFS Break */ + .word USBFSWakeUp_IRQHandler /* USBFS Wake up from suspend */ + .word USART4_IRQHandler /* USART4 */ + .word DMA1_Channel8_IRQHandler /* DMA1 Channel8 */ + .word LPTIM_IRQHandler /* LPTIM */ + .word OPA_IRQHandler /* OPA */ + .word USBPD_IRQHandler /* USBPD */ + .word 0 + .word USBPDWakeUp_IRQHandler /* USBPD Wake Up */ + .word CMPWakeUp_IRQHandler /* CMP Wake Up */ + + .option rvc; + .section .text.vector_handler, "ax", @progbits + .weak NMI_Handler /* NMI */ + .weak HardFault_Handler /* Hard Fault */ + .weak Ecall_M_Mode_Handler /* Ecall M Mode */ + .weak Ecall_U_Mode_Handler /* Ecall U Mode */ + .weak Break_Point_Handler /* Break Point */ + .weak SysTick_Handler /* SysTick */ + .weak SW_Handler /* SW */ + .weak WWDG_IRQHandler /* Window Watchdog */ + .weak PVD_IRQHandler /* PVD through EXTI Line detect */ + .weak TAMPER_IRQHandler /* TAMPER */ + .weak RTC_IRQHandler /* RTC */ + .weak FLASH_IRQHandler /* Flash */ + .weak RCC_IRQHandler /* RCC */ + .weak EXTI0_IRQHandler /* EXTI Line 0 */ + .weak EXTI1_IRQHandler /* EXTI Line 1 */ + .weak EXTI2_IRQHandler /* EXTI Line 2 */ + .weak EXTI3_IRQHandler /* EXTI Line 3 */ + .weak EXTI4_IRQHandler /* EXTI Line 4 */ + .weak DMA1_Channel1_IRQHandler /* DMA1 Channel 1 */ + .weak DMA1_Channel2_IRQHandler /* DMA1 Channel 2 */ + .weak DMA1_Channel3_IRQHandler /* DMA1 Channel 3 */ + .weak DMA1_Channel4_IRQHandler /* DMA1 Channel 4 */ + .weak DMA1_Channel5_IRQHandler /* DMA1 Channel 5 */ + .weak DMA1_Channel6_IRQHandler /* DMA1 Channel 6 */ + .weak DMA1_Channel7_IRQHandler /* DMA1 Channel 7 */ + .weak ADC_IRQHandler /* ADC */ + .weak USB_HP_CAN1_TX_IRQHandler /* USB HP and CAN1 TX */ + .weak USB_LP_CAN1_RX0_IRQHandler /* USB LP and CAN1RX0 */ + .weak CAN1_RX1_IRQHandler /* CAN1 RX1 */ + .weak CAN1_SCE_IRQHandler /* CAN1 SCE */ + .weak EXTI9_5_IRQHandler /* EXTI Line 9..5 */ + .weak TIM1_BRK_IRQHandler /* TIM1 Break */ + .weak TIM1_UP_IRQHandler /* TIM1 Update */ + .weak TIM1_TRG_COM_IRQHandler /* TIM1 Trigger and Commutation */ + .weak TIM1_CC_IRQHandler /* TIM1 Capture Compare */ + .weak TIM2_IRQHandler /* TIM2 */ + .weak TIM3_IRQHandler /* TIM3 */ + .weak TIM4_IRQHandler /* TIM4 */ + .weak I2C1_EV_IRQHandler /* I2C1 Event */ + .weak I2C1_ER_IRQHandler /* I2C1 Error */ + .weak I2C2_EV_IRQHandler /* I2C2 Event */ + .weak I2C2_ER_IRQHandler /* I2C2 Error */ + .weak SPI1_IRQHandler /* SPI1 */ + .weak SPI2_IRQHandler /* SPI2 */ + .weak USART1_IRQHandler /* USART1 */ + .weak USART2_IRQHandler /* USART2 */ + .weak USART3_IRQHandler /* USART3 */ + .weak EXTI15_10_IRQHandler /* EXTI Line 15..10 */ + .weak RTCAlarm_IRQHandler /* RTC Alarm through EXTI Line */ + .weak LPTIMWakeUp_IRQHandler /* LPTIM Wake up */ + .weak USBFS_IRQHandler /* USBFS */ + .weak USBFSWakeUp_IRQHandler /* USBFS Wake Up */ + .weak USART4_IRQHandler /* USART4 */ + .weak DMA1_Channel8_IRQHandler /* DMA1 Channel8 */ + .weak LPTIM_IRQHandler /* LPTIM */ + .weak OPA_IRQHandler /* OPA */ + .weak USBPD_IRQHandler /* USBPD */ + .weak USBPDWakeUp_IRQHandler /* USBPD Wake Up */ + .weak CMPWakeUp_IRQHandler /* CMP Wake Up */ + +NMI_Handler: +HardFault_Handler: +Ecall_M_Mode_Handler: +Ecall_U_Mode_Handler: +Break_Point_Handler: +SysTick_Handler: +SW_Handler: +WWDG_IRQHandler: +PVD_IRQHandler: +TAMPER_IRQHandler: +RTC_IRQHandler: +FLASH_IRQHandler: +RCC_IRQHandler: +EXTI0_IRQHandler: +EXTI1_IRQHandler: +EXTI2_IRQHandler: +EXTI3_IRQHandler: +EXTI4_IRQHandler: +DMA1_Channel1_IRQHandler: +DMA1_Channel2_IRQHandler: +DMA1_Channel3_IRQHandler: +DMA1_Channel4_IRQHandler: +DMA1_Channel5_IRQHandler: +DMA1_Channel6_IRQHandler: +DMA1_Channel7_IRQHandler: +ADC_IRQHandler: +USB_HP_CAN1_TX_IRQHandler: +USB_LP_CAN1_RX0_IRQHandler: +CAN1_RX1_IRQHandler: +CAN1_SCE_IRQHandler: +EXTI9_5_IRQHandler: +TIM1_BRK_IRQHandler: +TIM1_UP_IRQHandler: +TIM1_TRG_COM_IRQHandler: +TIM1_CC_IRQHandler: +TIM2_IRQHandler: +TIM3_IRQHandler: +TIM4_IRQHandler: +I2C1_EV_IRQHandler: +I2C1_ER_IRQHandler: +I2C2_EV_IRQHandler: +I2C2_ER_IRQHandler: +SPI1_IRQHandler: +SPI2_IRQHandler: +USART1_IRQHandler: +USART2_IRQHandler: +USART3_IRQHandler: +EXTI15_10_IRQHandler: +RTCAlarm_IRQHandler: +LPTIMWakeUp_IRQHandler: +USBFS_IRQHandler: +USBFSWakeUp_IRQHandler: +USART4_IRQHandler: +DMA1_Channel8_IRQHandler: +LPTIM_IRQHandler: +OPA_IRQHandler: +USBPD_IRQHandler: +USBPDWakeUp_IRQHandler: +CMPWakeUp_IRQHandler: +1: + j 1b + + .section .text.handle_reset,"ax",@progbits + .weak handle_reset + .align 1 +handle_reset: +.option push +.option norelax + la gp, __global_pointer$ +.option pop +1: + la sp, _eusrstack +2: +/* Load data section from flash to RAM */ + la a0, _data_lma + la a1, _data_vma + la a2, _edata + bgeu a1, a2, 2f +1: + lw t0, (a0) + sw t0, (a1) + addi a0, a0, 4 + addi a1, a1, 4 + bltu a1, a2, 1b +2: +/* Clear bss section */ + la a0, _sbss + la a1, _ebss + bgeu a0, a1, 2f +1: + sw zero, (a0) + addi a0, a0, 4 + bltu a0, a1, 1b +2: +/* Configure pipelining and instruction prediction */ + li t0, 0x1f + csrw 0xbc0, t0 +/* Enable interrupt nesting and hardware stack */ + li t0, 0x3 + csrw 0x804, t0 +/* Enable global interrupt and configure privileged mode */ + li t0, 0x88 + csrw mstatus, t0 +/* Configure the interrupt vector table recognition mode and entry address mode */ + la t0, _vector_base + ori t0, t0, 3 + csrw mtvec, t0 + + jal SystemInit + la t0, main + csrw mepc, t0 + mret + + diff --git a/ZDBMS/BMS_MC/User/ch32l103_conf.h b/ZDBMS/BMS_MC/User/ch32l103_conf.h new file mode 100644 index 0000000..70a29b3 --- /dev/null +++ b/ZDBMS/BMS_MC/User/ch32l103_conf.h @@ -0,0 +1,38 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32l103_conf.h + * Author : WCH + * Version : V1.0.0 + * Date : 2023/07/08 + * Description : Library configuration file. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#ifndef __CH32L103_CONF_H +#define __CH32L103_CONF_H + +#include "ch32l103_adc.h" +#include "ch32l103_bkp.h" +#include "ch32l103_can.h" +#include "ch32l103_crc.h" +#include "ch32l103_dbgmcu.h" +#include "ch32l103_dma.h" +#include "ch32l103_exti.h" +#include "ch32l103_flash.h" +#include "ch32l103_gpio.h" +#include "ch32l103_i2c.h" +#include "ch32l103_iwdg.h" +#include "ch32l103_pwr.h" +#include "ch32l103_rcc.h" +#include "ch32l103_rtc.h" +#include "ch32l103_spi.h" +#include "ch32l103_tim.h" +#include "ch32l103_usart.h" +#include "ch32l103_wwdg.h" +#include "ch32l103_it.h" +#include "ch32l103_misc.h" +#include "ch32l103_lptim.h" +#include "ch32l103_opa.h" + +#endif diff --git a/ZDBMS/BMS_MC/User/ch32l103_it.c b/ZDBMS/BMS_MC/User/ch32l103_it.c new file mode 100644 index 0000000..7a8f132 --- /dev/null +++ b/ZDBMS/BMS_MC/User/ch32l103_it.c @@ -0,0 +1,47 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32l103_it.c + * Author : WCH + * Version : V1.0.0 + * Date : 2024/10/30 + * Description : Main Interrupt Service Routines. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#include "ch32l103_it.h" + +void NMI_Handler(void) __attribute__((interrupt("WCH-Interrupt-fast"))); +void HardFault_Handler(void) __attribute__((interrupt("WCH-Interrupt-fast"))); + +/********************************************************************* + * @fn NMI_Handler + * + * @brief This function handles NMI exception. + * + * @return none + */ +void NMI_Handler(void) +{ + while (1) + { + } +} + + +/********************************************************************* + * @fn HardFault_Handler + * + * @brief This function handles Hard Fault exception. + * + * @return none + */ +void HardFault_Handler(void) +{ + NVIC_SystemReset(); + while (1) + { + } +} + + diff --git a/ZDBMS/BMS_MC/User/ch32l103_it.h b/ZDBMS/BMS_MC/User/ch32l103_it.h new file mode 100644 index 0000000..9b40759 --- /dev/null +++ b/ZDBMS/BMS_MC/User/ch32l103_it.h @@ -0,0 +1,17 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32l103_it.h + * Author : WCH + * Version : V1.0.0 + * Date : 2023/07/08 + * Description : This file contains the headers of the interrupt handlers. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#ifndef __CH32L103_IT_H +#define __CH32L103_IT_H + +#include "debug.h" + +#endif diff --git a/ZDBMS/BMS_MC/User/main.c b/ZDBMS/BMS_MC/User/main.c new file mode 100644 index 0000000..5eedf03 --- /dev/null +++ b/ZDBMS/BMS_MC/User/main.c @@ -0,0 +1,50 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : main.c + * Author : WCH + * Version : V1.0.0 + * Date : 2023/12/26 + * Description : Main program body. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ + +/* + *@Note + *USART Print debugging routine: + *USART1_Tx(PA9). + *This example demonstrates using USART1(PA9) as a print debug port output. + * + */ + +#include "debug.h" + +/* Global typedef */ + +/* Global define */ + +/* Global Variable */ + +/********************************************************************* + * @fn main + * + * @brief Main program. + * + * @return none + */ +int main(void) +{ + NVIC_PriorityGroupConfig(NVIC_PriorityGroup_1); + SystemCoreClockUpdate(); + Delay_Init(); + USART_Printf_Init(115200); + printf("SystemClk:%d\r\n", SystemCoreClock); + printf( "ChipID:%08x\r\n", DBGMCU_GetCHIPID() ); + + while(1) + { + Delay_Ms(1000); + printf("This is printf example\r\n"); + } +} diff --git a/ZDBMS/BMS_MC/User/system_ch32l103.c b/ZDBMS/BMS_MC/User/system_ch32l103.c new file mode 100644 index 0000000..73ec2c8 --- /dev/null +++ b/ZDBMS/BMS_MC/User/system_ch32l103.c @@ -0,0 +1,754 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : system_ch32l103.c + * Author : WCH + * Version : V1.0.0 + * Date : 2024/01/22 + * Description : Device Peripheral Access Layer System Source File. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#include "ch32l103.h" + +/* +* Uncomment the line corresponding to the desired System clock (SYSCLK) frequency (after +* reset the HSI is used as SYSCLK source). +* If none of the define below is enabled, the HSI is used as System clock source. +*/ +//#define SYSCLK_FREQ_HSE HSE_VALUE +//#define SYSCLK_FREQ_48MHz_HSE 48000000 +//#define SYSCLK_FREQ_56MHz_HSE 56000000 +//#define SYSCLK_FREQ_72MHz_HSE 72000000 +//#define SYSCLK_FREQ_96MHz_HSE 96000000 +//#define SYSCLK_FREQ_HSI HSI_VALUE +//#define SYSCLK_FREQ_48MHz_HSI 48000000 +//#define SYSCLK_FREQ_56MHz_HSI 56000000 +//#define SYSCLK_FREQ_72MHz_HSI 72000000 +#define SYSCLK_FREQ_96MHz_HSI 96000000 +//#define SYSCLK_FREQ_HSI_LP HSI_LP_VALUE /* Baud rate support less than 62.5Kbps when using UART */ + +/* Clock Definitions */ +#ifdef SYSCLK_FREQ_HSE +uint32_t SystemCoreClock = SYSCLK_FREQ_HSE; /* System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_48MHz_HSE +uint32_t SystemCoreClock = SYSCLK_FREQ_48MHz_HSE; /* System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_56MHz_HSE +uint32_t SystemCoreClock = SYSCLK_FREQ_56MHz_HSE; /* System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_72MHz_HSE +uint32_t SystemCoreClock = SYSCLK_FREQ_72MHz_HSE; /* System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_96MHz_HSE +uint32_t SystemCoreClock = SYSCLK_FREQ_96MHz_HSE; /* System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_48MHz_HSI +uint32_t SystemCoreClock = SYSCLK_FREQ_48MHz_HSI; /* System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_56MHz_HSI +uint32_t SystemCoreClock = SYSCLK_FREQ_56MHz_HSI; /* System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_72MHz_HSI +uint32_t SystemCoreClock = SYSCLK_FREQ_72MHz_HSI; /* System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_96MHz_HSI +uint32_t SystemCoreClock = SYSCLK_FREQ_96MHz_HSI; /* System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_HSI_LP +uint32_t SystemCoreClock = SYSCLK_FREQ_HSI_LP; /* System Clock Frequency (Core Clock) */ +#else +uint32_t SystemCoreClock = HSI_VALUE; /* System Clock Frequency (Core Clock) */ + +#endif + +__I uint8_t HBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; + + +/* system_private_function_proto_types */ +static void SetSysClock(void); + +#ifdef SYSCLK_FREQ_HSE +static void SetSysClockToHSE( void ); +#elif defined SYSCLK_FREQ_48MHz_HSE +static void SetSysClockTo48_HSE( void ); +#elif defined SYSCLK_FREQ_56MHz_HSE +static void SetSysClockTo56_HSE( void ); +#elif defined SYSCLK_FREQ_72MHz_HSE +static void SetSysClockTo72_HSE( void ); +#elif defined SYSCLK_FREQ_96MHz_HSE +static void SetSysClockTo96_HSE( void ); +#elif defined SYSCLK_FREQ_48MHz_HSI +static void SetSysClockTo48_HSI( void ); +#elif defined SYSCLK_FREQ_56MHz_HSI +static void SetSysClockTo56_HSI( void ); +#elif defined SYSCLK_FREQ_72MHz_HSI +static void SetSysClockTo72_HSI( void ); +#elif defined SYSCLK_FREQ_96MHz_HSI +static void SetSysClockTo96_HSI( void ); +#elif defined SYSCLK_FREQ_HSI_LP +static void SetSysClockToHSI_LP( void ); + +#endif + +/********************************************************************* + * @fn SystemInit + * + * @brief Setup the microcontroller system Initialize the Embedded Flash Interface, + * the PLL and update the SystemCoreClock variable. + * + * @return none + */ +void SystemInit (void) +{ + RCC->CTLR |= (uint32_t)0x00000001; + RCC->CFGR0 &= (uint32_t)0x08FF0000; + RCC->CTLR &= (uint32_t)0xFEF6FFFB; + RCC->CTLR &= (uint32_t)0xFFFBFFFF; + RCC->CFGR0 &= (uint32_t)0xFF00FFFF; + RCC->INTR = 0x009F0000; + SetSysClock(); +} + +/********************************************************************* + * @fn SystemCoreClockUpdate + * + * @brief Update SystemCoreClock variable according to Clock Register Values. + * + * @return none + */ +void SystemCoreClockUpdate (void) +{ + uint32_t tmp = 0, pllmull = 0, pllsource = 0; + + tmp = RCC->CFGR0 & RCC_SWS; + + switch (tmp) + { + case 0x00: + if(RCC->CTLR & (1<<2)) + { + SystemCoreClock = HSI_LP_VALUE; + } + else { + SystemCoreClock = HSI_VALUE; + } + break; + case 0x04: + SystemCoreClock = HSE_VALUE; + break; + case 0x08: + pllmull = RCC->CFGR0 & RCC_PLLMULL; + pllsource = RCC->CFGR0 & RCC_PLLSRC; + pllmull = ( pllmull >> 18) + 2; + + if(pllmull == 17) pllmull = 18; + + if (pllsource == 0x00) + { + if(EXTEN->EXTEN_CTR & EXTEN_PLL_HSI_PRE){ + SystemCoreClock = HSI_VALUE * pllmull; + } + else{ + SystemCoreClock = (HSI_VALUE >> 1) * pllmull; + } + } + else + { + if ((RCC->CFGR0 & RCC_PLLXTPRE) != (uint32_t)RESET) + { + SystemCoreClock = (HSE_VALUE >> 1) * pllmull; + } + else + { + SystemCoreClock = HSE_VALUE * pllmull; + } + } + + break; + default: + SystemCoreClock = HSI_VALUE; + break; + } + + tmp = HBPrescTable[((RCC->CFGR0 & RCC_HPRE) >> 4)]; + SystemCoreClock >>= tmp; +} + +/********************************************************************* + * @fn SetSysClock + * + * @brief Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers. + * + * @return none + */ +static void SetSysClock(void) +{ + GPIO_IPD_Unused(); + +#ifdef SYSCLK_FREQ_HSE + SetSysClockToHSE(); +#elif defined SYSCLK_FREQ_48MHz_HSE + SetSysClockTo48_HSE(); +#elif defined SYSCLK_FREQ_56MHz_HSE + SetSysClockTo56_HSE(); +#elif defined SYSCLK_FREQ_72MHz_HSE + SetSysClockTo72_HSE(); +#elif defined SYSCLK_FREQ_96MHz_HSE + SetSysClockTo96_HSE(); +#elif defined SYSCLK_FREQ_48MHz_HSI + SetSysClockTo48_HSI(); +#elif defined SYSCLK_FREQ_56MHz_HSI + SetSysClockTo56_HSI(); +#elif defined SYSCLK_FREQ_72MHz_HSI + SetSysClockTo72_HSI(); +#elif defined SYSCLK_FREQ_96MHz_HSI + SetSysClockTo96_HSI(); +#elif defined SYSCLK_FREQ_HSI_LP + SetSysClockToHSI_LP(); + +#endif + + /* If none of the define above is enabled, the HSI is used as System clock + * source (default after reset) + */ +} + + +#ifdef SYSCLK_FREQ_HSE + +/********************************************************************* + * @fn SetSysClockToHSE + * + * @brief Sets HSE as System clock source and configure HCLK, PCLK2 and PCLK1 prescalers. + * + * @return none + */ +static void SetSysClockToHSE(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* Flash 0 wait state */ + FLASH->ACTLR = (uint32_t)FLASH_ACTLR_LATENCY_0; + + RCC->CTLR |= ((uint32_t)RCC_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CTLR & RCC_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CTLR & RCC_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* HCLK = SYSCLK */ + RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; + /* PCLK2 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1; + /* PCLK1 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV1; + + /* Select HSE as system clock source */ + RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW)); + RCC->CFGR0 |= (uint32_t)RCC_SW_HSE; + + /* Wait till HSE is used as system clock source */ + while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x04) + { + } + } + else + { + /* Flash 0 wait state */ + FLASH->ACTLR &= (uint32_t)((uint32_t)~FLASH_ACTLR_LATENCY); + + /* If HSE fails to start-up, the application will have wrong clock + * configuration. User can add here some code to deal with this error + */ + } +} + +#elif defined SYSCLK_FREQ_48MHz_HSE + +/********************************************************************* + * @fn SetSysClockTo48_HSE + * + * @brief Sets System clock frequency to 48MHz and configure HCLK, PCLK2 and PCLK1 prescalers. + * + * @return none + */ +static void SetSysClockTo48_HSE(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* Flash 1 wait state */ + FLASH->ACTLR = (uint32_t)FLASH_ACTLR_LATENCY_1; + + RCC->CTLR |= ((uint32_t)RCC_HSEON); + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CTLR & RCC_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CTLR & RCC_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* HCLK = SYSCLK */ + RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; + /* PCLK2 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1; + /* PCLK1 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2; + + /* PLL configuration: PLLCLK = HSE * 6 = 48 MHz (HSE=8MHZ) */ + RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL)); + RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL6); + + /* Enable PLL */ + RCC->CTLR |= RCC_PLLON; + /* Wait till PLL is ready */ + while((RCC->CTLR & RCC_PLLRDY) == 0) + { + } + /* Select PLL as system clock source */ + RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW)); + RCC->CFGR0 |= (uint32_t)RCC_SW_PLL; + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08) + { + } + } + else + { + /* Flash 0 wait state */ + FLASH->ACTLR &= (uint32_t)((uint32_t)~FLASH_ACTLR_LATENCY); + + /* If HSE fails to start-up, the application will have wrong clock + * configuration. User can add here some code to deal with this error + */ + } +} + +#elif defined SYSCLK_FREQ_56MHz_HSE + +/********************************************************************* + * @fn SetSysClockTo56_HSE + * + * @brief Sets System clock frequency to 56MHz and configure HCLK, PCLK2 and PCLK1 prescalers. + * + * @return none + */ +static void SetSysClockTo56_HSE(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* Flash 1 wait state */ + FLASH->ACTLR = (uint32_t)FLASH_ACTLR_LATENCY_1; + + RCC->CTLR |= ((uint32_t)RCC_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CTLR & RCC_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CTLR & RCC_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* HCLK = SYSCLK */ + RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; + /* PCLK2 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1; + /* PCLK1 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2; + + /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz (HSE=8MHZ) */ + RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL)); + RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL7); + + /* Enable PLL */ + RCC->CTLR |= RCC_PLLON; + /* Wait till PLL is ready */ + while((RCC->CTLR & RCC_PLLRDY) == 0) + { + } + + /* Select PLL as system clock source */ + RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW)); + RCC->CFGR0 |= (uint32_t)RCC_SW_PLL; + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08) + { + } + } + else + { + /* Flash 0 wait state */ + FLASH->ACTLR &= (uint32_t)((uint32_t)~FLASH_ACTLR_LATENCY); + + /* If HSE fails to start-up, the application will have wrong clock + * configuration. User can add here some code to deal with this error + */ + } +} + +#elif defined SYSCLK_FREQ_72MHz_HSE + +/********************************************************************* + * @fn SetSysClockTo72_HSE + * + * @brief Sets System clock frequency to 72MHz and configure HCLK, PCLK2 and PCLK1 prescalers. + * + * @return none + */ +static void SetSysClockTo72_HSE(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* Flash 1 wait state */ + FLASH->ACTLR = (uint32_t)FLASH_ACTLR_LATENCY_1; + + RCC->CTLR |= ((uint32_t)RCC_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CTLR & RCC_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CTLR & RCC_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* HCLK = SYSCLK */ + RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; + /* PCLK2 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1; + /* PCLK1 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2; + + /* PLL configuration: PLLCLK = HSE * 9 = 72 MHz (HSE=8MHZ) */ + RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL)); + RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL9); + + /* Enable PLL */ + RCC->CTLR |= RCC_PLLON; + /* Wait till PLL is ready */ + while((RCC->CTLR & RCC_PLLRDY) == 0) + { + } + /* Select PLL as system clock source */ + RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW)); + RCC->CFGR0 |= (uint32_t)RCC_SW_PLL; + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08) + { + } + } + else + { + /* Flash 0 wait state */ + FLASH->ACTLR &= (uint32_t)((uint32_t)~FLASH_ACTLR_LATENCY); + + /* If HSE fails to start-up, the application will have wrong clock + * configuration. User can add here some code to deal with this error + */ + } +} + + +#elif defined SYSCLK_FREQ_96MHz_HSE + +/********************************************************************* + * @fn SetSysClockTo96_HSE + * + * @brief Sets System clock frequency to 96MHz and configure HCLK, PCLK2 and PCLK1 prescalers. + * + * @return none + */ +static void SetSysClockTo96_HSE(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* Flash 2 wait state */ + FLASH->ACTLR = (uint32_t)FLASH_ACTLR_LATENCY_2; + + RCC->CTLR |= ((uint32_t)RCC_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CTLR & RCC_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CTLR & RCC_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* HCLK = SYSCLK */ + RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; + /* PCLK2 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1; + /* PCLK1 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2; + + /* PLL configuration: PLLCLK = HSE * 12 = 96 MHz (HSE=8MHZ) */ + RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL)); + RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL12); + + /* Enable PLL */ + RCC->CTLR |= RCC_PLLON; + /* Wait till PLL is ready */ + while((RCC->CTLR & RCC_PLLRDY) == 0) + { + } + /* Select PLL as system clock source */ + RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW)); + RCC->CFGR0 |= (uint32_t)RCC_SW_PLL; + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08) + { + } + } + else + { + /* Flash 0 wait state */ + FLASH->ACTLR &= (uint32_t)((uint32_t)~FLASH_ACTLR_LATENCY); + + /* If HSE fails to start-up, the application will have wrong clock + * configuration. User can add here some code to deal with this error + */ + } +} + +#elif defined SYSCLK_FREQ_48MHz_HSI + +/********************************************************************* + * @fn SetSysClockTo48_HSI + * + * @brief Sets System clock frequency to 48MHz and configure HCLK, PCLK2 and PCLK1 prescalers. + * + * @return none + */ +static void SetSysClockTo48_HSI(void) +{ + /* Flash 1 wait state */ + FLASH->ACTLR = (uint32_t)FLASH_ACTLR_LATENCY_1; + + EXTEN->EXTEN_CTR |= EXTEN_PLL_HSI_PRE; + + /* HCLK = SYSCLK */ + RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; + /* PCLK2 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1; + /* PCLK1 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2; + + /* PLL configuration: PLLCLK = HSI * 6 = 48 MHz */ + RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL)); + RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL6); + + /* Enable PLL */ + RCC->CTLR |= RCC_PLLON; + /* Wait till PLL is ready */ + while((RCC->CTLR & RCC_PLLRDY) == 0) + { + } + /* Select PLL as system clock source */ + RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW)); + RCC->CFGR0 |= (uint32_t)RCC_SW_PLL; + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08) + { + } +} + +#elif defined SYSCLK_FREQ_56MHz_HSI + +/********************************************************************* + * @fn SetSysClockTo56_HSI + * + * @brief Sets System clock frequency to 56MHz and configure HCLK, PCLK2 and PCLK1 prescalers. + * + * @return none + */ +static void SetSysClockTo56_HSI(void) +{ + /* Flash 1 wait state */ + FLASH->ACTLR = (uint32_t)FLASH_ACTLR_LATENCY_1; + + EXTEN->EXTEN_CTR |= EXTEN_PLL_HSI_PRE; + + /* HCLK = SYSCLK */ + RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; + /* PCLK2 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1; + /* PCLK1 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2; + + /* PLL configuration: PLLCLK = HSI * 7 = 56 MHz */ + RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL)); + RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL7); + + /* Enable PLL */ + RCC->CTLR |= RCC_PLLON; + /* Wait till PLL is ready */ + while((RCC->CTLR & RCC_PLLRDY) == 0) + { + } + /* Select PLL as system clock source */ + RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW)); + RCC->CFGR0 |= (uint32_t)RCC_SW_PLL; + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08) + { + } +} + +#elif defined SYSCLK_FREQ_72MHz_HSI + +/********************************************************************* + * @fn SetSysClockTo72_HSI + * + * @brief Sets System clock frequency to 72MHz and configure HCLK, PCLK2 and PCLK1 prescalers. + * + * @return none + */ +static void SetSysClockTo72_HSI(void) +{ + /* Flash 1 wait state */ + FLASH->ACTLR = (uint32_t)FLASH_ACTLR_LATENCY_1; + + EXTEN->EXTEN_CTR |= EXTEN_PLL_HSI_PRE; + + /* HCLK = SYSCLK */ + RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; + /* PCLK2 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1; + /* PCLK1 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2; + + /* PLL configuration: PLLCLK = HSI * 9 = 72 MHz */ + RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL)); + RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL9); + + /* Enable PLL */ + RCC->CTLR |= RCC_PLLON; + /* Wait till PLL is ready */ + while((RCC->CTLR & RCC_PLLRDY) == 0) + { + } + /* Select PLL as system clock source */ + RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW)); + RCC->CFGR0 |= (uint32_t)RCC_SW_PLL; + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08) + { + } +} + +#elif defined SYSCLK_FREQ_96MHz_HSI + +/********************************************************************* + * @fn SetSysClockTo96_HSI + * + * @brief Sets System clock frequency to 96MHz and configure HCLK, PCLK2 and PCLK1 prescalers. + * + * @return none + */ +static void SetSysClockTo96_HSI(void) +{ + /* Flash 2 wait state */ + FLASH->ACTLR = (uint32_t)FLASH_ACTLR_LATENCY_2; + + EXTEN->EXTEN_CTR |= EXTEN_PLL_HSI_PRE; + + /* HCLK = SYSCLK */ + RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; + /* PCLK2 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1; + /* PCLK1 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2; + + /* PLL configuration: PLLCLK = HSI * 12 = 96 MHz */ + RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL)); + RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL12); + + /* Enable PLL */ + RCC->CTLR |= RCC_PLLON; + /* Wait till PLL is ready */ + while((RCC->CTLR & RCC_PLLRDY) == 0) + { + } + /* Select PLL as system clock source */ + RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW)); + RCC->CFGR0 |= (uint32_t)RCC_SW_PLL; + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08) + { + } +} + +#elif defined SYSCLK_FREQ_HSI_LP + +/********************************************************************* + * @fn SetSysClockToHSI_LP + * + * @brief Sets HSI as System clock source of Low power and configure HCLK, PCLK2 and PCLK1 prescalers. + * In this mode, HSI is 1MHz and Baud rate support less than 62.5Kbps when using UART. + * + * @return none + */ +static void SetSysClockToHSI_LP(void) +{ + RCC_HSI_LP_Cmd(ENABLE); + + /* HCLK = SYSCLK */ + RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; + /* PCLK2 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1; + /* PCLK1 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV1; + /* Low power mode HSI */ + RCC_AdjustHSICalibrationValue((*(uint8_t*)HSI_LP_TRIM_BASE)&0x1F); +} + +#endif diff --git a/ZDBMS/BMS_MC/User/system_ch32l103.h b/ZDBMS/BMS_MC/User/system_ch32l103.h new file mode 100644 index 0000000..0143c56 --- /dev/null +++ b/ZDBMS/BMS_MC/User/system_ch32l103.h @@ -0,0 +1,29 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : system_ch32l103.h + * Author : WCH + * Version : V1.0.0 + * Date : 2023/07/08 + * Description : CH32L103 Device Peripheral Access Layer System Header File. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#ifndef __SYSTEM_ch32l103_H +#define __SYSTEM_ch32l103_H + +#ifdef __cplusplus +extern "C" { +#endif + +extern uint32_t SystemCoreClock; /* System Clock Frequency (Core Clock) */ + +/* System_Exported_Functions */ +extern void SystemInit(void); +extern void SystemCoreClockUpdate(void); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/ZDBMS/BMS_MC/obj/BMS_MC.elf b/ZDBMS/BMS_MC/obj/BMS_MC.elf new file mode 100644 index 0000000000000000000000000000000000000000..944f7d2358e2c6af83c76bd231b4b246bad33293 GIT binary patch literal 101624 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+:101E140000000000000000000000000000000000BE +:101E240000000000000000000000000000000000AE +:101E340000D8B80502040608C000002020000020D5 +:081E4400200000200000000056 +:00000001FF diff --git a/ZDBMS/BMS_MC/obj/BMS_MC.lst b/ZDBMS/BMS_MC/obj/BMS_MC.lst new file mode 100644 index 0000000..231a04b --- /dev/null +++ b/ZDBMS/BMS_MC/obj/BMS_MC.lst @@ -0,0 +1,3310 @@ + +BMS_MC.elf: file format elf32-littleriscv +BMS_MC.elf +architecture: riscv:rv32, flags 0x00000112: +EXEC_P, HAS_SYMS, D_PAGED +start address 0x00000000 + +Program Header: + LOAD off 0x00001000 vaddr 0x00000000 paddr 0x00000000 align 2**12 + filesz 0x00001db4 memsz 0x00001db4 flags r-x + LOAD off 0x00003000 vaddr 0x20000000 paddr 0x00001db4 align 2**12 + filesz 0x00000098 memsz 0x000000c0 flags rw- + LOAD off 0x00003800 vaddr 0x20004800 paddr 0x20004800 align 2**12 + filesz 0x00000000 memsz 0x00000800 flags rw- + +Sections: +Idx Name Size VMA LMA File off Algn + 0 .init 00000004 00000000 00000000 00001000 2**1 + CONTENTS, ALLOC, LOAD, READONLY, CODE + 1 .vector 0000013c 00000004 00000004 00001004 2**1 + CONTENTS, ALLOC, LOAD, READONLY, CODE + 2 .text 00001c74 00000140 00000140 00001140 2**2 + CONTENTS, ALLOC, LOAD, READONLY, CODE + 3 .fini 00000000 00001db4 00001db4 00003098 2**0 + CONTENTS, ALLOC, LOAD, CODE + 4 .dalign 00000000 20000000 20000000 00003098 2**0 + CONTENTS + 5 .dlalign 00000000 00001db4 00001db4 00003098 2**0 + CONTENTS + 6 .data 00000098 20000000 00001db4 00003000 2**2 + CONTENTS, ALLOC, LOAD, DATA + 7 .bss 00000028 20000098 00001e4c 00003098 2**2 + ALLOC + 8 .stack 00000800 20004800 20004800 00003800 2**0 + ALLOC + 9 .debug_info 0000857c 00000000 00000000 00003098 2**0 + CONTENTS, READONLY, DEBUGGING + 10 .debug_abbrev 0000197a 00000000 00000000 0000b614 2**0 + CONTENTS, READONLY, DEBUGGING + 11 .debug_aranges 00000430 00000000 00000000 0000cf90 2**3 + CONTENTS, READONLY, DEBUGGING + 12 .debug_ranges 000003e0 00000000 00000000 0000d3c0 2**3 + CONTENTS, READONLY, DEBUGGING + 13 .debug_line 00004fb9 00000000 00000000 0000d7a0 2**0 + CONTENTS, READONLY, DEBUGGING + 14 .debug_str 000018fc 00000000 00000000 00012759 2**0 + CONTENTS, READONLY, DEBUGGING + 15 .comment 00000033 00000000 00000000 00014055 2**0 + CONTENTS, READONLY + 16 .debug_frame 000010a0 00000000 00000000 00014088 2**2 + CONTENTS, READONLY, DEBUGGING + 17 .debug_loc 00001a6d 00000000 00000000 00015128 2**0 + CONTENTS, READONLY, DEBUGGING + 18 .stab 00000084 00000000 00000000 00016b98 2**2 + CONTENTS, READONLY, DEBUGGING + 19 .stabstr 00000117 00000000 00000000 00016c1c 2**0 + CONTENTS, READONLY, DEBUGGING +SYMBOL TABLE: +00000000 l d .init 00000000 .init +00000004 l d .vector 00000000 .vector +00000140 l d .text 00000000 .text +00001db4 l d .fini 00000000 .fini +20000000 l d .dalign 00000000 .dalign +00001db4 l d .dlalign 00000000 .dlalign +20000000 l d .data 00000000 .data +20000098 l d .bss 00000000 .bss +20004800 l d .stack 00000000 .stack +00000000 l d .debug_info 00000000 .debug_info +00000000 l d .debug_abbrev 00000000 .debug_abbrev +00000000 l d .debug_aranges 00000000 .debug_aranges +00000000 l d .debug_ranges 00000000 .debug_ranges +00000000 l d .debug_line 00000000 .debug_line +00000000 l d .debug_str 00000000 .debug_str +00000000 l d .comment 00000000 .comment +00000000 l d .debug_frame 00000000 .debug_frame +00000000 l d .debug_loc 00000000 .debug_loc +00000000 l d .stab 00000000 .stab +00000000 l d .stabstr 00000000 .stabstr +00000000 l df *ABS* 00000000 ./Startup/startup_ch32l103.o +00000004 l .vector 00000000 _vector_base +00000000 l df *ABS* 00000000 ch32l103_it.c +00000000 l df *ABS* 00000000 main.c +00000000 l df *ABS* 00000000 system_ch32l103.c +00000000 l df *ABS* 00000000 ch32l103_dbgmcu.c +00000000 l df *ABS* 00000000 ch32l103_gpio.c +00000000 l df *ABS* 00000000 ch32l103_misc.c +00000000 l df *ABS* 00000000 ch32l103_rcc.c +20000010 l O .data 00000010 PBHBPrescTable +20000084 l O .data 00000004 ADCPrescTable +00000000 l df *ABS* 00000000 ch32l103_usart.c +00000000 l df *ABS* 00000000 debug.c +200000b0 l O .bss 00000002 p_ms +200000b2 l O .bss 00000002 p_us +20000088 l O .data 00000004 curbrk.5011 +00000000 l df *ABS* 00000000 printf.c +00000000 l df *ABS* 00000000 puts.c +00000000 l df *ABS* 00000000 wbuf.c +00000000 l df *ABS* 00000000 wsetup.c +00000000 l df *ABS* 00000000 fflush.c +00000000 l df *ABS* 00000000 findfp.c +00000f94 l F .text 00000066 std +00000000 l df *ABS* 00000000 fwalk.c +00000000 l df *ABS* 00000000 makebuf.c +00000000 l df *ABS* 00000000 nano-mallocr.c +00000000 l df *ABS* 00000000 nano-mallocr.c +00000000 l df *ABS* 00000000 nano-vfprintf.c +0000141a l F .text 00000028 __sfputc_r +00000000 l df *ABS* 00000000 nano-vfprintf_i.c +00000000 l df *ABS* 00000000 sbrkr.c +00000000 l df *ABS* 00000000 stdio.c +00000000 l df *ABS* 00000000 writer.c +00000000 l df *ABS* 00000000 closer.c +00000000 l df *ABS* 00000000 fstatr.c +00000000 l df *ABS* 00000000 isattyr.c +00000000 l df *ABS* 00000000 lseekr.c +00000000 l df *ABS* 00000000 memchr.c +00000000 l df *ABS* 00000000 mlock.c +00000000 l df *ABS* 00000000 readr.c +00000000 l df *ABS* 00000000 close.c +00000000 l df *ABS* 00000000 fstat.c +00000000 l df *ABS* 00000000 isatty.c +00000000 l df *ABS* 00000000 lseek.c +00000000 l df *ABS* 00000000 read.c +00000000 l df *ABS* 00000000 impure.c +20000020 l O .data 00000060 impure_data +00000000 l df *ABS* 00000000 reent.c +0000040a w .text 00000000 EXTI2_IRQHandler +00001c06 g F .text 00000028 _isatty_r +00000b6a g F .text 000000d4 _puts_r +00001c2e g F .text 0000002c _lseek_r +00000b2a g F .text 00000040 printf +20000880 g .data 00000000 __global_pointer$ +00000148 g F .text 00000028 .hidden __riscv_save_8 +0000040a w .text 00000000 TIM1_CC_IRQHandler +00001b50 g F .text 00000030 __sseek +0000104a g F .text 00000066 __sinit +00000c48 g F .text 000000bc __swbuf_r +0000024a g F .text 00000010 HardFault_Handler +00001004 g F .text 00000046 __sfmoreglue +00001c74 g F .text 00000002 __malloc_unlock +0000040a w .text 00000000 USBPD_IRQHandler +00000194 g F .text 0000000c .hidden __riscv_restore_3 +0000040a w .text 00000000 SysTick_Handler +0000040a w .text 00000000 PVD_IRQHandler +00000180 g F .text 00000020 .hidden __riscv_restore_10 +00000248 g F .text 00000002 NMI_Handler +0000040a w .text 00000000 EXTI3_IRQHandler +00000148 g F .text 00000028 .hidden __riscv_save_11 +00000492 g F .text 00000006 DBGMCU_GetCHIPID +00000a18 g F .text 0000000a USART_GetFlagStatus +00001bdc g F .text 0000002a _fstat_r +200000a8 g O .bss 00000002 USBPD_CFG +200000bc g O .bss 00000004 errno +20000098 g .bss 00000000 _sbss +00000800 g *ABS* 00000000 __stack_size +00000a78 g F .text 00000052 USART_Printf_Init +0000040a w .text 00000000 USBFS_IRQHandler +00000194 g F .text 0000000c .hidden __riscv_restore_2 +00000ffa g F .text 0000000a _cleanup_r +00000558 g F .text 0000012c GPIO_PinRemapConfig +0000040a w .text 00000000 EXTI0_IRQHandler +0000040a w .text 00000000 I2C2_EV_IRQHandler +0000040a w .text 00000000 LPTIM_IRQHandler +00000c3e g F .text 0000000a puts +20000080 g O .data 00000004 SystemCoreClock +00001cae g F .text 0000000c _fstat +00000004 g .init 00000000 _einit +00000140 g F .text 00000030 .hidden __riscv_save_12 +00000498 g F .text 000000c0 GPIO_Init +0000040a w .text 00000000 Break_Point_Handler +00000180 g F .text 00000020 .hidden __riscv_restore_11 +200000ac g O .bss 00000004 NVIC_Priority_Group +0000040a w .text 00000000 SPI1_IRQHandler +000009fa g F .text 00000016 USART_Cmd +00001ab2 g F .text 0000002a _sbrk_r +2000009c g O .bss 00000004 CHIPID +0000040a w .text 00000000 TAMPER_IRQHandler +00000170 g F .text 0000000c .hidden __riscv_save_1 +00000194 g F .text 0000000c .hidden __riscv_restore_0 +00001c76 g F .text 0000002c _read_r +00000156 g F .text 0000001a .hidden __riscv_save_7 +0000040a w .text 00000000 Ecall_M_Mode_Handler +20004800 g .stack 00000000 _heap_end +00001cba g F .text 0000000c _isatty +20000090 g O .data 00000004 _global_impure_ptr +0000018a g F .text 00000016 .hidden __riscv_restore_5 +20000098 g O .bss 00000002 ADC_Trim +0000040a w .text 00000000 DMA1_Channel4_IRQHandler +00000b04 g F .text 00000026 _sbrk +0000018a g F .text 00000016 .hidden __riscv_restore_6 +0000040a w .text 00000000 USART3_IRQHandler +0000040a w .text 00000000 RTC_IRQHandler +200000c0 g .bss 00000000 _ebss +0000040a w .text 00000000 DMA1_Channel7_IRQHandler +0000040a w .text 00000000 CAN1_RX1_IRQHandler +00000a22 g F .text 00000020 Delay_Init +00000922 g F .text 0000001e RCC_PB2PeriphClockCmd +00000684 g F .text 000001c2 GPIO_IPD_Unused +0000040a w .text 00000000 USBPDWakeUp_IRQHandler +0000040a w .text 00000000 TIM4_IRQHandler +00000148 g F .text 00000028 .hidden __riscv_save_9 +00001d18 g O .text 00000020 __sf_fake_stderr +00000156 g F .text 0000001a .hidden __riscv_save_4 +0000040a w .text 00000000 I2C1_EV_IRQHandler +0000040a w .text 00000000 USART4_IRQHandler +0000084c g F .text 000000d6 RCC_GetClocksFreq +0000040a w .text 00000000 DMA1_Channel6_IRQHandler +00001442 g F .text 00000040 __sfputs_r +200000a4 g O .bss 00000004 TS_Val +00001c5a g F .text 00000018 memchr +00000940 g F .text 000000ba USART_Init +0000129e g F .text 000000a8 _free_r +0000040a w .text 00000000 TIM3_IRQHandler +0000040a w .text 00000000 RCC_IRQHandler +00000170 g F .text 0000000c .hidden __riscv_save_3 +0000040a w .text 00000000 TIM1_TRG_COM_IRQHandler +0000040a w .text 00000000 DMA1_Channel1_IRQHandler +00000000 g .init 00000000 _start +00001cc6 g F .text 0000000c _lseek +0000040a w .text 00000000 EXTI15_10_IRQHandler +0000040a w .text 00000000 ADC_IRQHandler +200000a0 g O .bss 00000004 OPA_Trim +0000040a w .text 00000000 DMA1_Channel8_IRQHandler +00001bb4 g F .text 00000028 _close_r +20000000 g .dalign 00000000 _data_vma +00000d04 g F .text 000000fc __swsetup_r +0000040a w .text 00000000 EXTI9_5_IRQHandler +000010b0 g F .text 0000009c __sfp +00000148 g F .text 00000028 .hidden __riscv_save_10 +00001adc g F .text 0000002c __sread +00001c72 g F .text 00000002 __malloc_lock +0000018a g F .text 00000016 .hidden __riscv_restore_4 +00000180 g F .text 00000020 .hidden __riscv_restore_8 +00000f30 g F .text 00000064 _fflush_r +00000156 g F .text 0000001a .hidden __riscv_save_6 +0000040a w .text 00000000 SPI2_IRQHandler +00001d38 g O .text 00000020 __sf_fake_stdin +000001a0 g F .text 000000a8 memset +00000180 g F .text 00000020 .hidden __riscv_restore_9 +0000018a g F .text 00000016 .hidden __riscv_restore_7 +0000025a g F .text 00000052 main +00001b80 g F .text 00000006 __sclose +00001346 g F .text 000000d4 _malloc_r +0000040a w .text 00000000 DMA1_Channel5_IRQHandler +0000040a w .text 00000000 EXTI4_IRQHandler +00000a42 g F .text 00000036 Delay_Ms +0000040a w .text 00000000 USB_LP_CAN1_RX0_IRQHandler +000002ac g F .text 000000ba SystemInit +00000b2a g F .text 00000040 iprintf +0000040a w .text 00000000 USB_HP_CAN1_TX_IRQHandler +00000000 g .init 00000000 _sinit +0000040a w .text 00000000 CMPWakeUp_IRQHandler +00001b86 g F .text 0000002e _write_r +0000040a w .text 00000000 DMA1_Channel3_IRQHandler +00001706 g F .text 0000010c _printf_common +2000008c g O .data 00000004 _impure_ptr +0000040a w .text 00000000 TIM1_UP_IRQHandler +00000e00 g F .text 00000130 __sflush_r +0000040a w .text 00000000 LPTIMWakeUp_IRQHandler +0000040a w .text 00000000 WWDG_IRQHandler +0000040a w .text 00000000 Ecall_U_Mode_Handler +0000040a w .text 00000000 TIM2_IRQHandler +20005000 g .stack 00000000 _eusrstack +00000170 g F .text 0000000c .hidden __riscv_save_2 +0000040a w .text 00000000 SW_Handler +0000040a w .text 00000000 TIM1_BRK_IRQHandler +000011b6 g F .text 00000058 __swhatbuf_r +00000a10 g F .text 00000008 USART_SendData +0000040a w .text 00000000 OPA_IRQHandler +0000040a w .text 00000000 EXTI1_IRQHandler +00000156 g F .text 0000001a .hidden __riscv_save_5 +00000aca g F .text 0000003a _write +20000098 g .data 00000000 _edata +200000c0 g .bss 00000000 _end +0000040a w .text 00000000 RTCAlarm_IRQHandler +00001db4 g .dlalign 00000000 _data_lma +0000040a w .text 00000000 USART2_IRQHandler +00001b08 g F .text 00000048 __swrite +00001482 g F .text 00000284 _vfiprintf_r +0000114c g F .text 0000006a _fwalk_reent +00000366 g F .text 000000a4 SystemCoreClockUpdate +0000040a w .text 00000000 I2C2_ER_IRQHandler +0000040a w .text 00000000 DMA1_Channel2_IRQHandler +00001d58 g O .text 00000020 __sf_fake_stdout +20000000 g O .data 00000010 HBPrescTable +0000017c g F .text 00000024 .hidden __riscv_restore_12 +00001cd2 g F .text 0000000c _read +0000040c w .text 00000000 handle_reset +0000040a w .text 00000000 CAN1_SCE_IRQHandler +00000170 g F .text 0000000c .hidden __riscv_save_0 +0000040a w .text 00000000 FLASH_IRQHandler +0000040a w .text 00000000 USBFSWakeUp_IRQHandler +0000040a w .text 00000000 USART1_IRQHandler +0000120e g F .text 00000090 __smakebuf_r +00001812 g F .text 000002a0 _printf_i +200000b8 g O .bss 00000004 __malloc_sbrk_start +0000040a w .text 00000000 I2C1_ER_IRQHandler +00000846 g F .text 00000006 NVIC_PriorityGroupConfig +200000b4 g O .bss 00000004 __malloc_free_list +00000194 g F .text 0000000c .hidden __riscv_restore_1 +00001482 g F .text 00000284 _vfprintf_r +00001ca2 g F .text 0000000c _close + + + +Disassembly of section .init: + +00000000 <_sinit>: + 0: 40c0006f j 40c + +Disassembly of section .vector: + +00000004 <_vector_base>: + ... + c: 0248 addi a0,sp,260 + e: 0000 unimp + 10: 024a slli tp,tp,0x12 + 12: 0000 unimp + 14: 0000 unimp + 16: 0000 unimp + 18: 040a slli s0,s0,0x2 + ... + 22: 0000 unimp + 24: 040a slli s0,s0,0x2 + 26: 0000 unimp + 28: 040a slli s0,s0,0x2 + ... + 32: 0000 unimp + 34: 040a slli s0,s0,0x2 + 36: 0000 unimp + 38: 0000 unimp + 3a: 0000 unimp + 3c: 040a slli s0,s0,0x2 + 3e: 0000 unimp + 40: 0000 unimp + 42: 0000 unimp + 44: 040a slli s0,s0,0x2 + 46: 0000 unimp + 48: 040a slli s0,s0,0x2 + 4a: 0000 unimp + 4c: 040a slli s0,s0,0x2 + 4e: 0000 unimp + 50: 040a slli s0,s0,0x2 + 52: 0000 unimp + 54: 040a slli s0,s0,0x2 + 56: 0000 unimp + 58: 040a slli s0,s0,0x2 + 5a: 0000 unimp + 5c: 040a slli s0,s0,0x2 + 5e: 0000 unimp + 60: 040a slli s0,s0,0x2 + 62: 0000 unimp + 64: 040a slli s0,s0,0x2 + 66: 0000 unimp + 68: 040a slli s0,s0,0x2 + 6a: 0000 unimp + 6c: 040a slli s0,s0,0x2 + 6e: 0000 unimp + 70: 040a slli s0,s0,0x2 + 72: 0000 unimp + 74: 040a slli s0,s0,0x2 + 76: 0000 unimp + 78: 040a slli s0,s0,0x2 + 7a: 0000 unimp + 7c: 040a slli s0,s0,0x2 + 7e: 0000 unimp + 80: 040a slli s0,s0,0x2 + 82: 0000 unimp + 84: 040a slli s0,s0,0x2 + 86: 0000 unimp + 88: 040a slli s0,s0,0x2 + 8a: 0000 unimp + 8c: 040a slli s0,s0,0x2 + 8e: 0000 unimp + 90: 040a slli s0,s0,0x2 + 92: 0000 unimp + 94: 040a slli s0,s0,0x2 + 96: 0000 unimp + 98: 040a slli s0,s0,0x2 + 9a: 0000 unimp + 9c: 040a slli s0,s0,0x2 + 9e: 0000 unimp + a0: 040a slli s0,s0,0x2 + a2: 0000 unimp + a4: 040a slli s0,s0,0x2 + a6: 0000 unimp + a8: 040a slli s0,s0,0x2 + aa: 0000 unimp + ac: 040a slli s0,s0,0x2 + ae: 0000 unimp + b0: 040a slli s0,s0,0x2 + b2: 0000 unimp + b4: 040a slli s0,s0,0x2 + b6: 0000 unimp + b8: 040a slli s0,s0,0x2 + ba: 0000 unimp + bc: 040a slli s0,s0,0x2 + be: 0000 unimp + c0: 040a slli s0,s0,0x2 + c2: 0000 unimp + c4: 040a slli s0,s0,0x2 + c6: 0000 unimp + c8: 040a slli s0,s0,0x2 + ca: 0000 unimp + cc: 040a slli s0,s0,0x2 + ce: 0000 unimp + d0: 040a slli s0,s0,0x2 + d2: 0000 unimp + d4: 040a slli s0,s0,0x2 + d6: 0000 unimp + d8: 040a slli s0,s0,0x2 + da: 0000 unimp + dc: 040a slli s0,s0,0x2 + de: 0000 unimp + e0: 040a slli s0,s0,0x2 + e2: 0000 unimp + e4: 040a slli s0,s0,0x2 + e6: 0000 unimp + e8: 040a slli s0,s0,0x2 + ea: 0000 unimp + ec: 040a slli s0,s0,0x2 + ee: 0000 unimp + f0: 040a slli s0,s0,0x2 + f2: 0000 unimp + f4: 040a slli s0,s0,0x2 + f6: 0000 unimp + f8: 040a slli s0,s0,0x2 + fa: 0000 unimp + fc: 040a slli s0,s0,0x2 + fe: 0000 unimp + 100: 040a slli s0,s0,0x2 + 102: 0000 unimp + 104: 040a slli s0,s0,0x2 + 106: 0000 unimp + 108: 040a slli s0,s0,0x2 + 10a: 0000 unimp + 10c: 0000 unimp + 10e: 0000 unimp + 110: 040a slli s0,s0,0x2 + 112: 0000 unimp + 114: 040a slli s0,s0,0x2 + ... + +Disassembly of section .text: + +00000140 <__riscv_save_12>: + 140: 7139 addi sp,sp,-64 + 142: 4301 li t1,0 + 144: c66e sw s11,12(sp) + 146: a019 j 14c <__riscv_save_10+0x4> + +00000148 <__riscv_save_10>: + 148: 7139 addi sp,sp,-64 + 14a: 5341 li t1,-16 + 14c: c86a sw s10,16(sp) + 14e: ca66 sw s9,20(sp) + 150: cc62 sw s8,24(sp) + 152: ce5e sw s7,28(sp) + 154: a019 j 15a <__riscv_save_4+0x4> + +00000156 <__riscv_save_4>: + 156: 7139 addi sp,sp,-64 + 158: 5301 li t1,-32 + 15a: d05a sw s6,32(sp) + 15c: d256 sw s5,36(sp) + 15e: d452 sw s4,40(sp) + 160: d64e sw s3,44(sp) + 162: d84a sw s2,48(sp) + 164: da26 sw s1,52(sp) + 166: dc22 sw s0,56(sp) + 168: de06 sw ra,60(sp) + 16a: 40610133 sub sp,sp,t1 + 16e: 8282 jr t0 + +00000170 <__riscv_save_0>: + 170: 1141 addi sp,sp,-16 + 172: c04a sw s2,0(sp) + 174: c226 sw s1,4(sp) + 176: c422 sw s0,8(sp) + 178: c606 sw ra,12(sp) + 17a: 8282 jr t0 + +0000017c <__riscv_restore_12>: + 17c: 4db2 lw s11,12(sp) + 17e: 0141 addi sp,sp,16 + +00000180 <__riscv_restore_10>: + 180: 4d02 lw s10,0(sp) + 182: 4c92 lw s9,4(sp) + 184: 4c22 lw s8,8(sp) + 186: 4bb2 lw s7,12(sp) + 188: 0141 addi sp,sp,16 + +0000018a <__riscv_restore_4>: + 18a: 4b02 lw s6,0(sp) + 18c: 4a92 lw s5,4(sp) + 18e: 4a22 lw s4,8(sp) + 190: 49b2 lw s3,12(sp) + 192: 0141 addi sp,sp,16 + +00000194 <__riscv_restore_0>: + 194: 4902 lw s2,0(sp) + 196: 4492 lw s1,4(sp) + 198: 4422 lw s0,8(sp) + 19a: 40b2 lw ra,12(sp) + 19c: 0141 addi sp,sp,16 + 19e: 8082 ret + +000001a0 : + 1a0: 433d li t1,15 + 1a2: 872a mv a4,a0 + 1a4: 02c37363 bgeu t1,a2,1ca + 1a8: 00f77793 andi a5,a4,15 + 1ac: efbd bnez a5,22a + 1ae: e5ad bnez a1,218 + 1b0: ff067693 andi a3,a2,-16 + 1b4: 8a3d andi a2,a2,15 + 1b6: 96ba add a3,a3,a4 + 1b8: c30c sw a1,0(a4) + 1ba: c34c sw a1,4(a4) + 1bc: c70c sw a1,8(a4) + 1be: c74c sw a1,12(a4) + 1c0: 0741 addi a4,a4,16 + 1c2: fed76be3 bltu a4,a3,1b8 + 1c6: e211 bnez a2,1ca + 1c8: 8082 ret + 1ca: 40c306b3 sub a3,t1,a2 + 1ce: 068a slli a3,a3,0x2 + 1d0: 00000297 auipc t0,0x0 + 1d4: 9696 add a3,a3,t0 + 1d6: 00a68067 jr 10(a3) + 1da: 00b70723 sb a1,14(a4) + 1de: 00b706a3 sb a1,13(a4) + 1e2: 00b70623 sb a1,12(a4) + 1e6: 00b705a3 sb a1,11(a4) + 1ea: 00b70523 sb a1,10(a4) + 1ee: 00b704a3 sb a1,9(a4) + 1f2: 00b70423 sb a1,8(a4) + 1f6: 00b703a3 sb a1,7(a4) + 1fa: 00b70323 sb a1,6(a4) + 1fe: 00b702a3 sb a1,5(a4) + 202: 00b70223 sb a1,4(a4) + 206: 00b701a3 sb a1,3(a4) + 20a: 00b70123 sb a1,2(a4) + 20e: 00b700a3 sb a1,1(a4) + 212: 00b70023 sb a1,0(a4) + 216: 8082 ret + 218: 0ff5f593 andi a1,a1,255 + 21c: 00859693 slli a3,a1,0x8 + 220: 8dd5 or a1,a1,a3 + 222: 01059693 slli a3,a1,0x10 + 226: 8dd5 or a1,a1,a3 + 228: b761 j 1b0 + 22a: 00279693 slli a3,a5,0x2 + 22e: 00000297 auipc t0,0x0 + 232: 9696 add a3,a3,t0 + 234: 8286 mv t0,ra + 236: fa8680e7 jalr -88(a3) + 23a: 8096 mv ra,t0 + 23c: 17c1 addi a5,a5,-16 + 23e: 8f1d sub a4,a4,a5 + 240: 963e add a2,a2,a5 + 242: f8c374e3 bgeu t1,a2,1ca + 246: b7a5 j 1ae + +00000248 : + 248: a001 j 248 + +0000024a : + 24a: beef07b7 lui a5,0xbeef0 + 24e: e000e737 lui a4,0xe000e + 252: 08078793 addi a5,a5,128 # beef0080 <_eusrstack+0x9eeeb080> + 256: c73c sw a5,72(a4) + 258: a001 j 258 + +0000025a

: + 25a: f17ff2ef jal t0,170 <__riscv_save_0> + 25e: 4505 li a0,1 + 260: 23dd jal 846 + 262: 2211 jal 366 + 264: 7be000ef jal ra,a22 + 268: 6571 lui a0,0x1c + 26a: 20050513 addi a0,a0,512 # 1c200 <_data_lma+0x1a44c> + 26e: 00b000ef jal ra,a78 + 272: 200007b7 lui a5,0x20000 + 276: 0807a583 lw a1,128(a5) # 20000080 + 27a: 00002537 lui a0,0x2 + 27e: ce050513 addi a0,a0,-800 # 1ce0 <_read+0xe> + 282: 0a9000ef jal ra,b2a + 286: 2431 jal 492 + 288: 85aa mv a1,a0 + 28a: 00002537 lui a0,0x2 + 28e: cf050513 addi a0,a0,-784 # 1cf0 <_read+0x1e> + 292: 099000ef jal ra,b2a + 296: 00002437 lui s0,0x2 + 29a: 3e800513 li a0,1000 + 29e: 7a4000ef jal ra,a42 + 2a2: d0040513 addi a0,s0,-768 # 1d00 <_read+0x2e> + 2a6: 199000ef jal ra,c3e + 2aa: bfc5 j 29a + +000002ac : + 2ac: ec5ff2ef jal t0,170 <__riscv_save_0> + 2b0: 40021437 lui s0,0x40021 + 2b4: 401c lw a5,0(s0) + 2b6: 08ff0737 lui a4,0x8ff0 + 2ba: 0017e793 ori a5,a5,1 + 2be: c01c sw a5,0(s0) + 2c0: 405c lw a5,4(s0) + 2c2: 8ff9 and a5,a5,a4 + 2c4: c05c sw a5,4(s0) + 2c6: 401c lw a5,0(s0) + 2c8: fef70737 lui a4,0xfef70 + 2cc: 176d addi a4,a4,-5 + 2ce: 8ff9 and a5,a5,a4 + 2d0: c01c sw a5,0(s0) + 2d2: 401c lw a5,0(s0) + 2d4: fffc0737 lui a4,0xfffc0 + 2d8: 177d addi a4,a4,-1 + 2da: 8ff9 and a5,a5,a4 + 2dc: c01c sw a5,0(s0) + 2de: 405c lw a5,4(s0) + 2e0: ff010737 lui a4,0xff010 + 2e4: 177d addi a4,a4,-1 + 2e6: 8ff9 and a5,a5,a4 + 2e8: c05c sw a5,4(s0) + 2ea: 009f07b7 lui a5,0x9f0 + 2ee: c41c sw a5,8(s0) + 2f0: 2e51 jal 684 + 2f2: 400227b7 lui a5,0x40022 + 2f6: 4709 li a4,2 + 2f8: c398 sw a4,0(a5) + 2fa: 40024737 lui a4,0x40024 + 2fe: 80072783 lw a5,-2048(a4) # 40023800 <_eusrstack+0x2001e800> + 302: 0107e793 ori a5,a5,16 + 306: 80f72023 sw a5,-2048(a4) + 30a: 405c lw a5,4(s0) + 30c: ffc10737 lui a4,0xffc10 + 310: 177d addi a4,a4,-1 + 312: c05c sw a5,4(s0) + 314: 405c lw a5,4(s0) + 316: c05c sw a5,4(s0) + 318: 405c lw a5,4(s0) + 31a: 4007e793 ori a5,a5,1024 + 31e: c05c sw a5,4(s0) + 320: 405c lw a5,4(s0) + 322: 8ff9 and a5,a5,a4 + 324: c05c sw a5,4(s0) + 326: 405c lw a5,4(s0) + 328: 00280737 lui a4,0x280 + 32c: 8fd9 or a5,a5,a4 + 32e: c05c sw a5,4(s0) + 330: 401c lw a5,0(s0) + 332: 01000737 lui a4,0x1000 + 336: 8fd9 or a5,a5,a4 + 338: c01c sw a5,0(s0) + 33a: 400217b7 lui a5,0x40021 + 33e: 4398 lw a4,0(a5) + 340: 00671693 slli a3,a4,0x6 + 344: fe06dde3 bgez a3,33e + 348: 43d8 lw a4,4(a5) + 34a: 400216b7 lui a3,0x40021 + 34e: 9b71 andi a4,a4,-4 + 350: c3d8 sw a4,4(a5) + 352: 43d8 lw a4,4(a5) + 354: 00276713 ori a4,a4,2 + 358: c3d8 sw a4,4(a5) + 35a: 4721 li a4,8 + 35c: 42dc lw a5,4(a3) + 35e: 8bb1 andi a5,a5,12 + 360: fee79ee3 bne a5,a4,35c + 364: bd05 j 194 <__riscv_restore_0> + +00000366 : + 366: 400216b7 lui a3,0x40021 + 36a: 42dc lw a5,4(a3) + 36c: 20000737 lui a4,0x20000 + 370: 4611 li a2,4 + 372: 8bb1 andi a5,a5,12 + 374: 08070713 addi a4,a4,128 # 20000080 + 378: 02c78f63 beq a5,a2,3b6 + 37c: 4621 li a2,8 + 37e: 04c78163 beq a5,a2,3c0 + 382: eb95 bnez a5,3b6 + 384: 429c lw a5,0(a3) + 386: 8b91 andi a5,a5,4 + 388: c79d beqz a5,3b6 + 38a: 000f47b7 lui a5,0xf4 + 38e: 24078793 addi a5,a5,576 # f4240 <_data_lma+0xf248c> + 392: c31c sw a5,0(a4) + 394: 400217b7 lui a5,0x40021 + 398: 43dc lw a5,4(a5) + 39a: 8391 srli a5,a5,0x4 + 39c: 00f7f693 andi a3,a5,15 + 3a0: 200007b7 lui a5,0x20000 + 3a4: 00078793 mv a5,a5 + 3a8: 97b6 add a5,a5,a3 + 3aa: 2394 lbu a3,0(a5) + 3ac: 431c lw a5,0(a4) + 3ae: 00d7d7b3 srl a5,a5,a3 + 3b2: c31c sw a5,0(a4) + 3b4: 8082 ret + 3b6: 007a17b7 lui a5,0x7a1 + 3ba: 20078793 addi a5,a5,512 # 7a1200 <_data_lma+0x79f44c> + 3be: bfd1 j 392 + 3c0: 42dc lw a5,4(a3) + 3c2: 42d4 lw a3,4(a3) + 3c4: 6641 lui a2,0x10 + 3c6: 83c9 srli a5,a5,0x12 + 3c8: 8bbd andi a5,a5,15 + 3ca: 8ef1 and a3,a3,a2 + 3cc: 0789 addi a5,a5,2 + 3ce: 4645 li a2,17 + 3d0: 00c79363 bne a5,a2,3d6 + 3d4: 47c9 li a5,18 + 3d6: ee81 bnez a3,3ee + 3d8: 400246b7 lui a3,0x40024 + 3dc: 8006a683 lw a3,-2048(a3) # 40023800 <_eusrstack+0x2001e800> + 3e0: 8ac1 andi a3,a3,16 + 3e2: ce89 beqz a3,3fc + 3e4: 007a16b7 lui a3,0x7a1 + 3e8: 20068693 addi a3,a3,512 # 7a1200 <_data_lma+0x79f44c> + 3ec: a821 j 404 + 3ee: 400216b7 lui a3,0x40021 + 3f2: 42d4 lw a3,4(a3) + 3f4: 00e69613 slli a2,a3,0xe + 3f8: fe0656e3 bgez a2,3e4 + 3fc: 003d16b7 lui a3,0x3d1 + 400: 90068693 addi a3,a3,-1792 # 3d0900 <_data_lma+0x3ceb4c> + 404: 02d787b3 mul a5,a5,a3 + 408: b769 j 392 + +0000040a : + 40a: a001 j 40a + +0000040c : + 40c: 20000197 auipc gp,0x20000 + 410: 47418193 addi gp,gp,1140 # 20000880 <__global_pointer$> + 414: 20005117 auipc sp,0x20005 + 418: bec10113 addi sp,sp,-1044 # 20005000 <_eusrstack> + 41c: 00002517 auipc a0,0x2 + 420: 99850513 addi a0,a0,-1640 # 1db4 <_data_lma> + 424: 20000597 auipc a1,0x20000 + 428: bdc58593 addi a1,a1,-1060 # 20000000 <_data_vma> + 42c: 81818613 addi a2,gp,-2024 # 20000098 <_edata> + 430: 00c5fa63 bgeu a1,a2,444 + 434: 00052283 lw t0,0(a0) + 438: 0055a023 sw t0,0(a1) + 43c: 0511 addi a0,a0,4 + 43e: 0591 addi a1,a1,4 + 440: fec5eae3 bltu a1,a2,434 + 444: 81818513 addi a0,gp,-2024 # 20000098 <_edata> + 448: 84018593 addi a1,gp,-1984 # 200000c0 <_ebss> + 44c: 00b57763 bgeu a0,a1,45a + 450: 00052023 sw zero,0(a0) + 454: 0511 addi a0,a0,4 + 456: feb56de3 bltu a0,a1,450 + 45a: 42fd li t0,31 + 45c: bc029073 csrw 0xbc0,t0 + 460: 428d li t0,3 + 462: 80429073 csrw 0x804,t0 + 466: 08800293 li t0,136 + 46a: 30029073 csrw mstatus,t0 + 46e: 00000297 auipc t0,0x0 + 472: b9628293 addi t0,t0,-1130 # 4 <_einit> + 476: 0032e293 ori t0,t0,3 + 47a: 30529073 csrw mtvec,t0 + 47e: e2fff0ef jal ra,2ac + 482: 00000297 auipc t0,0x0 + 486: dd828293 addi t0,t0,-552 # 25a
+ 48a: 34129073 csrw mepc,t0 + 48e: 30200073 mret + +00000492 : + 492: 81c1a503 lw a0,-2020(gp) # 2000009c + 496: 8082 ret + +00000498 : + 498: 459c lw a5,8(a1) + 49a: 0107f713 andi a4,a5,16 + 49e: 00f7f813 andi a6,a5,15 + 4a2: c701 beqz a4,4aa + 4a4: 41d8 lw a4,4(a1) + 4a6: 00e86833 or a6,a6,a4 + 4aa: 218e lhu a1,0(a1) + 4ac: 0ff5f713 andi a4,a1,255 + 4b0: c339 beqz a4,4f6 + 4b2: 4118 lw a4,0(a0) + 4b4: 4681 li a3,0 + 4b6: 4e85 li t4,1 + 4b8: 4f3d li t5,15 + 4ba: 02800f93 li t6,40 + 4be: 04800293 li t0,72 + 4c2: 4e21 li t3,8 + 4c4: 00de9633 sll a2,t4,a3 + 4c8: 00c5f8b3 and a7,a1,a2 + 4cc: 03161163 bne a2,a7,4ee + 4d0: 00269893 slli a7,a3,0x2 + 4d4: 011f1333 sll t1,t5,a7 + 4d8: fff34313 not t1,t1 + 4dc: 00e37733 and a4,t1,a4 + 4e0: 011818b3 sll a7,a6,a7 + 4e4: 00e8e733 or a4,a7,a4 + 4e8: 05f79f63 bne a5,t6,546 + 4ec: c950 sw a2,20(a0) + 4ee: 0685 addi a3,a3,1 + 4f0: fdc69ae3 bne a3,t3,4c4 + 4f4: c118 sw a4,0(a0) + 4f6: 0ff00713 li a4,255 + 4fa: 04b77563 bgeu a4,a1,544 + 4fe: 4154 lw a3,4(a0) + 500: 4621 li a2,8 + 502: 4e85 li t4,1 + 504: 4f3d li t5,15 + 506: 02800f93 li t6,40 + 50a: 04800293 li t0,72 + 50e: 4e41 li t3,16 + 510: 00ce98b3 sll a7,t4,a2 + 514: 0115f733 and a4,a1,a7 + 518: 02e89263 bne a7,a4,53c + 51c: 00261713 slli a4,a2,0x2 + 520: 1701 addi a4,a4,-32 + 522: 00ef1333 sll t1,t5,a4 + 526: fff34313 not t1,t1 + 52a: 00d376b3 and a3,t1,a3 + 52e: 00e81733 sll a4,a6,a4 + 532: 8ed9 or a3,a3,a4 + 534: 01f79d63 bne a5,t6,54e + 538: 01152a23 sw a7,20(a0) + 53c: 0605 addi a2,a2,1 + 53e: fdc619e3 bne a2,t3,510 + 542: c154 sw a3,4(a0) + 544: 8082 ret + 546: fa5794e3 bne a5,t0,4ee + 54a: c910 sw a2,16(a0) + 54c: b74d j 4ee + 54e: fe5797e3 bne a5,t0,53c + 552: 01152823 sw a7,16(a0) + 556: b7dd j 53c + +00000558 : + 558: c0000737 lui a4,0xc0000 + 55c: 00e577b3 and a5,a0,a4 + 560: 08e79563 bne a5,a4,5ea + 564: 40010737 lui a4,0x40010 + 568: 435c lw a5,4(a4) + 56a: 01b55693 srli a3,a0,0x1b + 56e: 4f58 lw a4,28(a4) + 570: 8a9d andi a3,a3,7 + 572: e69d bnez a3,5a0 + 574: 9bf9 andi a5,a5,-2 + 576: ff0006b7 lui a3,0xff000 + 57a: 16fd addi a3,a3,-1 + 57c: 8f75 and a4,a4,a3 + 57e: c989 beqz a1,590 + 580: 01051693 slli a3,a0,0x10 + 584: 82c1 srli a3,a3,0x10 + 586: 8fd5 or a5,a5,a3 + 588: 01ff06b7 lui a3,0x1ff0 + 58c: 8d75 and a0,a0,a3 + 58e: 8f49 or a4,a4,a0 + 590: 070006b7 lui a3,0x7000 + 594: 8fd5 or a5,a5,a3 + 596: 400106b7 lui a3,0x40010 + 59a: c2dc sw a5,4(a3) + 59c: ced8 sw a4,28(a3) + 59e: 8082 ret + 5a0: 4605 li a2,1 + 5a2: 00c69663 bne a3,a2,5ae + 5a6: 9bf5 andi a5,a5,-3 + 5a8: ff8006b7 lui a3,0xff800 + 5ac: b7f9 j 57a + 5ae: 4609 li a2,2 + 5b0: 00c69663 bne a3,a2,5bc + 5b4: 9bed andi a5,a5,-5 + 5b6: ffe806b7 lui a3,0xffe80 + 5ba: b7c1 j 57a + 5bc: 460d li a2,3 + 5be: 00c69663 bne a3,a2,5ca + 5c2: 9bdd andi a5,a5,-9 + 5c4: fffc06b7 lui a3,0xfffc0 + 5c8: bf4d j 57a + 5ca: 4611 li a2,4 + 5cc: 00c69763 bne a3,a2,5da + 5d0: f3f7f793 andi a5,a5,-193 + 5d4: ffc006b7 lui a3,0xffc00 + 5d8: b74d j 57a + 5da: 4615 li a2,5 + 5dc: fac691e3 bne a3,a2,57e + 5e0: cff7f793 andi a5,a5,-769 + 5e4: ffe006b7 lui a3,0xffe00 + 5e8: bf49 j 57a + 5ea: 40000737 lui a4,0x40000 + 5ee: 02e79163 bne a5,a4,610 + 5f2: 400107b7 lui a5,0x40010 + 5f6: 4fd8 lw a4,28(a5) + 5f8: 0542 slli a0,a0,0x10 + 5fa: 00a767b3 or a5,a4,a0 + 5fe: e589 bnez a1,608 + 600: fff54513 not a0,a0 + 604: 00e577b3 and a5,a0,a4 + 608: 40010737 lui a4,0x40010 + 60c: cf5c sw a5,28(a4) + 60e: 8082 ret + 610: e3a9 bnez a5,652 + 612: 40010837 lui a6,0x40010 + 616: 003007b7 lui a5,0x300 + 61a: 00482603 lw a2,4(a6) # 40010004 <_eusrstack+0x2000b004> + 61e: 01051713 slli a4,a0,0x10 + 622: 00f576b3 and a3,a0,a5 + 626: 8341 srli a4,a4,0x10 + 628: 02f69663 bne a3,a5,654 + 62c: f90006b7 lui a3,0xf9000 + 630: 16fd addi a3,a3,-1 + 632: 00d677b3 and a5,a2,a3 + 636: 00482603 lw a2,4(a6) + 63a: 8ef1 and a3,a3,a2 + 63c: 00d82223 sw a3,4(a6) + 640: c591 beqz a1,64c + 642: 8155 srli a0,a0,0x15 + 644: 0512 slli a0,a0,0x4 + 646: 00a71533 sll a0,a4,a0 + 64a: 8fc9 or a5,a5,a0 + 64c: 40010737 lui a4,0x40010 + 650: c35c sw a5,4(a4) + 652: 8082 ret + 654: 00b51793 slli a5,a0,0xb + 658: 0207d063 bgez a5,678 + 65c: 01055793 srli a5,a0,0x10 + 660: 00f7f693 andi a3,a5,15 + 664: 478d li a5,3 + 666: 00d797b3 sll a5,a5,a3 + 66a: fff7c793 not a5,a5 + 66e: 8ff1 and a5,a5,a2 + 670: 070006b7 lui a3,0x7000 + 674: 8fd5 or a5,a5,a3 + 676: b7e9 j 640 + 678: 01555793 srli a5,a0,0x15 + 67c: 0792 slli a5,a5,0x4 + 67e: 00f717b3 sll a5,a4,a5 + 682: b7e5 j 66a + +00000684 : + 684: aedff2ef jal t0,170 <__riscv_save_0> + 688: 1ffff437 lui s0,0x1ffff + 68c: 72442703 lw a4,1828(s0) # 1ffff724 <_data_lma+0x1fffd970> + 690: 3e000637 lui a2,0x3e000 + 694: 1141 addi sp,sp,-16 + 696: 01971793 slli a5,a4,0x19 + 69a: fff74693 not a3,a4 + 69e: 8ff1 and a5,a5,a2 + 6a0: 0706 slli a4,a4,0x1 + 6a2: 003e0637 lui a2,0x3e0 + 6a6: 8f71 and a4,a4,a2 + 6a8: 8fd9 or a5,a5,a4 + 6aa: 01000637 lui a2,0x1000 + 6ae: 00969713 slli a4,a3,0x9 + 6b2: 8f71 and a4,a4,a2 + 6b4: 8fd9 or a5,a5,a4 + 6b6: 82bd srli a3,a3,0xf + 6b8: 6741 lui a4,0x10 + 6ba: 8ef9 and a3,a3,a4 + 6bc: c202 sw zero,4(sp) + 6be: c402 sw zero,8(sp) + 6c0: c602 sw zero,12(sp) + 6c2: 8fd5 or a5,a5,a3 + 6c4: 82f1a023 sw a5,-2016(gp) # 200000a0 + 6c8: 72845703 lhu a4,1832(s0) + 6cc: 4585 li a1,1 + 6ce: 80e19c23 sh a4,-2024(gp) # 20000098 <_edata> + 6d2: 72042703 lw a4,1824(s0) + 6d6: 03d00513 li a0,61 + 6da: 82e1a223 sw a4,-2012(gp) # 200000a4 + 6de: 70442703 lw a4,1796(s0) + 6e2: 80e1ae23 sw a4,-2020(gp) # 2000009c + 6e6: 73045703 lhu a4,1840(s0) + 6ea: 82e19423 sh a4,-2008(gp) # 200000a8 + 6ee: 2c15 jal 922 + 6f0: 70442783 lw a5,1796(s0) + 6f4: 103a0737 lui a4,0x103a0 + 6f8: 70070713 addi a4,a4,1792 # 103a0700 <_data_lma+0x1039e94c> + 6fc: f0f7f793 andi a5,a5,-241 + 700: 10e78363 beq a5,a4,806 <__stack_size+0x6> + 704: 00f76a63 bltu a4,a5,718 + 708: 10320737 lui a4,0x10320 + 70c: 70070713 addi a4,a4,1792 # 10320700 <_data_lma+0x1031e94c> + 710: 06e78f63 beq a5,a4,78e + 714: 0141 addi sp,sp,16 + 716: bcbd j 194 <__riscv_restore_0> + 718: 103b0737 lui a4,0x103b0 + 71c: 70070713 addi a4,a4,1792 # 103b0700 <_data_lma+0x103ae94c> + 720: 08e78b63 beq a5,a4,7b6 + 724: 103d0737 lui a4,0x103d0 + 728: 70070713 addi a4,a4,1792 # 103d0700 <_data_lma+0x103ce94c> + 72c: fee794e3 bne a5,a4,714 + 730: 4585 li a1,1 + 732: 6521 lui a0,0x8 + 734: 3515 jal 558 + 736: 40011437 lui s0,0x40011 + 73a: 77e1 lui a5,0xffff8 + 73c: 04800493 li s1,72 + 740: 004c addi a1,sp,4 + 742: 80040513 addi a0,s0,-2048 # 40010800 <_eusrstack+0x2000b800> + 746: 827c sh a5,4(sp) + 748: c626 sw s1,12(sp) + 74a: 33b9 jal 498 + 74c: 6785 lui a5,0x1 + 74e: 33878793 addi a5,a5,824 # 1338 <_free_r+0x9a> + 752: 004c addi a1,sp,4 + 754: c0040513 addi a0,s0,-1024 + 758: 827c sh a5,4(sp) + 75a: c626 sw s1,12(sp) + 75c: 3b35 jal 498 + 75e: 4791 li a5,4 + 760: 827c sh a5,4(sp) + 762: 004c addi a1,sp,4 + 764: 02800793 li a5,40 + 768: c0040513 addi a0,s0,-1024 + 76c: c63e sw a5,12(sp) + 76e: 332d jal 498 + 770: 77f9 lui a5,0xffffe + 772: 004c addi a1,sp,4 + 774: 40011537 lui a0,0x40011 + 778: 827c sh a5,4(sp) + 77a: c626 sw s1,12(sp) + 77c: 3b31 jal 498 + 77e: 478d li a5,3 + 780: 827c sh a5,4(sp) + 782: c626 sw s1,12(sp) + 784: 004c addi a1,sp,4 + 786: 40040513 addi a0,s0,1024 + 78a: 3339 jal 498 + 78c: b761 j 714 + 78e: 77e1 lui a5,0xffff8 + 790: 40011537 lui a0,0x40011 + 794: c007c793 xori a5,a5,-1024 + 798: 04800413 li s0,72 + 79c: 004c addi a1,sp,4 + 79e: c0050513 addi a0,a0,-1024 # 40010c00 <_eusrstack+0x2000bc00> + 7a2: 827c sh a5,4(sp) + 7a4: c622 sw s0,12(sp) + 7a6: 39cd jal 498 + 7a8: 6789 lui a5,0x2 + 7aa: 827c sh a5,4(sp) + 7ac: c622 sw s0,12(sp) + 7ae: 004c addi a1,sp,4 + 7b0: 40011537 lui a0,0x40011 + 7b4: bfd9 j 78a + 7b6: 4585 li a1,1 + 7b8: 6521 lui a0,0x8 + 7ba: 3b79 jal 558 + 7bc: 40011437 lui s0,0x40011 + 7c0: 77e1 lui a5,0xffff8 + 7c2: 04800493 li s1,72 + 7c6: 004c addi a1,sp,4 + 7c8: 80040513 addi a0,s0,-2048 # 40010800 <_eusrstack+0x2000b800> + 7cc: 827c sh a5,4(sp) + 7ce: c626 sw s1,12(sp) + 7d0: 31e1 jal 498 + 7d2: 21000793 li a5,528 + 7d6: 004c addi a1,sp,4 + 7d8: c0040513 addi a0,s0,-1024 + 7dc: 827c sh a5,4(sp) + 7de: c626 sw s1,12(sp) + 7e0: 3965 jal 498 + 7e2: 4791 li a5,4 + 7e4: 827c sh a5,4(sp) + 7e6: 004c addi a1,sp,4 + 7e8: 02800793 li a5,40 + 7ec: c0040513 addi a0,s0,-1024 + 7f0: c63e sw a5,12(sp) + 7f2: 315d jal 498 + 7f4: 77f9 lui a5,0xffffe + 7f6: 004c addi a1,sp,4 + 7f8: 40011537 lui a0,0x40011 + 7fc: 827c sh a5,4(sp) + 7fe: c626 sw s1,12(sp) + 800: 3961 jal 498 + 802: 4789 li a5,2 + 804: bfb5 j 780 + 806: 400114b7 lui s1,0x40011 + 80a: 77e1 lui a5,0xffff8 + 80c: 70078793 addi a5,a5,1792 # ffff8700 <_eusrstack+0xdfff3700> + 810: 04800413 li s0,72 + 814: 004c addi a1,sp,4 + 816: 80048513 addi a0,s1,-2048 # 40010800 <_eusrstack+0x2000b800> + 81a: 827c sh a5,4(sp) + 81c: c622 sw s0,12(sp) + 81e: 39ad jal 498 + 820: e3900793 li a5,-455 + 824: 004c addi a1,sp,4 + 826: c0048513 addi a0,s1,-1024 + 82a: 827c sh a5,4(sp) + 82c: c622 sw s0,12(sp) + 82e: 31ad jal 498 + 830: 4791 li a5,4 + 832: 827c sh a5,4(sp) + 834: 004c addi a1,sp,4 + 836: 02800793 li a5,40 + 83a: c0048513 addi a0,s1,-1024 + 83e: c63e sw a5,12(sp) + 840: 39a1 jal 498 + 842: 77f9 lui a5,0xffffe + 844: b79d j 7aa + +00000846 : + 846: 82a1a623 sw a0,-2004(gp) # 200000ac + 84a: 8082 ret + +0000084c : + 84c: 40021737 lui a4,0x40021 + 850: 435c lw a5,4(a4) + 852: 4691 li a3,4 + 854: 8bb1 andi a5,a5,12 + 856: 06d78c63 beq a5,a3,8ce + 85a: 46a1 li a3,8 + 85c: 06d78e63 beq a5,a3,8d8 + 860: e7bd bnez a5,8ce + 862: 431c lw a5,0(a4) + 864: 8b91 andi a5,a5,4 + 866: c7a5 beqz a5,8ce + 868: 000f47b7 lui a5,0xf4 + 86c: 24078793 addi a5,a5,576 # f4240 <_data_lma+0xf248c> + 870: c11c sw a5,0(a0) + 872: 40021637 lui a2,0x40021 + 876: 425c lw a5,4(a2) + 878: 20000737 lui a4,0x20000 + 87c: 01070713 addi a4,a4,16 # 20000010 + 880: 8391 srli a5,a5,0x4 + 882: 8bbd andi a5,a5,15 + 884: 97ba add a5,a5,a4 + 886: 2394 lbu a3,0(a5) + 888: 411c lw a5,0(a0) + 88a: 00d7d7b3 srl a5,a5,a3 + 88e: c15c sw a5,4(a0) + 890: 4254 lw a3,4(a2) + 892: 82a1 srli a3,a3,0x8 + 894: 8a9d andi a3,a3,7 + 896: 96ba add a3,a3,a4 + 898: 2294 lbu a3,0(a3) + 89a: 00d7d6b3 srl a3,a5,a3 + 89e: c514 sw a3,8(a0) + 8a0: 4254 lw a3,4(a2) + 8a2: 82ad srli a3,a3,0xb + 8a4: 8a9d andi a3,a3,7 + 8a6: 9736 add a4,a4,a3 + 8a8: 2314 lbu a3,0(a4) + 8aa: 00d7d6b3 srl a3,a5,a3 + 8ae: c554 sw a3,12(a0) + 8b0: 4258 lw a4,4(a2) + 8b2: 00074c63 bltz a4,8ca + 8b6: 425c lw a5,4(a2) + 8b8: 83b9 srli a5,a5,0xe + 8ba: 0037f713 andi a4,a5,3 + 8be: 80418793 addi a5,gp,-2044 # 20000084 + 8c2: 97ba add a5,a5,a4 + 8c4: 239c lbu a5,0(a5) + 8c6: 02f6d7b3 divu a5,a3,a5 + 8ca: c91c sw a5,16(a0) + 8cc: 8082 ret + 8ce: 007a17b7 lui a5,0x7a1 + 8d2: 20078793 addi a5,a5,512 # 7a1200 <_data_lma+0x79f44c> + 8d6: bf69 j 870 + 8d8: 435c lw a5,4(a4) + 8da: 4358 lw a4,4(a4) + 8dc: 66c1 lui a3,0x10 + 8de: 83c9 srli a5,a5,0x12 + 8e0: 8bbd andi a5,a5,15 + 8e2: 8f75 and a4,a4,a3 + 8e4: 0789 addi a5,a5,2 + 8e6: 46c5 li a3,17 + 8e8: 00d79363 bne a5,a3,8ee + 8ec: 47c9 li a5,18 + 8ee: ef01 bnez a4,906 + 8f0: 40024737 lui a4,0x40024 + 8f4: 80072703 lw a4,-2048(a4) # 40023800 <_eusrstack+0x2001e800> + 8f8: 8b41 andi a4,a4,16 + 8fa: cf09 beqz a4,914 + 8fc: 007a1737 lui a4,0x7a1 + 900: 20070713 addi a4,a4,512 # 7a1200 <_data_lma+0x79f44c> + 904: a821 j 91c + 906: 40021737 lui a4,0x40021 + 90a: 4358 lw a4,4(a4) + 90c: 00e71693 slli a3,a4,0xe + 910: fe06d6e3 bgez a3,8fc + 914: 003d1737 lui a4,0x3d1 + 918: 90070713 addi a4,a4,-1792 # 3d0900 <_data_lma+0x3ceb4c> + 91c: 02e787b3 mul a5,a5,a4 + 920: bf81 j 870 + +00000922 : + 922: c599 beqz a1,930 + 924: 40021737 lui a4,0x40021 + 928: 4f1c lw a5,24(a4) + 92a: 8d5d or a0,a0,a5 + 92c: cf08 sw a0,24(a4) + 92e: 8082 ret + 930: 400217b7 lui a5,0x40021 + 934: 4f98 lw a4,24(a5) + 936: fff54513 not a0,a0 + 93a: 8d79 and a0,a0,a4 + 93c: cf88 sw a0,24(a5) + 93e: 8082 ret + +00000940 : + 940: 831ff2ef jal t0,170 <__riscv_save_0> + 944: 2916 lhu a3,16(a0) + 946: 77f5 lui a5,0xffffd + 948: 17fd addi a5,a5,-1 + 94a: 8ff5 and a5,a5,a3 + 94c: 21f6 lhu a3,6(a1) + 94e: 25da lhu a4,12(a1) + 950: 7179 addi sp,sp,-48 + 952: 8fd5 or a5,a5,a3 + 954: a91e sh a5,16(a0) + 956: 2556 lhu a3,12(a0) + 958: 77fd lui a5,0xfffff + 95a: 9f378793 addi a5,a5,-1549 # ffffe9f3 <_eusrstack+0xdfff99f3> + 95e: 8ff5 and a5,a5,a3 + 960: 21d6 lhu a3,4(a1) + 962: 842a mv s0,a0 + 964: c62e sw a1,12(sp) + 966: 8fd5 or a5,a5,a3 + 968: 2596 lhu a3,8(a1) + 96a: 8fd5 or a5,a5,a3 + 96c: 25b6 lhu a3,10(a1) + 96e: 8fd5 or a5,a5,a3 + 970: a55e sh a5,12(a0) + 972: 295e lhu a5,20(a0) + 974: 07c2 slli a5,a5,0x10 + 976: 83c1 srli a5,a5,0x10 + 978: cff7f793 andi a5,a5,-769 + 97c: 8fd9 or a5,a5,a4 + 97e: a95e sh a5,20(a0) + 980: 0868 addi a0,sp,28 + 982: 35e9 jal 84c + 984: 400147b7 lui a5,0x40014 + 988: 80078793 addi a5,a5,-2048 # 40013800 <_eusrstack+0x2000e800> + 98c: 45b2 lw a1,12(sp) + 98e: 04f41a63 bne s0,a5,9e2 + 992: 57a2 lw a5,40(sp) + 994: 2456 lhu a3,12(s0) + 996: 4765 li a4,25 + 998: 02e787b3 mul a5,a5,a4 + 99c: 06c2 slli a3,a3,0x10 + 99e: 86c1 srai a3,a3,0x10 + 9a0: 4198 lw a4,0(a1) + 9a2: 0406d263 bgez a3,9e6 + 9a6: 0706 slli a4,a4,0x1 + 9a8: 2452 lhu a2,12(s0) + 9aa: 0642 slli a2,a2,0x10 + 9ac: 02e7d7b3 divu a5,a5,a4 + 9b0: 06400713 li a4,100 + 9b4: 8641 srai a2,a2,0x10 + 9b6: 02e7d6b3 divu a3,a5,a4 + 9ba: 02e7f7b3 remu a5,a5,a4 + 9be: 0692 slli a3,a3,0x4 + 9c0: 02065563 bgez a2,9ea + 9c4: 078e slli a5,a5,0x3 + 9c6: 03278793 addi a5,a5,50 + 9ca: 02e7d7b3 divu a5,a5,a4 + 9ce: 0077f713 andi a4,a5,7 + 9d2: 00d767b3 or a5,a4,a3 + 9d6: 07c2 slli a5,a5,0x10 + 9d8: 83c1 srli a5,a5,0x10 + 9da: a41e sh a5,8(s0) + 9dc: 6145 addi sp,sp,48 + 9de: fb6ff06f j 194 <__riscv_restore_0> + 9e2: 5792 lw a5,36(sp) + 9e4: bf45 j 994 + 9e6: 070a slli a4,a4,0x2 + 9e8: b7c1 j 9a8 + 9ea: 0792 slli a5,a5,0x4 + 9ec: 03278793 addi a5,a5,50 + 9f0: 02e7d7b3 divu a5,a5,a4 + 9f4: 8bbd andi a5,a5,15 + 9f6: 8fd5 or a5,a5,a3 + 9f8: bff9 j 9d6 + +000009fa : + 9fa: c591 beqz a1,a06 + 9fc: 255e lhu a5,12(a0) + 9fe: 6709 lui a4,0x2 + a00: 8fd9 or a5,a5,a4 + a02: a55e sh a5,12(a0) + a04: 8082 ret + a06: 255a lhu a4,12(a0) + a08: 77f9 lui a5,0xffffe + a0a: 17fd addi a5,a5,-1 + a0c: 8ff9 and a5,a5,a4 + a0e: bfd5 j a02 + +00000a10 : + a10: 1ff5f593 andi a1,a1,511 + a14: a14e sh a1,4(a0) + a16: 8082 ret + +00000a18 : + a18: 210a lhu a0,0(a0) + a1a: 8d6d and a0,a0,a1 + a1c: 00a03533 snez a0,a0 + a20: 8082 ret + +00000a22 : + a22: 200007b7 lui a5,0x20000 + a26: 0807a783 lw a5,128(a5) # 20000080 + a2a: 6709 lui a4,0x2 + a2c: f4070713 addi a4,a4,-192 # 1f40 <_data_lma+0x18c> + a30: 02e7d7b3 divu a5,a5,a4 + a34: 07c2 slli a5,a5,0x10 + a36: 83c1 srli a5,a5,0x10 + a38: 82f19923 sh a5,-1998(gp) # 200000b2 + a3c: 82f19823 sh a5,-2000(gp) # 200000b0 + a40: 8082 ret + +00000a42 : + a42: e000f7b7 lui a5,0xe000f + a46: 43d8 lw a4,4(a5) + a48: 4681 li a3,0 + a4a: 9b79 andi a4,a4,-2 + a4c: c3d8 sw a4,4(a5) + a4e: 8301d703 lhu a4,-2000(gp) # 200000b0 + a52: 02a70633 mul a2,a4,a0 + a56: cb90 sw a2,16(a5) + a58: cbd4 sw a3,20(a5) + a5a: 4398 lw a4,0(a5) + a5c: 01076713 ori a4,a4,16 + a60: c398 sw a4,0(a5) + a62: 4398 lw a4,0(a5) + a64: 02176713 ori a4,a4,33 + a68: c398 sw a4,0(a5) + a6a: 43d8 lw a4,4(a5) + a6c: 8b05 andi a4,a4,1 + a6e: df75 beqz a4,a6a + a70: 4398 lw a4,0(a5) + a72: 9b79 andi a4,a4,-2 + a74: c398 sw a4,0(a5) + a76: 8082 ret + +00000a78 : + a78: ef8ff2ef jal t0,170 <__riscv_save_0> + a7c: 842a mv s0,a0 + a7e: 6511 lui a0,0x4 + a80: 1101 addi sp,sp,-32 + a82: 4585 li a1,1 + a84: 0511 addi a0,a0,4 + a86: 3d71 jal 922 + a88: 20000793 li a5,512 + a8c: 827c sh a5,4(sp) + a8e: 40011537 lui a0,0x40011 + a92: 478d li a5,3 + a94: c43e sw a5,8(sp) + a96: 004c addi a1,sp,4 + a98: 47e1 li a5,24 + a9a: 80050513 addi a0,a0,-2048 # 40010800 <_eusrstack+0x2000b800> + a9e: c63e sw a5,12(sp) + aa0: 3ae5 jal 498 + aa2: c822 sw s0,16(sp) + aa4: 40014437 lui s0,0x40014 + aa8: 000807b7 lui a5,0x80 + aac: 080c addi a1,sp,16 + aae: 80040513 addi a0,s0,-2048 # 40013800 <_eusrstack+0x2000e800> + ab2: cc3e sw a5,24(sp) + ab4: ca02 sw zero,20(sp) + ab6: 00011e23 sh zero,28(sp) + aba: 3559 jal 940 + abc: 4585 li a1,1 + abe: 80040513 addi a0,s0,-2048 + ac2: 3f25 jal 9fa + ac4: 6105 addi sp,sp,32 + ac6: eceff06f j 194 <__riscv_restore_0> + +00000aca <_write>: + aca: e8cff2ef jal t0,156 <__riscv_save_4> + ace: 400144b7 lui s1,0x40014 + ad2: 89ae mv s3,a1 + ad4: 8932 mv s2,a2 + ad6: 4401 li s0,0 + ad8: 80048493 addi s1,s1,-2048 # 40013800 <_eusrstack+0x2000e800> + adc: 01244563 blt s0,s2,ae6 <_write+0x1c> + ae0: 854a mv a0,s2 + ae2: ea8ff06f j 18a <__riscv_restore_4> + ae6: 04000593 li a1,64 + aea: 8526 mv a0,s1 + aec: 3735 jal a18 + aee: dd65 beqz a0,ae6 <_write+0x1c> + af0: 008987b3 add a5,s3,s0 + af4: 00078583 lb a1,0(a5) # 80000 <_data_lma+0x7e24c> + af8: 8526 mv a0,s1 + afa: 0405 addi s0,s0,1 + afc: 05c2 slli a1,a1,0x10 + afe: 81c1 srli a1,a1,0x10 + b00: 3f01 jal a10 + b02: bfe9 j adc <_write+0x12> + +00000b04 <_sbrk>: + b04: 80818713 addi a4,gp,-2040 # 20000088 + b08: 431c lw a5,0(a4) + b0a: 84018693 addi a3,gp,-1984 # 200000c0 <_ebss> + b0e: 953e add a0,a0,a5 + b10: 00d56b63 bltu a0,a3,b26 <_sbrk+0x22> + b14: 200056b7 lui a3,0x20005 + b18: 80068693 addi a3,a3,-2048 # 20004800 <_heap_end> + b1c: 00a6e563 bltu a3,a0,b26 <_sbrk+0x22> + b20: c308 sw a0,0(a4) + b22: 853e mv a0,a5 + b24: 8082 ret + b26: 57fd li a5,-1 + b28: bfed j b22 <_sbrk+0x1e> + +00000b2a : + b2a: 7139 addi sp,sp,-64 + b2c: da3e sw a5,52(sp) + b2e: d22e sw a1,36(sp) + b30: d432 sw a2,40(sp) + b32: d636 sw a3,44(sp) + b34: d83a sw a4,48(sp) + b36: dc42 sw a6,56(sp) + b38: de46 sw a7,60(sp) + b3a: 80c18793 addi a5,gp,-2036 # 2000008c <_impure_ptr> + b3e: cc22 sw s0,24(sp) + b40: 4380 lw s0,0(a5) + b42: ca26 sw s1,20(sp) + b44: ce06 sw ra,28(sp) + b46: 84aa mv s1,a0 + b48: c409 beqz s0,b52 + b4a: 4c1c lw a5,24(s0) + b4c: e399 bnez a5,b52 + b4e: 8522 mv a0,s0 + b50: 29ed jal 104a <__sinit> + b52: 440c lw a1,8(s0) + b54: 1054 addi a3,sp,36 + b56: 8626 mv a2,s1 + b58: 8522 mv a0,s0 + b5a: c636 sw a3,12(sp) + b5c: 127000ef jal ra,1482 <_vfiprintf_r> + b60: 40f2 lw ra,28(sp) + b62: 4462 lw s0,24(sp) + b64: 44d2 lw s1,20(sp) + b66: 6121 addi sp,sp,64 + b68: 8082 ret + +00000b6a <_puts_r>: + b6a: 1101 addi sp,sp,-32 + b6c: ca26 sw s1,20(sp) + b6e: c84a sw s2,16(sp) + b70: ce06 sw ra,28(sp) + b72: cc22 sw s0,24(sp) + b74: c64e sw s3,12(sp) + b76: c452 sw s4,8(sp) + b78: 84aa mv s1,a0 + b7a: 892e mv s2,a1 + b7c: c501 beqz a0,b84 <_puts_r+0x1a> + b7e: 4d1c lw a5,24(a0) + b80: e391 bnez a5,b84 <_puts_r+0x1a> + b82: 21e1 jal 104a <__sinit> + b84: 4c9c lw a5,24(s1) + b86: 4480 lw s0,8(s1) + b88: e399 bnez a5,b8e <_puts_r+0x24> + b8a: 8526 mv a0,s1 + b8c: 297d jal 104a <__sinit> + b8e: 00001797 auipc a5,0x1 + b92: 1aa78793 addi a5,a5,426 # 1d38 <__sf_fake_stdin> + b96: 02f41b63 bne s0,a5,bcc <_puts_r+0x62> + b9a: 40c0 lw s0,4(s1) + b9c: 245e lhu a5,12(s0) + b9e: 8ba1 andi a5,a5,8 + ba0: c7b1 beqz a5,bec <_puts_r+0x82> + ba2: 481c lw a5,16(s0) + ba4: c7a1 beqz a5,bec <_puts_r+0x82> + ba6: 59fd li s3,-1 + ba8: 4a29 li s4,10 + baa: 441c lw a5,8(s0) + bac: 00094583 lbu a1,0(s2) + bb0: 17fd addi a5,a5,-1 + bb2: e9b1 bnez a1,c06 <_puts_r+0x9c> + bb4: c41c sw a5,8(s0) + bb6: 0607dd63 bgez a5,c30 <_puts_r+0xc6> + bba: 8622 mv a2,s0 + bbc: 45a9 li a1,10 + bbe: 8526 mv a0,s1 + bc0: 2061 jal c48 <__swbuf_r> + bc2: 57fd li a5,-1 + bc4: 02f50863 beq a0,a5,bf4 <_puts_r+0x8a> + bc8: 4529 li a0,10 + bca: a035 j bf6 <_puts_r+0x8c> + bcc: 00001797 auipc a5,0x1 + bd0: 18c78793 addi a5,a5,396 # 1d58 <__sf_fake_stdout> + bd4: 00f41463 bne s0,a5,bdc <_puts_r+0x72> + bd8: 4480 lw s0,8(s1) + bda: b7c9 j b9c <_puts_r+0x32> + bdc: 00001797 auipc a5,0x1 + be0: 13c78793 addi a5,a5,316 # 1d18 <__sf_fake_stderr> + be4: faf41ce3 bne s0,a5,b9c <_puts_r+0x32> + be8: 44c0 lw s0,12(s1) + bea: bf4d j b9c <_puts_r+0x32> + bec: 85a2 mv a1,s0 + bee: 8526 mv a0,s1 + bf0: 2a11 jal d04 <__swsetup_r> + bf2: d955 beqz a0,ba6 <_puts_r+0x3c> + bf4: 557d li a0,-1 + bf6: 40f2 lw ra,28(sp) + bf8: 4462 lw s0,24(sp) + bfa: 44d2 lw s1,20(sp) + bfc: 4942 lw s2,16(sp) + bfe: 49b2 lw s3,12(sp) + c00: 4a22 lw s4,8(sp) + c02: 6105 addi sp,sp,32 + c04: 8082 ret + c06: c41c sw a5,8(s0) + c08: 0905 addi s2,s2,1 + c0a: 0007d763 bgez a5,c18 <_puts_r+0xae> + c0e: 4c18 lw a4,24(s0) + c10: 00e7ca63 blt a5,a4,c24 <_puts_r+0xba> + c14: 01458863 beq a1,s4,c24 <_puts_r+0xba> + c18: 401c lw a5,0(s0) + c1a: 00178713 addi a4,a5,1 + c1e: c018 sw a4,0(s0) + c20: a38c sb a1,0(a5) + c22: b761 j baa <_puts_r+0x40> + c24: 8622 mv a2,s0 + c26: 8526 mv a0,s1 + c28: 2005 jal c48 <__swbuf_r> + c2a: f93510e3 bne a0,s3,baa <_puts_r+0x40> + c2e: b7d9 j bf4 <_puts_r+0x8a> + c30: 401c lw a5,0(s0) + c32: 00178713 addi a4,a5,1 + c36: c018 sw a4,0(s0) + c38: 4729 li a4,10 + c3a: a398 sb a4,0(a5) + c3c: b771 j bc8 <_puts_r+0x5e> + +00000c3e : + c3e: 80c18793 addi a5,gp,-2036 # 2000008c <_impure_ptr> + c42: 85aa mv a1,a0 + c44: 4388 lw a0,0(a5) + c46: b715 j b6a <_puts_r> + +00000c48 <__swbuf_r>: + c48: 1101 addi sp,sp,-32 + c4a: cc22 sw s0,24(sp) + c4c: ca26 sw s1,20(sp) + c4e: c84a sw s2,16(sp) + c50: ce06 sw ra,28(sp) + c52: c64e sw s3,12(sp) + c54: 84aa mv s1,a0 + c56: 892e mv s2,a1 + c58: 8432 mv s0,a2 + c5a: c501 beqz a0,c62 <__swbuf_r+0x1a> + c5c: 4d1c lw a5,24(a0) + c5e: e391 bnez a5,c62 <__swbuf_r+0x1a> + c60: 26ed jal 104a <__sinit> + c62: 00001797 auipc a5,0x1 + c66: 0d678793 addi a5,a5,214 # 1d38 <__sf_fake_stdin> + c6a: 06f41763 bne s0,a5,cd8 <__swbuf_r+0x90> + c6e: 40c0 lw s0,4(s1) + c70: 4c1c lw a5,24(s0) + c72: c41c sw a5,8(s0) + c74: 245e lhu a5,12(s0) + c76: 8ba1 andi a5,a5,8 + c78: c3c1 beqz a5,cf8 <__swbuf_r+0xb0> + c7a: 481c lw a5,16(s0) + c7c: cfb5 beqz a5,cf8 <__swbuf_r+0xb0> + c7e: 481c lw a5,16(s0) + c80: 4008 lw a0,0(s0) + c82: 0ff97993 andi s3,s2,255 + c86: 0ff97913 andi s2,s2,255 + c8a: 8d1d sub a0,a0,a5 + c8c: 485c lw a5,20(s0) + c8e: 00f54663 blt a0,a5,c9a <__swbuf_r+0x52> + c92: 85a2 mv a1,s0 + c94: 8526 mv a0,s1 + c96: 2c69 jal f30 <_fflush_r> + c98: e525 bnez a0,d00 <__swbuf_r+0xb8> + c9a: 441c lw a5,8(s0) + c9c: 0505 addi a0,a0,1 + c9e: 17fd addi a5,a5,-1 + ca0: c41c sw a5,8(s0) + ca2: 401c lw a5,0(s0) + ca4: 00178713 addi a4,a5,1 + ca8: c018 sw a4,0(s0) + caa: 01378023 sb s3,0(a5) + cae: 485c lw a5,20(s0) + cb0: 00a78863 beq a5,a0,cc0 <__swbuf_r+0x78> + cb4: 245e lhu a5,12(s0) + cb6: 8b85 andi a5,a5,1 + cb8: cb81 beqz a5,cc8 <__swbuf_r+0x80> + cba: 47a9 li a5,10 + cbc: 00f91663 bne s2,a5,cc8 <__swbuf_r+0x80> + cc0: 85a2 mv a1,s0 + cc2: 8526 mv a0,s1 + cc4: 24b5 jal f30 <_fflush_r> + cc6: ed0d bnez a0,d00 <__swbuf_r+0xb8> + cc8: 40f2 lw ra,28(sp) + cca: 4462 lw s0,24(sp) + ccc: 854a mv a0,s2 + cce: 44d2 lw s1,20(sp) + cd0: 4942 lw s2,16(sp) + cd2: 49b2 lw s3,12(sp) + cd4: 6105 addi sp,sp,32 + cd6: 8082 ret + cd8: 00001797 auipc a5,0x1 + cdc: 08078793 addi a5,a5,128 # 1d58 <__sf_fake_stdout> + ce0: 00f41463 bne s0,a5,ce8 <__swbuf_r+0xa0> + ce4: 4480 lw s0,8(s1) + ce6: b769 j c70 <__swbuf_r+0x28> + ce8: 00001797 auipc a5,0x1 + cec: 03078793 addi a5,a5,48 # 1d18 <__sf_fake_stderr> + cf0: f8f410e3 bne s0,a5,c70 <__swbuf_r+0x28> + cf4: 44c0 lw s0,12(s1) + cf6: bfad j c70 <__swbuf_r+0x28> + cf8: 85a2 mv a1,s0 + cfa: 8526 mv a0,s1 + cfc: 2021 jal d04 <__swsetup_r> + cfe: d141 beqz a0,c7e <__swbuf_r+0x36> + d00: 597d li s2,-1 + d02: b7d9 j cc8 <__swbuf_r+0x80> + +00000d04 <__swsetup_r>: + d04: 1141 addi sp,sp,-16 + d06: 80c18793 addi a5,gp,-2036 # 2000008c <_impure_ptr> + d0a: c226 sw s1,4(sp) + d0c: 4384 lw s1,0(a5) + d0e: c422 sw s0,8(sp) + d10: c04a sw s2,0(sp) + d12: c606 sw ra,12(sp) + d14: 892a mv s2,a0 + d16: 842e mv s0,a1 + d18: c489 beqz s1,d22 <__swsetup_r+0x1e> + d1a: 4c9c lw a5,24(s1) + d1c: e399 bnez a5,d22 <__swsetup_r+0x1e> + d1e: 8526 mv a0,s1 + d20: 262d jal 104a <__sinit> + d22: 00001797 auipc a5,0x1 + d26: 01678793 addi a5,a5,22 # 1d38 <__sf_fake_stdin> + d2a: 02f41b63 bne s0,a5,d60 <__swsetup_r+0x5c> + d2e: 40c0 lw s0,4(s1) + d30: 00c41703 lh a4,12(s0) + d34: 01071793 slli a5,a4,0x10 + d38: 83c1 srli a5,a5,0x10 + d3a: 0087f693 andi a3,a5,8 + d3e: eaad bnez a3,db0 <__swsetup_r+0xac> + d40: 0107f693 andi a3,a5,16 + d44: ee95 bnez a3,d80 <__swsetup_r+0x7c> + d46: 47a5 li a5,9 + d48: 00f92023 sw a5,0(s2) + d4c: 04076713 ori a4,a4,64 + d50: a45a sh a4,12(s0) + d52: 557d li a0,-1 + d54: 40b2 lw ra,12(sp) + d56: 4422 lw s0,8(sp) + d58: 4492 lw s1,4(sp) + d5a: 4902 lw s2,0(sp) + d5c: 0141 addi sp,sp,16 + d5e: 8082 ret + d60: 00001797 auipc a5,0x1 + d64: ff878793 addi a5,a5,-8 # 1d58 <__sf_fake_stdout> + d68: 00f41463 bne s0,a5,d70 <__swsetup_r+0x6c> + d6c: 4480 lw s0,8(s1) + d6e: b7c9 j d30 <__swsetup_r+0x2c> + d70: 00001797 auipc a5,0x1 + d74: fa878793 addi a5,a5,-88 # 1d18 <__sf_fake_stderr> + d78: faf41ce3 bne s0,a5,d30 <__swsetup_r+0x2c> + d7c: 44c0 lw s0,12(s1) + d7e: bf4d j d30 <__swsetup_r+0x2c> + d80: 8b91 andi a5,a5,4 + d82: c39d beqz a5,da8 <__swsetup_r+0xa4> + d84: 584c lw a1,52(s0) + d86: c989 beqz a1,d98 <__swsetup_r+0x94> + d88: 04440793 addi a5,s0,68 + d8c: 00f58463 beq a1,a5,d94 <__swsetup_r+0x90> + d90: 854a mv a0,s2 + d92: 2331 jal 129e <_free_r> + d94: 02042a23 sw zero,52(s0) + d98: 245e lhu a5,12(s0) + d9a: 00042223 sw zero,4(s0) + d9e: fdb7f793 andi a5,a5,-37 + da2: a45e sh a5,12(s0) + da4: 481c lw a5,16(s0) + da6: c01c sw a5,0(s0) + da8: 245e lhu a5,12(s0) + daa: 0087e793 ori a5,a5,8 + dae: a45e sh a5,12(s0) + db0: 481c lw a5,16(s0) + db2: eb99 bnez a5,dc8 <__swsetup_r+0xc4> + db4: 245e lhu a5,12(s0) + db6: 20000713 li a4,512 + dba: 2807f793 andi a5,a5,640 + dbe: 00e78563 beq a5,a4,dc8 <__swsetup_r+0xc4> + dc2: 85a2 mv a1,s0 + dc4: 854a mv a0,s2 + dc6: 21a1 jal 120e <__smakebuf_r> + dc8: 245e lhu a5,12(s0) + dca: 0017f713 andi a4,a5,1 + dce: c31d beqz a4,df4 <__swsetup_r+0xf0> + dd0: 485c lw a5,20(s0) + dd2: 00042423 sw zero,8(s0) + dd6: 40f007b3 neg a5,a5 + dda: cc1c sw a5,24(s0) + ddc: 481c lw a5,16(s0) + dde: 4501 li a0,0 + de0: fbb5 bnez a5,d54 <__swsetup_r+0x50> + de2: 00c41783 lh a5,12(s0) + de6: 0807f713 andi a4,a5,128 + dea: d72d beqz a4,d54 <__swsetup_r+0x50> + dec: 0407e793 ori a5,a5,64 + df0: a45e sh a5,12(s0) + df2: b785 j d52 <__swsetup_r+0x4e> + df4: 8b89 andi a5,a5,2 + df6: 4701 li a4,0 + df8: e391 bnez a5,dfc <__swsetup_r+0xf8> + dfa: 4858 lw a4,20(s0) + dfc: c418 sw a4,8(s0) + dfe: bff9 j ddc <__swsetup_r+0xd8> + +00000e00 <__sflush_r>: + e00: 25de lhu a5,12(a1) + e02: 1101 addi sp,sp,-32 + e04: cc22 sw s0,24(sp) + e06: ca26 sw s1,20(sp) + e08: ce06 sw ra,28(sp) + e0a: c84a sw s2,16(sp) + e0c: c64e sw s3,12(sp) + e0e: 0087f713 andi a4,a5,8 + e12: 84aa mv s1,a0 + e14: 842e mv s0,a1 + e16: eb79 bnez a4,eec <__sflush_r+0xec> + e18: 41d8 lw a4,4(a1) + e1a: 00e04d63 bgtz a4,e34 <__sflush_r+0x34> + e1e: 41b8 lw a4,64(a1) + e20: 00e04a63 bgtz a4,e34 <__sflush_r+0x34> + e24: 4501 li a0,0 + e26: 40f2 lw ra,28(sp) + e28: 4462 lw s0,24(sp) + e2a: 44d2 lw s1,20(sp) + e2c: 4942 lw s2,16(sp) + e2e: 49b2 lw s3,12(sp) + e30: 6105 addi sp,sp,32 + e32: 8082 ret + e34: 5458 lw a4,44(s0) + e36: d77d beqz a4,e24 <__sflush_r+0x24> + e38: 0004a903 lw s2,0(s1) + e3c: 01379693 slli a3,a5,0x13 + e40: 0004a023 sw zero,0(s1) + e44: 0606db63 bgez a3,eba <__sflush_r+0xba> + e48: 4870 lw a2,84(s0) + e4a: 245e lhu a5,12(s0) + e4c: 8b91 andi a5,a5,4 + e4e: c799 beqz a5,e5c <__sflush_r+0x5c> + e50: 405c lw a5,4(s0) + e52: 8e1d sub a2,a2,a5 + e54: 585c lw a5,52(s0) + e56: c399 beqz a5,e5c <__sflush_r+0x5c> + e58: 403c lw a5,64(s0) + e5a: 8e1d sub a2,a2,a5 + e5c: 545c lw a5,44(s0) + e5e: 500c lw a1,32(s0) + e60: 4681 li a3,0 + e62: 8526 mv a0,s1 + e64: 9782 jalr a5 + e66: 57fd li a5,-1 + e68: 245a lhu a4,12(s0) + e6a: 00f51d63 bne a0,a5,e84 <__sflush_r+0x84> + e6e: 4094 lw a3,0(s1) + e70: 47f5 li a5,29 + e72: 06d7e863 bltu a5,a3,ee2 <__sflush_r+0xe2> + e76: 204007b7 lui a5,0x20400 + e7a: 0785 addi a5,a5,1 + e7c: 00d7d7b3 srl a5,a5,a3 + e80: 8b85 andi a5,a5,1 + e82: c3a5 beqz a5,ee2 <__sflush_r+0xe2> + e84: 481c lw a5,16(s0) + e86: 00042223 sw zero,4(s0) + e8a: c01c sw a5,0(s0) + e8c: 01371793 slli a5,a4,0x13 + e90: 0007d863 bgez a5,ea0 <__sflush_r+0xa0> + e94: 57fd li a5,-1 + e96: 00f51463 bne a0,a5,e9e <__sflush_r+0x9e> + e9a: 409c lw a5,0(s1) + e9c: e391 bnez a5,ea0 <__sflush_r+0xa0> + e9e: c868 sw a0,84(s0) + ea0: 584c lw a1,52(s0) + ea2: 0124a023 sw s2,0(s1) + ea6: ddbd beqz a1,e24 <__sflush_r+0x24> + ea8: 04440793 addi a5,s0,68 + eac: 00f58463 beq a1,a5,eb4 <__sflush_r+0xb4> + eb0: 8526 mv a0,s1 + eb2: 26f5 jal 129e <_free_r> + eb4: 02042a23 sw zero,52(s0) + eb8: b7b5 j e24 <__sflush_r+0x24> + eba: 500c lw a1,32(s0) + ebc: 4601 li a2,0 + ebe: 4685 li a3,1 + ec0: 8526 mv a0,s1 + ec2: 9702 jalr a4 + ec4: 57fd li a5,-1 + ec6: 862a mv a2,a0 + ec8: f8f511e3 bne a0,a5,e4a <__sflush_r+0x4a> + ecc: 409c lw a5,0(s1) + ece: dfb5 beqz a5,e4a <__sflush_r+0x4a> + ed0: 4775 li a4,29 + ed2: 00e78563 beq a5,a4,edc <__sflush_r+0xdc> + ed6: 4759 li a4,22 + ed8: 04e79363 bne a5,a4,f1e <__sflush_r+0x11e> + edc: 0124a023 sw s2,0(s1) + ee0: b791 j e24 <__sflush_r+0x24> + ee2: 04076713 ori a4,a4,64 + ee6: a45a sh a4,12(s0) + ee8: 557d li a0,-1 + eea: bf35 j e26 <__sflush_r+0x26> + eec: 0105a983 lw s3,16(a1) + ef0: f2098ae3 beqz s3,e24 <__sflush_r+0x24> + ef4: 0005a903 lw s2,0(a1) + ef8: 8b8d andi a5,a5,3 + efa: 0135a023 sw s3,0(a1) + efe: 41390933 sub s2,s2,s3 + f02: 4701 li a4,0 + f04: e391 bnez a5,f08 <__sflush_r+0x108> + f06: 49d8 lw a4,20(a1) + f08: c418 sw a4,8(s0) + f0a: f1205de3 blez s2,e24 <__sflush_r+0x24> + f0e: 541c lw a5,40(s0) + f10: 500c lw a1,32(s0) + f12: 86ca mv a3,s2 + f14: 864e mv a2,s3 + f16: 8526 mv a0,s1 + f18: 9782 jalr a5 + f1a: 00a04763 bgtz a0,f28 <__sflush_r+0x128> + f1e: 245e lhu a5,12(s0) + f20: 0407e793 ori a5,a5,64 + f24: a45e sh a5,12(s0) + f26: b7c9 j ee8 <__sflush_r+0xe8> + f28: 99aa add s3,s3,a0 + f2a: 40a90933 sub s2,s2,a0 + f2e: bff1 j f0a <__sflush_r+0x10a> + +00000f30 <_fflush_r>: + f30: 499c lw a5,16(a1) + f32: cfb9 beqz a5,f90 <_fflush_r+0x60> + f34: 1101 addi sp,sp,-32 + f36: cc22 sw s0,24(sp) + f38: ce06 sw ra,28(sp) + f3a: 842a mv s0,a0 + f3c: c511 beqz a0,f48 <_fflush_r+0x18> + f3e: 4d1c lw a5,24(a0) + f40: e781 bnez a5,f48 <_fflush_r+0x18> + f42: c62e sw a1,12(sp) + f44: 2219 jal 104a <__sinit> + f46: 45b2 lw a1,12(sp) + f48: 00001797 auipc a5,0x1 + f4c: df078793 addi a5,a5,-528 # 1d38 <__sf_fake_stdin> + f50: 00f59b63 bne a1,a5,f66 <_fflush_r+0x36> + f54: 404c lw a1,4(s0) + f56: 00c59783 lh a5,12(a1) + f5a: c795 beqz a5,f86 <_fflush_r+0x56> + f5c: 8522 mv a0,s0 + f5e: 4462 lw s0,24(sp) + f60: 40f2 lw ra,28(sp) + f62: 6105 addi sp,sp,32 + f64: bd71 j e00 <__sflush_r> + f66: 00001797 auipc a5,0x1 + f6a: df278793 addi a5,a5,-526 # 1d58 <__sf_fake_stdout> + f6e: 00f59463 bne a1,a5,f76 <_fflush_r+0x46> + f72: 440c lw a1,8(s0) + f74: b7cd j f56 <_fflush_r+0x26> + f76: 00001797 auipc a5,0x1 + f7a: da278793 addi a5,a5,-606 # 1d18 <__sf_fake_stderr> + f7e: fcf59ce3 bne a1,a5,f56 <_fflush_r+0x26> + f82: 444c lw a1,12(s0) + f84: bfc9 j f56 <_fflush_r+0x26> + f86: 40f2 lw ra,28(sp) + f88: 4462 lw s0,24(sp) + f8a: 4501 li a0,0 + f8c: 6105 addi sp,sp,32 + f8e: 8082 ret + f90: 4501 li a0,0 + f92: 8082 ret + +00000f94 : + f94: 1141 addi sp,sp,-16 + f96: c422 sw s0,8(sp) + f98: c606 sw ra,12(sp) + f9a: 842a mv s0,a0 + f9c: a54e sh a1,12(a0) + f9e: a572 sh a2,14(a0) + fa0: 00052023 sw zero,0(a0) + fa4: 00052223 sw zero,4(a0) + fa8: 00052423 sw zero,8(a0) + fac: 06052223 sw zero,100(a0) + fb0: 00052823 sw zero,16(a0) + fb4: 00052a23 sw zero,20(a0) + fb8: 00052c23 sw zero,24(a0) + fbc: 4621 li a2,8 + fbe: 4581 li a1,0 + fc0: 05c50513 addi a0,a0,92 + fc4: 9dcff0ef jal ra,1a0 + fc8: 00001797 auipc a5,0x1 + fcc: b1478793 addi a5,a5,-1260 # 1adc <__sread> + fd0: d05c sw a5,36(s0) + fd2: 00001797 auipc a5,0x1 + fd6: b3678793 addi a5,a5,-1226 # 1b08 <__swrite> + fda: d41c sw a5,40(s0) + fdc: 00001797 auipc a5,0x1 + fe0: b7478793 addi a5,a5,-1164 # 1b50 <__sseek> + fe4: d45c sw a5,44(s0) + fe6: 00001797 auipc a5,0x1 + fea: b9a78793 addi a5,a5,-1126 # 1b80 <__sclose> + fee: d000 sw s0,32(s0) + ff0: d81c sw a5,48(s0) + ff2: 40b2 lw ra,12(sp) + ff4: 4422 lw s0,8(sp) + ff6: 0141 addi sp,sp,16 + ff8: 8082 ret + +00000ffa <_cleanup_r>: + ffa: 00000597 auipc a1,0x0 + ffe: f3658593 addi a1,a1,-202 # f30 <_fflush_r> + 1002: a2a9 j 114c <_fwalk_reent> + +00001004 <__sfmoreglue>: + 1004: 1141 addi sp,sp,-16 + 1006: c226 sw s1,4(sp) + 1008: 06800613 li a2,104 + 100c: fff58493 addi s1,a1,-1 + 1010: 02c484b3 mul s1,s1,a2 + 1014: c04a sw s2,0(sp) + 1016: 892e mv s2,a1 + 1018: c422 sw s0,8(sp) + 101a: c606 sw ra,12(sp) + 101c: 07448593 addi a1,s1,116 + 1020: 261d jal 1346 <_malloc_r> + 1022: 842a mv s0,a0 + 1024: cd01 beqz a0,103c <__sfmoreglue+0x38> + 1026: 00052023 sw zero,0(a0) + 102a: 01252223 sw s2,4(a0) + 102e: 0531 addi a0,a0,12 + 1030: c408 sw a0,8(s0) + 1032: 06848613 addi a2,s1,104 + 1036: 4581 li a1,0 + 1038: 968ff0ef jal ra,1a0 + 103c: 8522 mv a0,s0 + 103e: 40b2 lw ra,12(sp) + 1040: 4422 lw s0,8(sp) + 1042: 4492 lw s1,4(sp) + 1044: 4902 lw s2,0(sp) + 1046: 0141 addi sp,sp,16 + 1048: 8082 ret + +0000104a <__sinit>: + 104a: 4d1c lw a5,24(a0) + 104c: e3ad bnez a5,10ae <__sinit+0x64> + 104e: 1141 addi sp,sp,-16 + 1050: c606 sw ra,12(sp) + 1052: c422 sw s0,8(sp) + 1054: 00000797 auipc a5,0x0 + 1058: fa678793 addi a5,a5,-90 # ffa <_cleanup_r> + 105c: d51c sw a5,40(a0) + 105e: 81018793 addi a5,gp,-2032 # 20000090 <_global_impure_ptr> + 1062: 439c lw a5,0(a5) + 1064: 04052423 sw zero,72(a0) + 1068: 04052623 sw zero,76(a0) + 106c: 04052823 sw zero,80(a0) + 1070: 00f51463 bne a0,a5,1078 <__sinit+0x2e> + 1074: 4785 li a5,1 + 1076: cd1c sw a5,24(a0) + 1078: 842a mv s0,a0 + 107a: 281d jal 10b0 <__sfp> + 107c: c048 sw a0,4(s0) + 107e: 8522 mv a0,s0 + 1080: 2805 jal 10b0 <__sfp> + 1082: c408 sw a0,8(s0) + 1084: 8522 mv a0,s0 + 1086: 202d jal 10b0 <__sfp> + 1088: c448 sw a0,12(s0) + 108a: 4048 lw a0,4(s0) + 108c: 4601 li a2,0 + 108e: 4591 li a1,4 + 1090: 3711 jal f94 + 1092: 4408 lw a0,8(s0) + 1094: 4605 li a2,1 + 1096: 45a5 li a1,9 + 1098: 3df5 jal f94 + 109a: 4448 lw a0,12(s0) + 109c: 4609 li a2,2 + 109e: 45c9 li a1,18 + 10a0: 3dd5 jal f94 + 10a2: 4785 li a5,1 + 10a4: cc1c sw a5,24(s0) + 10a6: 40b2 lw ra,12(sp) + 10a8: 4422 lw s0,8(sp) + 10aa: 0141 addi sp,sp,16 + 10ac: 8082 ret + 10ae: 8082 ret + +000010b0 <__sfp>: + 10b0: 1141 addi sp,sp,-16 + 10b2: 81018793 addi a5,gp,-2032 # 20000090 <_global_impure_ptr> + 10b6: c226 sw s1,4(sp) + 10b8: 4384 lw s1,0(a5) + 10ba: c04a sw s2,0(sp) + 10bc: c606 sw ra,12(sp) + 10be: 4c9c lw a5,24(s1) + 10c0: c422 sw s0,8(sp) + 10c2: 892a mv s2,a0 + 10c4: e399 bnez a5,10ca <__sfp+0x1a> + 10c6: 8526 mv a0,s1 + 10c8: 3749 jal 104a <__sinit> + 10ca: 04848493 addi s1,s1,72 + 10ce: 4480 lw s0,8(s1) + 10d0: 40dc lw a5,4(s1) + 10d2: 17fd addi a5,a5,-1 + 10d4: 0007d663 bgez a5,10e0 <__sfp+0x30> + 10d8: 409c lw a5,0(s1) + 10da: cfb9 beqz a5,1138 <__sfp+0x88> + 10dc: 4084 lw s1,0(s1) + 10de: bfc5 j 10ce <__sfp+0x1e> + 10e0: 00c41703 lh a4,12(s0) + 10e4: e739 bnez a4,1132 <__sfp+0x82> + 10e6: 77c1 lui a5,0xffff0 + 10e8: 0785 addi a5,a5,1 + 10ea: 06042223 sw zero,100(s0) + 10ee: 00042023 sw zero,0(s0) + 10f2: 00042223 sw zero,4(s0) + 10f6: 00042423 sw zero,8(s0) + 10fa: c45c sw a5,12(s0) + 10fc: 00042823 sw zero,16(s0) + 1100: 00042a23 sw zero,20(s0) + 1104: 00042c23 sw zero,24(s0) + 1108: 4621 li a2,8 + 110a: 4581 li a1,0 + 110c: 05c40513 addi a0,s0,92 + 1110: 890ff0ef jal ra,1a0 + 1114: 02042a23 sw zero,52(s0) + 1118: 02042c23 sw zero,56(s0) + 111c: 04042423 sw zero,72(s0) + 1120: 04042623 sw zero,76(s0) + 1124: 8522 mv a0,s0 + 1126: 40b2 lw ra,12(sp) + 1128: 4422 lw s0,8(sp) + 112a: 4492 lw s1,4(sp) + 112c: 4902 lw s2,0(sp) + 112e: 0141 addi sp,sp,16 + 1130: 8082 ret + 1132: 06840413 addi s0,s0,104 + 1136: bf71 j 10d2 <__sfp+0x22> + 1138: 4591 li a1,4 + 113a: 854a mv a0,s2 + 113c: 35e1 jal 1004 <__sfmoreglue> + 113e: c088 sw a0,0(s1) + 1140: fd51 bnez a0,10dc <__sfp+0x2c> + 1142: 47b1 li a5,12 + 1144: 00f92023 sw a5,0(s2) + 1148: 4401 li s0,0 + 114a: bfe9 j 1124 <__sfp+0x74> + +0000114c <_fwalk_reent>: + 114c: 7179 addi sp,sp,-48 + 114e: d422 sw s0,40(sp) + 1150: d04a sw s2,32(sp) + 1152: cc52 sw s4,24(sp) + 1154: ca56 sw s5,20(sp) + 1156: c85a sw s6,16(sp) + 1158: c65e sw s7,12(sp) + 115a: d606 sw ra,44(sp) + 115c: d226 sw s1,36(sp) + 115e: ce4e sw s3,28(sp) + 1160: 8a2a mv s4,a0 + 1162: 8aae mv s5,a1 + 1164: 04850413 addi s0,a0,72 + 1168: 4901 li s2,0 + 116a: 4b05 li s6,1 + 116c: 5bfd li s7,-1 + 116e: ec09 bnez s0,1188 <_fwalk_reent+0x3c> + 1170: 50b2 lw ra,44(sp) + 1172: 5422 lw s0,40(sp) + 1174: 854a mv a0,s2 + 1176: 5492 lw s1,36(sp) + 1178: 5902 lw s2,32(sp) + 117a: 49f2 lw s3,28(sp) + 117c: 4a62 lw s4,24(sp) + 117e: 4ad2 lw s5,20(sp) + 1180: 4b42 lw s6,16(sp) + 1182: 4bb2 lw s7,12(sp) + 1184: 6145 addi sp,sp,48 + 1186: 8082 ret + 1188: 4404 lw s1,8(s0) + 118a: 00442983 lw s3,4(s0) + 118e: 19fd addi s3,s3,-1 + 1190: 0009d463 bgez s3,1198 <_fwalk_reent+0x4c> + 1194: 4000 lw s0,0(s0) + 1196: bfe1 j 116e <_fwalk_reent+0x22> + 1198: 24de lhu a5,12(s1) + 119a: 00fb7b63 bgeu s6,a5,11b0 <_fwalk_reent+0x64> + 119e: 00e49783 lh a5,14(s1) + 11a2: 01778763 beq a5,s7,11b0 <_fwalk_reent+0x64> + 11a6: 85a6 mv a1,s1 + 11a8: 8552 mv a0,s4 + 11aa: 9a82 jalr s5 + 11ac: 00a96933 or s2,s2,a0 + 11b0: 06848493 addi s1,s1,104 + 11b4: bfe9 j 118e <_fwalk_reent+0x42> + +000011b6 <__swhatbuf_r>: + 11b6: 7119 addi sp,sp,-128 + 11b8: daa6 sw s1,116(sp) + 11ba: 84ae mv s1,a1 + 11bc: 00e59583 lh a1,14(a1) + 11c0: dca2 sw s0,120(sp) + 11c2: de86 sw ra,124(sp) + 11c4: 8432 mv s0,a2 + 11c6: 0005db63 bgez a1,11dc <__swhatbuf_r+0x26> + 11ca: 24de lhu a5,12(s1) + 11cc: 0006a023 sw zero,0(a3) + 11d0: 0807f793 andi a5,a5,128 + 11d4: e785 bnez a5,11fc <__swhatbuf_r+0x46> + 11d6: 40000793 li a5,1024 + 11da: a01d j 1200 <__swhatbuf_r+0x4a> + 11dc: 0830 addi a2,sp,24 + 11de: c636 sw a3,12(sp) + 11e0: 1fd000ef jal ra,1bdc <_fstat_r> + 11e4: 46b2 lw a3,12(sp) + 11e6: fe0542e3 bltz a0,11ca <__swhatbuf_r+0x14> + 11ea: 4772 lw a4,28(sp) + 11ec: 67bd lui a5,0xf + 11ee: 8ff9 and a5,a5,a4 + 11f0: 7779 lui a4,0xffffe + 11f2: 97ba add a5,a5,a4 + 11f4: 0017b793 seqz a5,a5 + 11f8: c29c sw a5,0(a3) + 11fa: bff1 j 11d6 <__swhatbuf_r+0x20> + 11fc: 04000793 li a5,64 + 1200: c01c sw a5,0(s0) + 1202: 50f6 lw ra,124(sp) + 1204: 5466 lw s0,120(sp) + 1206: 54d6 lw s1,116(sp) + 1208: 4501 li a0,0 + 120a: 6109 addi sp,sp,128 + 120c: 8082 ret + +0000120e <__smakebuf_r>: + 120e: 25de lhu a5,12(a1) + 1210: 1101 addi sp,sp,-32 + 1212: cc22 sw s0,24(sp) + 1214: ce06 sw ra,28(sp) + 1216: ca26 sw s1,20(sp) + 1218: c84a sw s2,16(sp) + 121a: 8b89 andi a5,a5,2 + 121c: 842e mv s0,a1 + 121e: cf89 beqz a5,1238 <__smakebuf_r+0x2a> + 1220: 04740793 addi a5,s0,71 + 1224: c01c sw a5,0(s0) + 1226: c81c sw a5,16(s0) + 1228: 4785 li a5,1 + 122a: c85c sw a5,20(s0) + 122c: 40f2 lw ra,28(sp) + 122e: 4462 lw s0,24(sp) + 1230: 44d2 lw s1,20(sp) + 1232: 4942 lw s2,16(sp) + 1234: 6105 addi sp,sp,32 + 1236: 8082 ret + 1238: 0074 addi a3,sp,12 + 123a: 0030 addi a2,sp,8 + 123c: 84aa mv s1,a0 + 123e: 3fa5 jal 11b6 <__swhatbuf_r> + 1240: 45a2 lw a1,8(sp) + 1242: 892a mv s2,a0 + 1244: 8526 mv a0,s1 + 1246: 2201 jal 1346 <_malloc_r> + 1248: e919 bnez a0,125e <__smakebuf_r+0x50> + 124a: 00c41783 lh a5,12(s0) + 124e: 2007f713 andi a4,a5,512 + 1252: ff69 bnez a4,122c <__smakebuf_r+0x1e> + 1254: 9bf1 andi a5,a5,-4 + 1256: 0027e793 ori a5,a5,2 + 125a: a45e sh a5,12(s0) + 125c: b7d1 j 1220 <__smakebuf_r+0x12> + 125e: 00000797 auipc a5,0x0 + 1262: d9c78793 addi a5,a5,-612 # ffa <_cleanup_r> + 1266: d49c sw a5,40(s1) + 1268: 245e lhu a5,12(s0) + 126a: c008 sw a0,0(s0) + 126c: c808 sw a0,16(s0) + 126e: 0807e793 ori a5,a5,128 + 1272: a45e sh a5,12(s0) + 1274: 47a2 lw a5,8(sp) + 1276: c85c sw a5,20(s0) + 1278: 47b2 lw a5,12(sp) + 127a: cf81 beqz a5,1292 <__smakebuf_r+0x84> + 127c: 00e41583 lh a1,14(s0) + 1280: 8526 mv a0,s1 + 1282: 185000ef jal ra,1c06 <_isatty_r> + 1286: c511 beqz a0,1292 <__smakebuf_r+0x84> + 1288: 245e lhu a5,12(s0) + 128a: 9bf1 andi a5,a5,-4 + 128c: 0017e793 ori a5,a5,1 + 1290: a45e sh a5,12(s0) + 1292: 245e lhu a5,12(s0) + 1294: 00f96933 or s2,s2,a5 + 1298: 01241623 sh s2,12(s0) + 129c: bf41 j 122c <__smakebuf_r+0x1e> + +0000129e <_free_r>: + 129e: c1dd beqz a1,1344 <_free_r+0xa6> + 12a0: ffc5a783 lw a5,-4(a1) + 12a4: 1141 addi sp,sp,-16 + 12a6: c422 sw s0,8(sp) + 12a8: c606 sw ra,12(sp) + 12aa: c226 sw s1,4(sp) + 12ac: ffc58413 addi s0,a1,-4 + 12b0: 0007d363 bgez a5,12b6 <_free_r+0x18> + 12b4: 943e add s0,s0,a5 + 12b6: 84aa mv s1,a0 + 12b8: 1bb000ef jal ra,1c72 <__malloc_lock> + 12bc: 83418793 addi a5,gp,-1996 # 200000b4 <__malloc_free_list> + 12c0: 439c lw a5,0(a5) + 12c2: ef81 bnez a5,12da <_free_r+0x3c> + 12c4: 00042223 sw zero,4(s0) + 12c8: 8281aa23 sw s0,-1996(gp) # 200000b4 <__malloc_free_list> + 12cc: 4422 lw s0,8(sp) + 12ce: 40b2 lw ra,12(sp) + 12d0: 8526 mv a0,s1 + 12d2: 4492 lw s1,4(sp) + 12d4: 0141 addi sp,sp,16 + 12d6: 19f0006f j 1c74 <__malloc_unlock> + 12da: 00f47e63 bgeu s0,a5,12f6 <_free_r+0x58> + 12de: 4014 lw a3,0(s0) + 12e0: 00d40733 add a4,s0,a3 + 12e4: 00e79663 bne a5,a4,12f0 <_free_r+0x52> + 12e8: 4398 lw a4,0(a5) + 12ea: 43dc lw a5,4(a5) + 12ec: 9736 add a4,a4,a3 + 12ee: c018 sw a4,0(s0) + 12f0: c05c sw a5,4(s0) + 12f2: bfd9 j 12c8 <_free_r+0x2a> + 12f4: 87ba mv a5,a4 + 12f6: 43d8 lw a4,4(a5) + 12f8: c319 beqz a4,12fe <_free_r+0x60> + 12fa: fee47de3 bgeu s0,a4,12f4 <_free_r+0x56> + 12fe: 4394 lw a3,0(a5) + 1300: 00d78633 add a2,a5,a3 + 1304: 00861f63 bne a2,s0,1322 <_free_r+0x84> + 1308: 4010 lw a2,0(s0) + 130a: 96b2 add a3,a3,a2 + 130c: c394 sw a3,0(a5) + 130e: 00d78633 add a2,a5,a3 + 1312: fac71de3 bne a4,a2,12cc <_free_r+0x2e> + 1316: 4310 lw a2,0(a4) + 1318: 4358 lw a4,4(a4) + 131a: 96b2 add a3,a3,a2 + 131c: c394 sw a3,0(a5) + 131e: c3d8 sw a4,4(a5) + 1320: b775 j 12cc <_free_r+0x2e> + 1322: 00c47563 bgeu s0,a2,132c <_free_r+0x8e> + 1326: 47b1 li a5,12 + 1328: c09c sw a5,0(s1) + 132a: b74d j 12cc <_free_r+0x2e> + 132c: 4010 lw a2,0(s0) + 132e: 00c406b3 add a3,s0,a2 + 1332: 00d71663 bne a4,a3,133e <_free_r+0xa0> + 1336: 4314 lw a3,0(a4) + 1338: 4358 lw a4,4(a4) + 133a: 96b2 add a3,a3,a2 + 133c: c014 sw a3,0(s0) + 133e: c058 sw a4,4(s0) + 1340: c3c0 sw s0,4(a5) + 1342: b769 j 12cc <_free_r+0x2e> + 1344: 8082 ret + +00001346 <_malloc_r>: + 1346: 1101 addi sp,sp,-32 + 1348: ca26 sw s1,20(sp) + 134a: 00358493 addi s1,a1,3 + 134e: 98f1 andi s1,s1,-4 + 1350: ce06 sw ra,28(sp) + 1352: cc22 sw s0,24(sp) + 1354: c84a sw s2,16(sp) + 1356: c64e sw s3,12(sp) + 1358: 04a1 addi s1,s1,8 + 135a: 47b1 li a5,12 + 135c: 04f4f363 bgeu s1,a5,13a2 <_malloc_r+0x5c> + 1360: 44b1 li s1,12 + 1362: 04b4e263 bltu s1,a1,13a6 <_malloc_r+0x60> + 1366: 892a mv s2,a0 + 1368: 10b000ef jal ra,1c72 <__malloc_lock> + 136c: 83418793 addi a5,gp,-1996 # 200000b4 <__malloc_free_list> + 1370: 4398 lw a4,0(a5) + 1372: 843a mv s0,a4 + 1374: e039 bnez s0,13ba <_malloc_r+0x74> + 1376: 83818793 addi a5,gp,-1992 # 200000b8 <__malloc_sbrk_start> + 137a: 439c lw a5,0(a5) + 137c: e791 bnez a5,1388 <_malloc_r+0x42> + 137e: 4581 li a1,0 + 1380: 854a mv a0,s2 + 1382: 2f05 jal 1ab2 <_sbrk_r> + 1384: 82a1ac23 sw a0,-1992(gp) # 200000b8 <__malloc_sbrk_start> + 1388: 85a6 mv a1,s1 + 138a: 854a mv a0,s2 + 138c: 271d jal 1ab2 <_sbrk_r> + 138e: 59fd li s3,-1 + 1390: 07351963 bne a0,s3,1402 <_malloc_r+0xbc> + 1394: 47b1 li a5,12 + 1396: 00f92023 sw a5,0(s2) + 139a: 854a mv a0,s2 + 139c: 0d9000ef jal ra,1c74 <__malloc_unlock> + 13a0: a029 j 13aa <_malloc_r+0x64> + 13a2: fc04d0e3 bgez s1,1362 <_malloc_r+0x1c> + 13a6: 47b1 li a5,12 + 13a8: c11c sw a5,0(a0) + 13aa: 4501 li a0,0 + 13ac: 40f2 lw ra,28(sp) + 13ae: 4462 lw s0,24(sp) + 13b0: 44d2 lw s1,20(sp) + 13b2: 4942 lw s2,16(sp) + 13b4: 49b2 lw s3,12(sp) + 13b6: 6105 addi sp,sp,32 + 13b8: 8082 ret + 13ba: 401c lw a5,0(s0) + 13bc: 8f85 sub a5,a5,s1 + 13be: 0207cf63 bltz a5,13fc <_malloc_r+0xb6> + 13c2: 46ad li a3,11 + 13c4: 00f6f663 bgeu a3,a5,13d0 <_malloc_r+0x8a> + 13c8: c01c sw a5,0(s0) + 13ca: 943e add s0,s0,a5 + 13cc: c004 sw s1,0(s0) + 13ce: a031 j 13da <_malloc_r+0x94> + 13d0: 405c lw a5,4(s0) + 13d2: 02871363 bne a4,s0,13f8 <_malloc_r+0xb2> + 13d6: 82f1aa23 sw a5,-1996(gp) # 200000b4 <__malloc_free_list> + 13da: 854a mv a0,s2 + 13dc: 099000ef jal ra,1c74 <__malloc_unlock> + 13e0: 00b40513 addi a0,s0,11 + 13e4: 00440793 addi a5,s0,4 + 13e8: 9961 andi a0,a0,-8 + 13ea: 40f50733 sub a4,a0,a5 + 13ee: df5d beqz a4,13ac <_malloc_r+0x66> + 13f0: 943a add s0,s0,a4 + 13f2: 8f89 sub a5,a5,a0 + 13f4: c01c sw a5,0(s0) + 13f6: bf5d j 13ac <_malloc_r+0x66> + 13f8: c35c sw a5,4(a4) + 13fa: b7c5 j 13da <_malloc_r+0x94> + 13fc: 8722 mv a4,s0 + 13fe: 4040 lw s0,4(s0) + 1400: bf95 j 1374 <_malloc_r+0x2e> + 1402: 00350413 addi s0,a0,3 + 1406: 9871 andi s0,s0,-4 + 1408: fc8502e3 beq a0,s0,13cc <_malloc_r+0x86> + 140c: 40a405b3 sub a1,s0,a0 + 1410: 854a mv a0,s2 + 1412: 2545 jal 1ab2 <_sbrk_r> + 1414: fb351ce3 bne a0,s3,13cc <_malloc_r+0x86> + 1418: bfb5 j 1394 <_malloc_r+0x4e> + +0000141a <__sfputc_r>: + 141a: 461c lw a5,8(a2) + 141c: 17fd addi a5,a5,-1 + 141e: c61c sw a5,8(a2) + 1420: 0007da63 bgez a5,1434 <__sfputc_r+0x1a> + 1424: 4e18 lw a4,24(a2) + 1426: 00e7c563 blt a5,a4,1430 <__sfputc_r+0x16> + 142a: 47a9 li a5,10 + 142c: 00f59463 bne a1,a5,1434 <__sfputc_r+0x1a> + 1430: 819ff06f j c48 <__swbuf_r> + 1434: 421c lw a5,0(a2) + 1436: 852e mv a0,a1 + 1438: 00178713 addi a4,a5,1 + 143c: c218 sw a4,0(a2) + 143e: a38c sb a1,0(a5) + 1440: 8082 ret + +00001442 <__sfputs_r>: + 1442: 1101 addi sp,sp,-32 + 1444: cc22 sw s0,24(sp) + 1446: ca26 sw s1,20(sp) + 1448: c84a sw s2,16(sp) + 144a: c64e sw s3,12(sp) + 144c: c452 sw s4,8(sp) + 144e: ce06 sw ra,28(sp) + 1450: 892a mv s2,a0 + 1452: 89ae mv s3,a1 + 1454: 8432 mv s0,a2 + 1456: 00d604b3 add s1,a2,a3 + 145a: 5a7d li s4,-1 + 145c: 00941463 bne s0,s1,1464 <__sfputs_r+0x22> + 1460: 4501 li a0,0 + 1462: a801 j 1472 <__sfputs_r+0x30> + 1464: 200c lbu a1,0(s0) + 1466: 864e mv a2,s3 + 1468: 854a mv a0,s2 + 146a: 3f45 jal 141a <__sfputc_r> + 146c: 0405 addi s0,s0,1 + 146e: ff4517e3 bne a0,s4,145c <__sfputs_r+0x1a> + 1472: 40f2 lw ra,28(sp) + 1474: 4462 lw s0,24(sp) + 1476: 44d2 lw s1,20(sp) + 1478: 4942 lw s2,16(sp) + 147a: 49b2 lw s3,12(sp) + 147c: 4a22 lw s4,8(sp) + 147e: 6105 addi sp,sp,32 + 1480: 8082 ret + +00001482 <_vfiprintf_r>: + 1482: 7135 addi sp,sp,-160 + 1484: cd22 sw s0,152(sp) + 1486: cb26 sw s1,148(sp) + 1488: c94a sw s2,144(sp) + 148a: c74e sw s3,140(sp) + 148c: cf06 sw ra,156(sp) + 148e: c552 sw s4,136(sp) + 1490: c356 sw s5,132(sp) + 1492: c15a sw s6,128(sp) + 1494: dede sw s7,124(sp) + 1496: dce2 sw s8,120(sp) + 1498: dae6 sw s9,116(sp) + 149a: 89aa mv s3,a0 + 149c: 84ae mv s1,a1 + 149e: 8932 mv s2,a2 + 14a0: 8436 mv s0,a3 + 14a2: c501 beqz a0,14aa <_vfiprintf_r+0x28> + 14a4: 4d1c lw a5,24(a0) + 14a6: e391 bnez a5,14aa <_vfiprintf_r+0x28> + 14a8: 364d jal 104a <__sinit> + 14aa: 00001797 auipc a5,0x1 + 14ae: 88e78793 addi a5,a5,-1906 # 1d38 <__sf_fake_stdin> + 14b2: 0cf49763 bne s1,a5,1580 <_vfiprintf_r+0xfe> + 14b6: 0049a483 lw s1,4(s3) + 14ba: 24de lhu a5,12(s1) + 14bc: 8ba1 andi a5,a5,8 + 14be: c3fd beqz a5,15a4 <_vfiprintf_r+0x122> + 14c0: 489c lw a5,16(s1) + 14c2: c3ed beqz a5,15a4 <_vfiprintf_r+0x122> + 14c4: 02000793 li a5,32 + 14c8: 02f104a3 sb a5,41(sp) + 14cc: 03000793 li a5,48 + 14d0: d202 sw zero,36(sp) + 14d2: 02f10523 sb a5,42(sp) + 14d6: c622 sw s0,12(sp) + 14d8: 02500b93 li s7,37 + 14dc: 00001a97 auipc s5,0x1 + 14e0: 89ca8a93 addi s5,s5,-1892 # 1d78 <__sf_fake_stdout+0x20> + 14e4: 4c05 li s8,1 + 14e6: 4b29 li s6,10 + 14e8: 844a mv s0,s2 + 14ea: 201c lbu a5,0(s0) + 14ec: c399 beqz a5,14f2 <_vfiprintf_r+0x70> + 14ee: 0d779e63 bne a5,s7,15ca <_vfiprintf_r+0x148> + 14f2: 41240cb3 sub s9,s0,s2 + 14f6: 000c8d63 beqz s9,1510 <_vfiprintf_r+0x8e> + 14fa: 86e6 mv a3,s9 + 14fc: 864a mv a2,s2 + 14fe: 85a6 mv a1,s1 + 1500: 854e mv a0,s3 + 1502: 3781 jal 1442 <__sfputs_r> + 1504: 57fd li a5,-1 + 1506: 1cf50f63 beq a0,a5,16e4 <_vfiprintf_r+0x262> + 150a: 5692 lw a3,36(sp) + 150c: 96e6 add a3,a3,s9 + 150e: d236 sw a3,36(sp) + 1510: 201c lbu a5,0(s0) + 1512: 1c078963 beqz a5,16e4 <_vfiprintf_r+0x262> + 1516: 57fd li a5,-1 + 1518: 00140913 addi s2,s0,1 + 151c: c802 sw zero,16(sp) + 151e: ce02 sw zero,28(sp) + 1520: ca3e sw a5,20(sp) + 1522: cc02 sw zero,24(sp) + 1524: 040109a3 sb zero,83(sp) + 1528: d482 sw zero,104(sp) + 152a: 00094583 lbu a1,0(s2) + 152e: 4615 li a2,5 + 1530: 8556 mv a0,s5 + 1532: 2725 jal 1c5a + 1534: 00190413 addi s0,s2,1 + 1538: 47c2 lw a5,16(sp) + 153a: e951 bnez a0,15ce <_vfiprintf_r+0x14c> + 153c: 0107f713 andi a4,a5,16 + 1540: c709 beqz a4,154a <_vfiprintf_r+0xc8> + 1542: 02000713 li a4,32 + 1546: 04e109a3 sb a4,83(sp) + 154a: 0087f713 andi a4,a5,8 + 154e: c709 beqz a4,1558 <_vfiprintf_r+0xd6> + 1550: 02b00713 li a4,43 + 1554: 04e109a3 sb a4,83(sp) + 1558: 00094683 lbu a3,0(s2) + 155c: 02a00713 li a4,42 + 1560: 06e68f63 beq a3,a4,15de <_vfiprintf_r+0x15c> + 1564: 47f2 lw a5,28(sp) + 1566: 844a mv s0,s2 + 1568: 4681 li a3,0 + 156a: 4625 li a2,9 + 156c: 2018 lbu a4,0(s0) + 156e: 00140593 addi a1,s0,1 + 1572: fd070713 addi a4,a4,-48 # ffffdfd0 <_eusrstack+0xdfff8fd0> + 1576: 0ae67763 bgeu a2,a4,1624 <_vfiprintf_r+0x1a2> + 157a: cab5 beqz a3,15ee <_vfiprintf_r+0x16c> + 157c: ce3e sw a5,28(sp) + 157e: a885 j 15ee <_vfiprintf_r+0x16c> + 1580: 00000797 auipc a5,0x0 + 1584: 7d878793 addi a5,a5,2008 # 1d58 <__sf_fake_stdout> + 1588: 00f49563 bne s1,a5,1592 <_vfiprintf_r+0x110> + 158c: 0089a483 lw s1,8(s3) + 1590: b72d j 14ba <_vfiprintf_r+0x38> + 1592: 00000797 auipc a5,0x0 + 1596: 78678793 addi a5,a5,1926 # 1d18 <__sf_fake_stderr> + 159a: f2f490e3 bne s1,a5,14ba <_vfiprintf_r+0x38> + 159e: 00c9a483 lw s1,12(s3) + 15a2: bf21 j 14ba <_vfiprintf_r+0x38> + 15a4: 85a6 mv a1,s1 + 15a6: 854e mv a0,s3 + 15a8: f5cff0ef jal ra,d04 <__swsetup_r> + 15ac: dd01 beqz a0,14c4 <_vfiprintf_r+0x42> + 15ae: 557d li a0,-1 + 15b0: 40fa lw ra,156(sp) + 15b2: 446a lw s0,152(sp) + 15b4: 44da lw s1,148(sp) + 15b6: 494a lw s2,144(sp) + 15b8: 49ba lw s3,140(sp) + 15ba: 4a2a lw s4,136(sp) + 15bc: 4a9a lw s5,132(sp) + 15be: 4b0a lw s6,128(sp) + 15c0: 5bf6 lw s7,124(sp) + 15c2: 5c66 lw s8,120(sp) + 15c4: 5cd6 lw s9,116(sp) + 15c6: 610d addi sp,sp,160 + 15c8: 8082 ret + 15ca: 0405 addi s0,s0,1 + 15cc: bf39 j 14ea <_vfiprintf_r+0x68> + 15ce: 41550533 sub a0,a0,s5 + 15d2: 00ac1533 sll a0,s8,a0 + 15d6: 8fc9 or a5,a5,a0 + 15d8: c83e sw a5,16(sp) + 15da: 8922 mv s2,s0 + 15dc: b7b9 j 152a <_vfiprintf_r+0xa8> + 15de: 4732 lw a4,12(sp) + 15e0: 00470693 addi a3,a4,4 + 15e4: 4318 lw a4,0(a4) + 15e6: c636 sw a3,12(sp) + 15e8: 02074763 bltz a4,1616 <_vfiprintf_r+0x194> + 15ec: ce3a sw a4,28(sp) + 15ee: 2018 lbu a4,0(s0) + 15f0: 02e00793 li a5,46 + 15f4: 04f71d63 bne a4,a5,164e <_vfiprintf_r+0x1cc> + 15f8: 3018 lbu a4,1(s0) + 15fa: 02a00793 li a5,42 + 15fe: 02f71b63 bne a4,a5,1634 <_vfiprintf_r+0x1b2> + 1602: 47b2 lw a5,12(sp) + 1604: 0409 addi s0,s0,2 + 1606: 00478713 addi a4,a5,4 + 160a: 439c lw a5,0(a5) + 160c: c63a sw a4,12(sp) + 160e: 0207c163 bltz a5,1630 <_vfiprintf_r+0x1ae> + 1612: ca3e sw a5,20(sp) + 1614: a82d j 164e <_vfiprintf_r+0x1cc> + 1616: 40e00733 neg a4,a4 + 161a: 0027e793 ori a5,a5,2 + 161e: ce3a sw a4,28(sp) + 1620: c83e sw a5,16(sp) + 1622: b7f1 j 15ee <_vfiprintf_r+0x16c> + 1624: 036787b3 mul a5,a5,s6 + 1628: 4685 li a3,1 + 162a: 842e mv s0,a1 + 162c: 97ba add a5,a5,a4 + 162e: bf3d j 156c <_vfiprintf_r+0xea> + 1630: 57fd li a5,-1 + 1632: b7c5 j 1612 <_vfiprintf_r+0x190> + 1634: 0405 addi s0,s0,1 + 1636: ca02 sw zero,20(sp) + 1638: 4681 li a3,0 + 163a: 4781 li a5,0 + 163c: 4625 li a2,9 + 163e: 2018 lbu a4,0(s0) + 1640: 00140593 addi a1,s0,1 + 1644: fd070713 addi a4,a4,-48 + 1648: 06e67463 bgeu a2,a4,16b0 <_vfiprintf_r+0x22e> + 164c: f2f9 bnez a3,1612 <_vfiprintf_r+0x190> + 164e: 200c lbu a1,0(s0) + 1650: 460d li a2,3 + 1652: 00000517 auipc a0,0x0 + 1656: 72e50513 addi a0,a0,1838 # 1d80 <__sf_fake_stdout+0x28> + 165a: 2501 jal 1c5a + 165c: cd11 beqz a0,1678 <_vfiprintf_r+0x1f6> + 165e: 00000797 auipc a5,0x0 + 1662: 72278793 addi a5,a5,1826 # 1d80 <__sf_fake_stdout+0x28> + 1666: 8d1d sub a0,a0,a5 + 1668: 04000793 li a5,64 + 166c: 00a797b3 sll a5,a5,a0 + 1670: 4542 lw a0,16(sp) + 1672: 0405 addi s0,s0,1 + 1674: 8d5d or a0,a0,a5 + 1676: c82a sw a0,16(sp) + 1678: 200c lbu a1,0(s0) + 167a: 4619 li a2,6 + 167c: 00000517 auipc a0,0x0 + 1680: 70850513 addi a0,a0,1800 # 1d84 <__sf_fake_stdout+0x2c> + 1684: 00140913 addi s2,s0,1 + 1688: 02b10423 sb a1,40(sp) + 168c: 23f9 jal 1c5a + 168e: c135 beqz a0,16f2 <_vfiprintf_r+0x270> + 1690: fffff797 auipc a5,0xfffff + 1694: 97078793 addi a5,a5,-1680 # 0 <_sinit> + 1698: e795 bnez a5,16c4 <_vfiprintf_r+0x242> + 169a: 4742 lw a4,16(sp) + 169c: 47b2 lw a5,12(sp) + 169e: 10077713 andi a4,a4,256 + 16a2: cf09 beqz a4,16bc <_vfiprintf_r+0x23a> + 16a4: 0791 addi a5,a5,4 + 16a6: c63e sw a5,12(sp) + 16a8: 5792 lw a5,36(sp) + 16aa: 97d2 add a5,a5,s4 + 16ac: d23e sw a5,36(sp) + 16ae: bd2d j 14e8 <_vfiprintf_r+0x66> + 16b0: 036787b3 mul a5,a5,s6 + 16b4: 4685 li a3,1 + 16b6: 842e mv s0,a1 + 16b8: 97ba add a5,a5,a4 + 16ba: b751 j 163e <_vfiprintf_r+0x1bc> + 16bc: 079d addi a5,a5,7 + 16be: 9be1 andi a5,a5,-8 + 16c0: 07a1 addi a5,a5,8 + 16c2: b7d5 j 16a6 <_vfiprintf_r+0x224> + 16c4: 0078 addi a4,sp,12 + 16c6: 00000697 auipc a3,0x0 + 16ca: d7c68693 addi a3,a3,-644 # 1442 <__sfputs_r> + 16ce: 8626 mv a2,s1 + 16d0: 080c addi a1,sp,16 + 16d2: 854e mv a0,s3 + 16d4: 00000097 auipc ra,0x0 + 16d8: 000000e7 jalr zero # 0 <_sinit> + 16dc: 57fd li a5,-1 + 16de: 8a2a mv s4,a0 + 16e0: fcf514e3 bne a0,a5,16a8 <_vfiprintf_r+0x226> + 16e4: 24de lhu a5,12(s1) + 16e6: 0407f793 andi a5,a5,64 + 16ea: ec0792e3 bnez a5,15ae <_vfiprintf_r+0x12c> + 16ee: 5512 lw a0,36(sp) + 16f0: b5c1 j 15b0 <_vfiprintf_r+0x12e> + 16f2: 0078 addi a4,sp,12 + 16f4: 00000697 auipc a3,0x0 + 16f8: d4e68693 addi a3,a3,-690 # 1442 <__sfputs_r> + 16fc: 8626 mv a2,s1 + 16fe: 080c addi a1,sp,16 + 1700: 854e mv a0,s3 + 1702: 2a01 jal 1812 <_printf_i> + 1704: bfe1 j 16dc <_vfiprintf_r+0x25a> + +00001706 <_printf_common>: + 1706: 7179 addi sp,sp,-48 + 1708: ca56 sw s5,20(sp) + 170a: 499c lw a5,16(a1) + 170c: 8aba mv s5,a4 + 170e: 4598 lw a4,8(a1) + 1710: d422 sw s0,40(sp) + 1712: d226 sw s1,36(sp) + 1714: ce4e sw s3,28(sp) + 1716: cc52 sw s4,24(sp) + 1718: d606 sw ra,44(sp) + 171a: d04a sw s2,32(sp) + 171c: c85a sw s6,16(sp) + 171e: c65e sw s7,12(sp) + 1720: 89aa mv s3,a0 + 1722: 842e mv s0,a1 + 1724: 84b2 mv s1,a2 + 1726: 8a36 mv s4,a3 + 1728: 00e7d363 bge a5,a4,172e <_printf_common+0x28> + 172c: 87ba mv a5,a4 + 172e: c09c sw a5,0(s1) + 1730: 04344703 lbu a4,67(s0) + 1734: c319 beqz a4,173a <_printf_common+0x34> + 1736: 0785 addi a5,a5,1 + 1738: c09c sw a5,0(s1) + 173a: 401c lw a5,0(s0) + 173c: 0207f793 andi a5,a5,32 + 1740: c781 beqz a5,1748 <_printf_common+0x42> + 1742: 409c lw a5,0(s1) + 1744: 0789 addi a5,a5,2 + 1746: c09c sw a5,0(s1) + 1748: 00042903 lw s2,0(s0) + 174c: 00697913 andi s2,s2,6 + 1750: 00091a63 bnez s2,1764 <_printf_common+0x5e> + 1754: 01940b13 addi s6,s0,25 + 1758: 5bfd li s7,-1 + 175a: 445c lw a5,12(s0) + 175c: 4098 lw a4,0(s1) + 175e: 8f99 sub a5,a5,a4 + 1760: 04f94c63 blt s2,a5,17b8 <_printf_common+0xb2> + 1764: 401c lw a5,0(s0) + 1766: 04344683 lbu a3,67(s0) + 176a: 0207f793 andi a5,a5,32 + 176e: 00d036b3 snez a3,a3 + 1772: eba5 bnez a5,17e2 <_printf_common+0xdc> + 1774: 04340613 addi a2,s0,67 + 1778: 85d2 mv a1,s4 + 177a: 854e mv a0,s3 + 177c: 9a82 jalr s5 + 177e: 57fd li a5,-1 + 1780: 04f50363 beq a0,a5,17c6 <_printf_common+0xc0> + 1784: 401c lw a5,0(s0) + 1786: 4611 li a2,4 + 1788: 4098 lw a4,0(s1) + 178a: 8b99 andi a5,a5,6 + 178c: 4454 lw a3,12(s0) + 178e: 4481 li s1,0 + 1790: 00c79763 bne a5,a2,179e <_printf_common+0x98> + 1794: 40e684b3 sub s1,a3,a4 + 1798: 0004d363 bgez s1,179e <_printf_common+0x98> + 179c: 4481 li s1,0 + 179e: 441c lw a5,8(s0) + 17a0: 4818 lw a4,16(s0) + 17a2: 00f75463 bge a4,a5,17aa <_printf_common+0xa4> + 17a6: 8f99 sub a5,a5,a4 + 17a8: 94be add s1,s1,a5 + 17aa: 4901 li s2,0 + 17ac: 0469 addi s0,s0,26 + 17ae: 5b7d li s6,-1 + 17b0: 05249863 bne s1,s2,1800 <_printf_common+0xfa> + 17b4: 4501 li a0,0 + 17b6: a809 j 17c8 <_printf_common+0xc2> + 17b8: 4685 li a3,1 + 17ba: 865a mv a2,s6 + 17bc: 85d2 mv a1,s4 + 17be: 854e mv a0,s3 + 17c0: 9a82 jalr s5 + 17c2: 01751e63 bne a0,s7,17de <_printf_common+0xd8> + 17c6: 557d li a0,-1 + 17c8: 50b2 lw ra,44(sp) + 17ca: 5422 lw s0,40(sp) + 17cc: 5492 lw s1,36(sp) + 17ce: 5902 lw s2,32(sp) + 17d0: 49f2 lw s3,28(sp) + 17d2: 4a62 lw s4,24(sp) + 17d4: 4ad2 lw s5,20(sp) + 17d6: 4b42 lw s6,16(sp) + 17d8: 4bb2 lw s7,12(sp) + 17da: 6145 addi sp,sp,48 + 17dc: 8082 ret + 17de: 0905 addi s2,s2,1 + 17e0: bfad j 175a <_printf_common+0x54> + 17e2: 00d40733 add a4,s0,a3 + 17e6: 03000613 li a2,48 + 17ea: 04c701a3 sb a2,67(a4) + 17ee: 04544703 lbu a4,69(s0) + 17f2: 00168793 addi a5,a3,1 + 17f6: 97a2 add a5,a5,s0 + 17f8: 0689 addi a3,a3,2 + 17fa: 04e781a3 sb a4,67(a5) + 17fe: bf9d j 1774 <_printf_common+0x6e> + 1800: 4685 li a3,1 + 1802: 8622 mv a2,s0 + 1804: 85d2 mv a1,s4 + 1806: 854e mv a0,s3 + 1808: 9a82 jalr s5 + 180a: fb650ee3 beq a0,s6,17c6 <_printf_common+0xc0> + 180e: 0905 addi s2,s2,1 + 1810: b745 j 17b0 <_printf_common+0xaa> + +00001812 <_printf_i>: + 1812: 7179 addi sp,sp,-48 + 1814: d422 sw s0,40(sp) + 1816: d226 sw s1,36(sp) + 1818: d04a sw s2,32(sp) + 181a: ce4e sw s3,28(sp) + 181c: d606 sw ra,44(sp) + 181e: cc52 sw s4,24(sp) + 1820: ca56 sw s5,20(sp) + 1822: c85a sw s6,16(sp) + 1824: 89b6 mv s3,a3 + 1826: 2d94 lbu a3,24(a1) + 1828: 06900793 li a5,105 + 182c: 8932 mv s2,a2 + 182e: 84aa mv s1,a0 + 1830: 842e mv s0,a1 + 1832: 04358613 addi a2,a1,67 + 1836: 02f68d63 beq a3,a5,1870 <_printf_i+0x5e> + 183a: 06d7e263 bltu a5,a3,189e <_printf_i+0x8c> + 183e: 05800793 li a5,88 + 1842: 18f68563 beq a3,a5,19cc <_printf_i+0x1ba> + 1846: 00d7ed63 bltu a5,a3,1860 <_printf_i+0x4e> + 184a: 20068d63 beqz a3,1a64 <_printf_i+0x252> + 184e: 04300793 li a5,67 + 1852: 0af68e63 beq a3,a5,190e <_printf_i+0xfc> + 1856: 04240a93 addi s5,s0,66 + 185a: 04d40123 sb a3,66(s0) + 185e: a0c9 j 1920 <_printf_i+0x10e> + 1860: 06300793 li a5,99 + 1864: 0af68563 beq a3,a5,190e <_printf_i+0xfc> + 1868: 06400793 li a5,100 + 186c: fef695e3 bne a3,a5,1856 <_printf_i+0x44> + 1870: 401c lw a5,0(s0) + 1872: 4308 lw a0,0(a4) + 1874: 0807f693 andi a3,a5,128 + 1878: 00450593 addi a1,a0,4 + 187c: c6c5 beqz a3,1924 <_printf_i+0x112> + 187e: 411c lw a5,0(a0) + 1880: c30c sw a1,0(a4) + 1882: 0007d863 bgez a5,1892 <_printf_i+0x80> + 1886: 02d00713 li a4,45 + 188a: 40f007b3 neg a5,a5 + 188e: 04e401a3 sb a4,67(s0) + 1892: 00000697 auipc a3,0x0 + 1896: 4fa68693 addi a3,a3,1274 # 1d8c <__sf_fake_stdout+0x34> + 189a: 4729 li a4,10 + 189c: a865 j 1954 <_printf_i+0x142> + 189e: 07000793 li a5,112 + 18a2: 16f68163 beq a3,a5,1a04 <_printf_i+0x1f2> + 18a6: 02d7e563 bltu a5,a3,18d0 <_printf_i+0xbe> + 18aa: 06e00793 li a5,110 + 18ae: 18f68863 beq a3,a5,1a3e <_printf_i+0x22c> + 18b2: 06f00793 li a5,111 + 18b6: faf690e3 bne a3,a5,1856 <_printf_i+0x44> + 18ba: 400c lw a1,0(s0) + 18bc: 431c lw a5,0(a4) + 18be: 0805f813 andi a6,a1,128 + 18c2: 00478513 addi a0,a5,4 + 18c6: 06080763 beqz a6,1934 <_printf_i+0x122> + 18ca: c308 sw a0,0(a4) + 18cc: 439c lw a5,0(a5) + 18ce: a885 j 193e <_printf_i+0x12c> + 18d0: 07500793 li a5,117 + 18d4: fef683e3 beq a3,a5,18ba <_printf_i+0xa8> + 18d8: 07800793 li a5,120 + 18dc: 12f68863 beq a3,a5,1a0c <_printf_i+0x1fa> + 18e0: 07300793 li a5,115 + 18e4: f6f699e3 bne a3,a5,1856 <_printf_i+0x44> + 18e8: 431c lw a5,0(a4) + 18ea: 41d0 lw a2,4(a1) + 18ec: 4581 li a1,0 + 18ee: 00478693 addi a3,a5,4 + 18f2: c314 sw a3,0(a4) + 18f4: 0007aa83 lw s5,0(a5) + 18f8: 8556 mv a0,s5 + 18fa: 2685 jal 1c5a + 18fc: c501 beqz a0,1904 <_printf_i+0xf2> + 18fe: 41550533 sub a0,a0,s5 + 1902: c048 sw a0,4(s0) + 1904: 405c lw a5,4(s0) + 1906: c81c sw a5,16(s0) + 1908: 040401a3 sb zero,67(s0) + 190c: a861 j 19a4 <_printf_i+0x192> + 190e: 431c lw a5,0(a4) + 1910: 04240a93 addi s5,s0,66 + 1914: 00478693 addi a3,a5,4 + 1918: 439c lw a5,0(a5) + 191a: c314 sw a3,0(a4) + 191c: 04f40123 sb a5,66(s0) + 1920: 4785 li a5,1 + 1922: b7d5 j 1906 <_printf_i+0xf4> + 1924: 0407f693 andi a3,a5,64 + 1928: 411c lw a5,0(a0) + 192a: c30c sw a1,0(a4) + 192c: dab9 beqz a3,1882 <_printf_i+0x70> + 192e: 07c2 slli a5,a5,0x10 + 1930: 87c1 srai a5,a5,0x10 + 1932: bf81 j 1882 <_printf_i+0x70> + 1934: 0405f593 andi a1,a1,64 + 1938: c308 sw a0,0(a4) + 193a: d9c9 beqz a1,18cc <_printf_i+0xba> + 193c: 239e lhu a5,0(a5) + 193e: 06f00713 li a4,111 + 1942: 0ee68663 beq a3,a4,1a2e <_printf_i+0x21c> + 1946: 00000697 auipc a3,0x0 + 194a: 44668693 addi a3,a3,1094 # 1d8c <__sf_fake_stdout+0x34> + 194e: 4729 li a4,10 + 1950: 040401a3 sb zero,67(s0) + 1954: 404c lw a1,4(s0) + 1956: c40c sw a1,8(s0) + 1958: 0005c563 bltz a1,1962 <_printf_i+0x150> + 195c: 4008 lw a0,0(s0) + 195e: 996d andi a0,a0,-5 + 1960: c008 sw a0,0(s0) + 1962: e399 bnez a5,1968 <_printf_i+0x156> + 1964: 8ab2 mv s5,a2 + 1966: cd89 beqz a1,1980 <_printf_i+0x16e> + 1968: 8ab2 mv s5,a2 + 196a: 02e7f5b3 remu a1,a5,a4 + 196e: 1afd addi s5,s5,-1 + 1970: 95b6 add a1,a1,a3 + 1972: 218c lbu a1,0(a1) + 1974: 00ba8023 sb a1,0(s5) + 1978: 02e7d5b3 divu a1,a5,a4 + 197c: 0ae7ff63 bgeu a5,a4,1a3a <_printf_i+0x228> + 1980: 47a1 li a5,8 + 1982: 00f71e63 bne a4,a5,199e <_printf_i+0x18c> + 1986: 401c lw a5,0(s0) + 1988: 8b85 andi a5,a5,1 + 198a: cb91 beqz a5,199e <_printf_i+0x18c> + 198c: 4058 lw a4,4(s0) + 198e: 481c lw a5,16(s0) + 1990: 00e7c763 blt a5,a4,199e <_printf_i+0x18c> + 1994: 03000793 li a5,48 + 1998: fefa8fa3 sb a5,-1(s5) + 199c: 1afd addi s5,s5,-1 + 199e: 41560633 sub a2,a2,s5 + 19a2: c810 sw a2,16(s0) + 19a4: 874e mv a4,s3 + 19a6: 86ca mv a3,s2 + 19a8: 0070 addi a2,sp,12 + 19aa: 85a2 mv a1,s0 + 19ac: 8526 mv a0,s1 + 19ae: 3ba1 jal 1706 <_printf_common> + 19b0: 5a7d li s4,-1 + 19b2: 0b451d63 bne a0,s4,1a6c <_printf_i+0x25a> + 19b6: 557d li a0,-1 + 19b8: 50b2 lw ra,44(sp) + 19ba: 5422 lw s0,40(sp) + 19bc: 5492 lw s1,36(sp) + 19be: 5902 lw s2,32(sp) + 19c0: 49f2 lw s3,28(sp) + 19c2: 4a62 lw s4,24(sp) + 19c4: 4ad2 lw s5,20(sp) + 19c6: 4b42 lw s6,16(sp) + 19c8: 6145 addi sp,sp,48 + 19ca: 8082 ret + 19cc: 04d582a3 sb a3,69(a1) + 19d0: 00000697 auipc a3,0x0 + 19d4: 3bc68693 addi a3,a3,956 # 1d8c <__sf_fake_stdout+0x34> + 19d8: 400c lw a1,0(s0) + 19da: 4308 lw a0,0(a4) + 19dc: 0805f813 andi a6,a1,128 + 19e0: 411c lw a5,0(a0) + 19e2: 0511 addi a0,a0,4 + 19e4: 02080d63 beqz a6,1a1e <_printf_i+0x20c> + 19e8: c308 sw a0,0(a4) + 19ea: 0015f713 andi a4,a1,1 + 19ee: c701 beqz a4,19f6 <_printf_i+0x1e4> + 19f0: 0205e593 ori a1,a1,32 + 19f4: c00c sw a1,0(s0) + 19f6: 4741 li a4,16 + 19f8: ffa1 bnez a5,1950 <_printf_i+0x13e> + 19fa: 400c lw a1,0(s0) + 19fc: fdf5f593 andi a1,a1,-33 + 1a00: c00c sw a1,0(s0) + 1a02: b7b9 j 1950 <_printf_i+0x13e> + 1a04: 419c lw a5,0(a1) + 1a06: 0207e793 ori a5,a5,32 + 1a0a: c19c sw a5,0(a1) + 1a0c: 07800793 li a5,120 + 1a10: 04f402a3 sb a5,69(s0) + 1a14: 00000697 auipc a3,0x0 + 1a18: 38c68693 addi a3,a3,908 # 1da0 <__sf_fake_stdout+0x48> + 1a1c: bf75 j 19d8 <_printf_i+0x1c6> + 1a1e: 0405f813 andi a6,a1,64 + 1a22: c308 sw a0,0(a4) + 1a24: fc0803e3 beqz a6,19ea <_printf_i+0x1d8> + 1a28: 07c2 slli a5,a5,0x10 + 1a2a: 83c1 srli a5,a5,0x10 + 1a2c: bf7d j 19ea <_printf_i+0x1d8> + 1a2e: 00000697 auipc a3,0x0 + 1a32: 35e68693 addi a3,a3,862 # 1d8c <__sf_fake_stdout+0x34> + 1a36: 4721 li a4,8 + 1a38: bf21 j 1950 <_printf_i+0x13e> + 1a3a: 87ae mv a5,a1 + 1a3c: b73d j 196a <_printf_i+0x158> + 1a3e: 4194 lw a3,0(a1) + 1a40: 431c lw a5,0(a4) + 1a42: 49cc lw a1,20(a1) + 1a44: 0806f813 andi a6,a3,128 + 1a48: 00478513 addi a0,a5,4 + 1a4c: 00080663 beqz a6,1a58 <_printf_i+0x246> + 1a50: c308 sw a0,0(a4) + 1a52: 439c lw a5,0(a5) + 1a54: c38c sw a1,0(a5) + 1a56: a039 j 1a64 <_printf_i+0x252> + 1a58: c308 sw a0,0(a4) + 1a5a: 0406f693 andi a3,a3,64 + 1a5e: 439c lw a5,0(a5) + 1a60: daf5 beqz a3,1a54 <_printf_i+0x242> + 1a62: a38e sh a1,0(a5) + 1a64: 00042823 sw zero,16(s0) + 1a68: 8ab2 mv s5,a2 + 1a6a: bf2d j 19a4 <_printf_i+0x192> + 1a6c: 4814 lw a3,16(s0) + 1a6e: 8656 mv a2,s5 + 1a70: 85ca mv a1,s2 + 1a72: 8526 mv a0,s1 + 1a74: 9982 jalr s3 + 1a76: f54500e3 beq a0,s4,19b6 <_printf_i+0x1a4> + 1a7a: 401c lw a5,0(s0) + 1a7c: 8b89 andi a5,a5,2 + 1a7e: e78d bnez a5,1aa8 <_printf_i+0x296> + 1a80: 47b2 lw a5,12(sp) + 1a82: 4448 lw a0,12(s0) + 1a84: f2f55ae3 bge a0,a5,19b8 <_printf_i+0x1a6> + 1a88: 853e mv a0,a5 + 1a8a: b73d j 19b8 <_printf_i+0x1a6> + 1a8c: 4685 li a3,1 + 1a8e: 8656 mv a2,s5 + 1a90: 85ca mv a1,s2 + 1a92: 8526 mv a0,s1 + 1a94: 9982 jalr s3 + 1a96: f36500e3 beq a0,s6,19b6 <_printf_i+0x1a4> + 1a9a: 0a05 addi s4,s4,1 + 1a9c: 445c lw a5,12(s0) + 1a9e: 4732 lw a4,12(sp) + 1aa0: 8f99 sub a5,a5,a4 + 1aa2: fefa45e3 blt s4,a5,1a8c <_printf_i+0x27a> + 1aa6: bfe9 j 1a80 <_printf_i+0x26e> + 1aa8: 4a01 li s4,0 + 1aaa: 01940a93 addi s5,s0,25 + 1aae: 5b7d li s6,-1 + 1ab0: b7f5 j 1a9c <_printf_i+0x28a> + +00001ab2 <_sbrk_r>: + 1ab2: 1141 addi sp,sp,-16 + 1ab4: c422 sw s0,8(sp) + 1ab6: 842a mv s0,a0 + 1ab8: 852e mv a0,a1 + 1aba: 8201ae23 sw zero,-1988(gp) # 200000bc + 1abe: c606 sw ra,12(sp) + 1ac0: 844ff0ef jal ra,b04 <_sbrk> + 1ac4: 57fd li a5,-1 + 1ac6: 00f51763 bne a0,a5,1ad4 <_sbrk_r+0x22> + 1aca: 83c18793 addi a5,gp,-1988 # 200000bc + 1ace: 439c lw a5,0(a5) + 1ad0: c391 beqz a5,1ad4 <_sbrk_r+0x22> + 1ad2: c01c sw a5,0(s0) + 1ad4: 40b2 lw ra,12(sp) + 1ad6: 4422 lw s0,8(sp) + 1ad8: 0141 addi sp,sp,16 + 1ada: 8082 ret + +00001adc <__sread>: + 1adc: 1141 addi sp,sp,-16 + 1ade: c422 sw s0,8(sp) + 1ae0: 842e mv s0,a1 + 1ae2: 00e59583 lh a1,14(a1) + 1ae6: c606 sw ra,12(sp) + 1ae8: 2279 jal 1c76 <_read_r> + 1aea: 00054963 bltz a0,1afc <__sread+0x20> + 1aee: 487c lw a5,84(s0) + 1af0: 97aa add a5,a5,a0 + 1af2: c87c sw a5,84(s0) + 1af4: 40b2 lw ra,12(sp) + 1af6: 4422 lw s0,8(sp) + 1af8: 0141 addi sp,sp,16 + 1afa: 8082 ret + 1afc: 245e lhu a5,12(s0) + 1afe: 777d lui a4,0xfffff + 1b00: 177d addi a4,a4,-1 + 1b02: 8ff9 and a5,a5,a4 + 1b04: a45e sh a5,12(s0) + 1b06: b7fd j 1af4 <__sread+0x18> + +00001b08 <__swrite>: + 1b08: 25de lhu a5,12(a1) + 1b0a: 1101 addi sp,sp,-32 + 1b0c: cc22 sw s0,24(sp) + 1b0e: ca26 sw s1,20(sp) + 1b10: c84a sw s2,16(sp) + 1b12: c64e sw s3,12(sp) + 1b14: ce06 sw ra,28(sp) + 1b16: 1007f793 andi a5,a5,256 + 1b1a: 84aa mv s1,a0 + 1b1c: 842e mv s0,a1 + 1b1e: 8932 mv s2,a2 + 1b20: 89b6 mv s3,a3 + 1b22: c791 beqz a5,1b2e <__swrite+0x26> + 1b24: 00e59583 lh a1,14(a1) + 1b28: 4689 li a3,2 + 1b2a: 4601 li a2,0 + 1b2c: 2209 jal 1c2e <_lseek_r> + 1b2e: 245e lhu a5,12(s0) + 1b30: 777d lui a4,0xfffff + 1b32: 177d addi a4,a4,-1 + 1b34: 8ff9 and a5,a5,a4 + 1b36: a45e sh a5,12(s0) + 1b38: 00e41583 lh a1,14(s0) + 1b3c: 4462 lw s0,24(sp) + 1b3e: 40f2 lw ra,28(sp) + 1b40: 86ce mv a3,s3 + 1b42: 864a mv a2,s2 + 1b44: 49b2 lw s3,12(sp) + 1b46: 4942 lw s2,16(sp) + 1b48: 8526 mv a0,s1 + 1b4a: 44d2 lw s1,20(sp) + 1b4c: 6105 addi sp,sp,32 + 1b4e: a825 j 1b86 <_write_r> + +00001b50 <__sseek>: + 1b50: 1141 addi sp,sp,-16 + 1b52: c422 sw s0,8(sp) + 1b54: 842e mv s0,a1 + 1b56: 00e59583 lh a1,14(a1) + 1b5a: c606 sw ra,12(sp) + 1b5c: 28c9 jal 1c2e <_lseek_r> + 1b5e: 57fd li a5,-1 + 1b60: 245a lhu a4,12(s0) + 1b62: 00f51a63 bne a0,a5,1b76 <__sseek+0x26> + 1b66: 77fd lui a5,0xfffff + 1b68: 17fd addi a5,a5,-1 + 1b6a: 8ff9 and a5,a5,a4 + 1b6c: a45e sh a5,12(s0) + 1b6e: 40b2 lw ra,12(sp) + 1b70: 4422 lw s0,8(sp) + 1b72: 0141 addi sp,sp,16 + 1b74: 8082 ret + 1b76: 6785 lui a5,0x1 + 1b78: 8fd9 or a5,a5,a4 + 1b7a: a45e sh a5,12(s0) + 1b7c: c868 sw a0,84(s0) + 1b7e: bfc5 j 1b6e <__sseek+0x1e> + +00001b80 <__sclose>: + 1b80: 00e59583 lh a1,14(a1) + 1b84: a805 j 1bb4 <_close_r> + +00001b86 <_write_r>: + 1b86: 1141 addi sp,sp,-16 + 1b88: c422 sw s0,8(sp) + 1b8a: 842a mv s0,a0 + 1b8c: 852e mv a0,a1 + 1b8e: 85b2 mv a1,a2 + 1b90: 8636 mv a2,a3 + 1b92: 8201ae23 sw zero,-1988(gp) # 200000bc + 1b96: c606 sw ra,12(sp) + 1b98: f33fe0ef jal ra,aca <_write> + 1b9c: 57fd li a5,-1 + 1b9e: 00f51763 bne a0,a5,1bac <_write_r+0x26> + 1ba2: 83c18793 addi a5,gp,-1988 # 200000bc + 1ba6: 439c lw a5,0(a5) + 1ba8: c391 beqz a5,1bac <_write_r+0x26> + 1baa: c01c sw a5,0(s0) + 1bac: 40b2 lw ra,12(sp) + 1bae: 4422 lw s0,8(sp) + 1bb0: 0141 addi sp,sp,16 + 1bb2: 8082 ret + +00001bb4 <_close_r>: + 1bb4: 1141 addi sp,sp,-16 + 1bb6: c422 sw s0,8(sp) + 1bb8: 842a mv s0,a0 + 1bba: 852e mv a0,a1 + 1bbc: 8201ae23 sw zero,-1988(gp) # 200000bc + 1bc0: c606 sw ra,12(sp) + 1bc2: 20c5 jal 1ca2 <_close> + 1bc4: 57fd li a5,-1 + 1bc6: 00f51763 bne a0,a5,1bd4 <_close_r+0x20> + 1bca: 83c18793 addi a5,gp,-1988 # 200000bc + 1bce: 439c lw a5,0(a5) + 1bd0: c391 beqz a5,1bd4 <_close_r+0x20> + 1bd2: c01c sw a5,0(s0) + 1bd4: 40b2 lw ra,12(sp) + 1bd6: 4422 lw s0,8(sp) + 1bd8: 0141 addi sp,sp,16 + 1bda: 8082 ret + +00001bdc <_fstat_r>: + 1bdc: 1141 addi sp,sp,-16 + 1bde: c422 sw s0,8(sp) + 1be0: 842a mv s0,a0 + 1be2: 852e mv a0,a1 + 1be4: 85b2 mv a1,a2 + 1be6: 8201ae23 sw zero,-1988(gp) # 200000bc + 1bea: c606 sw ra,12(sp) + 1bec: 20c9 jal 1cae <_fstat> + 1bee: 57fd li a5,-1 + 1bf0: 00f51763 bne a0,a5,1bfe <_fstat_r+0x22> + 1bf4: 83c18793 addi a5,gp,-1988 # 200000bc + 1bf8: 439c lw a5,0(a5) + 1bfa: c391 beqz a5,1bfe <_fstat_r+0x22> + 1bfc: c01c sw a5,0(s0) + 1bfe: 40b2 lw ra,12(sp) + 1c00: 4422 lw s0,8(sp) + 1c02: 0141 addi sp,sp,16 + 1c04: 8082 ret + +00001c06 <_isatty_r>: + 1c06: 1141 addi sp,sp,-16 + 1c08: c422 sw s0,8(sp) + 1c0a: 842a mv s0,a0 + 1c0c: 852e mv a0,a1 + 1c0e: 8201ae23 sw zero,-1988(gp) # 200000bc + 1c12: c606 sw ra,12(sp) + 1c14: 205d jal 1cba <_isatty> + 1c16: 57fd li a5,-1 + 1c18: 00f51763 bne a0,a5,1c26 <_isatty_r+0x20> + 1c1c: 83c18793 addi a5,gp,-1988 # 200000bc + 1c20: 439c lw a5,0(a5) + 1c22: c391 beqz a5,1c26 <_isatty_r+0x20> + 1c24: c01c sw a5,0(s0) + 1c26: 40b2 lw ra,12(sp) + 1c28: 4422 lw s0,8(sp) + 1c2a: 0141 addi sp,sp,16 + 1c2c: 8082 ret + +00001c2e <_lseek_r>: + 1c2e: 1141 addi sp,sp,-16 + 1c30: c422 sw s0,8(sp) + 1c32: 842a mv s0,a0 + 1c34: 852e mv a0,a1 + 1c36: 85b2 mv a1,a2 + 1c38: 8636 mv a2,a3 + 1c3a: 8201ae23 sw zero,-1988(gp) # 200000bc + 1c3e: c606 sw ra,12(sp) + 1c40: 2059 jal 1cc6 <_lseek> + 1c42: 57fd li a5,-1 + 1c44: 00f51763 bne a0,a5,1c52 <_lseek_r+0x24> + 1c48: 83c18793 addi a5,gp,-1988 # 200000bc + 1c4c: 439c lw a5,0(a5) + 1c4e: c391 beqz a5,1c52 <_lseek_r+0x24> + 1c50: c01c sw a5,0(s0) + 1c52: 40b2 lw ra,12(sp) + 1c54: 4422 lw s0,8(sp) + 1c56: 0141 addi sp,sp,16 + 1c58: 8082 ret + +00001c5a : + 1c5a: 0ff5f593 andi a1,a1,255 + 1c5e: 962a add a2,a2,a0 + 1c60: 00c51463 bne a0,a2,1c68 + 1c64: 4501 li a0,0 + 1c66: 8082 ret + 1c68: 211c lbu a5,0(a0) + 1c6a: feb78ee3 beq a5,a1,1c66 + 1c6e: 0505 addi a0,a0,1 + 1c70: bfc5 j 1c60 + +00001c72 <__malloc_lock>: + 1c72: 8082 ret + +00001c74 <__malloc_unlock>: + 1c74: 8082 ret + +00001c76 <_read_r>: + 1c76: 1141 addi sp,sp,-16 + 1c78: c422 sw s0,8(sp) + 1c7a: 842a mv s0,a0 + 1c7c: 852e mv a0,a1 + 1c7e: 85b2 mv a1,a2 + 1c80: 8636 mv a2,a3 + 1c82: 8201ae23 sw zero,-1988(gp) # 200000bc + 1c86: c606 sw ra,12(sp) + 1c88: 20a9 jal 1cd2 <_read> + 1c8a: 57fd li a5,-1 + 1c8c: 00f51763 bne a0,a5,1c9a <_read_r+0x24> + 1c90: 83c18793 addi a5,gp,-1988 # 200000bc + 1c94: 439c lw a5,0(a5) + 1c96: c391 beqz a5,1c9a <_read_r+0x24> + 1c98: c01c sw a5,0(s0) + 1c9a: 40b2 lw ra,12(sp) + 1c9c: 4422 lw s0,8(sp) + 1c9e: 0141 addi sp,sp,16 + 1ca0: 8082 ret + +00001ca2 <_close>: + 1ca2: 05800793 li a5,88 + 1ca6: 82f1ae23 sw a5,-1988(gp) # 200000bc + 1caa: 557d li a0,-1 + 1cac: 8082 ret + +00001cae <_fstat>: + 1cae: 05800793 li a5,88 + 1cb2: 82f1ae23 sw a5,-1988(gp) # 200000bc + 1cb6: 557d li a0,-1 + 1cb8: 8082 ret + +00001cba <_isatty>: + 1cba: 05800793 li a5,88 + 1cbe: 82f1ae23 sw a5,-1988(gp) # 200000bc + 1cc2: 4501 li a0,0 + 1cc4: 8082 ret + +00001cc6 <_lseek>: + 1cc6: 05800793 li a5,88 + 1cca: 82f1ae23 sw a5,-1988(gp) # 200000bc + 1cce: 557d li a0,-1 + 1cd0: 8082 ret + +00001cd2 <_read>: + 1cd2: 05800793 li a5,88 + 1cd6: 82f1ae23 sw a5,-1988(gp) # 200000bc + 1cda: 557d li a0,-1 + 1cdc: 8082 ret + 1cde: 0000 unimp + 1ce0: 74737953 0x74737953 + 1ce4: 6d65 lui s10,0x19 + 1ce6: 3a6b6c43 fmadd.d fs8,fs6,ft6,ft7,unknown + 1cea: 6425 lui s0,0x9 + 1cec: 0a0d addi s4,s4,3 + 1cee: 0000 unimp + 1cf0: 70696843 fmadd.s fa6,fs2,ft6,fa4,unknown + 1cf4: 4449 li s0,18 + 1cf6: 253a lhu a4,10(a0) + 1cf8: 3830 lbu a2,19(s0) + 1cfa: 0d78 addi a4,sp,668 + 1cfc: 000a c.slli zero,0x2 + 1cfe: 0000 unimp + 1d00: 6854 flw fa3,20(s0) + 1d02: 7369 lui t1,0xffffa + 1d04: 6920 flw fs0,80(a0) + 1d06: 72702073 csrr zero,0x727 + 1d0a: 6e69 lui t3,0x1a + 1d0c: 6674 flw fa3,76(a2) + 1d0e: 6520 flw fs0,72(a0) + 1d10: 6178 flw fa4,68(a0) + 1d12: 706d c.lui zero,0xffffb + 1d14: 656c flw fa1,76(a0) + 1d16: 000d c.nop 3 + +00001d18 <__sf_fake_stderr>: + ... + +00001d38 <__sf_fake_stdin>: + ... + +00001d58 <__sf_fake_stdout>: + ... + 1d78: 2d23 2b30 0020 0000 6c68 004c 6665 4567 #-0+ ...hlL.efgE + 1d88: 4746 0000 3130 3332 3534 3736 3938 4241 FG..0123456789AB + 1d98: 4443 4645 0000 0000 3130 3332 3534 3736 CDEF....01234567 + 1da8: 3938 6261 6463 6665 0000 0000 89abcdef.... diff --git a/ZDBMS/BMS_MC/obj/BMS_MC.map b/ZDBMS/BMS_MC/obj/BMS_MC.map new file mode 100644 index 0000000..7f22a0d --- /dev/null +++ b/ZDBMS/BMS_MC/obj/BMS_MC.map @@ -0,0 +1,2100 @@ +Archive member included to satisfy reference by file (symbol) + +d:/tool/code/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/rv32imacxw/ilp32\libgcc.a(save-restore.o) + ./Peripheral/src/ch32l103_flash.o (__riscv_save_7) +d:/tool/code/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib/rv32imacxw/ilp32\libg_nano.a(lib_a-printf.o) + ./User/main.o (printf) +d:/tool/code/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib/rv32imacxw/ilp32\libg_nano.a(lib_a-puts.o) + ./User/main.o (puts) +d:/tool/code/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib/rv32imacxw/ilp32\libg_nano.a(lib_a-wbuf.o) + d:/tool/code/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib/rv32imacxw/ilp32\libg_nano.a(lib_a-puts.o) (__swbuf_r) +d:/tool/code/mounriver_studio/toolchain/risc-v embedded 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gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib/rv32imacxw/ilp32\libnosys.a(read.o) + +Memory Configuration + +Name Origin Length Attributes +FLASH 0x0000000000000000 0x0000000000010000 xr +RAM 0x0000000020000000 0x0000000000005000 xrw +*default* 0x0000000000000000 0xffffffffffffffff + +Linker script and memory map + +LOAD ./User/ch32l103_it.o +LOAD ./User/main.o +LOAD ./User/system_ch32l103.o +LOAD ./Startup/startup_ch32l103.o +LOAD ./Peripheral/src/ch32l103_adc.o +LOAD ./Peripheral/src/ch32l103_bkp.o +LOAD ./Peripheral/src/ch32l103_can.o +LOAD ./Peripheral/src/ch32l103_crc.o +LOAD ./Peripheral/src/ch32l103_dbgmcu.o +LOAD ./Peripheral/src/ch32l103_dma.o +LOAD ./Peripheral/src/ch32l103_exti.o +LOAD ./Peripheral/src/ch32l103_flash.o +LOAD ./Peripheral/src/ch32l103_gpio.o +LOAD ./Peripheral/src/ch32l103_i2c.o +LOAD ./Peripheral/src/ch32l103_iwdg.o +LOAD ./Peripheral/src/ch32l103_lptim.o +LOAD ./Peripheral/src/ch32l103_misc.o +LOAD ./Peripheral/src/ch32l103_opa.o +LOAD ./Peripheral/src/ch32l103_pwr.o +LOAD ./Peripheral/src/ch32l103_rcc.o +LOAD ./Peripheral/src/ch32l103_rtc.o +LOAD ./Peripheral/src/ch32l103_spi.o +LOAD ./Peripheral/src/ch32l103_tim.o +LOAD ./Peripheral/src/ch32l103_usart.o +LOAD ./Peripheral/src/ch32l103_wwdg.o +LOAD ./Debug/debug.o +LOAD ./Core/core_riscv.o +LOAD d:/tool/code/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/rv32imacxw/ilp32\libgcc.a +LOAD d:/tool/code/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib/rv32imacxw/ilp32\libg_nano.a +LOAD d:/tool/code/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib/rv32imacxw/ilp32\libc_nano.a +LOAD d:/tool/code/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/rv32imacxw/ilp32\libgcc.a +START GROUP +LOAD d:/tool/code/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/rv32imacxw/ilp32\libgcc.a +LOAD d:/tool/code/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib/rv32imacxw/ilp32\libc_nano.a +LOAD d:/tool/code/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib/rv32imacxw/ilp32\libnosys.a +END GROUP +START GROUP +LOAD d:/tool/code/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/rv32imacxw/ilp32\libgcc.a +LOAD d:/tool/code/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib/rv32imacxw/ilp32\libc_nano.a +LOAD d:/tool/code/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib/rv32imacxw/ilp32\libnosys.a +END GROUP + 0x0000000000000800 __stack_size = 0x800 + [!provide] PROVIDE (_stack_size = __stack_size) + +.init 0x0000000000000000 0x4 + 0x0000000000000000 _sinit = . + 0x0000000000000000 . = ALIGN (0x4) + *(SORT_NONE(.init)) + .init 0x0000000000000000 0x4 ./Startup/startup_ch32l103.o + 0x0000000000000000 _start + 0x0000000000000004 . = ALIGN (0x4) + 0x0000000000000004 _einit = . + +.vector 0x0000000000000004 0x13c + *(.vector) + .vector 0x0000000000000004 0x114 ./Startup/startup_ch32l103.o + 0x0000000000000140 . = ALIGN (0x40) + *fill* 0x0000000000000118 0x28 + +.text 0x0000000000000140 0x1c74 + 0x0000000000000140 . = ALIGN (0x4) + *(.text) + .text 0x0000000000000140 0x60 d:/tool/code/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/rv32imacxw/ilp32\libgcc.a(save-restore.o) + 0x0000000000000140 __riscv_save_12 + 0x0000000000000148 __riscv_save_9 + 0x0000000000000148 __riscv_save_11 + 0x0000000000000148 __riscv_save_10 + 0x0000000000000148 __riscv_save_8 + 0x0000000000000156 __riscv_save_4 + 0x0000000000000156 __riscv_save_6 + 0x0000000000000156 __riscv_save_5 + 0x0000000000000156 __riscv_save_7 + 0x0000000000000170 __riscv_save_3 + 0x0000000000000170 __riscv_save_2 + 0x0000000000000170 __riscv_save_1 + 0x0000000000000170 __riscv_save_0 + 0x000000000000017c __riscv_restore_12 + 0x0000000000000180 __riscv_restore_11 + 0x0000000000000180 __riscv_restore_9 + 0x0000000000000180 __riscv_restore_10 + 0x0000000000000180 __riscv_restore_8 + 0x000000000000018a __riscv_restore_5 + 0x000000000000018a __riscv_restore_7 + 0x000000000000018a __riscv_restore_6 + 0x000000000000018a __riscv_restore_4 + 0x0000000000000194 __riscv_restore_3 + 0x0000000000000194 __riscv_restore_0 + 0x0000000000000194 __riscv_restore_2 + 0x0000000000000194 __riscv_restore_1 + .text 0x00000000000001a0 0xa8 d:/tool/code/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib/rv32imacxw/ilp32\libg_nano.a(lib_a-memset.o) + 0x00000000000001a0 memset + *(.text.*) + .text.NMI_Handler + 0x0000000000000248 0x2 ./User/ch32l103_it.o + 0x0000000000000248 NMI_Handler + .text.HardFault_Handler + 0x000000000000024a 0x10 ./User/ch32l103_it.o + 0x000000000000024a HardFault_Handler + .text.startup.main + 0x000000000000025a 0x52 ./User/main.o + 0x000000000000025a main + .text.SystemInit + 0x00000000000002ac 0xba ./User/system_ch32l103.o + 0x00000000000002ac SystemInit + .text.SystemCoreClockUpdate + 0x0000000000000366 0xa4 ./User/system_ch32l103.o + 0x0000000000000366 SystemCoreClockUpdate + .text.vector_handler + 0x000000000000040a 0x2 ./Startup/startup_ch32l103.o + 0x000000000000040a EXTI2_IRQHandler + 0x000000000000040a TIM1_CC_IRQHandler + 0x000000000000040a USBPD_IRQHandler + 0x000000000000040a SysTick_Handler + 0x000000000000040a PVD_IRQHandler + 0x000000000000040a EXTI3_IRQHandler + 0x000000000000040a USBFS_IRQHandler + 0x000000000000040a EXTI0_IRQHandler + 0x000000000000040a I2C2_EV_IRQHandler + 0x000000000000040a LPTIM_IRQHandler + 0x000000000000040a Break_Point_Handler + 0x000000000000040a SPI1_IRQHandler + 0x000000000000040a TAMPER_IRQHandler + 0x000000000000040a Ecall_M_Mode_Handler + 0x000000000000040a DMA1_Channel4_IRQHandler + 0x000000000000040a USART3_IRQHandler + 0x000000000000040a RTC_IRQHandler + 0x000000000000040a DMA1_Channel7_IRQHandler + 0x000000000000040a CAN1_RX1_IRQHandler + 0x000000000000040a USBPDWakeUp_IRQHandler + 0x000000000000040a TIM4_IRQHandler + 0x000000000000040a I2C1_EV_IRQHandler + 0x000000000000040a USART4_IRQHandler + 0x000000000000040a DMA1_Channel6_IRQHandler + 0x000000000000040a TIM3_IRQHandler + 0x000000000000040a RCC_IRQHandler + 0x000000000000040a TIM1_TRG_COM_IRQHandler + 0x000000000000040a DMA1_Channel1_IRQHandler + 0x000000000000040a EXTI15_10_IRQHandler + 0x000000000000040a ADC_IRQHandler + 0x000000000000040a DMA1_Channel8_IRQHandler + 0x000000000000040a EXTI9_5_IRQHandler + 0x000000000000040a SPI2_IRQHandler + 0x000000000000040a DMA1_Channel5_IRQHandler + 0x000000000000040a EXTI4_IRQHandler + 0x000000000000040a USB_LP_CAN1_RX0_IRQHandler + 0x000000000000040a USB_HP_CAN1_TX_IRQHandler + 0x000000000000040a CMPWakeUp_IRQHandler + 0x000000000000040a DMA1_Channel3_IRQHandler + 0x000000000000040a TIM1_UP_IRQHandler + 0x000000000000040a LPTIMWakeUp_IRQHandler + 0x000000000000040a WWDG_IRQHandler + 0x000000000000040a Ecall_U_Mode_Handler + 0x000000000000040a TIM2_IRQHandler + 0x000000000000040a SW_Handler + 0x000000000000040a TIM1_BRK_IRQHandler + 0x000000000000040a OPA_IRQHandler + 0x000000000000040a EXTI1_IRQHandler + 0x000000000000040a RTCAlarm_IRQHandler + 0x000000000000040a USART2_IRQHandler + 0x000000000000040a I2C2_ER_IRQHandler + 0x000000000000040a DMA1_Channel2_IRQHandler + 0x000000000000040a CAN1_SCE_IRQHandler + 0x000000000000040a FLASH_IRQHandler + 0x000000000000040a USBFSWakeUp_IRQHandler + 0x000000000000040a USART1_IRQHandler + 0x000000000000040a I2C1_ER_IRQHandler + .text.handle_reset + 0x000000000000040c 0x86 ./Startup/startup_ch32l103.o + 0x000000000000040c handle_reset + .text.DBGMCU_GetCHIPID + 0x0000000000000492 0x6 ./Peripheral/src/ch32l103_dbgmcu.o + 0x0000000000000492 DBGMCU_GetCHIPID + .text.GPIO_Init + 0x0000000000000498 0xc0 ./Peripheral/src/ch32l103_gpio.o + 0x0000000000000498 GPIO_Init + .text.GPIO_PinRemapConfig + 0x0000000000000558 0x12c ./Peripheral/src/ch32l103_gpio.o + 0x0000000000000558 GPIO_PinRemapConfig + .text.GPIO_IPD_Unused + 0x0000000000000684 0x1c2 ./Peripheral/src/ch32l103_gpio.o + 0x0000000000000684 GPIO_IPD_Unused + .text.NVIC_PriorityGroupConfig + 0x0000000000000846 0x6 ./Peripheral/src/ch32l103_misc.o + 0x0000000000000846 NVIC_PriorityGroupConfig + .text.RCC_GetClocksFreq + 0x000000000000084c 0xd6 ./Peripheral/src/ch32l103_rcc.o + 0x000000000000084c RCC_GetClocksFreq + .text.RCC_PB2PeriphClockCmd + 0x0000000000000922 0x1e ./Peripheral/src/ch32l103_rcc.o + 0x0000000000000922 RCC_PB2PeriphClockCmd + .text.USART_Init + 0x0000000000000940 0xba ./Peripheral/src/ch32l103_usart.o + 0x0000000000000940 USART_Init + .text.USART_Cmd + 0x00000000000009fa 0x16 ./Peripheral/src/ch32l103_usart.o + 0x00000000000009fa USART_Cmd + .text.USART_SendData + 0x0000000000000a10 0x8 ./Peripheral/src/ch32l103_usart.o + 0x0000000000000a10 USART_SendData + .text.USART_GetFlagStatus + 0x0000000000000a18 0xa ./Peripheral/src/ch32l103_usart.o + 0x0000000000000a18 USART_GetFlagStatus + .text.Delay_Init + 0x0000000000000a22 0x20 ./Debug/debug.o + 0x0000000000000a22 Delay_Init + .text.Delay_Ms + 0x0000000000000a42 0x36 ./Debug/debug.o + 0x0000000000000a42 Delay_Ms + .text.USART_Printf_Init + 0x0000000000000a78 0x52 ./Debug/debug.o + 0x0000000000000a78 USART_Printf_Init + .text._write 0x0000000000000aca 0x3a ./Debug/debug.o + 0x0000000000000aca _write + .text._sbrk 0x0000000000000b04 0x26 ./Debug/debug.o + 0x0000000000000b04 _sbrk + .text.printf 0x0000000000000b2a 0x40 d:/tool/code/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib/rv32imacxw/ilp32\libg_nano.a(lib_a-printf.o) + 0x0000000000000b2a iprintf + 0x0000000000000b2a printf + .text._puts_r 0x0000000000000b6a 0xd4 d:/tool/code/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib/rv32imacxw/ilp32\libg_nano.a(lib_a-puts.o) + 0x0000000000000b6a _puts_r + .text.puts 0x0000000000000c3e 0xa d:/tool/code/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib/rv32imacxw/ilp32\libg_nano.a(lib_a-puts.o) + 0x0000000000000c3e puts + .text.__swbuf_r + 0x0000000000000c48 0xbc d:/tool/code/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib/rv32imacxw/ilp32\libg_nano.a(lib_a-wbuf.o) + 0x0000000000000c48 __swbuf_r + .text.__swsetup_r + 0x0000000000000d04 0xfc d:/tool/code/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib/rv32imacxw/ilp32\libg_nano.a(lib_a-wsetup.o) + 0x0000000000000d04 __swsetup_r + .text.__sflush_r + 0x0000000000000e00 0x130 d:/tool/code/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib/rv32imacxw/ilp32\libg_nano.a(lib_a-fflush.o) + 0x0000000000000e00 __sflush_r + .text._fflush_r + 0x0000000000000f30 0x64 d:/tool/code/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib/rv32imacxw/ilp32\libg_nano.a(lib_a-fflush.o) + 0x0000000000000f30 _fflush_r + .text.std 0x0000000000000f94 0x66 d:/tool/code/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib/rv32imacxw/ilp32\libg_nano.a(lib_a-findfp.o) + .text._cleanup_r + 0x0000000000000ffa 0xa d:/tool/code/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib/rv32imacxw/ilp32\libg_nano.a(lib_a-findfp.o) + 0x0000000000000ffa _cleanup_r + .text.__sfmoreglue + 0x0000000000001004 0x46 d:/tool/code/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib/rv32imacxw/ilp32\libg_nano.a(lib_a-findfp.o) + 0x0000000000001004 __sfmoreglue + .text.__sinit 0x000000000000104a 0x66 d:/tool/code/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib/rv32imacxw/ilp32\libg_nano.a(lib_a-findfp.o) + 0x000000000000104a __sinit + .text.__sfp 0x00000000000010b0 0x9c d:/tool/code/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib/rv32imacxw/ilp32\libg_nano.a(lib_a-findfp.o) + 0x00000000000010b0 __sfp + .text._fwalk_reent + 0x000000000000114c 0x6a d:/tool/code/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib/rv32imacxw/ilp32\libg_nano.a(lib_a-fwalk.o) + 0x000000000000114c _fwalk_reent + .text.__swhatbuf_r + 0x00000000000011b6 0x58 d:/tool/code/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib/rv32imacxw/ilp32\libg_nano.a(lib_a-makebuf.o) + 0x00000000000011b6 __swhatbuf_r + .text.__smakebuf_r + 0x000000000000120e 0x90 d:/tool/code/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib/rv32imacxw/ilp32\libg_nano.a(lib_a-makebuf.o) + 0x000000000000120e __smakebuf_r + .text._free_r 0x000000000000129e 0xa8 d:/tool/code/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib/rv32imacxw/ilp32\libg_nano.a(lib_a-nano-freer.o) + 0x000000000000129e _free_r + .text._malloc_r + 0x0000000000001346 0xd4 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.text._printf_common + 0x0000000000001706 0x10c d:/tool/code/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib/rv32imacxw/ilp32\libg_nano.a(lib_a-nano-vfprintf_i.o) + 0x0000000000001706 _printf_common + .text._printf_i + 0x0000000000001812 0x2a0 d:/tool/code/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib/rv32imacxw/ilp32\libg_nano.a(lib_a-nano-vfprintf_i.o) + 0x0000000000001812 _printf_i + .text._sbrk_r 0x0000000000001ab2 0x2a d:/tool/code/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib/rv32imacxw/ilp32\libg_nano.a(lib_a-sbrkr.o) + 0x0000000000001ab2 _sbrk_r + .text.__sread 0x0000000000001adc 0x2c d:/tool/code/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib/rv32imacxw/ilp32\libg_nano.a(lib_a-stdio.o) + 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0x0000000000001d38 __sf_fake_stdin + .rodata.__sf_fake_stdout + 0x0000000000001d58 0x20 d:/tool/code/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib/rv32imacxw/ilp32\libg_nano.a(lib_a-findfp.o) + 0x0000000000001d58 __sf_fake_stdout + .rodata._vfprintf_r.str1.4 + 0x0000000000001d78 0x13 d:/tool/code/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib/rv32imacxw/ilp32\libg_nano.a(lib_a-nano-vfprintf.o) + *fill* 0x0000000000001d8b 0x1 + .rodata._printf_i.str1.4 + 0x0000000000001d8c 0x28 d:/tool/code/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib/rv32imacxw/ilp32\libg_nano.a(lib_a-nano-vfprintf_i.o) + 0x25 (size before relaxing) + *(.gnu.linkonce.t.*) + 0x0000000000001db4 . = ALIGN (0x4) + +.rela.dyn 0x0000000000001db4 0x0 + .rela.init 0x0000000000001db4 0x0 ./User/ch32l103_it.o + .rela.vector 0x0000000000001db4 0x0 ./User/ch32l103_it.o + .rela.text.handle_reset + 0x0000000000001db4 0x0 ./User/ch32l103_it.o + .rela.text._sbrk + 0x0000000000001db4 0x0 ./User/ch32l103_it.o + .rela.sdata.curbrk.5011 + 0x0000000000001db4 0x0 ./User/ch32l103_it.o + .rela.text._vfprintf_r + 0x0000000000001db4 0x0 ./User/ch32l103_it.o + .rela.text._sbrk_r + 0x0000000000001db4 0x0 ./User/ch32l103_it.o + .rela.text._write_r + 0x0000000000001db4 0x0 ./User/ch32l103_it.o + .rela.text._close_r + 0x0000000000001db4 0x0 ./User/ch32l103_it.o + .rela.text._fstat_r + 0x0000000000001db4 0x0 ./User/ch32l103_it.o + .rela.text._isatty_r + 0x0000000000001db4 0x0 ./User/ch32l103_it.o + .rela.text._lseek_r + 0x0000000000001db4 0x0 ./User/ch32l103_it.o + .rela.text._read_r + 0x0000000000001db4 0x0 ./User/ch32l103_it.o + .rela.text._close + 0x0000000000001db4 0x0 ./User/ch32l103_it.o + .rela.text._fstat + 0x0000000000001db4 0x0 ./User/ch32l103_it.o + .rela.text._isatty + 0x0000000000001db4 0x0 ./User/ch32l103_it.o + .rela.text._lseek + 0x0000000000001db4 0x0 ./User/ch32l103_it.o + .rela.text._read + 0x0000000000001db4 0x0 ./User/ch32l103_it.o + +.fini 0x0000000000001db4 0x0 + *(SORT_NONE(.fini)) + 0x0000000000001db4 . = ALIGN (0x4) + [!provide] PROVIDE (_etext = .) + [!provide] PROVIDE (_eitcm = .) + +.preinit_array 0x0000000000001db4 0x0 + [!provide] PROVIDE (__preinit_array_start = .) + *(.preinit_array) + [!provide] PROVIDE (__preinit_array_end = .) + +.init_array 0x0000000000001db4 0x0 + [!provide] PROVIDE (__init_array_start = .) + *(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)) + *(.init_array EXCLUDE_FILE(*crtend?.o *crtend.o *crtbegin?.o *crtbegin.o) .ctors) + [!provide] PROVIDE (__init_array_end = .) + +.fini_array 0x0000000000001db4 0x0 + [!provide] PROVIDE (__fini_array_start = .) + *(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*)) + *(.fini_array EXCLUDE_FILE(*crtend?.o *crtend.o *crtbegin?.o *crtbegin.o) .dtors) + [!provide] PROVIDE (__fini_array_end = .) + +.ctors + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT_BY_NAME(.ctors.*)) + *(.ctors) + +.dtors + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT_BY_NAME(.dtors.*)) + *(.dtors) + +.dalign 0x0000000020000000 0x0 load address 0x0000000000001db4 + 0x0000000020000000 . = ALIGN (0x4) + 0x0000000020000000 PROVIDE (_data_vma = .) + +.dlalign 0x0000000000001db4 0x0 + 0x0000000000001db4 . = ALIGN (0x4) + 0x0000000000001db4 PROVIDE (_data_lma = .) + +.data 0x0000000020000000 0x98 load address 0x0000000000001db4 + *(.gnu.linkonce.r.*) + *(.data .data.*) + .data.HBPrescTable + 0x0000000020000000 0x10 ./User/system_ch32l103.o + 0x0000000020000000 HBPrescTable + .data.PBHBPrescTable + 0x0000000020000010 0x10 ./Peripheral/src/ch32l103_rcc.o + .data.impure_data + 0x0000000020000020 0x60 d:/tool/code/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib/rv32imacxw/ilp32\libg_nano.a(lib_a-impure.o) + *(.gnu.linkonce.d.*) + 0x0000000020000080 . = ALIGN (0x8) + 0x0000000020000880 PROVIDE (__global_pointer$ = (. + 0x800)) + *(.sdata .sdata.*) + .sdata.SystemCoreClock + 0x0000000020000080 0x4 ./User/system_ch32l103.o + 0x0000000020000080 SystemCoreClock + .sdata.ADCPrescTable + 0x0000000020000084 0x4 ./Peripheral/src/ch32l103_rcc.o + .sdata.curbrk.5011 + 0x0000000020000088 0x4 ./Debug/debug.o + .sdata._impure_ptr + 0x000000002000008c 0x4 d:/tool/code/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib/rv32imacxw/ilp32\libg_nano.a(lib_a-impure.o) + 0x000000002000008c _impure_ptr + *(.sdata2.*) + .sdata2._global_impure_ptr + 0x0000000020000090 0x4 d:/tool/code/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib/rv32imacxw/ilp32\libg_nano.a(lib_a-impure.o) + 0x0000000020000090 _global_impure_ptr + *(.gnu.linkonce.s.*) + 0x0000000020000098 . = ALIGN (0x8) + *fill* 0x0000000020000094 0x4 + *(.srodata.cst16) + *(.srodata.cst8) + *(.srodata.cst4) + *(.srodata.cst2) + *(.srodata .srodata.*) + 0x0000000020000098 . = ALIGN (0x4) + 0x0000000020000098 PROVIDE (_edata = .) + +.bss 0x0000000020000098 0x28 load address 0x0000000000001e4c + 0x0000000020000098 . = ALIGN (0x4) + 0x0000000020000098 PROVIDE (_sbss = .) + *(.sbss*) + .sbss.ADC_Trim + 0x0000000020000098 0x2 ./Peripheral/src/ch32l103_gpio.o + 0x0000000020000098 ADC_Trim + *fill* 0x000000002000009a 0x2 + .sbss.CHIPID 0x000000002000009c 0x4 ./Peripheral/src/ch32l103_gpio.o + 0x000000002000009c CHIPID + .sbss.OPA_Trim + 0x00000000200000a0 0x4 ./Peripheral/src/ch32l103_gpio.o + 0x00000000200000a0 OPA_Trim + .sbss.TS_Val 0x00000000200000a4 0x4 ./Peripheral/src/ch32l103_gpio.o + 0x00000000200000a4 TS_Val + .sbss.USBPD_CFG + 0x00000000200000a8 0x2 ./Peripheral/src/ch32l103_gpio.o + 0x00000000200000a8 USBPD_CFG + *fill* 0x00000000200000aa 0x2 + .sbss.NVIC_Priority_Group + 0x00000000200000ac 0x4 ./Peripheral/src/ch32l103_misc.o + 0x00000000200000ac NVIC_Priority_Group + .sbss.p_ms 0x00000000200000b0 0x2 ./Debug/debug.o + .sbss.p_us 0x00000000200000b2 0x2 ./Debug/debug.o + .sbss.__malloc_free_list + 0x00000000200000b4 0x4 d:/tool/code/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib/rv32imacxw/ilp32\libg_nano.a(lib_a-nano-mallocr.o) + 0x00000000200000b4 __malloc_free_list + .sbss.__malloc_sbrk_start + 0x00000000200000b8 0x4 d:/tool/code/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib/rv32imacxw/ilp32\libg_nano.a(lib_a-nano-mallocr.o) + 0x00000000200000b8 __malloc_sbrk_start + *(.gnu.linkonce.sb.*) + *(.bss*) + *(.gnu.linkonce.b.*) + *(COMMON*) + COMMON 0x00000000200000bc 0x4 d:/tool/code/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib/rv32imacxw/ilp32\libg_nano.a(lib_a-reent.o) + 0x00000000200000bc errno + 0x00000000200000c0 . = ALIGN (0x4) + 0x00000000200000c0 PROVIDE (_ebss = .) + 0x00000000200000c0 PROVIDE (_end = _ebss) + [!provide] PROVIDE (end = .) + +.stack 0x0000000020004800 0x800 + 0x0000000020004800 PROVIDE (_heap_end = .) + 0x0000000020004800 . = ALIGN (0x4) + [!provide] PROVIDE (_susrstack = .) + 0x0000000020005000 . = (. + __stack_size) + *fill* 0x0000000020004800 0x800 + 0x0000000020005000 PROVIDE (_eusrstack = .) +OUTPUT(BMS_MC.elf elf32-littleriscv) + +.debug_info 0x0000000000000000 0x857c + .debug_info 0x0000000000000000 0xc14 ./User/ch32l103_it.o + .debug_info 0x0000000000000c14 0xaa6 ./User/main.o + .debug_info 0x00000000000016ba 0xc31 ./User/system_ch32l103.o + .debug_info 0x00000000000022eb 0x22 ./Startup/startup_ch32l103.o + .debug_info 0x000000000000230d 0xae8 ./Peripheral/src/ch32l103_dbgmcu.o + .debug_info 0x0000000000002df5 0x12e4 ./Peripheral/src/ch32l103_gpio.o + .debug_info 0x00000000000040d9 0xede ./Peripheral/src/ch32l103_misc.o + .debug_info 0x0000000000004fb7 0x12b1 ./Peripheral/src/ch32l103_rcc.o + .debug_info 0x0000000000006268 0x13f0 ./Peripheral/src/ch32l103_usart.o + .debug_info 0x0000000000007658 0xf24 ./Debug/debug.o + +.debug_abbrev 0x0000000000000000 0x197a + .debug_abbrev 0x0000000000000000 0x22c ./User/ch32l103_it.o + .debug_abbrev 0x000000000000022c 0x226 ./User/main.o + .debug_abbrev 0x0000000000000452 0x2b4 ./User/system_ch32l103.o + .debug_abbrev 0x0000000000000706 0x12 ./Startup/startup_ch32l103.o + .debug_abbrev 0x0000000000000718 0x2f7 ./Peripheral/src/ch32l103_dbgmcu.o + .debug_abbrev 0x0000000000000a0f 0x347 ./Peripheral/src/ch32l103_gpio.o + .debug_abbrev 0x0000000000000d56 0x2ea ./Peripheral/src/ch32l103_misc.o + .debug_abbrev 0x0000000000001040 0x351 ./Peripheral/src/ch32l103_rcc.o + .debug_abbrev 0x0000000000001391 0x312 ./Peripheral/src/ch32l103_usart.o + .debug_abbrev 0x00000000000016a3 0x2d7 ./Debug/debug.o + +.debug_aranges 0x0000000000000000 0x430 + .debug_aranges + 0x0000000000000000 0x28 ./User/ch32l103_it.o + .debug_aranges + 0x0000000000000028 0x20 ./User/main.o + .debug_aranges + 0x0000000000000048 0x28 ./User/system_ch32l103.o + .debug_aranges + 0x0000000000000070 0x30 ./Startup/startup_ch32l103.o + .debug_aranges + 0x00000000000000a0 0x48 ./Peripheral/src/ch32l103_dbgmcu.o + .debug_aranges + 0x00000000000000e8 0xa8 ./Peripheral/src/ch32l103_gpio.o + .debug_aranges + 0x0000000000000190 0x28 ./Peripheral/src/ch32l103_misc.o + .debug_aranges + 0x00000000000001b8 0x130 ./Peripheral/src/ch32l103_rcc.o + .debug_aranges + 0x00000000000002e8 0x100 ./Peripheral/src/ch32l103_usart.o + .debug_aranges + 0x00000000000003e8 0x48 ./Debug/debug.o + +.debug_ranges 0x0000000000000000 0x3e0 + .debug_ranges 0x0000000000000000 0x18 ./User/ch32l103_it.o + .debug_ranges 0x0000000000000018 0x10 ./User/main.o + .debug_ranges 0x0000000000000028 0x18 ./User/system_ch32l103.o + .debug_ranges 0x0000000000000040 0x28 ./Startup/startup_ch32l103.o + .debug_ranges 0x0000000000000068 0x50 ./Peripheral/src/ch32l103_dbgmcu.o + .debug_ranges 0x00000000000000b8 0x98 ./Peripheral/src/ch32l103_gpio.o + .debug_ranges 0x0000000000000150 0x48 ./Peripheral/src/ch32l103_misc.o + .debug_ranges 0x0000000000000198 0x120 ./Peripheral/src/ch32l103_rcc.o + .debug_ranges 0x00000000000002b8 0xf0 ./Peripheral/src/ch32l103_usart.o + .debug_ranges 0x00000000000003a8 0x38 ./Debug/debug.o + +.debug_line 0x0000000000000000 0x4fb9 + .debug_line 0x0000000000000000 0x2a1 ./User/ch32l103_it.o + .debug_line 0x00000000000002a1 0x31e ./User/main.o + .debug_line 0x00000000000005bf 0x600 ./User/system_ch32l103.o + .debug_line 0x0000000000000bbf 0x11e ./Startup/startup_ch32l103.o + .debug_line 0x0000000000000cdd 0x37a ./Peripheral/src/ch32l103_dbgmcu.o + .debug_line 0x0000000000001057 0x1391 ./Peripheral/src/ch32l103_gpio.o + .debug_line 0x00000000000023e8 0x3c0 ./Peripheral/src/ch32l103_misc.o + .debug_line 0x00000000000027a8 0x11c4 ./Peripheral/src/ch32l103_rcc.o + .debug_line 0x000000000000396c 0xf8a ./Peripheral/src/ch32l103_usart.o + .debug_line 0x00000000000048f6 0x6c3 ./Debug/debug.o + +.debug_str 0x0000000000000000 0x18fc + .debug_str 0x0000000000000000 0x62e ./User/ch32l103_it.o + 0x6a7 (size before relaxing) + .debug_str 0x000000000000062e 0x90 ./User/main.o + 0x639 (size before relaxing) + .debug_str 0x00000000000006be 0x102 ./User/system_ch32l103.o + 0x6f9 (size before relaxing) + .debug_str 0x00000000000007c0 0x2a ./Startup/startup_ch32l103.o + 0x4a (size before relaxing) + .debug_str 0x00000000000007ea 0xa6 ./Peripheral/src/ch32l103_dbgmcu.o + 0x668 (size before relaxing) + .debug_str 0x0000000000000890 0x39e ./Peripheral/src/ch32l103_gpio.o + 0x98c (size before relaxing) + .debug_str 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+################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +C_SRCS += \ +../Debug/debug.c + +OBJS += \ +./Debug/debug.o + +C_DEPS += \ +./Debug/debug.d + + +# Each subdirectory must supply rules for building sources it contributes +Debug/%.o: ../Debug/%.c + @ @ riscv-none-embed-gcc -march=rv32imacxw -mabi=ilp32 -msmall-data-limit=8 -msave-restore -Os -fmessage-length=0 -fsigned-char -ffunction-sections -fdata-sections -fno-common -Wunused -Wuninitialized -g -I"E:\Y\MounRiver\ZDBMS\BMS_MC\Debug" -I"E:\Y\MounRiver\ZDBMS\BMS_MC\Core" -I"E:\Y\MounRiver\ZDBMS\BMS_MC\User" -I"E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc" -std=gnu99 -MMD -MP -MF"$(@:%.o=%.d)" -MT"$(@)" -c -o "$@" "$<" + @ @ + diff --git a/ZDBMS/BMS_MC/obj/Peripheral/src/ch32l103_adc.d b/ZDBMS/BMS_MC/obj/Peripheral/src/ch32l103_adc.d new file mode 100644 index 0000000..154b98a --- /dev/null +++ b/ZDBMS/BMS_MC/obj/Peripheral/src/ch32l103_adc.d @@ -0,0 +1,85 @@ +Peripheral/src/ch32l103_adc.o: ../Peripheral/src/ch32l103_adc.c \ + E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_adc.h \ + E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103.h \ + E:\Y\MounRiver\ZDBMS\BMS_MC\Core/core_riscv.h \ + E:\Y\MounRiver\ZDBMS\BMS_MC\User/system_ch32l103.h \ + E:\Y\MounRiver\ZDBMS\BMS_MC\User/ch32l103_conf.h \ + E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_bkp.h \ + E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_can.h \ + E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_crc.h \ + E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_dbgmcu.h \ + E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_dma.h \ + E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_exti.h \ + E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_flash.h \ + E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_gpio.h \ + E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_i2c.h \ + E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_iwdg.h \ + E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_pwr.h \ + E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_rcc.h \ + E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_rtc.h \ + E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_spi.h \ + E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_tim.h \ + E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_usart.h \ + E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_wwdg.h \ + E:\Y\MounRiver\ZDBMS\BMS_MC\User/ch32l103_it.h \ + E:\Y\MounRiver\ZDBMS\BMS_MC\Debug/debug.h \ + E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103.h \ + E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_misc.h \ + E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_lptim.h \ + E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_opa.h + +E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_adc.h: + +E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103.h: + +E:\Y\MounRiver\ZDBMS\BMS_MC\Core/core_riscv.h: + +E:\Y\MounRiver\ZDBMS\BMS_MC\User/system_ch32l103.h: + +E:\Y\MounRiver\ZDBMS\BMS_MC\User/ch32l103_conf.h: + +E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_bkp.h: + +E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_can.h: + +E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_crc.h: + +E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_dbgmcu.h: + +E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_dma.h: + +E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_exti.h: + +E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_flash.h: + +E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_gpio.h: + +E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_i2c.h: + +E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_iwdg.h: + +E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_pwr.h: + +E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_rcc.h: + +E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_rtc.h: + +E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_spi.h: + +E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_tim.h: + +E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_usart.h: + +E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_wwdg.h: + +E:\Y\MounRiver\ZDBMS\BMS_MC\User/ch32l103_it.h: + +E:\Y\MounRiver\ZDBMS\BMS_MC\Debug/debug.h: + +E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103.h: + +E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_misc.h: + +E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_lptim.h: + +E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_opa.h: diff --git a/ZDBMS/BMS_MC/obj/Peripheral/src/ch32l103_adc.o b/ZDBMS/BMS_MC/obj/Peripheral/src/ch32l103_adc.o new file mode 100644 index 0000000000000000000000000000000000000000..501998b098aa7be4754d1b930978c7b372b08511 GIT binary patch literal 98632 zcmeFacVJaT+CM($-rN)j5E2Lh0!9KP0)gBlLTC%A1SNowAYkwsl1qrBUiKFD!X>qg59<3;wrK>_&uL_X3oq#gpKgZ`}_X!9wq1VdFGjCo_Xe( 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E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_dbgmcu.h \ + E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_dma.h \ + E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_exti.h \ + E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_flash.h \ + E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_gpio.h \ + E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_i2c.h \ + E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_iwdg.h \ + E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_pwr.h \ + E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_rcc.h \ + E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_rtc.h \ + E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_spi.h \ + E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_tim.h \ + E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_usart.h \ + E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_wwdg.h \ + E:\Y\MounRiver\ZDBMS\BMS_MC\User/ch32l103_it.h \ + E:\Y\MounRiver\ZDBMS\BMS_MC\Debug/debug.h \ + E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103.h \ + E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_misc.h \ + E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_lptim.h \ + E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_opa.h + +E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_can.h: + +E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103.h: + +E:\Y\MounRiver\ZDBMS\BMS_MC\Core/core_riscv.h: + +E:\Y\MounRiver\ZDBMS\BMS_MC\User/system_ch32l103.h: + +E:\Y\MounRiver\ZDBMS\BMS_MC\User/ch32l103_conf.h: + +E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_adc.h: + +E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_bkp.h: + +E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_crc.h: + +E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_dbgmcu.h: + +E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_dma.h: + +E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_exti.h: + +E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_flash.h: + +E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_gpio.h: + +E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_i2c.h: + +E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_iwdg.h: + +E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_pwr.h: + +E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_rcc.h: + +E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_rtc.h: + +E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_spi.h: + +E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_tim.h: + +E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_usart.h: + +E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_wwdg.h: + +E:\Y\MounRiver\ZDBMS\BMS_MC\User/ch32l103_it.h: + +E:\Y\MounRiver\ZDBMS\BMS_MC\Debug/debug.h: + +E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103.h: + +E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_misc.h: + +E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_lptim.h: + +E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_opa.h: diff --git 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b/ZDBMS/BMS_MC/obj/Peripheral/src/ch32l103_dma.d @@ -0,0 +1,85 @@ +Peripheral/src/ch32l103_dma.o: ../Peripheral/src/ch32l103_dma.c \ + E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_dma.h \ + E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103.h \ + E:\Y\MounRiver\ZDBMS\BMS_MC\Core/core_riscv.h \ + E:\Y\MounRiver\ZDBMS\BMS_MC\User/system_ch32l103.h \ + E:\Y\MounRiver\ZDBMS\BMS_MC\User/ch32l103_conf.h \ + E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_adc.h \ + E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_bkp.h \ + E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_can.h \ + E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_crc.h \ + E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_dbgmcu.h \ + E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_exti.h \ + E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_flash.h \ + E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_gpio.h \ + E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_i2c.h \ + E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_iwdg.h \ + E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_pwr.h \ + E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_rcc.h \ + E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_rtc.h \ + E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_spi.h \ + E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_tim.h \ + E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_usart.h \ + E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_wwdg.h \ + E:\Y\MounRiver\ZDBMS\BMS_MC\User/ch32l103_it.h \ + E:\Y\MounRiver\ZDBMS\BMS_MC\Debug/debug.h \ + E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103.h \ + E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_misc.h \ + E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_lptim.h \ + E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_opa.h + +E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_dma.h: + +E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103.h: + 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E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_flash.h \ + E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103.h \ + E:\Y\MounRiver\ZDBMS\BMS_MC\Core/core_riscv.h \ + E:\Y\MounRiver\ZDBMS\BMS_MC\User/system_ch32l103.h \ + E:\Y\MounRiver\ZDBMS\BMS_MC\User/ch32l103_conf.h \ + E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_adc.h \ + E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_bkp.h \ + E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_can.h \ + E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_crc.h \ + E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_dbgmcu.h \ + E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_dma.h \ + E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_exti.h \ + E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_gpio.h \ + E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_i2c.h \ + E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_iwdg.h \ + E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_pwr.h \ + E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_rcc.h \ + E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_rtc.h \ + E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_spi.h \ + E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_tim.h \ + E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_usart.h \ + E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_wwdg.h \ + E:\Y\MounRiver\ZDBMS\BMS_MC\User/ch32l103_it.h \ + E:\Y\MounRiver\ZDBMS\BMS_MC\Debug/debug.h \ + E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103.h \ + E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_misc.h \ + E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_lptim.h \ + E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_opa.h + +E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_flash.h: + +E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103.h: + +E:\Y\MounRiver\ZDBMS\BMS_MC\Core/core_riscv.h: + +E:\Y\MounRiver\ZDBMS\BMS_MC\User/system_ch32l103.h: + +E:\Y\MounRiver\ZDBMS\BMS_MC\User/ch32l103_conf.h: + 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E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103.h \ + E:\Y\MounRiver\ZDBMS\BMS_MC\Core/core_riscv.h \ + E:\Y\MounRiver\ZDBMS\BMS_MC\User/system_ch32l103.h \ + E:\Y\MounRiver\ZDBMS\BMS_MC\User/ch32l103_conf.h \ + E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_adc.h \ + E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_bkp.h \ + E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_can.h \ + E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_crc.h \ + E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_dbgmcu.h \ + E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_dma.h \ + E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_exti.h \ + E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_flash.h \ + E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_i2c.h \ + E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_iwdg.h \ + E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_pwr.h \ + E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_rcc.h \ + E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_rtc.h \ + E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_spi.h \ + E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_tim.h \ + E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_usart.h \ + E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_wwdg.h \ + E:\Y\MounRiver\ZDBMS\BMS_MC\User/ch32l103_it.h \ + E:\Y\MounRiver\ZDBMS\BMS_MC\Debug/debug.h \ + E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103.h \ + E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_misc.h \ + E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_lptim.h \ + E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_opa.h + +E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_gpio.h: + +E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103.h: + +E:\Y\MounRiver\ZDBMS\BMS_MC\Core/core_riscv.h: + +E:\Y\MounRiver\ZDBMS\BMS_MC\User/system_ch32l103.h: + +E:\Y\MounRiver\ZDBMS\BMS_MC\User/ch32l103_conf.h: + +E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_adc.h: + +E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_bkp.h: + +E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_can.h: + +E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_crc.h: + +E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_dbgmcu.h: + +E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_dma.h: + +E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_exti.h: + +E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_flash.h: + +E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_i2c.h: + +E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_iwdg.h: + +E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_pwr.h: + +E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_rcc.h: + +E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_rtc.h: + +E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_spi.h: + +E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_tim.h: + +E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_usart.h: + +E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_wwdg.h: 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E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_i2c.h \ + E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103.h \ + E:\Y\MounRiver\ZDBMS\BMS_MC\Core/core_riscv.h \ + E:\Y\MounRiver\ZDBMS\BMS_MC\User/system_ch32l103.h \ + E:\Y\MounRiver\ZDBMS\BMS_MC\User/ch32l103_conf.h \ + E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_adc.h \ + E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_bkp.h \ + E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_can.h \ + E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_crc.h \ + E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_dbgmcu.h \ + E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_dma.h \ + E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_exti.h \ + E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_flash.h \ + E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_gpio.h \ + E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_iwdg.h \ + E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_pwr.h \ + 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E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_can.h \ + E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_crc.h \ + E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_dbgmcu.h \ + E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_dma.h \ + E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_exti.h \ + E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_flash.h \ + E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_gpio.h \ + E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_i2c.h \ + E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_iwdg.h \ + E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_pwr.h \ + E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_rcc.h \ + E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_rtc.h \ + E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_spi.h \ + E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_tim.h \ + E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_usart.h \ + E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_wwdg.h \ + E:\Y\MounRiver\ZDBMS\BMS_MC\User/ch32l103_it.h \ + E:\Y\MounRiver\ZDBMS\BMS_MC\Debug/debug.h \ + E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103.h \ + E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_lptim.h \ + E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_opa.h + +E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_misc.h: + +E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103.h: + +E:\Y\MounRiver\ZDBMS\BMS_MC\Core/core_riscv.h: + +E:\Y\MounRiver\ZDBMS\BMS_MC\User/system_ch32l103.h: + +E:\Y\MounRiver\ZDBMS\BMS_MC\User/ch32l103_conf.h: + +E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_adc.h: + +E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_bkp.h: + +E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_can.h: + +E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_crc.h: + +E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_dbgmcu.h: + +E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_dma.h: + +E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_exti.h: + +E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_flash.h: + +E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_gpio.h: + +E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_i2c.h: + +E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_iwdg.h: + +E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_pwr.h: + +E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_rcc.h: + +E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_rtc.h: + +E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_spi.h: + +E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_tim.h: + +E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_usart.h: + +E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_wwdg.h: + +E:\Y\MounRiver\ZDBMS\BMS_MC\User/ch32l103_it.h: + +E:\Y\MounRiver\ZDBMS\BMS_MC\Debug/debug.h: + +E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103.h: + +E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_lptim.h: + +E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_opa.h: diff --git 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HcmV?d00001 diff --git a/ZDBMS/BMS_MC/obj/Peripheral/src/ch32l103_rtc.d b/ZDBMS/BMS_MC/obj/Peripheral/src/ch32l103_rtc.d new file mode 100644 index 0000000..0f01064 --- /dev/null +++ b/ZDBMS/BMS_MC/obj/Peripheral/src/ch32l103_rtc.d @@ -0,0 +1,85 @@ +Peripheral/src/ch32l103_rtc.o: ../Peripheral/src/ch32l103_rtc.c \ + E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_rtc.h \ + E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103.h \ + E:\Y\MounRiver\ZDBMS\BMS_MC\Core/core_riscv.h \ + E:\Y\MounRiver\ZDBMS\BMS_MC\User/system_ch32l103.h \ + E:\Y\MounRiver\ZDBMS\BMS_MC\User/ch32l103_conf.h \ + E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_adc.h \ + E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_bkp.h \ + E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_can.h \ + E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_crc.h \ + E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_dbgmcu.h \ + E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_dma.h \ + E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_exti.h \ + E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_flash.h \ + E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_gpio.h \ + E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_i2c.h \ + E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_iwdg.h \ + E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_pwr.h \ + E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_rcc.h \ + E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_spi.h \ + E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_tim.h \ + E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_usart.h \ + E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_wwdg.h \ + E:\Y\MounRiver\ZDBMS\BMS_MC\User/ch32l103_it.h \ + E:\Y\MounRiver\ZDBMS\BMS_MC\Debug/debug.h \ + E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103.h \ + E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_misc.h \ + E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_lptim.h \ + E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_opa.h + +E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_rtc.h: + +E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103.h: + +E:\Y\MounRiver\ZDBMS\BMS_MC\Core/core_riscv.h: + +E:\Y\MounRiver\ZDBMS\BMS_MC\User/system_ch32l103.h: + +E:\Y\MounRiver\ZDBMS\BMS_MC\User/ch32l103_conf.h: + +E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_adc.h: + +E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_bkp.h: + +E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_can.h: + +E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_crc.h: + +E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_dbgmcu.h: + +E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_dma.h: + +E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_exti.h: + +E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_flash.h: + +E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_gpio.h: + +E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_i2c.h: + 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E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_crc.h \ + E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_dbgmcu.h \ + E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_dma.h \ + E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_exti.h \ + E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_flash.h \ + E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_gpio.h \ + E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_i2c.h \ + E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_iwdg.h \ + E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_pwr.h \ + E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_rcc.h \ + E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_rtc.h \ + E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_spi.h \ + E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_usart.h \ + E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_wwdg.h \ + E:\Y\MounRiver\ZDBMS\BMS_MC\User/ch32l103_it.h \ + E:\Y\MounRiver\ZDBMS\BMS_MC\Debug/debug.h \ + E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103.h \ + E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_misc.h \ + E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_lptim.h \ + E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_opa.h + +E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_tim.h: + +E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103.h: + +E:\Y\MounRiver\ZDBMS\BMS_MC\Core/core_riscv.h: + +E:\Y\MounRiver\ZDBMS\BMS_MC\User/system_ch32l103.h: + +E:\Y\MounRiver\ZDBMS\BMS_MC\User/ch32l103_conf.h: + +E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_adc.h: + +E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_bkp.h: + +E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_can.h: + +E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_crc.h: + +E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_dbgmcu.h: + +E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_dma.h: + +E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_exti.h: + +E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_flash.h: + +E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_gpio.h: + +E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_i2c.h: + +E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_iwdg.h: + +E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_pwr.h: + +E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_rcc.h: + +E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_rtc.h: + +E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_spi.h: + +E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_usart.h: + +E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_wwdg.h: + +E:\Y\MounRiver\ZDBMS\BMS_MC\User/ch32l103_it.h: + +E:\Y\MounRiver\ZDBMS\BMS_MC\Debug/debug.h: + +E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103.h: + +E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_misc.h: + +E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_lptim.h: + +E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_opa.h: diff --git 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variables +C_SRCS += \ +../User/ch32l103_it.c \ +../User/main.c \ +../User/system_ch32l103.c + +OBJS += \ +./User/ch32l103_it.o \ +./User/main.o \ +./User/system_ch32l103.o + +C_DEPS += \ +./User/ch32l103_it.d \ +./User/main.d \ +./User/system_ch32l103.d + + +# Each subdirectory must supply rules for building sources it contributes +User/%.o: ../User/%.c + @ @ riscv-none-embed-gcc -march=rv32imacxw -mabi=ilp32 -msmall-data-limit=8 -msave-restore -Os -fmessage-length=0 -fsigned-char -ffunction-sections -fdata-sections -fno-common -Wunused -Wuninitialized -g -I"E:\Y\MounRiver\ZDBMS\BMS_MC\Debug" -I"E:\Y\MounRiver\ZDBMS\BMS_MC\Core" -I"E:\Y\MounRiver\ZDBMS\BMS_MC\User" -I"E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc" -std=gnu99 -MMD -MP -MF"$(@:%.o=%.d)" -MT"$(@)" -c -o "$@" "$<" + @ @ + diff --git a/ZDBMS/BMS_MC/obj/User/system_ch32l103.d b/ZDBMS/BMS_MC/obj/User/system_ch32l103.d new file mode 100644 index 0000000..875fc0f --- /dev/null +++ b/ZDBMS/BMS_MC/obj/User/system_ch32l103.d @@ -0,0 +1,85 @@ +User/system_ch32l103.o: ../User/system_ch32l103.c \ + E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103.h \ + E:\Y\MounRiver\ZDBMS\BMS_MC\Core/core_riscv.h \ + E:\Y\MounRiver\ZDBMS\BMS_MC\User/system_ch32l103.h \ + E:\Y\MounRiver\ZDBMS\BMS_MC\User/ch32l103_conf.h \ + E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_adc.h \ + E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103.h \ + E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_bkp.h \ + E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_can.h \ + E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_crc.h \ + E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_dbgmcu.h \ + E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_dma.h \ + E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_exti.h \ + E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_flash.h \ + E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_gpio.h \ + E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_i2c.h \ + E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_iwdg.h \ + E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_pwr.h \ + E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_rcc.h \ + E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_rtc.h \ + E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_spi.h \ + E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_tim.h \ + E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_usart.h \ + E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_wwdg.h \ + E:\Y\MounRiver\ZDBMS\BMS_MC\User/ch32l103_it.h \ + E:\Y\MounRiver\ZDBMS\BMS_MC\Debug/debug.h \ + E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_misc.h \ + E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_lptim.h \ + E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_opa.h + +E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103.h: + +E:\Y\MounRiver\ZDBMS\BMS_MC\Core/core_riscv.h: + +E:\Y\MounRiver\ZDBMS\BMS_MC\User/system_ch32l103.h: + +E:\Y\MounRiver\ZDBMS\BMS_MC\User/ch32l103_conf.h: + +E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_adc.h: + +E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103.h: + +E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_bkp.h: + +E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_can.h: + +E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_crc.h: + +E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_dbgmcu.h: + +E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_dma.h: + +E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_exti.h: + +E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_flash.h: + +E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_gpio.h: + +E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_i2c.h: + +E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_iwdg.h: + +E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_pwr.h: + +E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_rcc.h: + +E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_rtc.h: + +E:\Y\MounRiver\ZDBMS\BMS_MC\Peripheral\inc/ch32l103_spi.h: + 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z&wT;HUzCoSD*KmORh_AnsTxfVbW~BTa{dzRU25hZc3KZr2i?oAO3|x&N!x1$ER} zetC+{u? z)9ywz;!Xlhfe&hKz4Kd)DMu#jh3j;^j{pZ{08MLwtWRR5AnyTS*WYRk5WoKDZ;Ixz z9Y4kqlmRqn!XNjRAO(3(L2&)u0Dslc=nqBG@%;ffCVX?{@9y zBF$rbf7ddsi)l}(F}yz*B-X{_9X$tj7tNOECz*D_2 JZlr0u{{yhdZBzgN literal 0 HcmV?d00001 diff --git a/ZDBMS/BMS_MC/obj/makefile b/ZDBMS/BMS_MC/obj/makefile new file mode 100644 index 0000000..c22c861 --- /dev/null +++ b/ZDBMS/BMS_MC/obj/makefile @@ -0,0 +1,75 @@ +################################################################################ +# MRS Version: 1.9.2 +# 自动生成的文件。不要编辑！ +################################################################################ + +-include ../makefile.init + +RM := rm -rf + +# All of the sources participating in the build are defined here +-include sources.mk +-include User/subdir.mk +-include Startup/subdir.mk +-include Peripheral/src/subdir.mk +-include Debug/subdir.mk +-include Core/subdir.mk +-include subdir.mk +-include objects.mk + +ifneq ($(MAKECMDGOALS),clean) +ifneq ($(strip $(ASM_UPPER_DEPS)),) +-include $(ASM_UPPER_DEPS) +endif +ifneq ($(strip $(ASM_DEPS)),) +-include $(ASM_DEPS) +endif +ifneq ($(strip $(S_DEPS)),) +-include $(S_DEPS) +endif +ifneq ($(strip $(S_UPPER_DEPS)),) +-include $(S_UPPER_DEPS) +endif +ifneq ($(strip $(C_DEPS)),) +-include $(C_DEPS) +endif +endif + +-include ../makefile.defs + +# Add inputs and outputs from these tool invocations to the build variables +SECONDARY_FLASH += \ +BMS_MC.hex \ + +SECONDARY_LIST += \ +BMS_MC.lst \ + +SECONDARY_SIZE += \ +BMS_MC.siz \ + + +# 所有目标 +all: BMS_MC.elf secondary-outputs + +# 工具调用 +BMS_MC.elf: $(OBJS) $(USER_OBJS) + @ @ riscv-none-embed-gcc -march=rv32imacxw -mabi=ilp32 -msmall-data-limit=8 -msave-restore -Os -fmessage-length=0 -fsigned-char -ffunction-sections -fdata-sections -fno-common -Wunused -Wuninitialized -g -T "E:\Y\MounRiver\ZDBMS\BMS_MC\Ld\Link.ld" -nostartfiles -Xlinker --gc-sections -Wl,-Map,"BMS_MC.map" --specs=nano.specs --specs=nosys.specs -o "BMS_MC.elf" $(OBJS) $(USER_OBJS) $(LIBS) + @ @ +BMS_MC.hex: BMS_MC.elf + @ riscv-none-embed-objcopy -O ihex "BMS_MC.elf" "BMS_MC.hex" + @ @ +BMS_MC.lst: BMS_MC.elf + @ riscv-none-embed-objdump --all-headers --demangle --disassemble -M xw "BMS_MC.elf" > "BMS_MC.lst" + @ @ +BMS_MC.siz: BMS_MC.elf + @ riscv-none-embed-size --format=berkeley "BMS_MC.elf" + @ @ +# 其他目标 +clean: + -$(RM) $(ASM_UPPER_DEPS)$(OBJS)$(SECONDARY_FLASH)$(SECONDARY_LIST)$(SECONDARY_SIZE)$(ASM_DEPS)$(S_DEPS)$(S_UPPER_DEPS)$(C_DEPS) BMS_MC.elf + -@ +secondary-outputs: $(SECONDARY_FLASH) $(SECONDARY_LIST) $(SECONDARY_SIZE) + +.PHONY: all clean dependents + +-include ../makefile.targets diff --git a/ZDBMS/BMS_MC/obj/objects.mk b/ZDBMS/BMS_MC/obj/objects.mk new file mode 100644 index 0000000..cccee33 --- /dev/null +++ b/ZDBMS/BMS_MC/obj/objects.mk @@ -0,0 +1,9 @@ +################################################################################ +# MRS Version: 1.9.2 +# 自动生成的文件。不要编辑！ +################################################################################ + +USER_OBJS := + +LIBS := + diff --git a/ZDBMS/BMS_MC/obj/sources.mk b/ZDBMS/BMS_MC/obj/sources.mk new file mode 100644 index 0000000..81b4ecc --- /dev/null +++ b/ZDBMS/BMS_MC/obj/sources.mk @@ -0,0 +1,31 @@ +################################################################################ +# MRS Version: 1.9.2 +# 自动生成的文件。不要编辑！ +################################################################################ + +ELF_SRCS := +OBJ_SRCS := +S_SRCS := +ASM_UPPER_SRCS := +ASM_SRCS := +C_SRCS := +S_UPPER_SRCS := +O_SRCS := +ASM_UPPER_DEPS := +OBJS := +SECONDARY_FLASH := +SECONDARY_LIST := +SECONDARY_SIZE := +ASM_DEPS := +S_DEPS := +S_UPPER_DEPS := +C_DEPS := + +# Every subdirectory with source files must be described here +SUBDIRS := \ +Core \ +Debug \ +Peripheral/src \ +Startup \ +User \ +