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取消硬件过压与短路
2025-02-22 08:59:29 +00:00
C51 COMPILER V9.01 DATAFLASH 02/22/2025 15:36:16 PAGE 1
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C51 COMPILER V9.01, COMPILATION OF MODULE DATAFLASH
OBJECT MODULE PLACED IN .\output\DataFlash.obj
COMPILER INVOKED BY: D:\Tool\Keil\C51\BIN\C51.EXE code_dataflash\DataFlash.c LARGE OPTIMIZE(7,SIZE) BROWSE INCDIR(.\head
-er) DEBUG OBJECTEXTEND PRINT(.\output\DataFlash.lst) OBJECT(.\output\DataFlash.obj)
line level source
1 /********************************************************************************
2 Copyright (C), Sinowealth Electronic. Ltd.
3 Author: Sino
4 Version: V0.0
5 Date: 2014/09/10
6 History:
7 V0.0 2014/09/10 Preliminary
8 ********************************************************************************/
9 //*** <<< use Configuration Wizard in Context Menu >>> ***
10 #define _RAM_CHECK_DATA 0x5A
11 #define _FLASH_CHECK_DATA 0x5AA5
12
13 // <h> ϵͳ<CFB5><CDB3>Ϣ<EFBFBD><CFA2>(SubClassID=0x00 length=48)
14 // <h> <20><><EFBFBD>ذ<EFBFBD><D8B0><EFBFBD>Ϣ<EFBFBD><CFA2>E2uiPackConfigMap<61><70>
15 // <q> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
16 #define _EPCM_LOAD_LOCK 0 //BIT15; 0<><30><EFBFBD><EFBFBD>ʹ<EFBFBD>ܸ<EFBFBD><DCB8><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>; 1<><31>ʹ<EFBFBD>ܸ<EFBFBD><DCB8><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
17 // <q> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
18 #define _EPCM_CHARGER_LOCK 0 //BIT14; 0<><30><EFBFBD><EFBFBD>֧<EFBFBD>ֳ<EFBFBD><D6B3><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>; 1<><31>֧<EFBFBD>ֳ<EFBFBD><D6B3><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
19 // <q> <20>¶ȼ<C2B6><C8BC><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
过流保护间隔一定时间自恢复，欠压过压保护还未验证
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20 #define _EPCM_TEMP_NUM 0 //BIT13; 0<><30><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>¶ȼ<C2B6><C8BC><EFBFBD><EFBFBD><EFBFBD> 1<><31><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>¶ȼ<C2B6><C8BC><EFBFBD><EFBFBD><EFBFBD>
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21 // <o> LED<45><44>ʾ<EFBFBD><CABE><EFBFBD><EFBFBD>
22 #define _EPCM_LED_NUM 0 //BIT11~12; δ<><CEB4><EFBFBD><EFBFBD>
23 // <o> <20><>о<EFBFBD><D0BE><EFBFBD><EFBFBD>
修改Flash默认电池串数
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24 #define _EPCM_CELL_NUM 4 //BIT8~10; <20><>о<EFBFBD><D0BE><EFBFBD><EFBFBD><EFBFBD><EFBFBD>6~10<31><30>
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25 // <q> <20><><EFBFBD><EFBFBD>EEPROM<4F><4D><EFBFBD><EFBFBD>
26 #define _EPCM_EEPROM_EN 0 //BIT7; 0<><30><EFBFBD><EFBFBD>ʹ<EFBFBD><CAB9><EFBFBD><EFBFBD><EFBFBD><EFBFBD>EE<45><45><EFBFBD>ݹ<EFBFBD><DDB9><EFBFBD>; 1<><31>ʹ<EFBFBD><CAB9><EFBFBD><EFBFBD><EFBFBD><EFBFBD>EE<45><45><EFBFBD>ݹ<EFBFBD><DDB9><EFBFBD>
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27 // <q> <20>ŵ<EFBFBD><C5B5><EFBFBD><EFBFBD><EFBFBD>MOS<4F><53><EFBFBD><EFBFBD>
28
29 #define _EPCM_OCPM 0 //BIT6; δ<><CEB4><EFBFBD>ã<EFBFBD>0<EFBFBD><30><EFBFBD>ŵ<EFBFBD><C5B5><EFBFBD><EFBFBD><EFBFBD><EFBFBD>رշŵ<D5B7>mos 1<><31><EFBFBD>ŵ<EFBFBD><C5B5><EFBFBD><EFBFBD><EFBFBD><EFBFBD>رճ<D8B1><D5B3>ŵ<EFBFBD>mos<6F><73>
30 // <q> <20><><EFBFBD>߼<EFBFBD><DFBC><EFBFBD>
31 #define _EPCM_CTO_EN 1 //BIT5; 0<><30><EFBFBD><EFBFBD>ʹ<EFBFBD>ܶ<EFBFBD><DCB6>߱<EFBFBD><DFB1><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>; 1<><31>ʹ<EFBFBD>ܶ<EFBFBD><DCB6>߱<EFBFBD><DFB1><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
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32 // <q> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
33 #define _EPCM_PF_EN 1 //BIT4; 0<><30><EFBFBD><EFBFBD>ʹ<EFBFBD>ܶ<EFBFBD><DCB6><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>; 1<><31>ʹ<EFBFBD>ܶ<EFBFBD><DCB6><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
34 // <q> <20><><EFBFBD><EFBFBD>
35 #define _EPCM_BAL_EN 1 //BIT3; 0<><30><EFBFBD><EFBFBD>ʹ<EFBFBD>ܾ<EFBFBD><DCBE>⹦<EFBFBD>ܣ<EFBFBD> 1<><31>ʹ<EFBFBD>ܾ<EFBFBD><DCBE>⹦<EFBFBD><E2B9A6>
36 // <q> <20><><EFBFBD><EFBFBD><EFBFBD>Իָ<D4BB>
37 #define _EPCM_OCRC_EN 1 //BIT2; 0:<3A><>ʹ<EFBFBD>ܹ<EFBFBD><DCB9><EFBFBD><EFBFBD>Իָ<D4BB><D6B8><EFBFBD><EFBFBD>ܣ<EFBFBD> 1<><31>ʹ<EFBFBD>ܹ<EFBFBD><DCB9><EFBFBD><EFBFBD>Իָ<D4BB><D6B8><EFBFBD><EFBFBD><EFBFBD>
38 // <q> Ӳ<><D3B2><EFBFBD><EFBFBD>ѹ<EFBFBD><D1B9><EFBFBD><EFBFBD>
39 #define _EPCM_OV_EN 1 //BIT1; 0:<3A><>ʹ<EFBFBD><CAB9>Ӳ<EFBFBD><D3B2><EFBFBD><EFBFBD>ѹ<EFBFBD><D1B9><EFBFBD>ܣ<EFBFBD> 1<><31>ʹ<EFBFBD><CAB9>Ӳ<EFBFBD><D3B2><EFBFBD><EFBFBD>ѹ<EFBFBD><D1B9><EFBFBD><EFBFBD>
40 // <q> Ӳ<><D3B2><EFBFBD><EFBFBD>·<EFBFBD><C2B7><EFBFBD><EFBFBD>
41 #define _EPCM_SC 1 //BIT0; 0:<3A><>ʹ<EFBFBD><CAB9>Ӳ<EFBFBD><D3B2><EFBFBD><EFBFBD>·<EFBFBD><C2B7><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ܣ<EFBFBD> 1<><31>ʹ<EFBFBD><CAB9>Ӳ<EFBFBD><D3B2><EFBFBD><EFBFBD>·<EFBFBD><C2B7><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
42
43 #define _E2_PACKCONFIGMAP (_EPCM_EEPROM_EN<<15)|(_EPCM_OCPM<<14)|(_EPCM_CTO_EN<<13)|(_EPCM_PF_EN<<12)
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44 |(_EPCM_BAL_EN<<11)|(_EPCM_OCRC_EN<<10)|(_EPCM_OV_EN<<9)\
45 |(_EPCM_SC<<8)|(_EPCM_LOAD_LOCK<<7)|(_EPCM_CHARGER_LOCK<<6)\
46 |(_EPCM_TEMP_NUM<<5)|(_EPCM_LED_NUM<<4)|(_EPCM_CELL_NUM-3) //U16 xdata E2uiPackConfigMap
47
48 // </h>
49
50 // <h>OCV<43><56>ѹ<EFBFBD><D1B9>mV<6D><56>
51 // 0%2.620
52 // <o>10%<25><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ӧ<EFBFBD><D3A6>ѹ
取消硬件过压与短路
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C51 COMPILER V9.01 DATAFLASH 02/22/2025 15:36:16 PAGE 2
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53 #define _E2_VOC10 3150 //U16 xdata VOC10
54 // <o>20%<25><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ӧ<EFBFBD><D3A6>ѹ
55 #define _E2_VOC20 3200 //U16 xdata VOC10
56 // <o>30%<25><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ӧ<EFBFBD><D3A6>ѹ
57 #define _E2_VOC30 3245 //U16 xdata VOC10
58 // <o>40%<25><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ӧ<EFBFBD><D3A6>ѹ
59 #define _E2_VOC40 3290 //U16 xdata VOC10
60 // <o>50%<25><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ӧ<EFBFBD><D3A6>ѹ
61 #define _E2_VOC50 3335 //U16 xdata VOC10
62 // <o>60%<25><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ӧ<EFBFBD><D3A6>ѹ
63 #define _E2_VOC60 3380 //U16 xdata VOC10
64 // <o>70%<25><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ӧ<EFBFBD><D3A6>ѹ
65 #define _E2_VOC70 3425 //U16 xdata VOC10
66 // <o>80%<25><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ӧ<EFBFBD><D3A6>ѹ
67 #define _E2_VOC80 3470 //U16 xdata VOC10
68 // <o>90%<25><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ӧ<EFBFBD><D3A6>ѹ
69 #define _E2_VOC90 3515 //U16 xdata VOC10
70 // <o>100%<25><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ӧ<EFBFBD><D3A6>ѹ
71 #define _E2_VOC100 3560 //U16 xdata VOC10
72 // </h>
73
74 // <h><3E><>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ԥ<EFBFBD><D4A4><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
75 // <o><3E><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>mAh<41><68>
76 #define _E2_ulDesignCapacity 7200 //U32 xdata E2ulDesignCapacity
77 // <o><3E><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>mAh<41><68>
78 #define _E2_ulFCC 6500 //U32 xdata E2ulFCC
79 // <o>ѭ<><D1AD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ֵ
80 #define _E2_ulCycleThreshold 6000 // U32 xdata E2ulCycleThreshold
81 // <o>ѭ<><D1AD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
82 #define _E2_uiCycleCount 0 // U16 xdata E2uiCycleCount
83 // <o><3E><><EFBFBD><EFBFBD>ѧϰ<D1A7><EFBFBD>
84 #define _E2_uiLearnLowTempe 2881 // U16 xdata E2uiLearnLowTempe
85 #define _E2_Reserve 0 // U16 xdata E2Reserve Ԥ<><D4A4>ռλ
86 // <o><3E><><EFBFBD>ŵ<EFBFBD><C5B5><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ֵ
87 #define _E2_siDfilterCur 50 // U16 xdata E2siDfilterCur
88 // <o><3E>͹<EFBFBD><CDB9>ļ<EFBFBD><C4BC><EFBFBD><EFBFBD><EFBFBD>ʱ
89 #define _E2_ucLowPowerDeley 20 // U16 xdata E2ucLowPowerDeley
90 // <o><3E><><EFBFBD>籸<EFBFBD>ݼ<EFBFBD><DDBC><EFBFBD><EFBFBD><EFBFBD>ʱ
91 #define _E2_ucChgBKDelay 1 // U16 xdata E2ucChgBKDelay
92 // <o><3E><><EFBFBD>籸<EFBFBD>ݼ<EFBFBD><DDBC><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
93 #define _E2_siChgBKCur 100 // U16 xdata E2siChgBKCur
94 // <o>RTC<54><43><EFBFBD>ݼ<EFBFBD><DDBC><EFBFBD><EFBFBD><EFBFBD>ʱ
95 #define _E2_ucRTCBKDelay 5 // U16 xdata E2ucRTCBKDelay
96 #define _E2_ucRamCheckFlg0 _RAM_CHECK_DATA // U16 xdata E2ucRamCheckFlg0
97 // </h>
98 // </h>
99
100 // <h><3E>û<EFBFBD><C3BB>Զ<EFBFBD><D4B6><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>(SubClassID=0x01 length=50)
101 // <o><3E><><EFBFBD><EFBFBD><EFBFBD>汾(EXP:0x0106 = V1.06)<0x0000-0xffff>
102 #define _E2_SWVersion 0x0215 // U16 xdata SWVersion
103 // <o>Ӳ<><D3B2><EFBFBD>汾(EXP:0x0106 = V1.06)<0x0000-0xffff>
104 #define _E2_HWVersion 0x0130 // U16 xdata HWVersion
105 // <o><3E>豸ID<0x00-0xff>
106 #define _E2_ID 0x00 // U8 xdata ID
107 // <s.12><3E><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
108 #define _E2_MNFName "Cerlink" // U8 xdata MNFName[12]
109 // <o> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ڣ<EFBFBD>exp<78><70>0x20230404=2023.04.04<EFBFBD><EFBFBD><0x00000000-0xffffffff>
110 #define _E2_MNFDate 0x20250212 // U32 xdata MNFDate
111 // <o><3E><><EFBFBD>к<EFBFBD><0x0000-0xffff>
112 #define _E2_SerialNum 0x0000 // U16 xdata SerialNum
113 // <s.12><3E>豸<EFBFBD><E8B1B8><EFBFBD><EFBFBD>
114 #define _E2_DeviceName "SH39F003" // U8 xdata DeviceName[12]
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C51 COMPILER V9.01 DATAFLASH 02/22/2025 15:36:16 PAGE 3
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115 // <s.4><3E><>о<EFBFBD><D0BE><EFBFBD><EFBFBD>
116 #define _E2_DeviceChem "LION" // U8 xdata DeviceChem[12]
117 // <o><3E><>о<EFBFBD><D0BE>ѧID<0x0000-0xffff>
118 #define _E2_ChemID 0x0000 // U16 xdata ChemID
119 #define _E2_ucRamCheckFlg1 _RAM_CHECK_DATA // U8 xdata E2ucRamCheckFlg2
120 // </h>
121
122 // <h><3E><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>(SubClassID=0x02 length=18)
123 // <o><3E><>ѹ<EFBFBD><D1B9><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ֵ
124 #define _E2_uiOVvol 3600 // U16 xdata E2uiOVvol
125 // <o><3E><>ѹ<EFBFBD><D1B9><EFBFBD><EFBFBD><EFBFBD>ָ<EFBFBD><D6B8><EFBFBD>ֵ
126 #define _E2_uiOVRvol 3400 // U16 xdata E2uiOVRvol
127 // <o><3E><>ѹ<EFBFBD><D1B9><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʱS
128 #define _E2_ucDelayOV 2 // U8 xdata E2ucDelayOV
129 // <o><3E><>ѹ<EFBFBD><D1B9><EFBFBD><EFBFBD><EFBFBD>ָ<EFBFBD><D6B8><EFBFBD>ʱS
130 #define _E2_ucDelayOVR 2 // U8 xdata E2ucDelayOVR
131 // <o><3E><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ֹ<EFBFBD><D6B9>ѹ(mV)
132 #define _E2_uiChgEndVol 3500 // U16 xdata E2uiChgEndVol
133 // <o><3E><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ֹ<EFBFBD><D6B9><EFBFBD><EFBFBD>(mA)
134 #define _E2_siChgEndCurr 100 // S16 xdata E2siChgEndCurr
135 // <o><3E><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ֹ<EFBFBD><D6B9>ʱ(S)
136 #define _E2_ucChgEndDelay 5 // U8 xdata E2ucChgEndDelay
137 // <o><3E><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ֵ
138 #define _E2_slOCCvol 25000 // U32 xdata E2slOCCvol
139 // <o><3E><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʱS
140 #define _E2_ucDelayOCC 2 // U8 xdata E2ucDelayOCC
141 // <o><3E><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ָ<EFBFBD><D6B8><EFBFBD>ʱS
142 #define _E2_ucDelayOCCR 60 // U8 xdata E2ucDelayOCCR
143 #define _E2_ucRamCheckFlg2 _RAM_CHECK_DATA // U8 xdata E2ucRamCheckFlg2
144 // </h>
145
146 // <h><3E>ŵ<EFBFBD><C5B5><EFBFBD><EFBFBD><EFBFBD>(SubClassID=0x03 length=21)
147 // <o>Ƿѹ<C7B7><D1B9><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ѹ
148 #define _E2_uiUVvol 2600 // U16 xdata E2uiUVvol
149 // <o>Ƿѹ<C7B7><D1B9><EFBFBD><EFBFBD><EFBFBD>ָ<EFBFBD><D6B8><EFBFBD>ѹ
150 #define _E2_uiUVRvol 3000 // U16 xdata E2uiUVRvol
151 // <o>Ƿѹ<C7B7><D1B9><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʱ
152 #define _E2_ucDelayUV 2 // U8 xdata E2ucDelayUV
153 // <o>Ƿѹ<C7B7><D1B9><EFBFBD><EFBFBD><EFBFBD>ָ<EFBFBD><D6B8><EFBFBD>ʱ
154 #define _E2_ucDelayUVR 2 // U8 xdata E2ucDelayUVR
155 // <o><3E>ŵ<EFBFBD><C5B5><EFBFBD>ֹ<EFBFBD><D6B9>ʱ(S)
156 #define _E2_ucDsgEndDelay 5 // U8 xdata E2ucDsgEndDelay
157 // <o><3E>ŵ<EFBFBD><C5B5><EFBFBD>ֹ<EFBFBD><D6B9>ѹ(mV)
158 #define _E2_uiDsgEndVol 2700 // U16 xdata E2uiDsgEndVol
159 // <o><3E>ŵ<EFBFBD><C5B5><EFBFBD><EFBFBD><EFBFBD>1<EFBFBD><31><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ֵ
160 #define _E2_uiOCDvol -20000 //U32 xdata E2uiOCDvol
161 // <o><3E>ŵ<EFBFBD><C5B5><EFBFBD><EFBFBD><EFBFBD>1<EFBFBD><31><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʱs
162 #define _E2_ucDelayOCD 2 //U8 xdata E2ucDelayOCD
163 // <o><3E>ŵ<EFBFBD><C5B5><EFBFBD><EFBFBD><EFBFBD>2<EFBFBD><32><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ֵ
164 #define _E2_slOCD2vol -40000 // S32 xdata E2slOCD2vol
165 // <o><3E>ŵ<EFBFBD><C5B5><EFBFBD><EFBFBD><EFBFBD>2<EFBFBD><32><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʱ125mS
166 #define _E2_ucDelayOCD2 2 //U8 xdata E2ucDelayOCD2
167 // <o><3E><><EFBFBD><EFBFBD><EFBFBD>Ƴ<EFBFBD><C6B3><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʱ
168 #define _E2_ucDelayLoadR 4 //U8 xdata E2ucDelayLoadR
169 #define _E2_ucRamCheckFlg3 _RAM_CHECK_DATA // U8 xdata E2ucRamCheckFlg3
170 // </h>
171
172 // <h><3E>ŵ<EFBFBD>PWM<57><4D><EFBFBD><EFBFBD>(SubClassID=0x05 length=5)
173 // <o>PWMƵ<4D><C6B5>(Hz)
174 #define _E2_DSG1PWMFreq 4000 // U16 xdata DSG1PWMFreq
175 // <o>PWM<57>͵<EFBFBD>ռ<EFBFBD>ձ<EFBFBD>(%)
176 #define _E2_DSG1PWMRatioL 30 // U8 xdata DSG1PWMRatioL
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177 // <o>PWM<57>ߵ<EFBFBD>ռ<EFBFBD>ձ<EFBFBD>(%)
178 #define _E2_DSG1PWMRatioH 70 // U8 xdata DSG1PWMRatioH
179 #define _E2_ucRamCheckFlg5 _RAM_CHECK_DATA // U8 xdata E2ucRamCheckFlg5
180 // </h>
181
182 // <h><3E><><EFBFBD><EFBFBD><EFBFBD>¶ȱ<C2B6><C8B1><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>(SubClassID=0x06 length=11)
183 // <o><3E><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>±<EFBFBD><C2B1><EFBFBD><EFBFBD><EFBFBD>(_E2_TempOTC=<3D><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>*10+2731)
184 #define _E2_TempOTC 3431 // U16 xdata TempOTC
185 // <o><3E><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>±<EFBFBD><C2B1><EFBFBD><EFBFBD>ͷ<EFBFBD><CDB7><EFBFBD>(_E2_TempOTCR=<3D>ͷ<EFBFBD><CDB7><EFBFBD>*10+2731)
186 #define _E2_TempOTCR 3331 // U16 xdata TempOTCR
187 // <o><3E><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>±<EFBFBD><C2B1><EFBFBD><EFBFBD><EFBFBD>(_E2_TempUTC=<3D><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>*10+2731)
188 #define _E2_TempUTC 2531 // U16 xdata TempUTC
189 // <o><3E><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>±<EFBFBD><C2B1><EFBFBD><EFBFBD>ͷ<EFBFBD><CDB7><EFBFBD>(_E2_TempUTCR=<3D>ͷ<EFBFBD><CDB7><EFBFBD>*10+2731)
190 #define _E2_TempUTCR 2631 // U16 xdata TempUTCR
191 // <o><3E>¶ȱ<C2B6><C8B1><EFBFBD><EFBFBD><EFBFBD>ʱ(s)
192 #define _E2_DelayOTC 3 // U8 xdata DelayOTC
193 // <o><3E>¶ȱ<C2B6><C8B1><EFBFBD><EFBFBD>ͷ<EFBFBD><CDB7><EFBFBD>ʱ(s)
194 #define _E2_DelayOTCR 3 // U8 xdata DelayOTCR
195 #define _E2_ucRamCheckFlg6 _RAM_CHECK_DATA // U8 xdata E2ucRamCheckFlg6
196 // </h>
197
198 // <h><3E>ŵ<EFBFBD><C5B5>¶ȱ<C2B6><C8B1><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>(SubClassID=0x07 length=9)
199 // <o><3E>ŵ<EFBFBD><C5B5><EFBFBD><EFBFBD>±<EFBFBD><C2B1><EFBFBD><EFBFBD><EFBFBD>(_E2_TempOTC=<3D><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>*10+2731)
200 #define _E2_TempOTD 3431 // U16 xdata TempOTD
201 // <o><3E>ŵ<EFBFBD><C5B5><EFBFBD><EFBFBD>±<EFBFBD><C2B1><EFBFBD><EFBFBD>ͷ<EFBFBD><CDB7><EFBFBD>(_E2_TempOTCR=<3D>ͷ<EFBFBD><CDB7><EFBFBD>*10+2731)
202 #define _E2_TempOTDR 3331 // U16 xdata TempOTDR
203 // <o><3E>ŵ<EFBFBD><C5B5><EFBFBD><EFBFBD>±<EFBFBD><C2B1><EFBFBD><EFBFBD><EFBFBD>(_E2_TempUTC=<3D><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>*10+2731)
204 #define _E2_TempUTD 2531 // U16 xdata TempUTD
205 // <o><3E>ŵ<EFBFBD><C5B5><EFBFBD><EFBFBD>±<EFBFBD><C2B1><EFBFBD><EFBFBD>ͷ<EFBFBD><CDB7><EFBFBD>(_E2_TempUTCR=<3D>ͷ<EFBFBD><CDB7><EFBFBD>*10+2731)
206 #define _E2_TempUTDR 2631 // U16 xdata TempUTDR
207 #define _E2_ucRamCheckFlg7 _RAM_CHECK_DATA // U8 xdata E2ucRamCheckFlg6
208 // </h>
209
210 // <h>ƽ<><C6BD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>(SubClassID=0x08 length=8)
211 // <o>ƽ<><C6BD><EFBFBD><EFBFBD>ѹ(mV)
212 #define _E2_BalanceVol 3000 // U16 xdata BalanceVol
213 // <o>ƽ<><C6BD>ѹ<EFBFBD><D1B9>(mV)
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214 #define _E2_BalanceVolDiff 50 // U16 xdata BalanceVolDiff
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215 // <o>ƽ<><C6BD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>(mA)
216 #define _E2_BalCurrent 100 // S16 xdata BalCurrent
217 // <o>ƽ<><C6BD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʱ(S)
218 #define _E2_BalanceDelay 2 // U8 xdata BalanceDelay
219 #define _E2_ucRamCheckFlg8 _RAM_CHECK_DATA // U8 xdata E2ucRamCheckFlg8
220 // </h>
221
222 // <h><3E><><EFBFBD><EFBFBD>ͳ<EFBFBD>Ʋ<EFBFBD><C6B2><EFBFBD>(SubClassID=0x09 length=17)
223 // <o><3E><><EFBFBD><EFBFBD><EFBFBD>ٷֱ<D9B7>SOC(%)
224 #define _E2_ucSOC 100 // U8 xdata E2ucSOC
225 // <o>ʣ<><CAA3><EFBFBD><EFBFBD><EFBFBD><EFBFBD>E2ulDfRC(mAh)
226 #define _E2_ulDfRC 3000 // U32 xdata E2ulLastFCC
227 // <o><3E>ŵ<EFBFBD><C5B5><EFBFBD>ֹ<EFBFBD><D6B9><EFBFBD><EFBFBD>
228 #define _E2_slDsgEndCurr -5000 // U32 xdata E2slDsgEndCurr
229 // <o><3E>ŵ<EFBFBD>ѭ<EFBFBD><D1AD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ֵ
230 #define _E2_ulCycleThresholdCount 0 // U32 xdata E2ulCycleThresholdCount
231 // <o><3E>ϴθ<CFB4><CEB8><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʱ<EFBFBD><CAB1>ѭ<EFBFBD><D1AD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
232 #define _E2_uiLastCCount 0 // U16 xdata E2uiLastCCount
233 // <o><3E>ŵ<EFBFBD><C5B5><EFBFBD>ֹ<EFBFBD><D6B9>־
234 #define _E2_ucDsgEndFlg 0 //U8 xdata E2ucDsgEndFlg
235 #define _E2_ucRamCheckFlg9 _RAM_CHECK_DATA // U8 xdata E2ucRamCheckFlg9
236 // </h>
237
238 // <h>AFE<46><45><EFBFBD><EFBFBD>(SubClassID=0x0A length=4)
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239 // <o><3E><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
240 #define _E2_AFEProtectConfig 0x74 // U8 xdata AFEProtectConfig
241 // <o>Ӳ<><D3B2><EFBFBD><EFBFBD>ѹ<EFBFBD><D1B9><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ֵ
242 #define _E2_AFEOVvol 4400 // U16 xdata AFEOVvol
243 #define _E2_ucRamCheckFlgA _RAM_CHECK_DATA // U8 xdata E2ucRamCheckFlgA
244 // </h>
245
246 // <h>У׼<D0A3><D7BC><EFBFBD><EFBFBD>(SubClassID=0x0B length=12)
247 // <o><3E><>ѹУ׼<D0A3><D7BC><EFBFBD><EFBFBD>
248 #define _E2_uiVPackGain 2594 // U16 xdata E2uiVPackGain
249 // <o><3E><><EFBFBD><EFBFBD>У׼<D0A3><D7BC><EFBFBD><EFBFBD>
250 #define _E2_siCadcGain -89 // S16 xdata E2siCadcGain
251 // <o><3E><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ư
252 #define _E2_siCadcOffset 4 // S16 xdata E2siCadcOffset
253 // <o><3E>ⲿ<EFBFBD><EFBFBD><C2B6><EFBFBD>Ư(TS0)
254 #define _E2_siTS0Offset 0 // S16 xdata E2siTS0Offset
255 // <o><3E>ⲿ<EFBFBD><EFBFBD><C2B6><EFBFBD>Ư(TS1)
256 #define _E2_siTS1Offset 0 // S16 xdata E2siTS1Offset
257 // <o>У׼<D0A3><D7BC><EFBFBD><EFBFBD>Ԥ<EFBFBD><D4A4>
258 #define _E2_ucCalibrated 0 // U8 xdata E2ucCalibrated
259 #define _E2_ucRamCheckFlgB _RAM_CHECK_DATA // U8 xdata E2ucRamCheckFlgB
260 // </h>
261
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262 /*********************************************************************************************************
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263 /*********************************************************************************************************
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264 /*********************************************************************************************************
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265 /*********************************************************************************************************
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266 /*********************************************************************************************************
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267 /*********************************************************************************************************
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268 /*********************************************************************************************************
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269 /*********************************************************************************************************
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270 /*********************************************************************************************************
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271 /*********************************************************************************************************
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272 /*********************************************************************************************************
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273 /*********************************************************************************************************
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274
275 struct DataFlashStu
276 {
277 //ϵͳ<CFB5><CDB3>Ϣ<EFBFBD><CFA2><EFBFBD><EFBFBD>ʼ SubClassID=0x00 length=48
278 unsigned int E2uiPackConfigMap;
279 unsigned int E2uiVOC[10];
280 unsigned long E2ulDesignCapacity;
281 unsigned long E2ulFCC;
282 unsigned long E2ulCycleThreshold;
283 unsigned int E2uiCycleCount;
284 unsigned int E2uiLearnLowTempe;
285 unsigned int E2Reserve;
286 signed int E2siDfilterCur;
287 unsigned char E2ucLowPowerDeley;
288 unsigned char E2ucChgBKDelay;
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289 unsigned int E2siChgBKCur;
290 unsigned char E2ucRTCBKDelay;
291 unsigned char E2ucRamCheckFlg0;
292
293 //<2F>û<EFBFBD><C3BB>Զ<EFBFBD><D4B6><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʼ SubClassID=0x01 langth=50
294 unsigned int E2uiSWVersion;
295 unsigned int E2uiHWVersion;
296 unsigned char E2ucID;
297 unsigned char E2ucMNFName[12];
298 unsigned long E2ulMNFDate;
299 unsigned int E2uiSerialNum;
300 unsigned char E2ucDeviceName[12];
301 unsigned char E2ucDeviceChem[12];
302 unsigned int E2uiChemID;
303 unsigned char E2ucRamCheckFlg1;
304
305 //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʼ SubClassID=0x02 langth=18
306 unsigned int E2uiOVvol;
307 unsigned int E2uiOVRvol;
308 unsigned char E2ucOVDelay;
309 unsigned char E2ucOVRDelay;
310 unsigned int E2uiChgEndVol0;
311 signed int E2siChgEndCurr0;
312 unsigned char E2ucChgEndDelay0;
313 signed long E2slOCCvol;
314 unsigned char E2ucDelayOCC;
315 unsigned char E2ucDelayOCCR;
316 unsigned char E2ucRamCheckFlg2;
317
318 //<2F>ŵ<EFBFBD><C5B5><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʼ SubClassID=0x03 langth=21
319 unsigned int E2uiUVvol;
320 unsigned int E2uiUVRvol;
321 unsigned char E2ucDelayUV;
322 unsigned char E2ucDelayUVR;
323 unsigned int E2uiDsgEndVol;
324 unsigned char E2ucDsgEndDelay;
325 signed long E2uiOCDvol;
326 unsigned char E2ucDelayOCD;
327 signed long E2slOCD2vol;
328 unsigned char E2ucDelayOCD2;
329 unsigned char E2ucDelayLoadR;
330 unsigned char E2ucRamCheckFlg3;
331
332 //<2F>ŵ<EFBFBD>PWM<57><4D><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʼ SubClassID=0x05 langth=5
333 unsigned int DSG1PWMFreq;
334 unsigned char DSG1PWMRatioL;
335 unsigned char DSG1PWMRatioH;
336 unsigned char E2ucRamCheckFlg5;
337
338
339 //<2F><><EFBFBD><EFBFBD><EFBFBD>¶ȱ<C2B6><C8B1><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʼ SubClassID=0x06 langth=11
340 unsigned int TempOTC;
341 unsigned int TempOTCR;
342 unsigned int TempUTC;
343 unsigned int TempUTCR;
344 unsigned char DelayOTC;
345 unsigned char DelayOTCR;
346 unsigned char E2ucRamCheckFlg6;
347
348 //<2F>ŵ<EFBFBD><C5B5>¶ȱ<C2B6><C8B1><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʼ SubClassID=0x07 langth=9
349 unsigned int TempOTD;
350 unsigned int TempOTDR;
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351 unsigned int TempUTD;
352 unsigned int TempUTDR;
353 unsigned char E2ucRamCheckFlg7;
354
355 //ƽ<><C6BD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʼ SubClassID=0x08 langth=8
356 unsigned int BalanceVol;
357 unsigned int BalanceVolDiff;
358 unsigned int BalCurrent;
359 unsigned char BalanceDelay;
360 unsigned char E2ucRamCheckFlg8;
361
362 //<2F><><EFBFBD><EFBFBD>ͳ<EFBFBD><CDB3> SubClassID=0x09 length=17
363 unsigned char E2ucSOC;
364 unsigned long E2ulDfRC;
365 signed long E2slDsgEndCurr;
366 unsigned long E2ulCycleThresholdCount;
367 unsigned int E2uiLastCCount;
368 unsigned char E2ucDsgEndFlg;
369 unsigned char E2ucRamCheckFlg9;
370
371 //AFE<46><45><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʼ SubClassID=0x0A length=4
372 unsigned char AFEProtectConfig;
373 unsigned int AFEOVvol;
374 unsigned char E2ucRamCheckFlgA;
375
376 //У׼<D0A3><D7BC><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʼ SubClassID=0x0B length=12
377 unsigned int E2uiVPackGain;
378 signed int E2siCadcGain;
379 unsigned int E2siCadcOffset;
380 unsigned int E2siTS0Offset;
381 unsigned int E2siTS1Offset;
382 unsigned char E2ucCalibrated;
383 unsigned char E2ucRamCheckFlgB;
384 };
385
386 union DataFlashUn
387 {
388 struct DataFlashStu DataFlashStu0; /*һ<><D2BB>Ҫ<EFBFBD><D2AA><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ṹ<EFBFBD><E1B9B9><EFBFBD>ٶ<EFBFBD><D9B6><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>*/
389 unsigned char reversed[510];
390 };
391
392 struct DataFlashStr
393 {
394 union DataFlashUn DataFlashUnRaw;
395 unsigned int FlashCheck1;
396 union DataFlashUn DataFlashUnBak;
397 unsigned int FlashCheck2;
398 };
399
400 struct DataFlashStr code dataflashstr =
401 {
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402 /*********************************************************************************************************
-********/
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403 //<2F><><EFBFBD><EFBFBD>A<EFBFBD><41>
404 /*********************************************************************************************************
-********/
405 //ϵͳ<CFB5><CDB3>Ϣ<EFBFBD><CFA2><EFBFBD><EFBFBD>ʼ SubClassID=0x00 length=48
406 {
407 _E2_PACKCONFIGMAP, //U16 xdata E2uiPackConfigMap
408 _E2_VOC10, //U16 xdata VOC10
409 _E2_VOC20, //U16 xdata VOC20
410 _E2_VOC30, //U16 xdata VOC30
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411 _E2_VOC40, //U16 xdata VOC40
412 _E2_VOC50, //U16 xdata VOC50
413 _E2_VOC60, //U16 xdata VOC60
414 _E2_VOC70, //U16 xdata VOC70
415 _E2_VOC80, //U16 xdata VOC80
416 _E2_VOC90, //U16 xdata VOC90
417 _E2_VOC100, //U16 xdata VOC100
418 _E2_ulDesignCapacity, // U32 xdata E2ulDesignCapacity
419 _E2_ulFCC, // U32 xdata E2ulFCC
420 _E2_ulCycleThreshold, // U32 xdata E2uiCycleThreshold
421 _E2_uiCycleCount, // U16 xdata E2uiCycleCount
422 _E2_uiLearnLowTempe, // U16 xdata E2uiLearnLowTempe
423 _E2_Reserve, // U16 xdata E2Reserve
424 _E2_siDfilterCur, // S16 xdata E2siDfilterCur
425 _E2_ucLowPowerDeley, // U8 xdata E2ucLowPowerDeley
426 _E2_ucChgBKDelay, // U8 xdata E2ucChgBKDelay
427 _E2_siChgBKCur, // S16 xdata E2siChgBKCur
428 _E2_ucRTCBKDelay, // U8 xdata E2ucRTCBKDelay
429 _E2_ucRamCheckFlg0, // U8 xdata E2ucRamCheckFlg0
430
431
432 //<2F>û<EFBFBD><C3BB>Զ<EFBFBD><D4B6><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʼ SubClassID=0x01 length=50
433 _E2_SWVersion, //U16 xdata SWVersion
434 _E2_HWVersion, //U16 xdata HWVersion
435 _E2_ID, //U8 xdata ID
436 _E2_MNFName, //U8 xdata MNFName[12]
437 _E2_MNFDate, //U32 xdata MNFDate
438 _E2_SerialNum, //U16 xdata SerialNum
439 _E2_DeviceName, //U8 xdata DeviceName[12]
440 _E2_DeviceChem, //U8 xdata DeviceChem[12]
441 _E2_ChemID, //U16 xdata ChemID
442 _E2_ucRamCheckFlg1, //U8 xdata E2ucRamCheckFlg1
443
444 //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʼ SubClassID=0x02 length=18
445 _E2_uiOVvol, //U16 xdata E2uiOVvol
446 _E2_uiOVRvol, //U16 xdata E2uiOVRvol
447 _E2_ucDelayOV, //U8 xdata E2ucDelayOV
448 _E2_ucDelayOVR, //U8 xdata E2ucDelayOVR
449 _E2_uiChgEndVol,
450 _E2_siChgEndCurr,
451 _E2_ucChgEndDelay,
452 _E2_slOCCvol, //S32 xdata E2slOCCvol
453 _E2_ucDelayOCC, //U8 xdata E2ucDelayOCC
454 _E2_ucDelayOCCR, //U8 xdata E2ucDelayOCCR
455 _E2_ucRamCheckFlg2, //U8 xdata E2ucRamCheckFlg2
456
457 //<2F>ŵ<EFBFBD><C5B5><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʼ SubClassID=0x03 langth=21
458 _E2_uiUVvol, //U16 xdata E2uiUVvol
459 _E2_uiUVRvol, //U16 xdata E2uiUVRvol
460 _E2_ucDelayUV, //U8 xdata E2ucDelayUV
461 _E2_ucDelayUVR, //U8 xdata E2ucDelayUVR
462 _E2_uiDsgEndVol,
463 _E2_ucDsgEndDelay,
464 _E2_uiOCDvol, //S32 xdata E2uiOCDvol
465 _E2_ucDelayOCD, //U8 xdata E2ucDelayOCD
466 _E2_slOCD2vol, //S32 xdata E2slOCD2vol
467 _E2_ucDelayOCD2, //U8 xdata E2ucDelayOCD2
468 _E2_ucDelayLoadR, //U8 xdata E2ucDelayLoadR
469 _E2_ucRamCheckFlg3, //U8 xdata E2ucRamCheckFlg3
470
471
472 //<2F>ŵ<EFBFBD>PWM<57><4D><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʼ SubClassID=0x05 langth=5
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473 _E2_DSG1PWMFreq, //U16 xdata DSG1PWMFreq
474 _E2_DSG1PWMRatioL, //U8 xdata DSG1PWMRatioL
475 _E2_DSG1PWMRatioH, //U8 xdata DSG1PWMRatioH
476 _E2_ucRamCheckFlg5, //U8 xdata E2ucRamCheckFlg5
477
478 //<2F><><EFBFBD><EFBFBD><EFBFBD>¶ȱ<C2B6><C8B1><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʼ SubClassID=0x06 langth=11
479 _E2_TempOTC, //U16 xdata TempOTC
480 _E2_TempOTCR, //U16 xdata TempOTCR
481 _E2_TempUTC, //U16 xdata TempUTC
482 _E2_TempUTCR, //U16 xdata TempUTCR
483 _E2_DelayOTC, //U8 xdata DelayOTC
484 _E2_DelayOTCR, //U8 xdata DelayOTCR
485 _E2_ucRamCheckFlg6, //U8 xdata E2ucRamCheckFlg6
486
487 //<2F>ŵ<EFBFBD><C5B5>¶ȱ<C2B6><C8B1><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʼ SubClassID=0x07 langth=9
488 _E2_TempOTD, //U16 xdata TempOTD
489 _E2_TempOTDR, //U16 xdata TempOTDR
490 _E2_TempUTD, //U16 xdata TempUTD
491 _E2_TempUTDR, //U16 xdata TempUTDR
492 _E2_ucRamCheckFlg7, //U8 xdata E2ucRamCheckFlg7
493
494 //ƽ<><C6BD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʼ SubClassID=0x08 langth=8
495 _E2_BalanceVol, // U16 xdata BalanceVol
496 _E2_BalanceVolDiff, // U16 xdata BalanceVolDiff
497 _E2_BalCurrent, // S16 xdata BalCurrent
498 _E2_BalanceDelay, // U8 xdata BalanceDelay
499 _E2_ucRamCheckFlg8, // U8 xdata E2ucRamCheckFlg8
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500
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501 //<2F><><EFBFBD><EFBFBD>ͳ<EFBFBD><CDB3> SubClassID=0x09 langth=17
502
503 _E2_ucSOC, //U8 xdata E2ucSOC
504
505 _E2_ulDfRC, //U32 xdata E2ulLastFCC
506
507 _E2_slDsgEndCurr, //U32 xdata E2slDsgEndCurr
508 _E2_ulCycleThresholdCount, //U32 xdata E2ulCycleThresholdCount
509 _E2_uiLastCCount,
510 _E2_ucDsgEndFlg, //U8 xdata E2ucDsgEndFlg
511 _E2_ucRamCheckFlg9, //U8 xdata E2ucRamCheckFlg9
512
513 //AFE<46><45><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʼ SubClassID=0x0A langth=4
514 _E2_AFEProtectConfig, // U8 xdata AFEProtectConfig
515 _E2_AFEOVvol, // U16 xdata AFEOVvol
516 _E2_ucRamCheckFlgA, // U8 xdata E2ucRamCheckFlgA
517
518 //У׼<D0A3><D7BC><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʼ SubClassID=0x0B langth=12
519 _E2_uiVPackGain, //U16 xdata E2uiVPackGain
520 _E2_siCadcGain, //S16 xdata E2siCadcGain
521 _E2_siCadcOffset, //S16 xdata E2siCadcOffset
522 _E2_siTS0Offset, //S16 xdata E2siTS0Offset
523 _E2_siTS1Offset, //S16 xdata E2siTS1Offset
524 _E2_ucCalibrated, //S16 xdata E2ucCalibrated
525 _E2_ucRamCheckFlgB, //U8 xdata E2ucRamCheckFlgB
526 },
527
528 _FLASH_CHECK_DATA, // U16 xdata FlashCheck
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529 /*********************************************************************************************************
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530 //<2F><><EFBFBD><EFBFBD>B<EFBFBD><42>
531 /*********************************************************************************************************
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532 /*********************************************************************************************************
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-********/
533 //ϵͳ<CFB5><CDB3>Ϣ<EFBFBD><CFA2><EFBFBD><EFBFBD>ʼ SubClassID=0x00 langth=48
534 {
535 _E2_PACKCONFIGMAP, //U16 xdata E2uiPackConfigMap
536 _E2_VOC10, //U16 xdata VOC10
537 _E2_VOC20, //U16 xdata VOC20
538 _E2_VOC30, //U16 xdata VOC30
539 _E2_VOC40, //U16 xdata VOC40
540 _E2_VOC50, //U16 xdata VOC50
541 _E2_VOC60, //U16 xdata VOC60
542 _E2_VOC70, //U16 xdata VOC70
543 _E2_VOC80, //U16 xdata VOC80
544 _E2_VOC90, //U16 xdata VOC90
545 _E2_VOC100, //U16 xdata VOC100
546 _E2_ulDesignCapacity, // U32 xdata E2ulDesignCapacity
547 _E2_ulFCC, // U32 xdata E2ulFCC
548 _E2_ulCycleThreshold, // U32 xdata E2uiCycleThreshold
549 _E2_uiCycleCount, // U16 xdata E2uiCycleCount
550 _E2_uiLearnLowTempe, // U16 xdata E2uiLearnLowTempe
551 _E2_Reserve, // U16 xdata E2Reserve
552 _E2_siDfilterCur, // S16 xdata E2siDfilterCur
553 _E2_ucLowPowerDeley, // U8 xdata E2ucLowPowerDeley
554 _E2_ucChgBKDelay, // U8 xdata E2ucChgBKDelay
555 _E2_siChgBKCur, // S16 xdata E2siChgBKCur
556 _E2_ucRTCBKDelay, // U8 xdata E2ucRTCBKDelay
557 _E2_ucRamCheckFlg0, // U8 xdata E2ucRamCheckFlg0
558
559
560 //<2F>û<EFBFBD><C3BB>Զ<EFBFBD><D4B6><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʼ SubClassID=0x01 length=50
561 _E2_SWVersion, //U16 xdata SWVersion
562 _E2_HWVersion, //U16 xdata HWVersion
563 _E2_ID, //U8 xdata ID
564 _E2_MNFName, //U8 xdata MNFName[12]
565 _E2_MNFDate, //U32 xdata MNFDate
566 _E2_SerialNum, //U16 xdata SerialNum
567 _E2_DeviceName, //U8 xdata DeviceName[12]
568 _E2_DeviceChem, //U8 xdata DeviceChem[12]
569 _E2_ChemID, //U16 xdata ChemID
570 _E2_ucRamCheckFlg1, //U8 xdata E2ucRamCheckFlg1
571
572 //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʼ SubClassID=0x02 length=18
573 _E2_uiOVvol, //U16 xdata E2uiOVvol
574 _E2_uiOVRvol, //U16 xdata E2uiOVRvol
575 _E2_ucDelayOV, //U8 xdata E2ucDelayOV
576 _E2_ucDelayOVR, //U8 xdata E2ucDelayOVR
577 _E2_uiChgEndVol,
578 _E2_siChgEndCurr,
579 _E2_ucChgEndDelay,
580 _E2_slOCCvol, //S32 xdata E2slOCCvol
581 _E2_ucDelayOCC, //U8 xdata E2ucDelayOCC
582 _E2_ucDelayOCCR, //U8 xdata E2ucDelayOCCR
583 _E2_ucRamCheckFlg2, //U8 xdata E2ucRamCheckFlg2
584
585 //<2F>ŵ<EFBFBD><C5B5><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʼ SubClassID=0x03 langth=21
586 _E2_uiUVvol, //U16 xdata E2uiUVvol
587 _E2_uiUVRvol, //U16 xdata E2uiUVRvol
588 _E2_ucDelayUV, //U8 xdata E2ucDelayUV
589 _E2_ucDelayUVR, //U8 xdata E2ucDelayUVR
590 _E2_uiDsgEndVol,
591 _E2_ucDsgEndDelay,
592 _E2_uiOCDvol, //S32 xdata E2uiOCDvol
593 _E2_ucDelayOCD, //U8 xdata E2ucDelayOCD
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C51 COMPILER V9.01 DATAFLASH 02/22/2025 15:36:16 PAGE 11
First commit
2025-02-06 07:35:32 +00:00
no message
2025-02-14 08:59:29 +00:00
594 _E2_slOCD2vol, //S32 xdata E2slOCD2vol
595 _E2_ucDelayOCD2, //U8 xdata E2ucDelayOCD2
596 _E2_ucDelayLoadR, //U8 xdata E2ucDelayLoadR
597 _E2_ucRamCheckFlg3, //U8 xdata E2ucRamCheckFlg3
598
599
600 //<2F>ŵ<EFBFBD>PWM<57><4D><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʼ SubClassID=0x05 langth=5
601 _E2_DSG1PWMFreq, //U16 xdata DSG1PWMFreq
602 _E2_DSG1PWMRatioL, //U8 xdata DSG1PWMRatioL
603 _E2_DSG1PWMRatioH, //U8 xdata DSG1PWMRatioH
604 _E2_ucRamCheckFlg5, //U8 xdata E2ucRamCheckFlg5
605
606 //<2F><><EFBFBD><EFBFBD><EFBFBD>¶ȱ<C2B6><C8B1><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʼ SubClassID=0x06 langth=11
607 _E2_TempOTC, //U16 xdata TempOTC
608 _E2_TempOTCR, //U16 xdata TempOTCR
609 _E2_TempUTC, //U16 xdata TempUTC
610 _E2_TempUTCR, //U16 xdata TempUTCR
611 _E2_DelayOTC, //U8 xdata DelayOTC
612 _E2_DelayOTCR, //U8 xdata DelayOTCR
613 _E2_ucRamCheckFlg6, //U8 xdata E2ucRamCheckFlg6
614
615 //<2F>ŵ<EFBFBD><C5B5>¶ȱ<C2B6><C8B1><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʼ SubClassID=0x07 langth=9
616 _E2_TempOTD, //U16 xdata TempOTD
617 _E2_TempOTDR, //U16 xdata TempOTDR
618 _E2_TempUTD, //U16 xdata TempUTD
619 _E2_TempUTDR, //U16 xdata TempUTDR
620 _E2_ucRamCheckFlg7, //U8 xdata E2ucRamCheckFlg7
621
622 //ƽ<><C6BD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʼ SubClassID=0x08 langth=8
623 _E2_BalanceVol, // U16 xdata BalanceVol
624 _E2_BalanceVolDiff, // U16 xdata BalanceVolDiff
625 _E2_BalCurrent, // S16 xdata BalCurrent
626 _E2_BalanceDelay, // U8 xdata BalanceDelay
627 _E2_ucRamCheckFlg8, // U8 xdata E2ucRamCheckFlg8
628
629 //<2F><><EFBFBD><EFBFBD>ͳ<EFBFBD><CDB3> SubClassID=0x09 langth=17
630 _E2_ucSOC, //U8 xdata E2ucSOC
631 _E2_ulDfRC, //U32 xdata E2ulLastFCC
632 _E2_slDsgEndCurr, //U32 xdata E2slDsgEndCurr
633 _E2_ulCycleThresholdCount, //U32 xdata E2ulCycleThresholdCount
634 _E2_uiLastCCount,
635 _E2_ucDsgEndFlg, //U8 xdata E2ucDsgEndFlg
636
637 _E2_ucRamCheckFlg9, //U8 xdata E2ucRamCheckFlg9
638
639 //AFE<46><45><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʼ SubClassID=0x0A langth=4
640 _E2_AFEProtectConfig, // U8 xdata AFEProtectConfig
641 _E2_AFEOVvol, // U16 xdata AFEOVvol
642 _E2_ucRamCheckFlgA, // U8 xdata E2ucRamCheckFlgA
643
644 //У׼<D0A3><D7BC><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʼ SubClassID=0x0B langth=12
645 _E2_uiVPackGain, //U16 xdata E2uiVPackGain
646 _E2_siCadcGain, //S16 xdata E2siCadcGain
647 _E2_siCadcOffset, //S16 xdata E2siCadcOffset
648 _E2_siTS0Offset, //S16 xdata E2siTS0Offset
649 _E2_siTS1Offset, //S16 xdata E2siTS1Offset
650 _E2_ucCalibrated, //S16 xdata E2ucCalibrated
651 _E2_ucRamCheckFlgB, //U8 xdata E2ucRamCheckFlgB
652 },
653
654 _FLASH_CHECK_DATA, // U16 xdata FlashCheck
655 };
取消硬件过压与短路
2025-02-22 08:59:29 +00:00
C51 COMPILER V9.01 DATAFLASH 02/22/2025 15:36:16 PAGE 12
First commit
2025-02-06 07:35:32 +00:00
no message
2025-02-14 08:59:29 +00:00
656
657 //*** <<< end of configuration section >>> ***
First commit
2025-02-06 07:35:32 +00:00
MODULE INFORMATION: STATIC OVERLAYABLE
CODE SIZE = ---- ----
CONSTANT SIZE = 1024 ----
XDATA SIZE = ---- ----
PDATA SIZE = ---- ----
DATA SIZE = ---- ----
IDATA SIZE = ---- ----
BIT SIZE = ---- ----
END OF MODULE INFORMATION.
C51 COMPILATION COMPLETE. 0 WARNING(S), 0 ERROR(S)